Display device

Abstract

A display device is provided. The display device has a display area and a non-display area disposed around the display area, and includes pixels disposed in the display area; and an in-pixel curved area disposed along a direction of each of the pixels.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0086662, filed with the Korean Intellectual Property Office on July 17, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Due to the continuous development of information technology, the demand for display devices of various shapes and sizes for displaying images has increased. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and televisions. A display device may include a display panel comprising pixels connected to scan lines, data lines, and power lines to display images.

[0005] It should be understood that, to some extent, this background section is intended to provide useful context for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were not part of what is known or understood by one of skill in the art prior to the corresponding valid submission date of the subject matter disclosed herein. Summary of the Invention

[0006] This disclosure provides a display device in which breakage caused by inorganic layers in pixels can be prevented.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0008] According to an aspect of this disclosure, a display device is provided having a display area and a non-display area arranged around the display area. The display device includes: pixels arranged in the display area; and an intra-pixel curved region arranged along one direction of each pixel.

[0009] The display device may further include an outer-pixel curved region arranged around each of the pixels, and the outer-pixel curved regions are arranged between the pixels.

[0010] The display device may further include a scan line passing through each of the pixels, wherein a curved region within the pixel may extend in the same direction as the scan line.

[0011] Each pixel may include a first transistor and a third transistor, and in a planar view, a curved region within the pixel may be arranged between the first transistor and the third transistor.

[0012] The first transistor may include a first semiconductor layer and a first gate electrode of the scan line, and the first semiconductor layer may be disconnected in a curved region within the pixel.

[0013] The first semiconductor layer may include a first active layer, a first electrode disposed on one side of the first active layer, and a second electrode disposed on the other side of the first active layer, wherein the second electrode may be disconnected in a curved region within the pixel.

[0014] The display device may further include a first substrate, a barrier layer disposed on the first substrate, a buffer layer disposed on the barrier layer, a first semiconductor layer disposed on the buffer layer, an insulating layer disposed on the first semiconductor layer, and a first flexible organic layer, wherein the first flexible organic layer can penetrate the insulating layer and the first semiconductor layer in a flexible region within a pixel.

[0015] The first curved organic layer can further penetrate the buffer layer and can be arranged on the surface of the barrier layer.

[0016] The first bent organic layer can further penetrate the barrier layer and can be disposed on the surface of the first substrate.

[0017] The in-pixel curved region may further include in-pixel interconnects disposed on the first curved organic layer, and the in-pixel interconnects may be electrically connected to the disconnected first semiconductor layer.

[0018] Intra-pixel interconnects and scan lines can be made of different materials.

[0019] Intra-pixel interconnects may include aluminum, and scan lines may include molybdenum.

[0020] Intra-pixel connecting lines can extend in directions that intersect or cross the extension direction of the curved region within the pixel.

[0021] The display device may further include an outwardly curved region surrounding each of the pixels, wherein the outwardly curved regions may be arranged between adjacent pixels.

[0022] Scan lines can be broken in curved areas outside the pixels.

[0023] The display device may further include a first substrate, a barrier layer disposed on the first substrate, a buffer layer disposed on the barrier layer, a scan line disposed on the buffer layer, an insulating layer disposed on the scan line, and a second bent organic layer, wherein the second bent organic layer can penetrate the insulating layer and the scan line in the bent region outside the pixel.

[0024] The display device may further include pixel external connection lines extending in the same direction as the scan lines, wherein the pixel external connection lines may be arranged on a second curved organic layer.

[0025] Pixel external connection lines can electrically connect disconnected scan lines.

[0026] The display device is foldable along the folding axis, and when the display device is folded along the folding axis, portions of the display areas separated by the folding axis overlap each other.

[0027] According to another aspect of this disclosure, a display device is provided, comprising: a first substrate; a barrier layer disposed on the first substrate; a buffer layer disposed on the barrier layer; a semiconductor layer disposed on the buffer layer; a scan line disposed on the semiconductor layer; an insulating layer disposed on the scan line; a bent organic layer penetrating the insulating layer and the scan line; and a pixel external connection line disposed on the bent organic layer, wherein the scan line is disconnected by the bent organic layer, and the pixel external connection line is electrically connected to the scan line disconnected by the bent organic layer.

[0028] Scan lines and pixel external connections can be made of different materials.

[0029] Pixel external connection lines may include aluminum, and scan lines may include molybdenum. Attached Figure Description

[0030] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 This is a perspective view of a display device according to an embodiment;

[0032] Figure 2 This is an exploded perspective view of a display device according to an embodiment;

[0033] Figure 3 This is a plan view of the display panel according to an embodiment;

[0034] Figure 4 This is a block diagram of the display panel and display driver circuit according to an embodiment;

[0035] Figure 5 This is a schematic plan view of the display panel according to an embodiment;

[0036] Figure 6 This is a circuit diagram of a sub-pixel according to an embodiment;

[0037] Figure 7 yes Figure 5 A plan view of area A;

[0038] Figure 8 It is along Figure 7 A schematic cross-sectional view of line I-I';

[0039] Figure 9 It is along Figure 7 A schematic cross-sectional view taken from line III-III';

[0040] Figure 10 It is along Figure 7 A schematic cross-sectional view of line IV-IV';

[0041] Figure 11 It is along Figure 7 A schematic cross-sectional view of the line V-V'.

[0042] Figure 12 It is along Figure 7 A schematic cross-sectional view of line VI-VI';

[0043] Figure 13 It is along Figure 7 A schematic cross-sectional view of line VII-VII';

[0044] Figure 14 It is along Figure 7 A schematic cross-sectional view of line VIII-VIII';

[0045] Figures 15 to 19 This is a schematic cross-sectional view of the display panel according to an embodiment;

[0046] Figure 20 This is a schematic plan view of the display panel according to an embodiment;

[0047] Figure 21 This is a schematic plan view of the display panel according to an embodiment;

[0048] Figure 22 This is a perspective view of a display device according to an embodiment;

[0049] Figure 23 It is along Figure 22 A schematic cross-sectional view taken from line II-II';

[0050] Figure 24 This is a schematic plan view of the display panel of the display device according to an embodiment;

[0051] Figure 25 This is a schematic plan view of the display panel of the display device according to an embodiment;

[0052] Figure 26 yes Figure 25 An enlarged view of region B; and

[0053] Figure 27yes Figure 25 A magnified view of region C. Detailed Implementation

[0054] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, can be more readily understood by referring to the following detailed description of embodiments and accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the contents of this disclosure to those skilled in the art, and this disclosure is defined by the appended claims.

[0055] In order to describe embodiments of the invention, some parts not associated with the specification may be omitted, and throughout the specification, the same reference numerals refer to the same elements.

[0056] In the accompanying drawings, the dimensions and thicknesses of the elements may be enlarged for clarity and ease of description. However, this disclosure is not limited to the dimensions and thicknesses shown in the drawings. The thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity in the drawings.

[0057] Furthermore, in this specification, the term "in a plan view" refers to the view of an object portion from above, and the term "in a schematic cross-sectional view" refers to a schematic cross-section taken by vertically cutting the object portion from the side. Additionally, the terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" may include layering, stacking, facing, variations thereof, extending over, covering, or partially covering, or any other suitable term known and understood by one of ordinary skill in the art. The term "facing" or variations thereof means that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, the first and second elements may be understood as indirectly opposite each other, but still facing each other. When an element is described as "non-overlapping" or "non-coincident" with another element, this may include the elements being spaced apart from each other, offset from each other, or located next to each other, or any other suitable term known and understood by one of ordinary skill in the art.

[0058] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0059] As used herein, “about” or “approximate” includes specified values ​​and average values ​​within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, taking into account the measured value in question and the error associated with the measured value of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±5% of a specified value.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an ideal or overly formal sense unless expressly defined in the specification.

[0061] The various features of the embodiments of this disclosure can be combined or integrated with each other in whole or in part, and various links and drivers are technically possible. Embodiments can be implemented independently or in association with each other or in combination.

[0062] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0063] Figure 1 This is a perspective view of the display device 10 according to an embodiment. Figure 2 This is an exploded perspective view of the display device 10 according to an embodiment.

[0064] refer to Figure 1 and Figure 2 The display device 10 according to the embodiment may include a cover window 100, a display panel 300, a display circuit board 310, a display driver circuit 320, a flexible film 390, a bracket 600, a main circuit board 700, sensor devices 740, 750, 760 and 770, and a bottom cover 900.

[0065] In this specification, the term "above" may indicate the direction in which the cover window 100 is arranged relative to the display panel 300, i.e., the Z-axis direction, and the term "below" may indicate the direction in which the support 600 is arranged relative to the display panel 300, i.e., the direction opposite to the Z-axis direction, or the direction opposite to the direction in which the cover window 100 is arranged relative to the display panel 300. Additionally, "left," "right," "up," and "down" may indicate the direction when the display panel 300 is viewed in a plan view. For example, "left" may indicate the direction opposite to the X-axis direction, "right" may indicate the direction opposite to "left" relative to the X-axis direction, "up" may indicate the Z-axis direction (or Y-axis direction), and "down" may indicate the direction opposite to "up" relative to the Z-axis direction (or the direction opposite to the Y-axis direction). In other words, for ease of description, the spatial relative terms "below," "below," "down," "above," "up," etc., may be used herein to describe the relationship between one element or component and another element or component as illustrated in the accompanying drawings. However, it should be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, in the case where the device illustrated in the accompanying drawings is flipped, a device placed "below" or "under" another device can be placed "above" another device. Therefore, the descriptive term "below" can include both lower and upper positions. The device can also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0066] Display device 10 can be a device for displaying moving or still images. For example, display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as in various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IoT). However, the device can be used in other devices and is not limited to the examples set forth herein.

[0067] The display device 10 can be rectangular in a plan view. For example, as shown... Figure 1 and Figure 2As illustrated, the display device 10 may have a rectangular planar shape, having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). However, it should be understood that the device may have a short side in the second direction (Y-axis direction) and a long side in the first direction (X-axis direction). Each angle where the short side extending in the first direction (X-axis direction) intersects the long side extending in the second direction (Y-axis direction) may be circular with a predetermined curvature or may be right angled. The planar shape of the display device 10 is not limited to a rectangular shape, but may also be other polygonal shapes, circular shapes, elliptical shapes, or other shapes within the spirit and scope of this disclosure.

[0068] The display device 10 may include a first region DR1 formed as a flat area and a second region DR2 extending from the right and left sides of the first region DR1. The second region DR2 may be formed as a flat area or as a curved area. When the second region DR2 is formed as a flat area, the angle formed by the first region DR1 and the second region DR2 may be an obtuse angle or an approximately obtuse angle. When the second region DR2 is formed as a curved area, it may have a constant curvature or a varying curvature.

[0069] exist Figure 1 In this embodiment, the second region DR2 can extend from each of the right and left sides of the first region DR1. However, the embodiment is not limited to this. For example, the second region DR2 may also extend from only one of the right and left sides of the first region DR1. In other embodiments, the second region DR2 may extend not only from the right and left sides of the first region DR1, but also from at least either the upper or lower side of the first region DR1. The case where the second region DR2 is arranged at the right and left edges of the display device 10 will be described below.

[0070] The cover window 100 can be arranged on the display panel 300 to cover the upper surface of the display panel 300. Therefore, the cover window 100 can protect the upper surface of the display panel 300.

[0071] Cover window 100 may be arranged in a first region DR1 and a second region DR2. Cover window 100 may include a light-transmitting portion DA100 corresponding to the display panel 300 and a light-shielding portion NDA100 corresponding to the area outside the display panel 300. The light-shielding portion NDA100 may be formed to be opaque. In other embodiments, the light-shielding portion NDA100 may be formed as a decorative layer having a pattern visible to the user when no image is displayed. Although not shown, cover window 100 may include a second light-transmitting portion.

[0072] The display panel 300 can be arranged below the cover window 100. The display panel 300 can be arranged in the first region DR1 and the second region DR2. Therefore, through the cover window 100, the image of the display panel 300 can be seen not only in the first region DR1, but also in the second region DR2. For example, the image displayed on the display panel 300 can be seen on the upper surface, left edge, and right edge of the display device 10 through the cover window 100.

[0073] The display panel 300 may include a display area DA and a non-display area NDA arranged around the display area DA. The display area DA may overlap with the light-transmitting portion DA100 of the cover window 100.

[0074] Display panel 300 can be a light-emitting display panel that includes light-emitting elements. For example, display panel 300 can be an organic light-emitting display panel using organic light-emitting diodes (OLEDs) including organic light-emitting layers, a micro light-emitting diode display panel using micro light-emitting diodes, a quantum dot light-emitting display panel including quantum dot light-emitting diodes containing quantum dot light-emitting layers, or an inorganic light-emitting display panel using inorganic light-emitting elements including inorganic semiconductors. However, display panel 300 is not limited to these and can include other types of display panels. The case where display panel 300 is an organic light-emitting display panel will be described below.

[0075] The display circuit board 310 and the display driver circuit 320 can be attached to one side of the display panel 300. One end of the display circuit board 310 can be attached to a pad DP provided on that side of the display panel 300 using, for example, an anisotropic conductive film (e.g., a...). Figure 3 (As shown in the figure). The display circuit board 310 can be a flexible printed circuit board that is bendable, a rigid printed circuit board that is not easily bent, or a composite printed circuit board that includes both rigid and flexible printed circuit boards.

[0076] The display driver circuit 320 can receive control signals and power supply voltages through the display circuit board 310, and can generate signals and voltages for driving the display panel 300. The display driver circuit 320 can be formed as an integrated circuit and can be attached to the display panel 300 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. However, the embodiments are not limited to this. For example, the display driver circuit 320 can be attached to the display circuit board 310.

[0077] Touch driver circuit 330 can be disposed on display circuit board 310. Touch driver circuit 330 can be formed as an integrated circuit and attached to the upper surface of display circuit board 310. Touch driver circuit 330 can be electrically connected to the touch electrodes of touch sensor layer of display panel 300 through display circuit board 310. Touch driver circuit 330 can send touch driving signals to the driving electrode in the touch electrode, and can detect the charge change of the capacitance between the driving electrode and the sensing electrode in the touch electrode through the sensing electrode to output touch data including the user's touch coordinates. Power supply unit 340 (see...) Figure 4 It can be arranged on the display circuit board 310 to supply the display driving voltage for driving the display driver circuit 320.

[0078] One side of the flexible film 390 can be attached to the upper surface of the display panel 300 from the underside using, for example, an anisotropic conductive film. The other side of the flexible film 390 can be attached to the upper surface of the display circuit board 310 from the upper side using, for example, an anisotropic conductive film. The flexible film 390 can be a bendable flexible film.

[0079] In this embodiment, the flexible film 390 may be omitted, and the display circuit board 310 may be attached (e.g., directly attached) to one side of the display panel 300. For example, one side of the display panel 300 may be bent toward the lower surface of the display panel 300.

[0080] The bracket 600 may be positioned below the display panel 300. The bracket 600 may comprise plastic, metal, or both. The bracket 600 may include: a first camera aperture CMH1 into which a first camera sensor 720 can be inserted; a battery aperture BH into which a battery 790 can be disposed; a cable aperture CAH through which a cable 314 connected to the display circuit board 310 passes; and a sensor aperture SH into which sensor devices 740, 750, 760, and 770 can be disposed. In other embodiments, the bracket 600 may not include the sensor aperture SH and may not overlap with the sensor area of ​​the display panel 300.

[0081] The main circuit board 700 and the battery 790 can be arranged below the bracket 600. The main circuit board 700 can be a printed circuit board or a flexible printed circuit board.

[0082] The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and sensor devices 740, 750, 760, and 770. The first camera sensor 720 may be disposed on both the upper and lower surfaces of the main circuit board 700, the main processor 710 may be disposed on the upper surface of the main circuit board 700, and the main connector 730 may be disposed on the lower surface of the main circuit board 700. Sensor devices 740, 750, 760, and 770 may be disposed on the upper surface of the main circuit board 700.

[0083] The main processor 710 can control the functions of the display device 10. For example, the main processor 710 can output digital video data to the display driver circuit 320 via the display circuit board 310, so that the display panel 300 can display images. The main processor 710 can receive touch data from the touch driver circuit 330, determine the user's touch coordinates, and then execute the application program indicated by the icon displayed at the user's touch coordinates.

[0084] The main processor 710 can control the display device 10 based on sensor signals received from sensor devices 740, 750, 760, and 770. For example, the main processor 710 can determine whether an object is near the upper surface of the display device 10 based on a proximity sensor signal received from proximity sensor 740. When an object is near the upper surface of the display device 10 during a call in which the user is using the display device 10 to communicate with another party, the main processor 710 may not execute the application indicated by the icon displayed at the touch coordinates, even if the user makes a touch gesture.

[0085] The main processor 710 can determine the brightness of the upper surface of the display device 10 based on the illuminance sensor signal received from the illuminance sensor 750. The main processor 710 can adjust the brightness of the image displayed on the display panel 300 based on the brightness of the upper surface of the display device 10.

[0086] The main processor 710 can determine whether the user's iris image is the same as an iris image, for example, pre-stored in memory, based on the iris sensor signal received from the iris sensor 760. When the user's iris image is the same as the iris image, the main processor 710 can unlock the display device 10 and display the main screen on the display panel 300. The sensor devices 740, 750, 760, and 770 are not limited to the above functions, but may include other types of sensors and other types of functions.

[0087] The first camera sensor 720 processes image frames, such as still images or moving images, obtained from the image sensor and outputs the processed image frames to the main processor 710. The first camera sensor 720 may be a complementary metal-oxide-semiconductor (CMOS) image sensor or a charge-coupled device (CCD) sensor. The first camera sensor 720 may be exposed through a second camera aperture CMH2 located in the lower surface of the bottom cover 900. Therefore, the first camera sensor 720 can capture images of objects or backgrounds arranged below the display device 10.

[0088] Cable 314, passing through cable hole CAH in bracket 600, can be connected to main connector 730. Therefore, main circuit board 700 can be electrically connected to display circuit board 310.

[0089] Sensor devices 740, 750, 760, and 770 may include a proximity sensor 740, an illumination sensor 750, an iris sensor 760, and a second camera sensor 770. Sensor devices 740, 750, 760, and 770 are not limited to those described above. Figure 2 Those shown in the diagram.

[0090] The proximity sensor 740 can be a sensor used to detect whether an object is located near the upper surface of the display device 10. The proximity sensor 740 may include a light source that outputs light and a light receiving unit that receives light reflected by the object. The proximity sensor 740 can determine the presence of an object near the upper surface of the display device 10 based on the amount of light reflected by the object. In the thickness direction (Z-axis direction) of the display panel 300, the proximity sensor 740 may overlap with the sensor hole SH, the sensor area of ​​the display panel 300, and the second light-transmitting portion of the cover window 100. Therefore, the proximity sensor 740 can generate a proximity sensor signal based on the presence of an object near the upper surface of the display device 10 and output the proximity sensor signal to the main processor 710.

[0091] The illuminance sensor 750 can be a sensor used to detect the brightness of the upper surface of the display device 10. The illuminance sensor 750 may include a resistor whose resistance value varies according to the brightness of the incident light. The illuminance sensor 750 can determine the brightness of the upper surface of the display device 10 based on the resistance value of the resistor. In the thickness direction (Z-axis direction) of the display panel 300, the illuminance sensor 750 may overlap with the sensor hole SH, the sensor area of ​​the display panel 300, and the second light-transmitting portion of the cover window 100. Therefore, the illuminance sensor 750 can generate an illuminance sensor signal based on the brightness of the upper surface of the display device 10 and output the illuminance sensor signal to the main processor 710.

[0092] The iris sensor 760 can be a sensor used to detect whether a captured image of a user's iris is the same as an iris image, for example, pre-stored in a memory. The iris sensor 760 can generate an iris sensor signal based on whether the user's iris image is the same as the captured image, and output the iris sensor signal to the main processor 710.

[0093] The second camera sensor 770 can process image frames, such as still images or moving images, obtained from the image sensor and output the processed image frames to the main processor 710. The second camera sensor 770 can be a CMOS image sensor or a CCD sensor. The number of pixels in the second camera sensor 770 can be less than the number of pixels in the first camera sensor 720, and the size of the second camera sensor 770 can be smaller than the size of the first camera sensor 720. In the thickness direction (Z-axis direction) of the display panel 300, the second camera sensor 770 can overlap with the sensor hole SH, the sensor area of ​​the display panel 300, and the second light-transmitting portion of the cover window 100. Therefore, the second camera sensor 770 can capture images of objects or backgrounds arranged above the display device 10. It should be understood that the number of pixels in the first camera sensor 720 and the second camera sensor 770 is not limited to the above description and can vary according to embodiments. Similarly, the sizes of the first camera sensor 720 and the second camera sensor 770 can vary according to embodiments.

[0094] The battery 790 can be arranged so that it does not overlap with the main circuit board 700 in the third direction (Z-axis direction). The battery 790 can overlap with the battery hole BH of the bracket 600.

[0095] The main circuit board 700 may be equipped with a mobile communication module, which is capable of transmitting wireless signals to or receiving wireless signals from at least one of a base station, an external terminal, and a server via a mobile communication network. The wireless signals may include voice signals, video call signals, or various forms of data transmitted / received according to text / multimedia messages.

[0096] The bottom cover 900 can be disposed below the main circuit board 700 and the battery 790. The bottom cover 900 can be fastened and secured to the bracket 600. The bottom cover 900 can form the bottom outer surface of the display device 10. The bottom cover 900 can include plastic, metal, or both plastic and metal.

[0097] A second camera hole CMH2, exposing the lower surface of the first camera sensor 720, can be formed in the bottom cover 900. The position of the first camera sensor 720 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the first camera sensor 720 are not limited to... Figure 2 The embodiment is illustrated in the figure.

[0098] Figure 3 This is a plan view of the display panel 300 according to an embodiment. Figure 4 This is a block diagram of the display panel 300 and the display driver circuit 320 according to an embodiment.

[0099] refer to Figure 3 and Figure 4 The display panel 300 may include a display area DA including subpixels SP and a non-display area NDA excluding subpixels SP.

[0100] Subpixel SP, scan line SL connected to subpixel SP, emitter line ECL, data line DL, and first drive voltage line VDDL can be arranged in display area DA. Scan line SL and emitter line ECL can extend parallel to each other in a first direction (X-axis direction), and data line DL can extend parallel to each other in a second direction (Y-axis direction) intersecting or crossing the first direction (X-axis direction). First drive voltage line VDDL can extend parallel to each other in display area DA along the second direction (Y-axis direction). The first drive voltage lines VDDL extending parallel to each other in display area DA along the second direction (Y-axis direction) can be connected to each other in non-display area NDA.

[0101] Each sub-pixel SP can be connected to at least one scan line SL, any one data line DL, at least one emitter line ECL, and any one of the first drive voltage lines VDDL. Figure 3 and Figure 4 In this illustration, for ease of description, each of the sub-pixels SP connected to two scan lines SL, one data line DL, one emitter line ECL, and one first drive voltage line VDDL is shown as an example. However, the embodiment is not limited to this. For example, each of the sub-pixels SP may also be connected to three scan lines SL instead of two scan lines SL.

[0102] Each of the sub-pixels SP may include a driving transistor DT, one or more transistors ST, a light-emitting element, and a capacitor (see [link to documentation]). Figure 6 The driving transistor DT can supply a driving current to the light-emitting element based on the data voltage applied to the gate electrode, thereby causing the light-emitting element to emit light. Both the driving transistor DT and the transistor ST can be thin-film transistors. The light-emitting element can emit light based on the driving current of the driving transistor DT. The light-emitting element can be an organic light-emitting diode (OLED) comprising a first electrode, an organic light-emitting layer, and a second electrode. A capacitor can maintain a constant data voltage applied to the gate electrode of the driving transistor DT.

[0103] The non-display area NDA can be defined as the area in the display panel 300 other than the display area DA. Within the non-display area NDA, a scan driver 410 for sending scan signals to scan line SL, a fan-out line FL connecting data line DL and display driver circuit 320, and a pad DP connected to display driver circuit 320 can be arranged. The display driver circuit 320 and pad DP can be arranged at the edge of the display panel 300. Pad DP can be arranged closer to the edge of the display panel 300 than the display driver circuit 320.

[0104] The scan driver 410 can be connected to the display driver circuit 320 via the first scan control line SCL1. The scan driver 410 can receive the scan control signal SCS from the display driver circuit 320 via the first scan control line SCL1. The scan driver 410 can generate scan signals according to the scan control signal SCS and output the scan signals sequentially to the scan line SL.

[0105] The transmit control driver 420 can be connected to the display driver circuit 320 via the second scan control line SCL2. The transmit control driver 420 can receive the transmit control signal ECS from the display driver circuit 320 via the second scan control line SCL2. The transmit control driver 420 can generate transmit control signals according to the transmit control signal ECS and output the transmit control signals sequentially to the transmit line ECL.

[0106] like Figure 3 As illustrated, the scan driver 410 may be arranged outside one side of the general area and the sensor area, and the transmit control driver 420 may be arranged outside the other side of the general area and the sensor area. The general area may be any area in the non-display area NDA. In other embodiments, both the scan driver 410 and the transmit control driver 420 may be arranged outside one side of the general area and the sensor area.

[0107] Scan driver 410 may include a thin-film transistor for generating a scan signal according to scan control signal SCS, and emit control driver 420 may include a thin-film transistor for generating an emit control signal according to emit control signal ECS. For example, the thin-film transistors of scan driver 410 and emit control driver 420 may be formed on the same layer as the thin-film transistors of sub-pixel SP.

[0108] like Figure 4 As shown in the figure, the driver circuit 320 may include a timing controller 321 and a data driver 322.

[0109] The timing controller 321 can receive data DATA (e.g., digital video data) and timing signals from the display circuit board 310. Based on the timing signals, the timing controller 321 can generate a scan control signal SCS for controlling the operating timing of the scan driver 410, a transmit control signal ECS for controlling the operating timing of the transmit control driver 420, and a data control signal DCS for controlling the operating timing of the data driver 322. The timing controller 321 can output the scan control signal SCS to the scan driver 410 and the transmit control signal ECS to the transmit control driver 420 via the first scan control line SCL1 and the second scan control line SCL2, respectively. The timing controller 321 can also output the digital video data DATA and the data control signal DCS to the data driver 322.

[0110] Data driver 322 can convert digital video data DATA into positive / negative analog data voltages and output the positive / negative analog data voltages to data line DL via fan-out line FL. Sub-pixels SP can be selected via the scan signal of scan driver 410, and data voltages can be supplied to the selected sub-pixels SP.

[0111] The power supply unit 340 can generate a first driving voltage and supply the first driving voltage to the first driving voltage line VDDL. The power supply unit 340 can generate a second driving voltage and supply the second driving voltage to the cathode of the organic light-emitting diode (OLED) in each of the sub-pixels SP. The first driving voltage can be a high potential voltage for driving the OLED, and the second driving voltage can be a low potential voltage for driving the OLED. For example, the first driving voltage can have a higher potential than the second driving voltage. The power supply unit 340 can generate driving voltages for driving the display driver circuit 320 and the scan driver 410, such as a display driving voltage, a gate high voltage, and a gate low voltage, and supply the driving voltage to the display driver circuit 320.

[0112] The display driver circuit 320 can be formed as an integrated circuit and can be attached to the display panel 300 using COG, COP, or ultrasonic bonding methods. However, the embodiments are not limited thereto. For example, the display driver circuit 320 can be attached to the display circuit board 310.

[0113] Figure 5 This is a schematic plan view of the display panel 300 according to an embodiment.

[0114] refer to Figure 5 Sub-pixels SP, including the first sub-pixel SP11 and the second sub-pixel SP12, can be along... Figure 3 The diagram shows the arrangement of the first direction (X-axis) and the second direction (Y-axis). Figure 5 In this context, subpixels SP can be arranged within the display area DA. The display area DA can include subpixels SP.

[0115] The outer curved region of a pixel may be located or arranged around the sub-pixel SP. The inner curved region of a pixel may be located or arranged in each of the sub-pixels SP. In a planar view, the outer curved region of a pixel may surround or substantially surround the periphery of each sub-pixel SP, or surround the periphery of each sub-pixel SP. In a planar view, the outer curved region of a pixel may be arranged between adjacent sub-pixels SP11 and SP12.

[0116] The outward curvature region of a pixel can be arranged in the display area DA and the non-display area NDA of the display panel 300. For example... Figure 5 As illustrated in the diagram, in a planar image, the curved regions outside a pixel can have a grid shape.

[0117] In a planar view, an intra-pixel curved region can be arranged in each of the sub-pixels SP. The intra-pixel curved region can extend along a first direction (X-axis direction).

[0118] Intra-pixel curved regions can be physically connected to adjacent extra-pixel curved regions.

[0119] The first curved organic layer PO1 can be arranged in the curved region outside the pixel. The second curved organic layer PO2 can be arranged in the curved region inside the pixel.

[0120] The first curved organic layer PO1 and the second curved organic layer PO2 will be described in detail below.

[0121] like Figure 5 As illustrated, the intra-pixel curved region may be located in or arranged in each of the sub-pixels SP arranged in the display area DA according to the embodiment. For example, the second curved organic layer PO2 of the intra-pixel curved region may be arranged in each of the sub-pixels SP.

[0122] In other embodiments, the intra-pixel curved region may be arranged in a first region of the display region DA, but may not be arranged in a second region of the display region DA other than the first region. For example, the intra-pixel curved region may be arranged in a portion of the display panel 300, but may not be arranged in any region other than that portion of the display panel 300.

[0123] In other embodiments, the intra-pixel curvature region may be arranged in a first group of sub-pixels SP, but may not be arranged in a second group of sub-pixels SP other than the first group of sub-pixels SP. For example, the intra-pixel curvature region may be applied on a grouping basis to prevent breakage of the layers in the pixel.

[0124] Figure 6This is a circuit diagram of the sub-pixel SP according to an embodiment.

[0125] exist Figure 6 In the diagram, sub-pixel SP can be connected to the (p-1)th scan line Sp-1, the pth scan line Sp, and the jth data line Dj.

[0126] refer to Figure 6 Sub-pixel SP can overlap with scan line p-1, scan line p, and data line j. Sub-pixel SP can be connected to the first driving voltage line VDDL supplied with the first driving voltage, the initialization voltage line VIL supplied with the initialization voltage, and the second driving voltage line VSSL supplied with the second driving voltage.

[0127] The sub-pixel SP may include a driving transistor DT, a light-emitting element EL, a switching element, a first capacitor C1, etc. The switching element may include the first transistor ST1 to the sixth transistor ST6.

[0128] The light-emitting element EL can be an organic light-emitting diode (OLED), which includes an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode. In other embodiments, the light-emitting element EL can be an inorganic light-emitting element, which includes an anode, a cathode, and an inorganic semiconductor disposed between the anode and the cathode. In other embodiments, the light-emitting element EL can be a quantum dot light-emitting element, which includes an anode, a cathode, and a quantum dot light-emitting layer disposed between the anode and the cathode. In other embodiments, the light-emitting element EL can be a microlight-emitting diode (microLED).

[0129] The light-emitting element EL may have an anode connected to the second electrode of the fifth transistor ST5 and a cathode connected to the second drive voltage line VSSL. A parasitic capacitance Cel may be formed between the anode and cathode of the light-emitting element EL.

[0130] The first transistor ST1 can be configured as a dual transistor comprising a first-1 transistor ST1-1 and a first-2 transistor ST1-2. Both transistors ST1-1 and ST1-2 are turned on by a scan signal via the p-1 scan line Sp-1 and are connected to the gate electrode of the driving transistor DT and the initialization voltage line VIL. The gate electrode of the driving transistor DT can be discharged to the initialization voltage of the initialization voltage line VIL. The first-1 transistor ST1-1 may have a gate electrode connected to the p-1 scan line Sp-1, a first electrode connected to the gate electrode of the driving transistor DT, and a second electrode connected to the first electrode of the first-2 transistor ST1-2. The first-2 transistor ST1-2 may have a gate electrode connected to the p-1 scan line Sp-1, a first electrode connected to the second electrode of the first-1 transistor ST1-1, and a second electrode connected to the initialization voltage line VIL.

[0131] The second transistor ST2 can be turned on by the scan signal of the p-th scan line Sp, and can be connected to the first electrode of the driving transistor DT and the j-th data line Dj. The second transistor ST2 may have a gate electrode connected to the p-th scan line Sp, a first electrode connected to the first electrode of the driving transistor DT, and a second electrode connected to the j-th data line Dj.

[0132] The third transistor ST3 can be formed as a dual transistor including a third-first transistor ST3-1 and a third-second transistor ST3-2. The third-first transistor ST3-1 and the third-second transistor ST3-2 can be turned on by the scan signal of the p-th scan line Sp, and can be connected to the gate electrode and the second electrode of the driving transistor DT. For example, since the gate electrode and the second electrode of the driving transistor DT can be connected when the third-first transistor ST3-1 and the third-second transistor ST3-2 are turned on, the driving transistor DT can be driven as a diode. The third-first transistor ST3-1 can have a gate electrode connected to the p-th scan line Sp, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the first electrode of the third-second transistor ST3-2. The third-second transistor ST3-2 can have a gate electrode connected to the p-th scan line Sp, a first electrode connected to the second electrode of the third-first transistor ST3-1, and a second electrode connected to the gate electrode of the driving transistor DT.

[0133] The fourth transistor ST4 can be turned on by the emitter control signal of the p-th emitter line Ep, and is connected to the first electrode of the driving transistor DT and the first driving voltage line VDDL. The fourth transistor ST4 may have a gate electrode connected to the p-th emitter line Ep, a first electrode connected to the first driving voltage line VDDL, and a second electrode connected to the first electrode of the driving transistor DT.

[0134] The fifth transistor ST5 can be connected between the second electrode of the driving transistor DT and the anode of the light-emitting element EL. The fifth transistor ST5 can be turned on by the emission control signal of the p-th emitter line Ep, and connects the second electrode of the driving transistor DT and the anode of the light-emitting element EL. The fifth transistor ST5 can have a gate electrode connected to the p-th emitter line Ep, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode of the light-emitting element EL. When both the fourth transistor ST4 and the fifth transistor ST5 are turned on, a drive current can be supplied to the light-emitting element EL.

[0135] The sixth transistor ST6 can be turned on by the scan signal of the p-th scan line Sp, and can be connected to the anode of the light-emitting element EL and the initialization voltage line VIL. The anode of the light-emitting element EL can be discharged to the initialization voltage. The sixth transistor ST6 can have a gate electrode connected to the p-th scan line Sp, a first electrode connected to the anode of the light-emitting element EL, and a second electrode connected to the initialization voltage line VIL.

[0136] A first capacitor C1 may be formed between the gate electrode of the driving transistor DT and the first driving voltage line VDDL. One electrode of the first capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first driving voltage line VDDL.

[0137] When the first electrode of each of the first transistors ST1 to ST6 and the driving transistor DT is a source electrode, the second electrode can be a drain electrode. In other embodiments, when the first electrode of each of the first transistors ST1 to ST6 and the driving transistor DT is a drain electrode, the second electrode can be a source electrode.

[0138] The active layer of each of the first transistors ST1 to the sixth transistor ST6 and the driving transistor DT can be made of at least one of polycrystalline silicon, amorphous silicon, and oxide semiconductor. When the semiconductor layer of each of the first transistors ST1 to the sixth transistor ST6 and the driving transistor DT is made of polycrystalline silicon, the process for forming the semiconductor layer can be a low-temperature polycrystalline silicon (LTPS) process.

[0139] Although the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can be formed as P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), the embodiments are not limited to this, and the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can also be formed as N-type MOSFETs.

[0140] Figure 7 yes Figure 5 A plan view of area A.

[0141] refer to Figure 7 Sub-pixel SP may include driving transistor DT, first transistor ST1 to sixth transistor ST6 and first capacitor C1.

[0142] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT may overlap with the gate electrode DT_G. The gate electrode DT_G of the driving transistor DT can be connected to the first connection electrode BE1 through a first contact hole CNT1. The first connection electrode BE1 can be connected to the first electrode S1-1 of the first-1 transistor ST1-1 and the drain electrode D3-2 of the third-2 transistor ST3-2 through a second contact hole CNT2. The first connection electrode BE1 may intersect or cross the p-th scan line Sp. The first electrode DT_S of the driving transistor DT can be connected to the first electrode S2 of the second transistor ST2. The second electrode DT_D of the driving transistor DT can be connected to the first electrode S3-1 of the third-1 transistor ST3-1 and the first electrode S5 of the fifth transistor ST5.

[0143] The first transistor ST1 can be configured as a dual transistor. The first transistor ST1 may include a first transistor ST1-1 and a first transistor ST1-2.

[0144] Transistor ST1-1 (first-1) may include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of transistor ST1-1 may be part of the p-1th scan line Sp-1, and may be the overlapping region between the active layer ACT1-1 and the p-1th scan line Sp-1. The first electrode S1-1 of transistor ST1-1 may be connected to the first connection electrode BE1 of the driving transistor DT via the second contact hole CNT2. The second electrode D1-1 of transistor ST1-1 may be connected to the first electrode S1-2 of transistor ST1-2 (first-2).

[0145] Transistor ST1-2 (first and second) may include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of transistor ST1-2 may be a portion of scan line Sp-1 (p-1), and may be the overlapping region between the active layer ACT1-2 and scan line Sp-1. The first electrode S1-2 of transistor ST1-2 may be connected to the second electrode D1-1 of transistor ST1-1. The second electrode D1-2 of transistor ST1-2 may be connected to the initialization connection electrode VIE via the fourth contact hole CNT4.

[0146] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 may be part of the p-th scan line Sp, and may be the overlapping region between the active layer ACT2 and the p-th scan line Sp. The first electrode S2 of the second transistor ST2 may be connected to the first electrode DT_S of the driving transistor DT. The second electrode D2 of the second transistor ST2 may be connected to the data line DL through a third contact hole CNT3.

[0147] The third transistor ST3 can be configured as a dual transistor. The third transistor ST3 may include the third-first transistor ST3-1 and the third-second transistor ST3-2.

[0148] Transistor ST3-1 (3-1) may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of transistor ST3-1 may be part of the p-th scan line Sp, and may be the overlapping region between the active layer ACT3-1 and the p-th scan line Sp. The first electrode S3-1 of transistor ST3-1 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D3-1 of transistor ST3-1 may be connected to the first electrode S3-2 of transistor ST3-2 (3-2).

[0149] Transistor ST3-2 (3-2) may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of transistor ST3-2 may be part of the p-th scan line Sp, and may be the overlapping region between the active layer ACT3-2 and the p-th scan line Sp. The first electrode S3-2 of transistor ST3-2 may be connected to the second electrode D3-1 of transistor ST3-1 (3-1). The second electrode D3-2 of transistor ST3-2 may be connected to the first connection electrode BE1 through the second contact hole CNT2.

[0150] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 may be part of the p-th emitter line Ep, and may be the overlapping region between the active layer ACT4 and the p-th emitter line Ep. The first electrode S4 of the fourth transistor ST4 can be connected to the second electrode CE12 of the first capacitor C1 through the seventh contact hole CNT7. The second electrode D4 of the fourth transistor ST4 can be connected to the first electrode DT_S of the driving transistor DT.

[0151] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 may be part of the p-th emitter line Ep, and may be the overlapping region between the active layer ACT5 and the p-th emitter line Ep. The first electrode S5 of the fifth transistor ST5 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D5 of the fifth transistor ST5 may be connected to the first electrode of the light-emitting element through the sixth contact hole CNT6.

[0152] The first electrode CE11 of the first capacitor C1 may be part of the gate electrode DT_G of the driving transistor DT. The second electrode CE12 of the first capacitor C1 may be part of the horizontal driving voltage line HVDDL connected to the first driving voltage line VDDL through the eighth contact hole CNT8. The first electrode CE11 and the second electrode CE12 may overlap each other.

[0153] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 may be part of the p-th scan line Sp, and may be the overlapping region between the active layer ACT6 and the p-th scan line Sp of the sixth transistor ST6. The first anode connection electrode ANDE1 can be connected to the first electrode S6 of the sixth transistor ST6 through the sixth contact hole CNT6. Figure 8 As shown in the diagram, the second anode connection electrode ANDE2 can be connected to the first anode connection electrode ANDE1 through the first anode contact hole AND_CNT1. Figure 8 As illustrated, the first electrode 171 of the light-emitting element 170 can be connected to the first anode connection electrode ANDE1 through the second anode contact hole AND_CNT2. The second electrode D6 of the sixth transistor ST6 can be connected to the initialization connection electrode VIE through the fourth contact hole CNT4. The initialization voltage line VIL can be connected to the initialization connection electrode VIE through the fifth contact hole CNT5, and the initialization connection electrode VIE can be connected to the second electrode D1-2 of the first-second transistor ST1-2 and the second electrode D6 of the sixth transistor ST6 through the fourth contact hole CNT4. The initialization connection electrode VIE can intersect or cross the p-1 scan line Sp-1.

[0154] refer to Figure 7 The outer-pixel curved region can be arranged between the first sub-pixel SP11 and the second sub-pixel SP12. The outer-pixel curved region can be arranged around each of the sub-pixels SP11 and SP12, and can surround or substantially surround each of the sub-pixels SP11 and SP12 in a planar view. As described above, the first curved organic layer PO1 can be arranged in the outer-pixel curved region.

[0155] An intra-pixel curved region may be provided in each of sub-pixels SP11 and SP12. The intra-pixel curved region may be arranged in each of sub-pixels SP11 and SP12. The intra-pixel curved region may extend along a first direction (X-axis direction).

[0156] The display panel 300 may include a first connecting line CL1 overlapping the initialization voltage line VIL, a second connecting line CL2 overlapping the (p-1)th scan line Sp-1, a third connecting line CL3 overlapping the p-th scan line Sp, and a fourth connecting line CL4 overlapping the p-th emission line Ep. The first connecting lines CL1 to the fourth connecting lines CL4 may extend in the same direction as the initialization voltage line VIL, the (p-1)th scan line Sp-1, the p-th scan line Sp, and the p-th emission line Ep. It should be understood that, depending on their location within or outside the bend region of a pixel, the connecting lines may be referred to as intra-pixel connecting lines or extra-pixel connecting lines.

[0157] Connection lines CL1 to CL4 can be connected to the first gate layer GTL1 and the second gate layer GTL2 (see...) Figure 8 The materials used may differ. For example, the first gate layer GTL1 may include molybdenum (Mo), and the interconnects CL1 to CL4 may include aluminum (Al). For example, the interconnects CL1 to CL4 may include a metal material that is softer than aluminum (Al).

[0158] The initialization voltage line VIL, the (p-1)th scan line Sp-1, the p-th scan line Sp, and the p-th emission line Ep can be disconnected by the first bent organic layer PO1 arranged between the first sub-pixel SP11 and the second sub-pixel SP12. Therefore, the connecting lines CL1 to CL4 can electrically connect the initialization voltage line VIL, the (p-1)th scan line Sp-1, the p-th scan line Sp, and the p-th emission line Ep, which are disconnected by the first bent organic layer PO1.

[0159] The first connecting line CL1 can pass through the first sub-pixel SP11 and the second sub-pixel SP12. For example... Figure 7 As illustrated, the first connecting line CL1 can be electrically connected to the disconnected initialization voltage line VIL through the ninth contact hole CNT9 and the tenth contact hole CNT10; the second connecting line CL2 can be electrically connected to the disconnected p-1 scan line Sp-1 through the eleventh contact hole CNT11 and the twelfth contact hole CNT12; the third connecting line CL3 can be electrically connected to the disconnected p scan line Sp through the thirteenth contact hole CNT13 and the fourteenth contact hole CNT14; and the fourth connecting line CL4 can be electrically connected to the disconnected p emission line Ep through the fifteenth contact hole CNT15 and the sixteenth contact hole CNT16.

[0160] Each of the connecting lines CL1 to CL4 can pass through the curved area outside the pixel.

[0161] The display panel 300 may further include a fifth connecting line CL5 and a sixth connecting line CL6 extending along a second direction (Y-axis direction) that intersects or crosses the extension direction of the curved region within the pixel.

[0162] The fifth connection line CL5 can overlap with the first electrode S1-1, the second electrode D1-1 and the active layer ACT1-1 of the first transistor ST1-1.

[0163] The sixth connection line CL6 can overlap with the first electrode S1-2, the second electrode D1-2 and the active layer ACT1-2 of the first-second transistor ST1-2.

[0164] Connecting wires CL5 and CL6 may contain the same material as connecting wires CL1 to CL4 described above.

[0165] For example, the connecting lines CL5 and CL6 may comprise a metal material that is more flexible than the material of the first gate layer GTL1.

[0166] Each of the first electrode S1-1 of transistor ST1-1 and the first electrode S1-2 of transistor ST1-2 can be disconnected by the second bent organic layer PO2 arranged in each of sub-pixels SP11 and SP12. Therefore, connecting lines CL5 and CL6 can electrically connect the disconnected first electrode S1-1 of transistor ST1-1 and the disconnected first electrode S1-2 of transistor ST1-2, respectively.

[0167] In a planar view, the curved region within a pixel can be arranged between the first transistors ST1-1 and ST1-2 and the third transistor ST3.

[0168] The fifth connecting line CL5 may overlap with the (p-1)th scan line Sp-1 and the first driving voltage line VDDL in the thickness direction. The sixth connecting line CL6 may overlap with the (p-1)th scan line Sp-1 in the thickness direction. Although in the figures, the sixth connecting line CL6 may not overlap with the first driving voltage line VDDL in the thickness direction, the embodiment is not limited to this, and the sixth connecting line CL6 may also overlap with the first driving voltage line VDDL in the thickness direction. The fifth connecting line CL5 and the sixth connecting line CL6 may be spaced apart from each other in the first direction (X-axis direction).

[0169] like Figure 7As shown, the fifth connecting line CL5 can be electrically connected to the disconnected first electrode S1-1 of the first-1 transistor ST1-1 through the seventeenth contact hole CNT17 and the eighteenth contact hole CNT18, and the sixth connecting line CL6 can be electrically connected to the disconnected first electrode S1-2 of the first-2 transistor ST1-2 through the nineteenth contact hole CNT19 and the twentieth contact hole CNT20.

[0170] Figure 8 It is along Figure 7 A schematic cross-sectional view taken from line I-I'. Figure 9 It is along Figure 7 A schematic cross-sectional view taken from line III-III'. Figure 10 It is along Figure 7 A schematic cross-sectional view taken from line IV-IV'. Figure 11 It is along Figure 7 A schematic cross-sectional view of the line V-V'. Figure 12 It is along Figure 7 A schematic cross-sectional view taken from line VI-VI'. Figure 13 It is along Figure 7 A schematic cross-sectional view of line VII-VII'. Figure 14 It is along Figure 7 A schematic cross-sectional view of line VIII-VIII'.

[0171] refer to Figures 8 to 14 The thin-film transistor layer, the light-emitting element layer, and the encapsulation layer TFE can be sequentially formed on the first substrate SUB1.

[0172] The thin-film transistor layer may include a light-shielding layer BSM, a barrier layer BR, a buffer layer BF, an active layer ACT, a first gate layer GTL1, a second gate layer GTL2, a third gate layer, a first source metal layer DTL1, a second source metal layer DTL2, a gate insulating layer 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a third interlayer insulating film 143, a protective layer 150, a first planarization layer 160, and a second planarization layer 180.

[0173] A light-shielding layer BSM can be formed on the surface of the first substrate SUB1. The light-shielding layer BSM can overlap with the active layer DT_ACT of the driving transistor DT to prevent leakage current from being generated due to light incident on the active layer DT_ACT of the driving transistor DT. Although the light-shielding layer BSM can overlap only with the active layer DT_ACT of the driving transistor DT, the embodiments are not limited to this. For example, the light-shielding layer BSM can overlap not only with the active layer DT_ACT of the driving transistor DT, but also with the active layers ACT1 of the first transistor ST1 to ACT6 of the sixth transistor ST6. The light-shielding layer BSM can be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Ne), copper (Cu), and their alloys.

[0174] A barrier layer BR can be formed on a light-shielding layer BSM. The barrier layer BR can be a multilayer in which one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked (e.g., alternately stacked). In other embodiments, the barrier layer BR may be omitted.

[0175] A buffer layer BF may be formed on the barrier layer BR. The buffer layer BF may be formed on the surface of the first substrate SUB1 to protect the organic light-emitting layer 172 of the thin-film transistor and light-emitting element layer from moisture introduced through the moisture-permeable first substrate SUB1. The buffer layer BF may consist of inorganic layers. For example, the buffer layer BF may be a multilayer in which one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked (e.g., alternately stacked). In other embodiments, the buffer layer BF may be omitted.

[0176] The active layer ACT can be formed on the first substrate SUB1 or the barrier layer BR. The active layer ACT can include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. When the active layer ACT is made of polycrystalline silicon, the ion-doped active layer ACT can be conductive. Therefore, the active layer ACT can include not only the active layer DT_ACT of the driving transistor DT of each of the first sub-pixel SP11 and the second sub-pixel SP12, and the active layers ACT1 of the first transistor ST1 to ACT6 of the sixth transistor ST6, but also the source electrodes DT_S, S1-1, S1-2, S2, S3-1, S3-2, S4, S5, and S6, and the drain electrodes DT_D, D1-1, D1-2, D2, D3-1, D3-2, D4, D5, and D6.

[0177] The gate insulating layer 130 can be formed on the active layer ACT. The gate insulating layer 130 can be an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0178] The first gate layer GTL1 may be formed on the gate insulating layer 130. The first gate layer GTL1 may include not only the gate electrode DT_G of the driving transistor DT of each of the first sub-pixels SP11 and the second sub-pixels SP12, and the gate electrodes G1 of the first transistor ST1 to G6 of the sixth transistor ST6, but also the scan line SL and the emitter line ECL. The first gate layer GTL1 may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Ne), copper (Cu), and their alloys. For example, the first gate layer GTL1 may include molybdenum (Mo).

[0179] The first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include an inorganic layer.

[0180] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include the initialization voltage line VIL and the second electrode CE12 of the first capacitor C1. The second gate layer GTL2 may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Ne), copper (Cu), and alloys thereof. For example, the second gate layer GTL2 may include molybdenum (Mo).

[0181] The second interlayer insulating film 142 can be formed on the second gate layer GTL2. The second interlayer insulating film 142 can be an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include an inorganic layer.

[0182] The connecting lines CL1 to CL6 can be disposed on the second interlayer insulating film 142. The connecting lines CL1 to CL6 may comprise a conductive material that is more flexible than the first gate layer GTL1 described above. For example, the connecting lines CL1 to CL6 may comprise aluminum (Al).

[0183] The third interlayer insulating film 143 can be disposed on the connecting lines CL1 to CL6. The third interlayer insulating film 143 can be an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The third interlayer insulating film 143 may include an inorganic layer.

[0184] The first source metal layer DTL1 can be formed on the third interlayer insulating film 143. The first source metal layer DTL1 may include a data line DL, a first drive voltage line VDDL, a first connection electrode BE1, a first anode connection electrode ANDE1, and an initialization connection electrode VIE. The first source metal layer DTL1 can be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Ne), copper (Cu), and their alloys.

[0185] The first planarization layer 160 may be formed on the first source metal layer DTL1 to planarize the steps caused by the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, and the first source metal layer DTL1. The first planarization layer 160 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0186] The protective layer 150 may be formed between the first source metal layer DTL1 and the first planarization layer 160. The protective layer 150 may be an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0187] The second source metal layer DTL2 may be formed on the first planarization layer 160. The second source metal layer DTL2 may include a second anode connection electrode ANDE2. The second source metal layer DTL2 may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Ne), copper (Cu) and their alloys.

[0188] The second planarization layer 180 can be formed on the second source metal layer DTL2. The second planarization layer 180 can be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0189] Although the illustration shows the driving transistor DT and each of the first transistors ST1 to ST6 of each sub-pixel SP as a top-gate type with the gate electrode located above the active layer, it should be noted that the embodiments are not limited thereto. For example, the driving transistor DT and each of the first transistors ST1 to ST6 of each sub-pixel SP can also be formed as a bottom-gate type with the gate electrode located below the active layer or as a dual-gate type with the gate electrodes located above and below the active layer.

[0190] The first contact hole CNT1 can penetrate from the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the gate electrode DT_G of the driving transistor DT. The first connection electrode BE1 can be connected to the gate electrode DT_G of the driving transistor DT through the first contact hole CNT1.

[0191] The second contact hole CNT2 can penetrate the gate insulating layer 130 and the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the first electrode S1-1 of the first-1 transistor ST1-1 and the second electrode D3-2 of the third-2 transistor ST3-2. The first connection electrode BE1 can be connected to the first electrode S1-1 of the first-1 transistor ST1-1 and the second electrode D3-2 of the third-2 transistor ST3-2 through the second contact hole CNT2.

[0192] The third contact hole CNT3 can penetrate the gate insulating layer 130 and the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the first electrode S2 of the second transistor ST2. The data line DL can be connected to the first electrode S2 of the second transistor ST2 through the third contact hole CNT3.

[0193] The fourth contact hole CNT4 can penetrate the gate insulating layer 130 and the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the second electrode D1-2 of the first-second transistor ST1-2 and the second electrode D6 of the sixth transistor ST6. The initialization connection electrode VIE can be connected to the second electrode D1-2 of the first-second transistor ST1-2, the second electrode D3-2 of the third-second transistor ST3-2, and the second electrode D6 of the sixth transistor ST6 through the fourth contact hole CNT4.

[0194] The fifth contact hole CNT5 can penetrate the second interlayer insulating film 142 and the third interlayer insulating film 143 to expose the initialization voltage line VIL. The initialization connection electrode VIE can be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0195] The sixth contact hole CNT6 can penetrate the gate insulating layer 130 and the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the second electrode D5 of the fifth transistor ST5. The first anode connection electrode ANDE1 can be connected to the second electrode D5 of the fifth transistor ST5 through the sixth contact hole CNT6.

[0196] The seventh contact hole CNT7 can penetrate the gate insulating layer 130 and the first interlayer insulating film 141 to the third interlayer insulating film 143 to expose the first electrode S4 of the fourth transistor ST4. The first drive voltage line VDDL can be connected to the first electrode S4 of the fourth transistor ST4 through the seventh contact hole CNT7.

[0197] The eighth contact hole CNT8 can penetrate the second interlayer insulating film 142 and the third interlayer insulating film 143 to expose the horizontal drive voltage line HVDDL. The first drive voltage line VDDL1 can be connected to the horizontal drive voltage line HVDDL through the eighth contact hole CNT8.

[0198] The first anode contact hole AND_CNT1 can penetrate the protective layer 150 and the first planarization layer 160 to expose the first anode connection electrode ANDE1.

[0199] The second anode contact hole AND_CNT2 can penetrate the second planarization layer 180 to expose the second anode connection electrode ANDE2.

[0200] The light-emitting element layer can be formed on the thin-film transistor layer. The light-emitting element layer may include a light-emitting element 170 and a pixel defining layer 190.

[0201] The light-emitting element 170 and the pixel defining layer 190 may be formed on the second planarization layer 180. Each of the light-emitting elements 170 may include a first electrode 171, an organic light-emitting layer 172, and a second electrode 173.

[0202] The first electrode 171 can be formed on the second planarization layer 180. The first electrode 171 can be connected to the second anode connection electrode ANDE2 through the second anode contact hole AND_CNT2 that penetrates the second planarization layer 180.

[0203] In the top-emitting structure where light can be emitted from the organic light-emitting layer 172 toward the second electrode 173, the first electrode 171 can be made of a metallic material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and indium tin oxide (ITO / APC / ITO). The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0204] A pixel defining layer 190 may be formed on the second planarization layer 180 to separate the first electrode 171 from the other first electrodes 171, thereby defining a light-emitting region EA for each of the first sub-pixels SP11 and the second sub-pixels SP12. The pixel defining layer 190 may be formed to cover the edge of each first electrode 171. The pixel defining layer 190 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0205] The light-emitting region EA of each sub-pixel SP can be a region in which a first electrode 171, an organic light-emitting layer 172, and a second electrode 173 are stacked sequentially such that holes from the first electrode 171 and electrons from the second electrode 173 combine in the organic light-emitting layer 172 to emit light.

[0206] An organic light-emitting layer 172 may be formed on the first electrode 171 and the pixel defining layer 190. The organic light-emitting layer 172 may include organic materials to emit light of a predetermined color. For example, the organic light-emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0207] The second electrode 173 can be formed on the organic light-emitting layer 172. The second electrode 173 can be formed to cover the organic light-emitting layer 172. The second electrode 173 can be a common layer shared by all sub-pixels. A capping layer can be formed on the second electrode 173.

[0208] In the top-emitting structure, the second electrode 173 can be made of a transparent conductive material (TCO) that is transparent to light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode 173 is made of a semi-transparent conductive material, the light output efficiency can be improved through the microcavity.

[0209] The encapsulation layer TFE can be formed on the light-emitting element layer. The encapsulation layer TFE may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer. For example, the encapsulation layer TFE may include at least one organic layer to protect the light-emitting element layer from foreign matter such as dust.

[0210] Instead of the TFE encapsulation layer, the second substrate can be disposed on the light-emitting element layer, and the space between the light-emitting element layer and the second substrate can be empty, such as a vacuum, or a filling film can be disposed in the space. The filling film can be an epoxy resin filling film or a silicone resin filling film.

[0211] refer to Figure 8 The third connection line CL3 can overlap with the second active layer ACT2 and the second gate electrode G2 of the second transistor ST2 in the thickness direction, and the fourth connection line CL4 can overlap with the fifth active layer ACT5 and the fifth gate electrode G5 of the fifth transistor ST5 in the thickness direction.

[0212] refer to Figure 9 The second connection line CL2 can overlap with the sixth active layer ACT6 and the sixth gate electrode G6 of the sixth transistor ST6 in the thickness direction.

[0213] refer to Figure 10The first curved organic layer PO1 can be disposed on the barrier layer BR in the curved region outside the pixel. The first curved organic layer PO1 may include a first-1 organic layer VIA0 and a first-2 organic layer VIA1 disposed on the first-1 organic layer VIA0. The first-1 organic layer VIA0 can be disposed on the barrier layer BR and penetrate the second interlayer insulating film 142, the initialization voltage line VIL, the first interlayer insulating film 141, the gate insulating layer 130, and the buffer layer BF.

[0214] For example, in the outer bending region of a pixel, the initialization voltage line VIL can be disconnected by the first-first organic layer VIA0. For example, in the outer bending region of a pixel, the second interlayer insulating film 142, the initialization voltage line VIL, the first interlayer insulating film 141, the gate insulating layer 130, and the buffer layer BF can be penetrated by the first-first organic layer VIA0. The first-first organic layer VIA0 can contact (e.g., directly contact) the upper surface of the barrier layer BR.

[0215] The first connection line CL1 can be disposed on the first-1 organic layer VIA0. The first connection line CL1 can be electrically connected to the initialization voltage line VIL below the first connection line CL1 through the contact holes CNT9 and CNT10 penetrating the second interlayer insulating film 142. For example, the first connection line CL1 can be electrically connected to the initialization voltage line VIL that is disconnected by the first-1 organic layer VIA0 in the outer curved region of the pixel.

[0216] In the curved region outside the pixel, the first and second organic layers VIA1 can be disposed on the first connecting line CL1. The first and second organic layers VIA1 can penetrate the third interlayer insulating film 143 in the thickness direction.

[0217] The protective layer 150 can be further arranged on the first and second organic layers VIA1.

[0218] refer to Figure 11 The first organic layer VIA0 can be disposed on the barrier layer BR and can penetrate the second interlayer insulating film 142, the first interlayer insulating film 141, the p-1 scan line Sp-1, the gate insulating layer 130 and the buffer layer BF.

[0219] For example, in the outer curved region of a pixel, the p-1th scan line Sp-1 can be disconnected by the first-1 organic layer VIA0. For example, in the outer curved region of a pixel, the second interlayer insulating film 142, the p-1th scan line Sp-1, the first interlayer insulating film 141, the gate insulating layer 130, and the buffer layer BF can be penetrated by the first-1 organic layer VIA0. The first-1 organic layer VIA0 can contact (e.g., directly contact) the upper surface of the barrier layer BR.

[0220] The second connecting line CL2 can be disposed on the first-1 organic layer VIA0. The second connecting line CL2 can be electrically connected to the p-1 scan line Sp-1 below the second connecting line CL2 through contact holes CNT11 and CNT12 that penetrate the second interlayer insulating film 142 and the first interlayer insulating film 141. For example, the second connecting line CL2 can be used to electrically connect the p-1 scan line Sp-1 that is disconnected by the first-1 organic layer VIA0 in the curved region outside the pixel.

[0221] In the curved region outside the pixel, the first and second organic layers VIA1 can be disposed on the second connecting line CL2. The first and second organic layers VIA1 can penetrate the third interlayer insulating film 143 in the thickness direction.

[0222] The protective layer 150 can be further arranged on the first and second organic layers VIA1.

[0223] refer to Figure 12 The first organic layer VIA0 can be disposed on the barrier layer BR and can penetrate the second interlayer insulating film 142, the first interlayer insulating film 141, the p-th scan line Sp, the gate insulating layer 130 and the buffer layer BF.

[0224] For example, in the outward bending region of a pixel, the p-th scan line Sp can be disconnected by the first-first organic layer VIA0. In the outward bending region of a pixel, the second interlayer insulating film 142, the p-th scan line Sp, the first interlayer insulating film 141, the gate insulating layer 130, and the buffer layer BF can be penetrated by the first-first organic layer VIA0. The first-first organic layer VIA0 can contact (e.g., directly contact) the upper surface of the barrier layer BR.

[0225] The third connection line CL3 can be disposed on the first-1 organic layer VIA0. The third connection line CL3 can be electrically connected to the p-th scan line Sp below the third connection line CL3 through contact holes CNT13 and CNT14 that penetrate the second interlayer insulating film 142 and the first interlayer insulating film 141. For example, the third connection line CL3 can be used to electrically connect the p-th scan line Sp that is disconnected by the first-1 organic layer VIA0 in the curved region outside the pixel.

[0226] In the curved region outside the pixel, the first and second organic layers VIA1 can be disposed on the third connecting line CL3. The first and second organic layers VIA1 can penetrate the third interlayer insulating film 143 in the thickness direction.

[0227] The protective layer 150 can be arranged on the first and second organic layers VIA1.

[0228] refer to Figure 13The first organic layer VIA0 can be disposed on the barrier layer BR and can penetrate the second interlayer insulating film 142, the first interlayer insulating film 141, the p-th emitter line Ep, the gate insulating layer 130 and the buffer layer BF.

[0229] For example, in the outer bending region of the pixel, the p-th emitter line Ep can be disconnected by the first-first organic layer VIA0. In the outer bending region of the pixel, the second interlayer insulating film 142, the p-th emitter line Ep, the first interlayer insulating film 141, the gate insulating layer 130, and the buffer layer BF can be penetrated by the first-first organic layer VIA0. The first-first organic layer VIA0 can contact (e.g., directly contact) the upper surface of the barrier layer BR.

[0230] The fourth connection line CL4 can be disposed on the first-first organic layer VIA0. The fourth connection line CL4 can be electrically connected to the p-th emitter line Ep below the fourth connection line CL4 through contact holes CNT15 and CNT16 that penetrate the second interlayer insulating film 142 and the first interlayer insulating film 141. For example, the p-th emitter line Ep, which is disconnected by the first-first organic layer VIA0 in the outer curved region of the pixel, can be electrically connected by the fourth connection line CL4.

[0231] In the curved region outside the pixel, the first and second organic layers VIA1 can be disposed on the fourth connecting line CL4. The first and second organic layers VIA1 can penetrate the third interlayer insulating film 143 in the thickness direction.

[0232] The protective layer 150 can be further arranged on the first and second organic layers VIA1.

[0233] refer to Figure 14 The first organic layer VIA0 can be disposed on the barrier layer BR and can penetrate the second interlayer insulating film 142, the first interlayer insulating film 141, the gate insulating layer 130, the first electrode S1-1 of the semiconductor layer of the first transistor ST1-1, and the buffer layer BF.

[0234] For example, in the curved region within a pixel, the first electrode S1-1 of the semiconductor layer of the first-1 transistor ST1-1 can be disconnected by the first-1 organic layer VIA0. In the curved region within a pixel, the second interlayer insulating film 142, the first interlayer insulating film 141, the gate insulating layer 130, the first electrode S1-1 of the semiconductor layer of the first-1 transistor ST1-1, and the buffer layer BF can be penetrated by the first-1 organic layer VIA0. The first-1 organic layer VIA0 can contact (e.g., directly contact) the upper surface of the barrier layer BR.

[0235] The fifth connection line CL5 can be disposed on the first organic layer VIA0. The fifth connection line CL5 can be electrically connected to the first electrode S1-1 of the semiconductor layer of the first transistor ST1-1 below the fifth connection line CL5 through contact holes CNT17 and CNT18 that penetrate the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating layer 130. For example, the fifth connection line CL5 can be used to electrically connect to the first electrode S1-1 of the semiconductor layer of the first transistor ST1-1, which is disconnected by the first organic layer VIA0 in a curved region within the pixel.

[0236] In the curved region within a pixel, the first and second organic layers VIA1 can be disposed on the fifth connecting line CL5. The first and second organic layers VIA1 can penetrate the third interlayer insulating film 143 in the thickness direction.

[0237] The protective layer 150 can be further arranged on the first and second organic layers VIA1.

[0238] The display device according to the embodiments will now be described. In the following embodiments, the same elements as those in the above embodiments will be indicated by the same reference numerals, and redundant descriptions will be omitted or given briefly.

[0239] Figures 15 to 19 This is a schematic cross-sectional view of the display panel according to an embodiment.

[0240] refer to Figures 15 to 19 The display panel according to the embodiment and according to Figures 8 to 14 The difference in the embodiment of the display panel 300 may be that: the first organic layer VIA0_1 further penetrates the barrier layer BR to contact the surface of the first substrate SUB1.

[0241] Other elements and features are the same as those described above, and therefore their redundant descriptions are omitted.

[0242] Figure 20 This is a schematic plan view of the display panel according to an embodiment.

[0243] refer to Figure 20 The display panel according to this embodiment and the display panel according to Figure 5 The difference in the display panel 300 of the embodiment may be that the display area DA_1 may include a first sub-pixel SP11, each of which includes an in-pixel curved area, and a third sub-pixel SP2, which does not include an in-pixel curved area.

[0244] For example, the display area DA_1 of the display panel according to this embodiment may include a first sub-pixel SP11, each of which includes an in-pixel curved region, and a third sub-pixel SP2, which does not include an in-pixel curved region.

[0245] like Figure 20 As shown in the figure, the first sub-pixel SP11 and the third sub-pixel SP2 can be arranged alternately along the first direction (X-axis direction).

[0246] Figure 21 This is a schematic plan view of the display panel according to an embodiment.

[0247] refer to Figure 21 The display panel according to this embodiment and the display panel according to Figure 5 The difference in the embodiment of the display panel 300 may be that the display area DA_2 may include a first sub-pixel SP11, a second sub-pixel SP12, and a third sub-pixel SP2 that does not include an in-pixel curved region, each of the first sub-pixel SP11 and the second sub-pixel SP12 including an in-pixel curved region.

[0248] For example, the display area DA_2 of the display panel according to this embodiment may include a first sub-pixel SP11 and a second sub-pixel SP12, each of which includes an in-pixel curved region, and a third sub-pixel SP2 that does not include an in-pixel curved region.

[0249] like Figure 21 As illustrated, the first sub-pixel SP11 and the third sub-pixel SP2 can be arranged alternately along the second direction (Y-axis direction). The first sub-pixel SP11 and the second sub-pixel SP12 can be adjacent to each other in the X-axis direction, and the first sub-pixel SP11 and the second sub-pixel SP12 can alternate in the X-axis direction and alternate with the third sub-pixel SP2 in the Y-axis direction.

[0250] Figure 22 This is a perspective view of the display device 10_1 according to an embodiment. Figure 23 It is along Figure 22 A schematic cross-sectional view taken from line II-II'. Figure 24 It is a display panel according to an embodiment (e.g., Figure 22 and Figure 23 A schematic plan view of the display panel 300_1 of the display device 10_1 in the image.

[0251] refer to Figures 22 to 24The display device 10_1 according to the embodiment may be a display device. As used herein, the term "foldable" may refer to a flexible state, and for example, may refer to something that is bendable, rollable, etc. Further, the term "foldable" may be interpreted as "partially foldable," "fully foldable," "foldable inward," and / or "foldable outward." The display device 10_1 may include a folding axis AXIS_F, which intersects the upper and lower sides of the display device 10_1 in a plan view. The display device 10_1 may be folded about the folding axis AXIS_F.

[0252] The display device 10_1 may be generally rectangular in plan view. The display device 10_1 may have a rectangular planar shape with right angles or a rectangular planar shape with rounded corners. The display device 10_1 may include four edges LS1, LS2, SS1, and SS2. The display device 10_1 may include long edges LS1 and LS2 and short edges SS1 and SS2. For example, the long edges LS1 and LS2 may extend in a first direction (X-axis direction), while the short edges SS1 and SS2 may extend in a second direction (Y-axis direction). Figure 22 The first direction (X-axis direction) that is defined in the middle can be Figure 1 The Y-axis direction, and the second direction (Y-axis direction) can be Figure 1 The X-axis direction.

[0253] like Figure 22 As illustrated, the folding axis AXIS_F can extend in a direction intersecting the long edges LS1 and LS2 (e.g., in a second direction (Y-axis direction)). For example, the long edges LS1 and LS2 of the display device 10_1 can be folded. Alternatively, the folding axis AXIS_F can intersect the short edges SS1 and SS2. In this case, the short edges SS1 and SS2 of the display device 10_1 can be folded. For ease of description, the case where the folding axis AXIS_F intersects the long edges LS1 and LS2 will be described below. The folding axis AXIS_F can intersect the middle portion of each of the long edges LS1 and LS2, but the embodiment is not limited to this.

[0254] Display device 10_1 may include a display area DA and a non-display area NDA arranged around the display area DA. The display area DA may be an area of ​​the display screen, and the non-display area NDA may be an area where no screen is displayed. The display area DA may be located in the central portion of the display device 10_1. When the display device 10_1 is folded, the portions of the display area DA separated by the folding axis AXIS_F may overlap each other. When the display device 10_1 is unfolded, a portion of the display area DA may be unfolded to display the screen.

[0255] In each adjacent region of the first long edge LS1 and the second long edge LS2 intersecting the folding axis AXIS_F of the display device 10_1, a recess (e.g., a notch) that is recessed upward or downward in the plan view can be formed, and a hinge member (not shown) for state change can be coupled to the recess. However, the embodiments are not limited thereto.

[0256] refer to Figure 23 The display device 10_1 can be divided into a folded region FR and non-folded regions NFR1 and NFR2 by the folding axis AXIS_F.

[0257] For example, the display device 10_1 may include a folded region FR and non-folded regions NFR1 and NFR2. The folded region FR is arranged in the central portion and includes a folding axis AXIS_F. The non-folded regions NFR1 and NFR2 are spaced apart from each other, and the folded region FR is located between the non-folded regions NFR1 and NFR2.

[0258] The folded region FR can be the area of ​​the display device 10_1 that is folded or bent with a predetermined curvature in the folding direction, and the non-folded regions NFR1 and NFR2 can be the areas of the display device 10_1 that are not folded, unlike the folded region FR. The non-folded regions NFR1 and NFR2 can be located or arranged in a flat surface forming the same plane, respectively. However, the embodiment is not limited to this, and the non-folded regions NFR1 and NFR2 can also be partially bent.

[0259] Display device 10_1 may include, for example, Figure 23 The stacked components are illustrated in the figure. The display device 10_1 may include a display panel 300_1, a lower functional component BUM disposed below the display panel 300_1, an upper functional component UUM disposed above the display panel 300_1, and a cover window 100 disposed above the upper functional component UUM.

[0260] The lower functional component (BUM) can be arranged below the display panel 300_1. The lower functional component BUM can include at least one functional layer. This functional layer can perform functions such as buffering, heat dissipation, electromagnetic wave shielding, grounding, strength enhancement, support, pressure sensing, and digitization. The lower functional component BUM can be a single layer. However, the lower functional component BUM is not limited to a single layer and can also include a stack of different functional layers.

[0261] For example, the lower functional member (BUM) may include a cushioning member. The cushioning member can prevent impact forces applied from the outside (e.g., from below the lower functional member (BUM)) from being transmitted to the display panel 300_1. The cushioning member may be made of a foam material such as polyurethane (PU), thermoplastic polyurethane (TPU), silicone (Si), or polydimethylacrylamide (PDMA).

[0262] The lower functional component (BUM) can have a lower light transmittance than the components arranged on the display panel 300_1, which will be described later. For example, the layer arranged on the display panel 300_1 can have a relatively high light transmittance to transmit light emitted upward from the display area of ​​the display panel 300_1. On the other hand, the lower functional component (BUM) can have a relatively low light transmittance to block light emitted downward from the display area of ​​the display panel 300_1.

[0263] Display panel 300_1 can be placed on the lower functional component BUM.

[0264] Display panel 300_1 can be used with the above... Figure 2 The display panel 300 described herein is essentially the same, and therefore its redundant description is omitted.

[0265] The upper functional component UUM can be arranged on the display panel 300_1.

[0266] The upper functional component UUM may include at least one functional layer. The functional layer may be a layer that performs touch sensing functions, color filtering functions, color conversion functions, polarization functions, anti-reflection functions, biometric identification functions (such as fingerprint recognition), etc. For example, the upper functional component UUM may include an anti-reflection component. The functional layer may be a sheet made of a sheet, a film made of a film, a thin film layer, a coating, a panel, a plate, etc. The upper functional component UUM may be a single functional layer. However, the upper functional component UUM is not limited to a single layer and may also include a stack of different functional layers.

[0267] Cover window 100 can be placed on the upper functional component UUM.

[0268] Display device 10_1 may include adhesive layers 901, 911, and 921 disposed between components 100, UUM, 300_1, and BUM to bond these components together. A first adhesive layer 901 may be disposed between the lower functional component BUM and the display panel 300_1 to bond them together, a second adhesive layer 911 may be disposed between the display panel 300_1 and the upper functional component UUM to bond them together, and a third adhesive layer 921 may be disposed between the upper functional component UUM and the cover window 100 to bond them together.

[0269] Adhesive layers 901, 911, and 921 may be layers with adhesive properties on their upper and lower surfaces, and may be, for example, pressure-sensitive adhesives (PSA), optically clear adhesives (OCA), or optically clear resins (OCR). Adhesive layers 901, 911, and 921 may comprise acrylic resins or silicone resins. Additionally, adhesive layers 901, 911, and 921 may have an elongation in the range of about 100% to about 1000%.

[0270] Display device 10_1 may include support plates 501 and 502 and a fourth adhesive layer 931. Support plates 501 and 502 can prevent the display panel 300_1 from bending due to external forces, or can reduce the degree of bending of the display panel 300_1 (e.g., bending angle or bending radius of curvature). For example, support plates 501 and 502 can resist external forces to keep the display panel 300_1 relatively flat.

[0271] Support plates 501 and 502 may comprise rigid or semi-rigid materials. For example, support plates 501 and 502 may comprise metallic materials such as stainless steel (SUS) or aluminum, or polymers such as polymethyl methacrylate (PMMA), polycarbonate (PC), polyvinyl alcohol (PVA), acrylonitrile-butadiene-styrene (ABS), or polyethylene terephthalate (PET). For example, support plates 501 and 502 may be stainless steel layers having a thickness in the range of approximately 150 μm to approximately 200 μm. As another example, support plates 501 and 502 may be aluminum layers having a thickness in the range of approximately 150 μm to approximately 200 μm.

[0272] In some embodiments, support plates 501 and 502 may include a first support plate 501 and a second support plate 502 spaced apart from each other. The first support plate 501 may overlap with a portion of the non-folded region NFR1 and the folded region FR. The second support plate 502 may overlap with a portion of the non-folded region NFR2 and the folded region FR. The first support plate 501 and the second support plate 502 may be spaced apart from each other by a distance D based on the folding axis AXIS_F. The distance D may be, for example, approximately 50 μm or less.

[0273] The fourth adhesive layer 931 can bond support plates 501 and 502 to the lower functional member BUM in the non-folded regions NFR1 and NFR2, and can bond an anti-adhesion pattern (not shown) to the lower functional member BUM in the folded region FR. The fourth adhesive layer 931 may comprise the same material as adhesive layers 901, 911, and 921. The fourth adhesive layer 931 may be, but is not limited to, PSA.

[0274] refer to Figure 24 Pixel SP (see) Figure 5The pixel SP, the outer curved region of the pixel, and the inner curved region of the pixel can be arranged in the display area DA of the display device 10_1 according to the embodiment. Figure 5 Those are the same, and therefore, redundant descriptions are omitted.

[0275] Figure 25 This is a schematic plan view of the display panel of a display device according to an embodiment. Figure 26 yes Figure 25 A magnified view of region B. Figure 27 yes Figure 25 A magnified view of region C.

[0276] refer to Figures 25 to 27 According to the embodiment, the display area DA_3 and Figure 24 The difference between the display area DA of the display device 10_1 and the display device 10_1 can be found in the following: Figure 20 The first sub-pixel SP11 described herein can be arranged in the folded region FR, and above it... Figure 20 The third sub-pixel SP2 described herein can be arranged in the non-folded regions NFR1 and NFR2.

[0277] Other components and features are the same as those mentioned above. Figure 20 and Figure 24 The components and features described are the same, and therefore redundant descriptions are omitted.

[0278] In the display device according to the embodiment, breakage caused by the inorganic layer in the pixel can be prevented.

[0279] However, the effects of the embodiments are not limited to those described herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon which the embodiments pertain by referring to the claims.

[0280] While this disclosure has been shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. The embodiments should be considered only in a descriptive sense and not for limiting purposes.

Claims

1. A display device having a display area and a non-display area arranged around the display area, the display device comprising: pixels arranged in the display area, each pixel including a plurality of sub-pixels; an in-pixel curved region arranged along a direction of the pixels and curving in a plan view through a first sub-pixel of the plurality of sub-pixels, the first sub-pixel including a first transistor including a first semiconductor layer; a first substrate; a barrier layer arranged on the first substrate; a buffer layer arranged on the barrier layer, the first semiconductor layer being arranged on the buffer layer; an insulating layer arranged on the first semiconductor layer; and a first curved organic layer, wherein the first curved organic layer penetrates the insulating layer and the first semiconductor layer in the in-pixel curved region such that the first semiconductor layer is broken in the in-pixel curved region.

2. The display device according to claim 1, further comprising: an out-pixel curved region arranged around each of the pixels.

3. The display device according to claim 1, further comprising: a scan line passing through the pixels, wherein the in-pixel curved region extends in the same direction as the scan line.

4. The display device according to claim 3, wherein each of the sub-pixels includes a first transistor and a third transistor, and in a plan view, the in-pixel curved region is arranged between the first transistor and the third transistor.

5. The display device according to claim 4, wherein the first transistor includes a first gate electrode of the scan line.

6. The display device according to claim 5, wherein the first semiconductor layer includes: a first active layer; a first electrode arranged on one side of the first active layer; and a second electrode arranged on the other side of the first active layer, wherein the second electrode is broken in the in-pixel curved region.

7. The display device according to claim 1, wherein the first curved organic layer further penetrates the buffer layer and is arranged on a surface of the barrier layer.

8. The display device according to claim 7, wherein the first curved organic layer further penetrates the barrier layer and is arranged on a surface of the first substrate.

9. The display device according to claim 3, wherein the in-pixel curved region further includes an in-pixel connection line arranged on the first curved organic layer, and the in-pixel connection line electrically connects the broken first semiconductor layer.

10. The display device according to claim 9, wherein the in-pixel connection line and the scan line include different materials.

11. The display device according to claim 10, wherein the in-pixel connection line includes aluminum, and the scan line includes molybdenum.

12. The display device according to claim 9, wherein the in-pixel connection line extends in a direction intersecting an extending direction of the in-pixel curved region.

13. The display device according to claim 2, wherein the out-pixel curved region is arranged between adjacent pixels.

14. The display device according to claim 13, further comprising: ​ ​ a scan line passing through the pixel, wherein the scan line is broken in the out-pixel bending area.

15. The display device of claim 14, further comprising: a second bending organic layer, wherein the second bending organic layer penetrates the insulating layer and the scan line in the out-pixel bending area.

16. The display device of claim 15, further comprising an out-pixel connection line extending in the same direction as the scan line, wherein the out-pixel connection line is disposed on the second bending organic layer.

17. The display device of claim 16, wherein the out-pixel connection line electrically connects the broken scan line.

18. The display device of claim 1, wherein the display device is foldable along a folding axis, and when the display device is folded along the folding axis, the portions of the display area separated by the folding axis overlap each other.

19. A display device, comprising: a first substrate; a barrier layer disposed on the first substrate; a buffer layer disposed on the barrier layer; a semiconductor layer disposed on the buffer layer; a scan line disposed on the semiconductor layer; an insulating layer disposed on the scan line; a bending organic layer penetrating the insulating layer and the scan line; and an out-pixel connection line disposed on the bending organic layer, wherein the scan line is broken by the bending organic layer, and the out-pixel connection line electrically connects the scan line broken by the bending organic layer.

20. The display device of claim 19, wherein the scan line and the out-pixel connection line comprise different materials.

21. The display device of claim 20, wherein the out-pixel connection line comprises aluminum, and the scan line comprises molybdenum. ​

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