Methods for forming all-to-the-ring gate field-effect transistors and semiconductor devices

Abstract

In a method for forming a full-all-around gate field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures, each stacked structure including a dielectric layer, a CNT located above the dielectric layer, and a support layer located above the CNT. A sacrificial gate structure is formed above the fin structure, an isolation insulating layer is formed, a source / drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source / drain opening, and a source / drain contact layer is formed in the source / drain opening. A source / drain contact is formed so that the source / drain contact is in direct contact only with a portion of the CNT, and a portion of the dielectric layer is disposed between the source / drain contact and the CNT. Embodiments of the present invention also relate to a semiconductor device having a full-all-around gate field effect transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to methods of forming a gate-all-around field effect transistor and semiconductor devices. Background Art

[0002] As the semiconductor industry enters nanotechnology process nodes in pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs (such as GAA structures). Non-Si-based low-dimensional materials are promising candidates for providing better electrostatics (e.g., for short channel effects) and higher performance (e.g., less surface scattering). Carbon nanotubes (CNTs) are considered to be a promising candidate due to their high carrier mobility and essentially one-dimensional structure. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming a gate-all-around field effect transistor (GAA FET), the method comprising: forming a fin structure, the fin structure comprising a plurality of stacked structures, each stacked structure comprising a dielectric layer, a carbon nanotube located above the dielectric layer, and a support layer located above the carbon nanotube; forming a sacrificial gate structure above the fin structure; forming an isolation insulating layer; forming a source / drain opening by patterning the isolation insulating layer; removing the support layer from each of the plurality of stacked structures in the source / drain opening; and forming a source / drain contact layer in the source / drain opening, wherein a source / drain contact is formed so that the source / drain contact is in direct contact only with a portion of the carbon nanotube, and a portion of the dielectric layer is disposed between the source / drain contact and the carbon nanotube.

[0004] Another embodiment of the present invention provides a method for forming a gate-all-around field effect transistor (GAA FET), the method comprising: forming a fin structure above a substrate, wherein a carbon nanotube (CNT) is embedded in a supporting material; forming a sacrificial gate structure above the fin structure; forming an insulating layer above the sacrificial gate structure and the fin structure; removing the sacrificial gate structure so that a portion of the fin structure is exposed; removing the supporting material from the exposed portion of the fin structure so that a channel region of the carbon nanotube is exposed; forming a gate structure around the exposed channel region of the carbon nanotube; forming a source / drain opening in the insulating layer; removing the source / drain opening The invention relates to a method for producing a carbon nanotube having a plurality of carbon nanotubes and a plurality of carbon nanotubes. The method comprises: forming a dielectric layer around the exposed carbon nanotubes in the source / drain openings, partially removing the dielectric layer, so that a portion of the dielectric layer remains on the carbon nanotubes in the source / drain openings; and forming a source / drain contact layer in the source / drain openings, wherein a source / drain contact is formed so that the source / drain contact is in direct contact with a portion of the carbon nanotubes and a remaining portion of the dielectric layer is disposed between the source / drain contact and the carbon nanotubes.

[0005] Another embodiment of the present invention provides a semiconductor device with a full-ring gate field effect transistor, comprising: a carbon nanotube (CNT) disposed above a substrate; a gate structure formed around the carbon nanotube in a channel region; and a source / drain contact formed around the carbon nanotube in a source / drain region, wherein: the source / drain contact is in direct contact with only a portion of the carbon nanotube, and the dielectric layer partially covers the carbon nanotube and is disposed between the source / drain contact and the carbon nanotube. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A schematic diagram of a GAA FET using carbon nanotubes (CNTs) according to an embodiment of the present invention is shown.

[0008] Figure 1B , Figure 1C and Figure 1D An embedded doping scheme according to an embodiment of the present invention is shown.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D Various embedded doping structures in the source / drain regions of a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0010] Figure 3A , Figure 3B , Figure 3C and Figure 3D Various embedded doping structures in the source / drain regions of a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D Various embedded doping structures in the source / drain regions of a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D Various embedded doping structures in the source / drain regions of a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0013] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F Various stages of a sequential fabrication process of a GAAFET using CNTs according to an embodiment of the present invention are shown.

[0014] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0015] Fig. 8A and Figure 8B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0016] Fig.9A and Fig. 9B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0017] Fig. 10A and Fig. 10BOne of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0018] Fig.11A and Fig. 11B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0019] Fig. 12A and Fig. 12B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0020] Fig.13A , Fig. 13B and Fig. 13C One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0021] Fig.14A and Fig. 14B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0022] Fig.15A and Fig. 15B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0023] Fig.16A , Fig. 16B and Fig. 16C One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0024] Fig.17A and Fig. 17B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0025] Fig.18A and Fig.18B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0026] Fig.19A , Fig.19B and Fig.19C Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0027] Fig.19D , Fig.19E and Fig.19F Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0028] Figure 19G , Fig.19H and Fig.19I Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0029] Fig. 20A and Fig. 20B A cross-sectional view of a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0030] Fig.21A , Fig.21B , Fig. 21C and Fig.21D Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0031] Fig.22A , Fig. 22B and Fig. 22C One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0032] Fig.23 One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0033] Fig.24A and Fig. 24B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0034] Fig.25A and Fig.25B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0035] Fig.26A and Fig.26B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0036] Fig.27A and Fig.27B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0037] Fig.28A and Fig.28BOne of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0038] Fig.29A , Fig.29B and Fig.29C One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0039] Fig. 30A and Fig. 30B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0040] Fig.31 One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0041] Fig.32A , Fig.32B , Fig.32C and Fig.32D Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0042] Fig.33A , Fig.33B , Fig.33C and Fig.33D Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0043] Fig.34A , Fig.34B , Fig.34C and Fig.34D Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0044] Fig.35A , Fig.35B and Fig.35C Various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention are shown.

[0045] Fig.36A and Fig.36B A planar FET using CNTs according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0046] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or desired properties of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For the purpose of simplicity and clarity, the various components may be arbitrarily drawn in different proportions. In the accompanying drawings, some layers / components are omitted for simplicity.

[0047] In addition, for ease of description, spacing relationship terms such as "below...", "below...", "lower part", "above...", "upper part", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the figure. In addition to the orientation shown in the figure, the spacing relationship terms are intended to include different orientations of the device in use or operation process. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. In addition, the term "made of..." can mean "including" or "consisting of...". In addition, in the following manufacturing process, there may be one or more additional operations in / between the described operations, and the order of operations may be changed. In the present invention, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C or A, B and C), unless otherwise specified, it does not mean one element from A, one element from B and one element from C. The same or similar materials, configurations, dimensions, processes, and / or operations as those described in one embodiment may be used in other embodiments, and detailed explanations may be omitted.

[0048] Due to their cylindrical geometry, excellent electrical and mechanical properties, carbon nanotubes (CNTs) with diameters in the nm range (e.g., about 1 nm) are considered to be the material of choice for making proportional FET devices. Field effect transistors (FETs) using CNTs with gate lengths of about 10 nm or less show excellent electrical properties. However, a manufacturing technology compatible with CMOS manufacturing technology has not yet been established. In the present invention, a lateral full-ring gate process flow compatible with CMOS technology is provided by stacking aligned layers of CNTs on a substrate and forming a fin structure by stacking CNTs.

[0049] In some embodiments, a semiconductor device includes a novel structure of a field effect transistor including stacked all-around gate (GAA) carbon nanotubes (CNTs). The semiconductor device includes an array of aligned CNTs, with a gate dielectric layer and a gate electrode layer wrapped around the CNTs. GAA FETs with CNTs can be applied to logic circuits in advanced technology nodes. However, it is often challenging to control the doping profile in CNTs. Typically, it is desirable to have an undoped channel region of a GAA FET with doped source / drain extension regions and source / drain contact regions.

[0050] In the present invention, electrostatic doping techniques are employed in the source / drain regions to induce charges in the semiconducting CNTs by placing one or more dielectric layers (embedded doping scheme) to provide more carriers in the CNTs and reduce contact resistance.

[0051] Figure 1A A schematic diagram of a GAA FET using carbon nanotubes (CNTs) according to an embodiment of the present invention is shown.

[0052] like Figure 1A As shown, a gate dielectric layer 102 is disposed around the CNT 100, and a gate electrode 105 is disposed on the gate dielectric layer 102, thereby forming a GAA structure. In the source / drain region, a source / drain contact 70 made of a conductive material is also disposed around the CNT 100. In some embodiments, the dielectric layer 200 partially covers the source / drain region of the CNT 100, so that the source / drain contact 70 is in direct contact with only a portion of the CNT 100, and the dielectric layer 200 is disposed between the source / drain contact 70 and the CNT 100.

[0053] Figures 1B to 1D An embedded doping scheme according to an embodiment of the present invention is shown. Figures 1B to 1D is corresponding to Figure 1A For the purpose of illustration, Figures 1B to 1D In the embodiment shown in FIG. 1 , the dielectric layer 200 completely covers the CNTs 100. However, in the following embodiment, the dielectric layer 200 only partially covers the CNTs 100 below the source / drain contacts.

[0054] exist Figure 1B In some embodiments, the dielectric layer 200 is a non-stoichiometric silicon nitride (e.g., SiN x). Since the dielectric layer 200 has a positive fixed charge, negative mobile charges are induced in the CNT 100 for the n-type FET. In some embodiments, the thickness of the dielectric layer 200 is in the range of about 1 nm to about 10 nm. In other embodiments, the dielectric layer 200 carries a negative fixed charge, which induces positive mobile charges in the CNT 100 for the p-type FET. The dielectric layer 200 carrying the negative fixed charge includes MoO3 or NiO2.

[0055] exist Figure 1C In the embodiment, the dielectric layer 200 includes a first dielectric layer 210 in contact with the CNT 100 and a second dielectric layer 220 located above the first dielectric layer 210. In some embodiments, the second dielectric layer 220 has a negative interface charge inside, and the first dielectric layer 210 has a positive interface charge inside. The dielectric dipole structure at the interface between the first dielectric layer and the second dielectric layer induces negative mobile charges in the CNT 100 for n-type FET. In some embodiments, the second dielectric layer 220 is made of hafnium oxide (HfO2), and the first dielectric layer is made of aluminum oxide (Al2O3) or aluminum oxynitride (AlO x N y ). In other embodiments, the first dielectric layer 210 is silicon oxide (SiO2), and the second dielectric layer 220 is one of Y2O3 and La2O3. In some embodiments, the thickness of the first dielectric layer and the second dielectric layer 200 is in the range of about 1nm to about 10nm. In some embodiments, the dielectric layer 200 includes a first dielectric layer in contact with the CNT, a second dielectric layer disposed above the first dielectric layer, and a third dielectric layer disposed above the second dielectric layer, which form a dielectric dipole structure at the interface between the first and second dielectric layers that induce positive charges in the CNT. In some embodiments, the first dielectric layer is made of aluminum oxide, the second dielectric layer is made of silicon oxide, and the third dielectric layer is made of aluminum oxide. The first and third dielectric layers include other oxides, such as scandium oxide, erbium oxide, molybdenum oxide, and nickel oxide.

[0056] exist Figure 1D In the embodiment, the dielectric layer 200 includes a third dielectric layer 230 in contact with the CNT 100 and a fourth dielectric layer 240 located above the third dielectric layer 230. In some embodiments, the fourth dielectric layer 240 has a positive charge inside, and the third dielectric layer 230 has a negative charge inside. The dielectric dipole structure at the interface between the first and second dielectric layers induces positive mobile charges in the CNT 100 for a p-type FET. In some embodiments, the third dielectric layer 230 is silicon oxide (SiO2), and the fourth dielectric layer 240 is one of Al2O3 and HfO2. In other embodiments, the third dielectric layer 230 is aluminum oxynitride (AlO x N y), and the fourth dielectric layer is aluminum oxide (Al2O3). In some embodiments, the thickness of the third dielectric layer and the fourth dielectric layer 200 is in the range of about 1 nm to about 10 nm.

[0057] FIG. 2A to FIG. 2D Various embedded doping structures in the source / drain region of a GAA FET using CNTs according to an embodiment of the present invention are shown. FIG. 2A to FIG. 2D As shown, a single layer of dielectric layer 200 partially covers CNT 100 below source / drain contact 70, and source / drain contact 70 further covers dielectric layer 200. Figure 2A In FIG. 1 , the left and right portions of the CNT 100 are covered by the dielectric layer 200, while the top and bottom of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 2B In FIG. 1 , the top and bottom of the CNT 100 are covered by the dielectric layer 200, while the left and right portions of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 2C In FIG. 1 , the top of CNT 100 is in direct contact with source / drain contact 70 and the rest of CNT 100 is covered by dielectric layer 200. Figure 2D In the embodiment of the present invention, the bottom of the CNT 100 is in direct contact with the source / drain contact 70 , and the remaining portion of the CNT 100 is covered by the dielectric layer 200 .

[0058] FIG. 3A to FIG. 3D Various embedded doping structures in the source / drain region of a GAA FET using CNTs according to an embodiment of the present invention are shown. FIG. 3A to FIG. 3D As shown, a single layer of dielectric layer 200 partially covers CNT 100 below source / drain contact 70, and source / drain contact 70 does not cover dielectric layer 200. Figure 3A In FIG. 1 , the left and right portions of the CNT 100 are covered by the dielectric layer 200, while the top and bottom of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 3B In FIG. 1 , the top and bottom of the CNT 100 are covered by the dielectric layer 200, while the left and right portions of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 3C In FIG. 1 , the top of CNT 100 is in direct contact with source / drain contact 70 and the rest of CNT 100 is covered by dielectric layer 200. Figure 3D In the embodiment of the present invention, the bottom of the CNT 100 is in direct contact with the source / drain contact 70 , and the remaining portion of the CNT 100 is covered by the dielectric layer 200 .

[0059] FIG. 4A to FIG. 4DVarious embedded doping structures in the source / drain region of a GAA FET using CNTs according to an embodiment of the present invention are shown. FIG. 4A to FIG. 4D As shown, the first and second dielectric layers 210 and 220 (or Figure 1D The double layer of dielectric layer 200 (third and fourth dielectric layers 230 and 240) partially covers the CNT 100 below the source / drain contact 70, and the source / drain contact 70 further covers the double layer of dielectric layer 200. Figure 4A In FIG. 1 , the left and right portions of the CNT 100 are covered by the dielectric layer 200, while the top and bottom of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 4B In FIG. 1 , the top and bottom of the CNT 100 are covered by the dielectric layer 200, while the left and right portions of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 4C In FIG. 1 , the top of CNT 100 is in direct contact with source / drain contact 70 and the rest of CNT 100 is covered by dielectric layer 200. Figure 4D In the embodiment of the present invention, the bottom of the CNT 100 is in direct contact with the source / drain contact 70 , and the remaining portion of the CNT 100 is covered by the dielectric layer 200 .

[0060] FIG. 5A to FIG. 5D Various embedded doping structures in the source / drain region of a GAA FET using CNTs according to an embodiment of the present invention are shown. FIG. 5A to FIG. 5D As shown, the first and second dielectric layers 210 and 220 (or Figure 1D The double layer of the dielectric layer 200 (the third and fourth dielectric layers 230 and 240) partially covers the CNT 100 under the source / drain contact 70, and the source / drain contact 70 does not cover the dielectric layer 200. Figure 5A In FIG. 1 , the left and right portions of the CNT 100 are covered by the dielectric layer 200, while the top and bottom of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 5B In FIG. 1 , the top and bottom of the CNT 100 are covered by the dielectric layer 200, while the left and right portions of the CNT 100 are in direct contact with the source / drain contacts 70. Figure 5C In FIG. 1 , the top of CNT 100 is in direct contact with source / drain contact 70 and the rest of CNT 100 is covered by dielectric layer 200. Figure 5D In the embodiment of the present invention, the bottom of the CNT 100 is in direct contact with the source / drain contact 70 , and the remaining portion of the CNT 100 is covered by the dielectric layer 200 .

[0061] In some embodiments, in a cross section perpendicular to the extension direction of the CNT, the dielectric layer 200 covers 25% to 90% of the circumference of the CNT 100. For example, Figure 2C As shown, the angle θ corresponding to the perimeter covered by the dielectric layer 200 is in the range of about 90 degrees to 324 degrees. In other embodiments, the angle θ is in the range of from about 120 degrees (33.3%) to about 270 degrees (75%). Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B As shown, when the dielectric layer 200 is divided into a plurality of regions, the angle θ is the sum of the angles of the respective regions.

[0062] In some embodiments, source / drain contacts 70 make ohmic contact with CNT 100. In other embodiments, source / drain contacts 70 make Schottky contact with CNT 100.

[0063] FIG. 6A to FIG. 19I 1 shows various stages of a sequential manufacturing process of a GAA FET using carbon nanotubes according to an embodiment of the present invention. It should be understood that FIG. 6A to FIG. 19I Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchanged. FIG. 1A to FIG. 5D The materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the described materials, configurations, dimensions, processes, and / or operations may be used in the following embodiments, and detailed descriptions may be omitted.

[0064] like Fig. 6AAs shown, a bottom support layer 15 is formed over the substrate 10. In some embodiments, the substrate 10 is made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide or indium gallium phosphide), etc. An insulating material such as glass can be used as a substrate. In some embodiments, the bottom support layer 15 is made of an insulating material. In some embodiments, the bottom support layer includes one or more layers of silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN or other suitable insulating materials. In other embodiments, the bottom support layer includes a polycrystalline or amorphous material of one of Si, Ge and SiGe. The bottom support layer 15 may be formed by a suitable film forming method such as thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, silicon oxide (eg, SiO 2 ) is used as the bottom support layer 15 .

[0065] Then, if Figure 6B As shown, one or more carbon nanotubes (CNT) 100 are arranged above the bottom support layer 15. In some embodiments, the bottom support layer is not used, and the CNT 100 is directly disposed on the substrate 10. The CNT is arranged on the bottom support layer 15 aligned with substantially the same direction (e.g., the Y direction). In some embodiments, the alignment of the CNT 100 deviates from the Y direction by about ±10 degrees, and in other embodiments by about ±5 degrees. In some embodiments, the deviation is about ±2 degrees. In some embodiments, the CNT 100 is arranged at a density of about 50 tubes / μm to about 300 tubes / μm along the X direction, and in other embodiments, the density along the X direction is in the range of about 100 tubes / μm to about 200 tubes / μm. In some embodiments, the length of the CNT 100 (in the Y direction) is in the range of about 0.5 μm to about 5 μm, and in other embodiments in the range of about 1 μm to about 2 μm. In some embodiments, the average diameter of the CNT 100 is in the range of about 1.0 nm to about 2.0 nm.

[0066] Carbon nanotubes can be formed by various methods, such as CVD, arc discharge or laser ablation methods using a metal catalyst on a substrate (e.g., quartz or sapphire). The formed CNTs are dispersed in a solvent, such as sodium dodecyl sulfate (SDS). In some embodiments, the CNTs can be transferred to and disposed on a substrate using various methods, such as a floating evaporation self-assembly method.

[0067] like Figure 6C As shown, after CNT 100 is transferred to bottom support layer 15, first support layer 21 is formed above CNT (first group of CNT) disposed on bottom support layer 15. In some embodiments, first support layer 21 comprises a polycrystalline or amorphous material of one of Si, Ge and SiGe. In other embodiments, first support layer 21 comprises one or more layers of silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN or other suitable insulating materials. In some embodiments, first support layer 21 comprises an organic material, such as an organic polymer. In certain embodiments, first support layer 21 is made of a material different from bottom support layer 15. In other embodiments, first support layer 21 is made of the same material as bottom support layer 15. First support layer 21 can be formed by a suitable film forming method, such as CVD, PVD or ALD. In one embodiment, ALD is used due to its high thickness uniformity and thickness controllability.

[0068] In some embodiments, when the first support layer is conformally formed above the first group of CNTs 100, the upper surface of the first support layer has a wavy shape of peaks and valleys. In some embodiments, the thickness of the first support layer 21 is in the range of about 2nm to about 10nm, and in other embodiments, in the range of about 3nm to 5nm. In other embodiments, after the first support layer 21 is formed with a wavy upper surface, one or more planarization operations are performed to planarize the upper surface of the support layer 21. The planarization operation includes an etch-back process or a chemical mechanical polishing (CMP) process. In one embodiment, CMP is used.

[0069] Then, if Fig.6D As shown, a second supporting layer 22 is formed over the first supporting layer 21. In some embodiments, the second supporting layer 22 is made of the same material as the first supporting layer 21. The thickness of the second supporting layer 22 is substantially the same as the thickness of the first supporting layer 21. In some embodiments, the thickness difference is within ±5% relative to the average thickness.

[0070] In addition, if Fig.6D As shown, the second group of CNTs 100 are disposed on the second support layer 22. When the upper surface of the first support layer has a wavy shape, the second group of CNTs 100 tend to be arranged at the valleys of the wavy shape.

[0071] In some embodiments, forming a CNT group and forming a support layer are repeated to form n support layers, and CNTs are embedded in each support layer, where n is an integer greater than 3. In some embodiments, n is up to 20. Fig.6DAn embodiment is shown in which six support layers 21, 22, 23, 24, 25, and 26 are formed, thereby forming six layers of CNTs disposed in the support layer 20. In the following description, the first to sixth support layers 21-26 are referred to as the support layer 20.

[0072] exist Fig.6D In the embodiment, the CNTs 100 in one layer are arranged at a substantially constant pitch, and the CNTs in the vertical direction are aligned. However, the arrangement of the CNTs in the support layer 20 is not limited to Fig.6D In some embodiments, the CNTs in a layer have random spacing in the X direction. In some embodiments, when the average diameter of CNT 100 is D CNT When the horizontal spacing P of CNT H D CNT ≤P H ≤10×D CNT In some embodiments, two adjacent CNTs are in contact with each other. In addition, in some embodiments, at least two CNTs 100 in different layers are not aligned with each other in the vertical direction. The vertical spacing P of the CNTs 100 is V Determined by the thickness of the support layer. In some embodiments, the vertical spacing PV of CNTs 100 in adjacent layers is 0.9×P A ≤P V ≤1.1×P A , where P A is the average spacing of the multiple layers. In other embodiments, the vertical spacing P V 0.95×P A ≤P V ≤1.05×P A .

[0073] In some embodiments, after CNT 100 is transferred onto substrate 10, the following steps are performed: 7A to 7E The trimming process shown. 7A to 7E As shown in FIG. 1 , after the CNT 100 is transferred onto the bottom support layer 15, a photoresist pattern 12 as a cover layer is formed over the central portion of the CNT 100 by using a photolithography operation. Figure 7C As shown, the end of CNT 100 is exposed. In some embodiments, the width W21 of the photoresist pattern 12 is in the range of about 50nm to about 2000nm, and in other embodiments in the range of about 100nm to about 1000nm. Then, as Fig.7D As shown, the exposed ends of CNT 100 are removed by etching. Fig. 7E As shown, the photoresist pattern 12 is then removed by dry etching and / or wet removal using an organic solvent.

[0074] Reference Fig. 6E , by using one or more photolithography and etching operations, a mask pattern 18 is formed over the support layer 20, and the support layer 20 having the CNT 100 is patterned into one or more fin structures 30, such as Fig. 6F As shown. In some embodiments, the mask pattern 18 is a photoresist layer, and in other embodiments may be a hard mask made of a dielectric material. In some embodiments, the fin structure 30 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fin structure.

[0075] In some embodiments, the width of the fin structure 30 in the X direction is in the range of about 5 nm to about 20 nm, and in other embodiments in the range of about 7 nm to about 12 nm. When the bottom support layer 15 is made of the same or similar material as the support layer 20, the bottom support layer 15 is also patterned into the fin structure, such as Fig. 6F In other embodiments, when the bottom supporting layer 15 is made of a different material from the supporting layer 20, the bottom supporting layer 15 is not patterned.

[0076] The total number of CNTs 100 per fin structure ranges from about 5 to about 100 in some embodiments, and from about 10 to about 50 in other embodiments.

[0077] Then, if Fig. 8A and Figure 8B As shown, a sacrificial gate structure 40 is formed over the fin structure 30 . Fig. 8A is the cross-sectional view along the X direction, Figure 8Bis a cross-sectional view along the Y direction. The sacrificial gate structure 40 is formed by blanket depositing a sacrificial gate electrode layer over the fin structure 30 so that the fin structure 30 is completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon, germanium or silicon germanium, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100nm to about 200nm. In some embodiments, the sacrificial gate electrode layer is planarized. The sacrificial gate electrode layer is deposited using CVD, PVD, ALD or other suitable processes including LPCVD and PECVD. In some embodiments, a sacrificial gate dielectric layer is not formed between the fin structure 30 and the sacrificial gate electrode layer, and in other embodiments, a sacrificial gate dielectric layer is formed between the fin structure 30 and the sacrificial gate electrode layer.

[0078] Subsequently, a mask layer 42 is formed over the sacrificial gate electrode layer 40. The mask layer 42 includes one or more of a silicon nitride (SiN) layer and a silicon oxide layer. Next, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer is patterned into a sacrificial gate structure 40, such as Fig. 8A and Figure 8B By patterning the sacrificial gate structure, the fin structure 30 is partially exposed on the opposite side of the sacrificial gate structure 40, thereby defining a source / drain (S / D) region, as shown in FIG. Figure 8B As shown. In the present invention, the source and drain can be used interchangeably, and their structures are basically the same. Fig. 8A and Figure 8B In the embodiment, two sacrificial gate structures 40 are formed above two fin structures 30, but the number of sacrificial gate structures is not limited to this configuration. In some embodiments, one or more two sacrificial gate structures may be arranged in the Y direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0079] like Fig.9A and Fig. 9B As shown, after forming the sacrificial gate structure 40, a blanket layer of insulating material for the gate sidewall spacer 44 is conformally formed by using CVD or other suitable methods. The blanket layer is deposited in a conformal manner so that it is formed to have substantially equal thickness on the vertical surfaces (e.g., sidewalls), horizontal surfaces, and top of the sacrificial gate structure 40. In some embodiments, the blanket layer is deposited to a thickness in the range of about 2 nm to about 10 nm. In some embodiments, the insulating material of the blanket layer is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN and combinations thereof. In certain embodiments, the insulating material is one of SiOC, SiCON, and SiCN. From Fig.9A and Fig. 9BIt is understood that in some embodiments, CNTs 100 are supported by support layer 20, but are not supported (anchored) by sidewall spacers 44. In some embodiments, support layer 20 is lightly etched to expose the ends of CNTs 100 before forming a blanket layer for sidewall spacers 44. In this case, the ends of CNTs 100 are supported (anchored) by sidewall spacers 44.

[0080] In addition, if Fig.9A and Fig. 9B As shown, gate sidewall spacers 44 are formed on opposite sidewalls of the sacrificial gate structure 40 by anisotropic etching. After the blanket layer is formed, anisotropic etching is performed on the blanket layer using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from the horizontal surfaces, leaving a dielectric spacer layer on the vertical surfaces (such as the sidewalls of the sacrificial gate structure and the sidewalls of the exposed fin structure). The mask layer 42 can be exposed from the sidewall spacers. In some embodiments, an isotropic etching process can be subsequently performed to remove the insulating material from the upper portion of the S / D region of the exposed fin structure 30.

[0081] Subsequently, a liner layer 46 (such as an etch stop layer) is formed to cover the gate structure 40 with the sidewall spacers 44 and the exposed fin structure 30. In some embodiments, the liner layer 46 includes a silicon nitride-based material such as silicon nitride, SiON, SiOCN or SiCN and combinations thereof formed by CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes. In some embodiments, the liner layer 46 is made of silicon nitride. In addition, as Fig.9A and Fig. 9B As shown, a first interlayer dielectric (ILD) layer 50 is formed. Materials for the first ILD layer 50 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the first ILD layer 50.

[0082] After forming the first ILD layer 50, a planarization operation such as CMP is performed to expose the sacrificial gate electrode layer 40. Fig. 10A and Fig. 10B Then, as Fig.11A and Fig. 11B As shown, the sacrificial gate electrode layer 40 is removed, thereby exposing the channel region of the fin structure in the gate spacer 55. The sacrificial gate structure 40 may be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 40 is polysilicon and the first ILD layer 50 is silicon oxide, a wet etchant such as a TMAH solution may be used to selectively remove the sacrificial gate electrode layer 40.

[0083] In addition, if Fig. 12A and Fig. 12B As shown, the support layer 20 in the gate spacer 55 is removed to release the CNT 100. The support layer 20 can be selectively removed using plasma dry etching and / or wet etching to release the CNT 100. When the support layer 20 is polysilicon or amorphous silicon and the first ILD layer 50 is silicon oxide, a wet etchant such as a TMAH solution is used. When the sacrificial gate electrode layer 40 and the support layer 20 are made of the same material, the removal of the sacrificial gate electrode layer 40 and the removal of the support layer 20 are performed by the same etching operation.

[0084] After releasing the channel region of the CNT 100, a gate dielectric layer 102 is formed around the CNT 100, such as FIG. 13A to FIG. 13C shown. Fig. 13C is an enlarged view of the gate structure. In some embodiments, the gate dielectric layer 102 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, for n-channel FETs, the gate dielectric layer 102 is made of HfO2, and for p-channel FETs, it is made of Al2O3. In some embodiments, the gate dielectric layer 102 has a thickness in the range of about 0.5nm to about 2.5nm, and in other embodiments has a thickness in the range of about 1.0nm to about 2.0nm. The gate dielectric layer 102 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 102 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed around each channel region of the CNT 100 .

[0085] In some embodiments, an interfacial layer (not shown) is formed around the CNTs before forming the gate dielectric layer 102. The interfacial layer is made of, for example, SiO2, and has a thickness in the range of about 0.5 nm to about 1.5 nm in some embodiments. In other embodiments, the thickness of the interfacial layer is in the range of about 0.6 nm to about 1.0 nm.

[0086] In some embodiments, one or more work function adjustment layers 104 are formed on the gate dielectric layer 102. The work function adjustment layer 104 is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. In some embodiments, TiN is used as the work function adjustment layer 104. The work function adjustment layer 104 can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, for n-channel FETs and p-channel FETs that can use different metal layers, the work function adjustment layer 104 can be formed separately.

[0087] Then, if Fig.13A and Fig. 13B As shown, a gate electrode layer 106 is formed over the work function adjustment layer 104. The gate electrode layer 106 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 106 may be formed by CVD, ALD, electroplating or other suitable methods. The gate electrode layer 106 is also deposited over the upper surface of the first ILD layer 50, and then the gate dielectric layer 102, the work function adjustment layer 104 and the gate electrode layer 106 formed over the first ILD layer 50 are planarized by using, for example, CMP until the first ILD layer 50 is exposed.

[0088] exist Fig.13A and Fig. 13B In the embodiment, the gate dielectric layer completely wraps around each CNT 100, the work function adjustment layer 104 also completely wraps around each CNT 100, and the gap formed between the work function adjustment layers 104 of adjacent CNTs 100 is filled by the gate electrode layer 106. In other embodiments, such as Fig.14A and Fig. 14B As shown, the work function adjusting layer 104 fills the space between the gate dielectric layers 102 of adjacent CNTs 100 , and the gate electrode layer 106 covers the outer surface of the work function adjusting layer 104 .

[0089] Then, if Fig.15A and Fig. 15B As shown, a second ILD layer 60 is formed over the first ILD layer 50, and source / drain contact openings 65 are formed by using one or more photolithography and etching operations. By this operation, the support layer 20 is removed, and thus the source / drain regions of the CNT 100 are exposed to the source / drain contact openings 65. Fig. 15BIn the embodiment, a portion of the support layer 20 remains under the sidewall spacer 44. When the support layer 20 is made of a dielectric material, the remaining support layer 20 serves as an inner spacer separating the gate electrode layer 106 and the subsequently formed source / drain contacts 70 / 72.

[0090] Then, if Fig.16A As shown, a dielectric layer 200 is formed around the exposed CNT 100. In some embodiments, the dielectric layer 200 is a single layer, and in other embodiments, the dielectric layer 200 is a double layer structure. In certain embodiments, three or more dielectric layers are formed as the dielectric layer 200. In some embodiments, the dielectric layer 200 is formed by ALD or CVD or any suitable film forming method.

[0091] In some embodiments, Fig. 16B As shown in FIG. 1 , when the interval between adjacent CNTs 100 is relatively wide, the dielectric layer 200 is wrapped around each CNT 100. In other embodiments, as shown in FIG. Fig. 16C As shown, when the interval between adjacent CNTs 100 is relatively narrow, the dielectric layer 200 wrapping one CNT 100 is continuous with the dielectric layer 200 wrapping the adjacent CNT 100 .

[0092] Next, if Fig.17A and Fig. 17B As shown, a portion of the dielectric layer 200 is removed from the source / drain region of the CNT 100, thereby exposing a portion of the source / drain region of the CNT 100. In some embodiments, as Fig. 17B As shown, a portion of the dielectric layer is removed from the top of CNT 100. In some embodiments, anisotropic dry etching is used. In other embodiments, anisotropic etching and isotropic etching are performed alternately.

[0093] Next, if Fig.18A and Fig.18B As shown, the source / drain contact opening 65 is filled with one or more layers of conductive material. The conductive material includes one or more of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt and Zr, or any other suitable conductive material. In some embodiments, the lower contact layer 70 is wrapped around the source / drain region of the CNT 100 with the interposed dielectric layer 200, and the upper contact layer 72 is formed on the lower contact layer 70.

[0094] In some embodiments, the lower contact layer 70 is one or more of TiN, Ti, and TaN. In some embodiments, the upper contact layer is one or more of W, Cu, and Co. In addition, in some embodiments, one or more gate contacts are formed simultaneously with the source / drain contacts or by a different operation than the source / drain contacts.

[0095] FIG. 19A to FIG. 19C and FIG. 19D to FIG. 19F 1 shows various stages of a sequential manufacturing process of a GAA FET using CNTs according to an embodiment of the present invention. Fig.19A As shown, the dielectric layer 200 includes a first dielectric layer 210 and a second dielectric layer 220 (or a third dielectric layer 230 and a fourth dielectric layer 240 ).

[0096] In some embodiments, when the interval between adjacent CNTs 100 is relatively wide, the dielectric layer 200 is wrapped around each CNT 100. In other embodiments, as FIG. 19A to FIG. 19C As shown, when the interval between adjacent CNTs 100 is relatively narrow, the first dielectric layer 210 is wrapped around each CNT 100, and the second dielectric layer 220 wrapped around one CNT 100 is continuous with the second dielectric layer 220 wrapped around the adjacent CNT 100. In other embodiments, as FIG. 19D to FIG. 19F As shown, when the interval between adjacent CNTs 100 is narrow, the first dielectric layer 210 wrapped around each CNT 100 and the second dielectric layer 220 wrapped around one CNT 100 are continuous with the first and second dielectric layers wrapped around adjacent CNTs 100 .

[0097] Figure 19G , Fig.19H and Fig.19I 1 shows various stages of a sequential manufacturing process of a GAA FET using CNTs according to an embodiment of the present invention. Figure 19G As shown, along the vertical direction (Z direction), a dielectric layer 200 (or bilayer) is wrapped around each CNT 100. In the etching operation that removes part of the dielectric layer, the top and sides of the topmost CNT 100 are exposed, and the sides of the CNTs 100 below the topmost CNT 100 are exposed. Therefore, the coverage of the dielectric layer 200 is different between the topmost CNT 100 and the other CNTs below.

[0098] In some embodiments, the total number of CNTs 100 in one GAA FET is in the range of about 5 to about 100, and in other embodiments is in the range of about 10 to about 50. In some embodiments, the total number of CNTs in one GAA FET is different from the total number of CNTs in another GAA FET. In some embodiments, in the GAA FET, two of the CNTs contact each other in the horizontal direction, and no CNT contacts another CNT in the vertical direction. In some embodiments, the source / drain contacts are formed first, and then the gate structure is formed.

[0099] Fig. 20A and Fig. 20B FIG. 4 is a cross-sectional view of a GAA FET using CNT according to another embodiment of the present invention. FIG. 1A to FIG. 19I The materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the described materials, configurations, dimensions, processes, and / or operations may be used in the following embodiments, and detailed descriptions may be omitted. Fig. 20B yes Fig. 20A Magnified view of the enclosed area AR.

[0100] In this embodiment, the dielectric layer 200 (including the first dielectric layer 210 and the second dielectric layer 220 in some embodiments) is disposed below the source / drain region of the CNT 100 and contacts the gate dielectric layer 102. In addition, the gate electrode (e.g., the work function adjustment layer 104) is electrically isolated from the source / drain contact 70 by the dielectric layer 102 and the insulating inner spacer 80. In some embodiments, the insulating inner spacer is disposed between the CNT 100 and the gate dielectric layer 102. In some embodiments, the gate dielectric layer 102 is disposed between the insulating inner spacer and the CNT 100. In some embodiments, the gate dielectric layer 102 is disposed between the source / drain contact 70 and the CNT 100. In some embodiments, instead of or in addition to the gate sidewall spacer 44, a contact spacer 54 is formed between the gate dielectric layer 102 and the source / drain contact 70 at a height above the channel region.

[0101] Subsequently, further CMOS processes are performed to form various features, such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0102] FIG. 21A to FIG. 31 The use of an embodiment according to the present invention is shown Fig. 20A and Fig. 20B The various stages of the manufacturing operation of the carbon nanotube GAA FET are shown. It should be understood that FIG. 21A to FIG. 31Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchanged. FIG. 1A to FIG. 19I The materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the described materials, configurations, dimensions, processes, and / or operations may be used in the following embodiments, and detailed descriptions may be omitted.

[0103] Similar to Fig. 6A ,like Fig.21A As shown, a bottom support layer 15 is formed on the substrate 10, and then a dielectric layer 200 is formed on the bottom support layer 15. In some embodiments, the dielectric layer 200 is a single layer or a double layer of the first and second dielectric layers 210 and 220 or the third and fourth dielectric layers 230 and 240. Then, similar to Figure 6B , one or more carbon nanotubes (CNTs) 100 are arranged above the dielectric layer 200. Then, similar to Figure 6C ,like Fig. 21C As shown, a support layer 20 is formed on the CNT 100. Fig.21D As shown, the formation of dielectric layer 200, the placement of CNT 100, and the formation of support layer 20 are repeated. In some embodiments, support layer 20 is formed on bottom support layer 15, and dielectric layer 200 is formed on support layer 20.

[0104] Fig.22A , Fig. 22B and Fig. 22C One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0105] In some embodiments, stacked structures 29 including support layer 20, dielectric layer 200 and CNT 100 are repeatedly formed over bottom support layer 15 (and substrate 100). The number of stacked structures 29 is as few as one or two, three or more. In some embodiments, the number of stacked structures 29 is as many as 20.

[0106] Fig.23 FIG. 1 shows one of the various stages of a sequential manufacturing process for a GAA FET using CNTs according to an embodiment of the present invention. Fig. 6F ,like Fig.23 As shown, a mask pattern is formed over the topmost support layer 20 and the stack structure 29 is patterned into one or more fin structures 30 by using one or more photolithography and etching operations.

[0107] Fig.24A and Fig. 24BFIG. 1 shows one of the various stages of a sequential manufacturing process for a GAA FET using CNTs according to an embodiment of the present invention. Fig. 8A and Figure 8B ,like Fig.24A and Fig. 24B As shown, a sacrificial gate structure 40 having a hard mask pattern 42 is formed over the fin structure 30. Furthermore, in some embodiments, a first ILD layer 50 is formed between the sacrificial gate structures 40 having the hard mask pattern 42. In some embodiments, after forming the thick ILD layer, a CMP operation is performed to expose the hard mask pattern 42. In some embodiments, before forming a sacrificial gate structure (e.g., a polysilicon layer), a sacrificial gate dielectric layer 41 is formed over the fin structure 30 and the bottom support layer 15 by, for example, ALD or CVD.

[0108] Fig.25A and Fig.25B One of the various stages of a sequential manufacturing process of a GAA FET using CNTs according to an embodiment of the present invention is shown. A second ILD layer 60 is formed over the first ILD layer 50 and the hard mask pattern 42. In some embodiments, the material of the second ILD layer 60 is the same as the first ILD layer 50, and in other embodiments, is different from the material of the first ILD layer 50. In some embodiments, the second ILD layer 60 is made of silicon nitride and / or SiON.

[0109] In some embodiments, Fig.25A and Fig.25B As shown, an isolation structure 52 is formed. In some embodiments, the first ILD layer 50 and the stacked structure 29 are patterned by one or more photolithography and etching operations to form an opening, and then the opening is filled with one or more insulating materials. Fig.25A and Fig.25B As shown, a hard mask layer 62 is formed and patterned, and then the source / drain contact openings 65 are formed by etching the second ILD layer 60 and the first ILD layer 50. Fig.25B As shown, the stack structure 29 of the fin structure 30 is exposed in the source / drain contact opening 65 . In some embodiments, a portion of the first ILD layer remains along the contact sidewall 54 of the sacrificial gate structure 40 .

[0110] Fig.26A and Fig.26B FIG. 1 shows one of the various stages of a sequential manufacturing process of a GAA FET using CNTs according to an embodiment of the present invention. After forming source / drain contact openings 65, Fig.25A and Fig.25BThe exposed stack structure 29 shown selectively removes the support layer 20. In some embodiments, dry etching and / or wet etching are performed to remove the support layer 20. Fig.26A and Fig.26B As shown, the stack of dielectric layer 200 and CNT 100 remains in source / drain contact openings 65 .

[0111] Fig.27A and Fig.27B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0112] After the support layer 20 in the source / drain contact opening 65 is removed, an insulating layer 80 for insulating the inner spacer is formed inside the source / drain contact opening 65. Fig.27B As shown, the insulating layer 80 is conformally formed, for example, by ALD or CVD. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, SiON, SiCN, SiOC, SiOCN or any other suitable material.

[0113] Fig.28A and Fig.28B FIG. 1 shows one of the various stages of a sequential manufacturing process of a GAA FET using CNTs according to an embodiment of the present invention. The insulating layer is then etched to form an insulating inner spacer 80 on the end of the support layer 20 below the sacrificial gate structure 40, as shown in FIG. Fig.28A and Fig.28B As shown, the stack of dielectric layer 200 and CNT 100 is again exposed in source / drain contact opening 65 .

[0114] FIG. 29A to FIG. 29C FIG. 1 shows one of the various stages of a sequential manufacturing process for a GAA FET using CNTs according to an embodiment of the present invention. Fig.18A and Fig.18B ,like FIG. 29A to FIG. 29C As shown, the source / drain contact opening 65 is filled with one or more layers of conductive material to form a lower contact layer 70 and an upper contact layer 72. In some embodiments, the lower contact layer 70 and the upper contact layer are collectively referred to as the source / drain contact layer 70. Fig.29C As shown, the lower contact layer 70 is in contact with the CNT 100 , and the bottom of the CNT 100 is covered by the dielectric layer 40 and is thus separated from the contact layer 70 .

[0115] Fig. 30A and Fig. 30B One of the various stages of a sequential fabrication process for a GAA FET using CNTs according to an embodiment of the present invention is shown.

[0116] Then, similar to FIG. 11A to FIG. 12B ,like Fig. 30A and Fig. 30B As shown, the hard mask pattern 42 and the sacrificial gate structure 40 are removed to form a gate spacer 55, and in the gate spacer, the support layer 20 and the dielectric layer 200 are removed, and the CNT 100 is fully exposed. In some embodiments, a portion of the dielectric layer 200 under the inner spacer 80 is also removed. In some embodiments, a portion of the dielectric layer 200 between the source / drain contact layers 70 is also removed.

[0117] Fig.31 FIG. 1 shows one of the various stages of a sequential manufacturing process for a GAA FET using CNTs according to an embodiment of the present invention. FIG. 13A to FIG. 14B ,like Fig.31 As shown, after releasing the channel region of the CNT 100, a gate dielectric layer 102 is formed around the CNT 100, one or more work function adjustment layers 104 are formed on the gate dielectric layer 102, and a gate electrode layer 106 is formed above the work function adjustment layer 104. Subsequently, further CMOS processes are performed to form various components, such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0118] FIG. 32A to FIG. 35C The following embodiments show the various stages of a sequential manufacturing process of a GAA FET using CNTs according to other embodiments of the present invention. FIG. 22A to FIG. 22C The various structures and operations of the stacked structure 29 are shown. FIG. 32A to FIG. 32D In the embodiment, a bottom dielectric layer 200A is formed on the support layer 20 (or the bottom support layer 15), and CNTs 100 are disposed on the bottom dielectric layer 200A. Then, as shown in FIG. Fig.32A As shown, an upper dielectric layer 200B is formed to cover the CNT 100. Fig.32B As shown, a planarization operation such as an etch-back operation and a CMP operation is performed, and the upper dielectric layer 200B is partially removed to expose the upper portion of the CNT 100. Then, as shown in FIG. Fig.32C As shown, an additional support layer 20 is formed over the upper dielectric layer 200B and the CNTs 100 . Fig.32D The structure is shown after forming source / drain contacts 70 .

[0119] exist FIG. 33A to FIG. 33D In the embodiment, the CNT 100 is disposed on the support layer 20, and then the dielectric layer 200 is formed to cover the CNT 100, as shown in FIG. Fig.33A As shown. Fig.33B As shown, a planarization operation (such as an etch-back operation and a CMP operation) partially removes the dielectric layer 200 to expose the upper portion of the CNT 100. Then, as shown in FIG. Fig.33CAs shown, an additional support layer 20 is formed over the dielectric layer 200 and the CNTs 100 . Fig.33D The structure is shown after forming source / drain contacts 70. In some embodiments, the bottom of CNT 100 is in contact with source / drain contacts 70.

[0120] exist FIG. 34A to FIG. 34D In the embodiment, a bottom dielectric layer 200A is formed on the support layer 20 (or the bottom support layer 15), and CNTs 100 are disposed on the bottom dielectric layer 200A. Then, as shown in FIG. Fig.34A As shown, an upper dielectric layer 200B is formed to cover the CNT 100. Fig.34B As shown, an etch-back operation is performed to form a sidewall of the dielectric layer on the side of the CNT 100 and expose the upper portion of the CNT 100. Then, as shown in FIG. Fig.34C As shown, an additional support layer 20 is formed over the CNT 100 . Fig.34D 2 shows the structure after forming source / drain contacts 70. In some embodiments, similar to FIG. 33A to FIG. 33D , no bottom dielectric layer is formed.

[0121] exist FIG. 35A to FIG. 35C In the embodiment, a bottom second dielectric layer 220A is formed on the support layer 20 (or the bottom support layer 15), and a bottom first dielectric layer 210A is formed on the bottom second dielectric layer 220A. The CNT 100 is disposed on the bottom first dielectric layer 210A. Then, an upper first dielectric layer 210B is formed to cover the CNT 100, and an upper second dielectric layer 220B is formed on the upper first dielectric layer 210B, as shown in FIG. Fig.35A In some embodiments, the upper first dielectric layer and the upper second dielectric layer are formed conformally. Fig.35B As shown, a planarization operation such as an etch-back operation and a CMP operation is performed, and the upper first dielectric layer and the upper second dielectric layer are partially removed to expose the upper portion of the CNT 100. Then, an additional support layer 20 is formed over the upper dielectric layer 200A and the CNT 100. Fig.35C 2 shows the structure after forming source / drain contacts 70. In some embodiments, similar to FIG. 33A to FIG. 33D , no bottom first and / or second dielectric layer is formed.

[0122] Fig.36A and Fig.36B 1 shows a cross-sectional view of a planar FET using CNTs according to an embodiment of the present invention. Figures 1A to 35C The materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the described materials, configurations, dimensions, processes, and / or operations may be used in the following embodiments, and detailed descriptions may be omitted. Fig.36AA cross-sectional view along the source-drain (Y) direction is shown, and Fig.36B A cross-sectional view along the gate extension direction (X) is shown.

[0123] like Fig.36A and Fig.36B As shown, a bottom support layer (or isolation layer) 15 is formed over the substrate 10. In some embodiments, a second dielectric layer 220 is formed over the bottom support layer 15, and a first dielectric layer 210 is formed over the second dielectric layer 220. In addition, the CNT 100 is disposed on the first dielectric layer 210. In some embodiments, a single dielectric layer or a triple dielectric layer is used. A gate dielectric layer is disposed over the channel region of the CNT 100, and a gate electrode layer 144 is disposed over the gate dielectric layer 142. A gate sidewall spacer 143 is disposed on opposite sides of the gate electrode layer 144. The source / drain electrode 170 is disposed over the source / drain region of the CNT 100. Similar to the GAA FET described above, the source / drain electrode 170 partially covers the CNT 100, and the dielectric layer (e.g., dielectric dipole layers 210 and 220) covers the remaining portion of the CNT 100 in the source / drain region.

[0124] It will be understood that not all advantages must be discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages. For example, in the present invention, because the stacked structure of CNTs is formed as a fin structure, the CNT density within a GAA FET can be increased. In addition, by utilizing an embedded doping structure in the source / drain region of the CNT, the mobile carriers in the source / drain region can be increased and the contact resistance in the source / drain region can be reduced.

[0125] According to aspects of the present invention, in a method for forming a full-ring gate field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures, each stacked structure including a dielectric layer, a CNT located above the dielectric layer, and a support layer located above the CNT. A sacrificial gate structure is formed above the fin structure, an isolation insulating layer is formed, a source / drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source / drain opening, and a source / drain contact layer is formed in the source / drain opening. A source / drain contact is formed so that the source / drain contact is in direct contact only with a portion of the CNT, and a portion of the dielectric layer is disposed between the source / drain contact and the CNT. In one or more of the foregoing and following embodiments, a portion of the dielectric layer includes a fixed positive charge inside, inducing a negative charge in the CNT. In one or more of the foregoing and following embodiments, the dielectric layer is made of non-stoichiometric silicon nitride. In one or more of the foregoing and following embodiments, the dielectric layer includes a first dielectric layer in contact with the CNT and a second dielectric layer formed on the first dielectric layer, and in a portion of the dielectric layer, the first dielectric layer and the second dielectric layer constitute a dielectric dipole structure, inducing negative charge in the CNT. In one or more of the foregoing and following embodiments, the first dielectric layer is made of aluminum oxide, and the second dielectric layer is made of hafnium oxide. In one or more of the foregoing and following embodiments, the dielectric layer includes a first dielectric layer in contact with the CNT, a second dielectric layer disposed above the first dielectric layer, and a third dielectric layer disposed above the second dielectric layer, and in a portion of the dielectric layer, the first to third dielectric layers constitute a dielectric dipole structure, inducing positive charge in the CNT. In one or more of the foregoing and following embodiments, the first dielectric layer is made of aluminum oxide, the second dielectric layer is made of silicon oxide, and the third dielectric layer is made of aluminum oxide. In one or more of the foregoing and following embodiments, in a cross section, a portion of the dielectric layer covers 25% to 90% of the periphery of the CNT. In one or more of the foregoing and following embodiments, after forming the source / drain contacts, a gate spacer is formed by removing the sacrificial gate structure, removing the dielectric layer and the support layer in the gate spacer so that the CNT is exposed to the gate spacer, and a gate dielectric layer is formed around the CNT, and a gate electrode is formed above the gate dielectric layer. In one or more of the foregoing and following embodiments, after removing the support layer and before forming the source / drain contacts, an insulating internal spacer is formed at the end of the support layer below the sacrificial gate structure. In one or more of the foregoing and following embodiments, when removing the dielectric layer and the support layer in the gate spacer, a portion of the dielectric layer disposed between the insulating internal spacer and the CNT is removed. In one or more of the foregoing and following embodiments, when removing the dielectric layer and the support layer in the gate spacer, a portion of the dielectric layer disposed between the source / drain contacts and the CNT is removed.In one or more of the foregoing and following embodiments, a plurality of CNTs are included in each of the plurality of stacked structures. In one or more of the foregoing and following embodiments, the support layer is made of a polycrystalline or amorphous material of one of Si, Ge, and SiGe. In one or more of the foregoing and following embodiments, the support layer is made of a dielectric material different from that of the dielectric layer.

[0126] According to another aspect of the present invention, in a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed above a substrate, wherein carbon nanotubes (CNTs) are embedded in a supporting material, a sacrificial gate structure is formed above the fin structure, an insulating layer is formed above the sacrificial gate structure and the fin structure, the sacrificial gate structure is removed so that a portion of the fin structure is exposed, the supporting material is removed from the exposed portion of the fin structure so that a channel region of the CNT is exposed, a gate structure is formed around the exposed channel region of the CNT, source / drain openings are formed in the insulating layer, the supporting material in the source / drain openings is removed so that a source / drain region of the CNT is exposed, a dielectric layer is formed around the exposed CNT in the source / drain openings, the dielectric layer is partially removed so that a portion of the dielectric layer remains on the CNT in the source / drain openings, and a source / drain contact layer is formed in the source / drain openings. A source / drain contact is formed such that the source / drain contact is in direct contact with a portion of the CNT, and a remaining portion of the dielectric layer is disposed between the source / drain contact and the CNT. In one or more of the foregoing and following embodiments, the portion of the dielectric layer is a single dielectric layer having a fixed positive charge inside. In one or more of the foregoing and following embodiments, the dielectric layer includes a first dielectric layer in contact with the CNT and a second dielectric layer formed on the first dielectric layer, and in the remaining portion of the dielectric layer, the first dielectric layer and the second dielectric layer constitute a dielectric dipole structure. In one or more of the foregoing and following embodiments, in a cross section, the remaining portion of the dielectric layer covers 25% to 90% of the periphery of each CNT.

[0127] According to another aspect of the present invention, in a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed above a substrate, wherein carbon nanotubes (CNTs) are embedded in a supporting material, an isolation insulating layer is formed, a gate structure is formed around a channel region of the CNTs by using a gate replacement technique, and a source / drain contact is formed in contact with a source / drain region of the CNTs. The source / drain contact is formed so that the source / drain contact is in direct contact with only a portion of each CNT, and a dielectric layer partially covers each CNT and is disposed between the source / drain contact and each CNT.

[0128] According to one aspect of the present invention, a semiconductor device having a full-ring gate field effect transistor includes: a carbon nanotube (CNT) disposed above a substrate; a gate structure formed around the CNT in a channel region; and a source / drain contact formed around the CNT in a source / drain region. The source / drain contact is in direct contact with only a portion of the CNT, and a dielectric layer partially covers the CNT and is disposed between the source / drain contact and the CNT. In one or more of the foregoing and following embodiments, the interior of the dielectric layer includes a fixed positive charge, inducing a negative charge in the CNT. In one or more of the foregoing and following embodiments, the dielectric layer is made of non-stoichiometric silicon nitride. In one or more of the foregoing and following embodiments, the dielectric layer includes a first dielectric layer in contact with the CNT and a second dielectric layer formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer constitute a dielectric dipole structure, which induces a negative charge in the CNT. In one or more of the foregoing and following embodiments, the first dielectric layer is made of aluminum oxide, and the second dielectric layer is made of hafnium oxide. In one or more of the foregoing and following embodiments, the dielectric layer includes a first dielectric layer in contact with the CNT, a second dielectric layer disposed above the first dielectric layer, and a third dielectric layer disposed above the second dielectric layer, and the first dielectric layer to the third dielectric layer constitute a dielectric dipole structure that induces positive charge in the CNT. In one or more of the foregoing and following embodiments, the first dielectric layer is made of aluminum oxide, the second dielectric layer is made of silicon oxide, and the third dielectric layer is made of aluminum oxide. In one or more of the foregoing and following embodiments, in a cross section, the dielectric layer covers 25% to 90% of the periphery of the CNT. In one or more of the foregoing and following embodiments, the semiconductor device also includes an insulating internal spacer disposed between the gate structure and the source / drain contact. In one or more of the foregoing and following embodiments, the insulating internal spacer is disposed between the CNT and the gate dielectric layer of the gate structure. In one or more of the foregoing and following embodiments, the gate dielectric layer is disposed between the CNT and the source / drain contact. In one or more of the foregoing and following embodiments, a dielectric layer is disposed at the bottom of the CNTs, and the tops of the CNTs are covered by source / drain contacts.

[0129] According to another aspect of the present invention, a semiconductor device having a full-ring gate field effect transistor includes: a carbon nanotube (CNT) disposed above a substrate; a gate structure formed around the CNT in a channel region; and a source / drain contact formed around the CNT in a source / drain region. The source / drain contact is in direct contact with only a portion of each CNT, and the dielectric layer partially covers each CNT and is located between the source / drain contact and each CNT, and no CNT contacts another CNT in a vertical direction. In one or more of the foregoing and following embodiments, the gate structure includes a gate dielectric layer wrapping each CNT, a work function adjustment layer formed on the gate dielectric layer, and a bulk gate electrode layer formed on the work function adjustment layer. In one or more of the foregoing and following embodiments, the work function adjustment layer partially wraps around the CNT with the gate dielectric layer. In one or more of the foregoing and following embodiments, the work function adjustment layer completely wraps around each CNT with the gate dielectric layer. In one or more of the foregoing and following embodiments, the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3. In one or more of the foregoing and following embodiments, the work function adjusting layer includes TiN. In one or more of the foregoing and following embodiments, the semiconductor device further includes an internal spacer formed between the gate structure and the source / drain contacts.

[0130] According to another aspect of the present invention, a semiconductor device having a gate-all-around field effect transistor (GAA FET) includes a first GAA FET and a second GAA FET. Each of the first GAA FET and the second GAA FET includes a carbon nanotube (CNT) disposed above a substrate, a gate structure formed around the CNT in a channel region, and a source / drain contact formed around the CNT in a source / drain region. The source / drain contact is in direct contact with only a portion of the CNT, and a dielectric layer partially covers the CNT and is disposed between the source / drain contact and the CNT.

[0131] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

Claims

1. A method for forming a gate-all-around field effect transistor, the method comprising: forming a fin structure, wherein the fin structure comprises a plurality of stacked structures, each stacked structure comprises a dielectric layer, a carbon nanotube located above the dielectric layer, and a support layer located above the carbon nanotube; forming a sacrificial gate structure over the fin structure; forming an isolation insulating layer over the sacrificial gate structure and the fin structure; Forming a source / drain opening exposing a portion of the fin structure by patterning the isolation insulating layer; removing the support layer from each of the plurality of stacked structures in the source / drain openings; as well as forming a source / drain contact layer in the source / drain opening, The source / drain contacts are formed such that the source / drain contacts are in direct contact with only a portion of the carbon nanotubes, and a portion of the dielectric layer is disposed between the source / drain contacts and the carbon nanotubes.

2. The method according to claim 1, wherein: The interior of the portion of the dielectric layer includes a fixed positive charge that induces a negative charge in the carbon nanotubes.

3. The method according to claim 1, wherein: The dielectric layer is made of non-stoichiometric silicon nitride.

4. The method according to claim 1, wherein: The dielectric layer includes a first dielectric layer in contact with the carbon nanotubes and a second dielectric layer formed on the first dielectric layer, and In the portion of the dielectric layer, the first dielectric layer and the second dielectric layer constitute an interfacial dielectric dipole structure, and the interfacial dielectric dipole structure induces negative charges in the carbon nanotubes.

5. The method according to claim 4, wherein: The first dielectric layer is made of aluminum oxide, and the second dielectric layer is made of hafnium oxide.

6. The method according to claim 1, wherein: The dielectric layer includes a first dielectric layer in contact with the carbon nanotubes, a second dielectric layer disposed above the first dielectric layer, and a third dielectric layer disposed above the second dielectric layer, and In the portion of the dielectric layer, the first to third dielectric layers constitute an interfacial dielectric dipole structure, and the interfacial dielectric dipole structure induces positive charges in the carbon nanotubes.

7. The method according to claim 6, wherein: The first dielectric layer is made of aluminum oxide, the second dielectric layer is made of silicon oxide, and the third dielectric layer is made of aluminum oxide.

8. The method according to claim 1, wherein: In cross section, the portion of the dielectric layer covers 25% to 90% of a circumference of the carbon nanotube.

9. The method of claim 1 , further comprising, after forming the source / drain contacts: forming a gate spacer by removing the sacrificial gate structure; removing the dielectric layer and the support layer in the gate gap so that the carbon nanotubes are exposed in the gate gap; A gate dielectric layer is formed around the carbon nanotubes, and a gate electrode is formed over the gate dielectric layer. 10 . The method of claim 9 , further comprising, after removing the support layer and before forming the source / drain contacts, forming an insulating inner spacer at an end of the support layer under the sacrificial gate structure.

11. The method according to claim 10, wherein: When removing the dielectric layer and the support layer in the gate spacer, a portion of the dielectric layer disposed between the insulating inner spacer and the carbon nanotubes is removed.

12. The method according to claim 11, wherein: When removing the dielectric layer and the support layer in the gate spacers, portions of the dielectric layer disposed between the source / drain contacts and the carbon nanotubes are removed.

13. The method according to claim 11, wherein: The support layer is made of a dielectric material different from that of the dielectric layer.

14. The method according to claim 1, wherein: A plurality of carbon nanotubes is included in each of the plurality of stacked structures.

15. The method according to claim 1, wherein: The support layer is made of a polycrystalline or amorphous material of one of Si, Ge and SiGe.

16. A method for forming a gate-all-around field effect transistor, the method comprising: forming a fin structure over the substrate, wherein the carbon nanotubes are embedded in a supporting material; forming a sacrificial gate structure over the fin structure; forming an insulating layer over the sacrificial gate structure and the fin structure; removing the sacrificial gate structure so that a portion of the fin structure is exposed; removing the support material from the exposed portion of the fin structure so that the channel region of the carbon nanotube is exposed; forming a gate structure around the exposed channel region of the carbon nanotube; forming source / drain openings in the insulating layer; Removing the support material in the source / drain openings to expose the source / drain regions of the carbon nanotubes; forming a dielectric layer around the exposed carbon nanotubes in the source / drain openings; partially removing the dielectric layer so that portions of the dielectric layer remain on the carbon nanotubes in the source / drain openings; and forming a source / drain contact layer in the source / drain opening, The source / drain contacts are formed such that the source / drain contacts are in direct contact with a portion of the carbon nanotubes, and a remaining portion of the dielectric layer is disposed between the source / drain contacts and the carbon nanotubes.

17. The method according to claim 16, wherein: The portion of the dielectric layer is a single dielectric layer having a fixed positive charge inside.

18. The method of claim 16, wherein: The dielectric layer includes a first dielectric layer in contact with the carbon nanotubes and a second dielectric layer formed on the first dielectric layer, and In the remaining portion of the dielectric layer, the first dielectric layer and the second dielectric layer constitute a dielectric dipole structure.

19. The method according to claim 16, wherein: In cross section, the remaining portion of the dielectric layer covers 25% to 90% of the circumference of each of the carbon nanotubes.

20. A semiconductor device having a gate-all-around field effect transistor, comprising: carbon nanotubes disposed above the substrate; a gate structure formed around the carbon nanotubes in the channel region; as well as Source / drain contacts are formed around the carbon nanotubes in the source / drain regions, wherein: The source / drain contacts are in direct contact with only a portion of the carbon nanotubes, and a dielectric layer partially covers the carbon nanotubes and is disposed between the source / drain contacts and the carbon nanotubes, The dielectric layer is a single-layer structure, and the dielectric layer of the single-layer structure has a fixed charge, so that mobile charges with opposite polarities are induced in the carbon nanotubes in the source / drain region. Alternatively, the dielectric layer is a multi-layer structure, and the dielectric layers of the multi-layer structure form an interface dielectric dipole structure, and the interface dielectric dipole structure induces positive mobile charges or negative mobile charges in the carbon nanotubes in the source / drain region.

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