A Phase-Locked Loop Circuit with High Power Supply Noise Rejection Ratio

Abstract

The present invention discloses a phase-locked loop circuit with a high power supply noise suppression ratio, comprising: a phase frequency detector, a charge pump, a loop filter and a frequency divider, and also comprising: a self-calibration frequency circuit and a power supply noise suppression voltage-controlled oscillator, wherein the output end of the phase frequency detector is connected to the input end of the charge pump; the output end of the charge pump is connected to the input end of the loop filter and the first input end of the power supply noise suppression voltage-controlled oscillator; the output end of the power supply noise suppression voltage-controlled oscillator is used as the circuit signal output end and connected to the input end of the frequency divider; the output end of the frequency divider outputs a feedback clock to one input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock. The present invention solves the problems of excessive area consumption and narrow tuning range in the existing power supply noise suppression technology.

Description

Technical Field

[0001] The invention relates to a phase locked loop circuit. Background Art

[0002] Phase-locked loop technology has been widely used in the communication field and almost all digital systems to generate clocks. With the improvement of process technology and the decrease of power supply voltage, the design of phase-locked loops has become more and more stringent, mainly including low jitter output, small footprint, wide tuning range and high suppression of power supply noise in order to be used in very large-scale integrated circuit systems.

[0003] like Figure 2 As shown in the figure, the traditional phase-locked loop circuit is mainly composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a divider. The specific working principle is that the phase frequency detector can identify the frequency and phase difference between the input reference clock (REFCLK) and the feedback clock (FBCLK). The difference can be converted into a charge and discharge current through the charge pump, and then the voltage control signal VCTRL of the voltage-controlled oscillator is output through the loop filter. The voltage-controlled oscillator generates a clock signal CKOUT based on the loop parameters according to the input voltage signal.

[0004] In chips with large-scale digital circuits, in order to achieve smaller output jitter characteristics under poor power supply noise conditions, two methods are often used to design phase-locked loop circuits. The first is to use an LC oscillator with low jitter output, but the VCO based on the LC architecture consumes a lot of area and power. Another method is to use power modulation phase-locked loop technology based on linear regulators, but due to its limited input control voltage range, the tuning range is relatively narrow, which does not meet the current requirements for wide tuning range in large-scale integrated circuits. Summary of the invention

[0005] The object of the present invention is to provide a phase-locked loop circuit with a high power supply noise suppression ratio, so as to solve the problems of excessive area and power consumption and narrow tuning range in the existing power supply noise suppression technology.

[0006] The technical solution to achieve the above purpose is:

[0007] A phase-locked loop circuit with high power supply noise suppression ratio comprises: a frequency detector, a charge pump, a loop filter and a frequency divider, and also comprises: a self-calibration frequency circuit and a power supply noise suppression voltage-controlled oscillator.

[0008] The output end of the frequency and phase detector is connected to the input end of the charge pump;

[0009] The output end of the charge pump is connected to the input end of the loop filter and the first input end of the power supply noise suppression voltage controlled oscillator;

[0010] The output end of the power supply noise suppression voltage-controlled oscillator serves as a circuit signal output end and is connected to the input end of the frequency divider;

[0011] The output end of the frequency divider outputs a feedback clock to an input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock;

[0012] The two input ends of the self-calibration frequency circuit receive the feedback clock and the reference clock respectively, and the output end is connected to the second input end of the power supply noise suppression voltage-controlled oscillator.

[0013] Preferably, the self-calibration frequency circuit comprises: a frequency detector and a state machine control unit,

[0014] The two input ends of the frequency detector receive the feedback clock and the reference clock respectively, and the output end is connected to the input end of the state machine control unit. The output end of the state machine control unit is connected to the second input end of the power supply noise suppression voltage controlled oscillator.

[0015] Preferably, the power supply noise suppression voltage-controlled oscillator comprises: an operational amplifier, a PMOS tube, a K-bit current source array circuit, a resistor, a capacitor and a delay cell (DELAY CELL), wherein:

[0016] The inverting input terminal of the operational amplifier serves as the first input terminal of the power supply noise suppression voltage-controlled oscillator, and the non-inverting input terminal is grounded through the resistor;

[0017] The output end of the operational amplifier is connected to the gate of the PMOS tube and the first input end of the K-bit current source array circuit respectively;

[0018] The second input end of the K-bit current source array circuit serves as the second input end of the power supply noise suppression voltage-controlled oscillator;

[0019] The source of the PMOS tube is connected to the gate of the PMOS tube through the capacitor on one hand, and connected to the power supply on the other hand; the drain of the PMOS tube is grounded through the resistor;

[0020] The output end of the K-bit current source array circuit is connected to the input end of the delay unit, and the output end of the delay unit serves as the output end of the power supply noise suppression voltage-controlled oscillator.

[0021] Preferably, the inverting input terminal of the operational amplifier receives the output of the loop filter;

[0022] The K-bit current source array circuit receives the code K output by the self-calibration frequency circuit and switches the band of the VCO;

[0023] The delay unit outputs a clock signal.

[0024] The beneficial effects of the present invention are as follows: the present invention is based on the traditional phase-locked loop circuit architecture, combined with the self-calibration frequency circuit (AFC) and the power supply noise suppression voltage-controlled oscillator (SRVCO) circuit design, which can achieve a smaller KVCO (VCO gain) under the condition of a wide tuning range, and adapt to the requirements of the latest large-scale integrated circuits for a wide output range of the phase-locked loop. And through the voltage-controlled oscillator with power supply noise suppression capability, the performance of improving the output jitter (Jitter) by about 2-5 times compared with the traditional architecture is achieved, which has a great advantage in suppressing power supply noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural diagram of a phase-locked loop circuit of the present invention;

[0026] Figure 2 It is a phase-locked loop circuit structure diagram in the prior art;

[0027] Figure 3 is a comparison diagram of the characteristics of the voltage controlled oscillator KVCO using the AFC technology and not using the AFC technology in the present invention;

[0028] Figure 4 The invention discloses a circuit diagram of a voltage-controlled oscillator for suppressing power supply noise. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings.

[0030] See also Figure 1 and Figure 3 The phase-locked loop circuit with high power supply noise suppression ratio of the present invention comprises: a frequency detector 1, a charge pump 2, a loop filter 3, a frequency divider 4, a self-calibration frequency circuit 5 and a power supply noise suppression voltage-controlled oscillator 6.

[0031] The output end of the frequency detector 1 is connected to the input end of the charge pump 2; the output end of the charge pump 2 is connected to the input end of the loop filter 3 and the first input end of the power supply noise suppression voltage controlled oscillator 6; the output end of the power supply noise suppression voltage controlled oscillator 6 serves as the circuit signal output end and is connected to the input end of the frequency divider 4.

[0032] The output terminal of the frequency divider 4 outputs the feedback clock FBCLK to one input terminal of the phase frequency detector 1, and the other input terminal of the phase frequency detector 1 receives the reference clock REFCLK.

[0033] Two input terminals of the self-calibration frequency circuit 5 receive the feedback clock FBCLK and the reference clock REFCLK respectively, and the output terminal is connected to the second input terminal of the power supply noise suppression voltage-controlled oscillator 6 .

[0034] The self-calibration frequency circuit 5 includes: a frequency detector (Frequency Detector, FD) and a state machine control (State Machine) unit. The two input ends of the frequency detector receive the feedback clock FBCLK and the reference clock REFCLK respectively, and the output end is connected to the input end of the state machine control unit, and the output end of the state machine control unit is connected to the second input end of the power supply noise suppression voltage-controlled oscillator 6.

[0035] For phase-locked loops used in large-scale digital integrated circuit systems, power supply noise is the main factor limiting the performance of ring oscillator phase-locked loops. With the advancement of technology, it is hoped that the phase-locked loop can cover a wider tuning range, which will require a larger KVCO. The increased KVCO will directly affect the ability of the entire phase-locked loop to suppress power supply noise, as shown in Formula 1. It is easy to deduce from the formula that reducing KVCO can directly reduce the impact of power supply noise on the output clock jitter performance.

[0036] ---Formula 1

[0037] Among them, KVCO represents the gain of VCO; Icp represents the charge and discharge current of the charge pump; N represents the divider ratio; H LPF (s) represents the transfer function of the loop filter; V DD (s) refers to the power supply voltage input signal; Φ out (s) refers to the phase signal of the output clock.

[0038] Therefore, the present invention adopts the self-calibration frequency technology (AFC) to expand the tuning range of the entire voltage-controlled oscillator, and a smaller KVCO can be achieved in a single BAND (band), such as Figure 3 As shown in the figure, KVCO and the suppression capability of the phase-locked loop power supply noise are inversely proportional, that is, the smaller KVCO is, the stronger the phase-locked loop's suppression capability of power supply noise is, and the better the clock performance of the entire phase-locked loop output is.

[0039] like Figure 4 As shown, the power supply noise suppression voltage controlled oscillator 6 includes: an operational amplifier A1, a PMOS tube M1, a K-bit current source array circuit M2, a resistor R1, a capacitor C1 and a delay unit 61.

[0040] The inverting input terminal of the operational amplifier A1 serves as the first input terminal of the power supply noise suppression voltage controlled oscillator 6, and the non-inverting input terminal is grounded through the resistor R1. The output terminal of the operational amplifier A1 is respectively connected to the gate of the PMOS tube M1 and the first input terminal of the K-bit current source array circuit M2. The second input terminal of the K-bit current source array circuit M2 serves as the second input terminal of the power supply noise suppression voltage controlled oscillator 6. The source of the PMOS tube M1 is connected to the gate of the PMOS tube M1 through the capacitor C1 on the one hand, and to the power supply VDD on the other hand; the drain of the PMOS tube M1 is grounded through the resistor R1. The output terminal of the K-bit current source array circuit M2 is connected to the input terminal of the delay unit 61, and the output terminal of the delay unit 61 serves as the output terminal of the power supply noise suppression voltage controlled oscillator 6.

[0041] The inverting input terminal of the operational amplifier A1 receives the output VCTRL of the loop filter. The delay unit 61 outputs the clock signal CKOUT. The operational amplifier A1, the PMOS tube M1, the resistor R1 and the capacitor C1 constitute a voltage-to-current circuit for generating the supply current of the delay unit 61. The K-bit current source array circuit M2 receives the code K output by the self-calibration frequency circuit 5 to realize the Band switching of multiple VCOs, which can effectively reduce the KVCO of the entire power supply noise suppression voltage-controlled oscillator 6. In the figure, V ICO is the output of the K-bit current source array circuit M2.

[0042] The basic principle is to ensure that the gate-source voltage of the linear regulator remains constant through feedforward capacitor coupling, so that the output drain current is not affected by power supply noise, and the current mirrored to the DELAYCELL is not affected by the power supply voltage, which can achieve better high-frequency power supply suppression capability. At the same time, the low-frequency power supply noise capability is determined by the entire linear regulator loop gain. The specific formula is as follows:

[0043] ---Formula 2

[0044] Among them, K represents the gain control bit of the AFC output; Gm2 represents the transconductance value of a single MOS tube in the current array; R ICO represents the equivalent output resistance of the delay unit 61 during oscillation; LOOP(s) represents the loop gain of the linear regulator with feedforward cancellation technology.

[0045] From the above derivation process, it can be seen that compared with the traditional linear modulator voltage-controlled oscillator technology, the voltage-controlled oscillator with power supply suppression capability can attenuate the power supply noise by times the loop gain, thereby improving the VCO's ability to suppress power supply noise. Through simulation, a power supply noise suppression effect of more than 30dB can be achieved.

[0046] In summary, the present invention combines the self-calibration frequency technology and the circuit structure of the voltage-controlled oscillator with power supply suppression capability, which can effectively improve the jitter performance of the output clock signal by 2-5 times and has a great advantage in suppressing power supply noise. The simulation results are shown in the following table.

[0047]

[0048] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the relevant technical field may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by the claims.

Claims

1. A phase-locked loop circuit with high power supply noise rejection ratio, comprising: The invention relates to a frequency detector, a phase detector, a charge pump, a loop filter and a frequency divider, characterized in that it also includes: a self-calibration frequency circuit and a power supply noise suppression voltage-controlled oscillator, The output end of the frequency and phase detector is connected to the input end of the charge pump; The output end of the charge pump is connected to the input end of the loop filter and the first input end of the power supply noise suppression voltage controlled oscillator; The output end of the power supply noise suppression voltage-controlled oscillator serves as a circuit signal output end and is connected to the input end of the frequency divider; The output end of the frequency divider outputs a feedback clock to an input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock; The two input ends of the self-calibration frequency circuit receive the feedback clock and the reference clock respectively, and the output end is connected to the second input end of the power supply noise suppression voltage-controlled oscillator; The power supply noise suppression voltage-controlled oscillator comprises: an operational amplifier, a PMOS tube, a K-bit current source array circuit, a resistor, a capacitor and a delay unit, wherein: The inverting input terminal of the operational amplifier serves as the first input terminal of the power supply noise suppression voltage-controlled oscillator, and the non-inverting input terminal is grounded through the resistor; The output end of the operational amplifier is connected to the gate of the PMOS tube and the first input end of the K-bit current source array circuit respectively; The second input end of the K-bit current source array circuit serves as the second input end of the power supply noise suppression voltage-controlled oscillator; The source of the PMOS tube is connected to the gate of the PMOS tube through the capacitor on one hand, and connected to the power supply on the other hand; the drain of the PMOS tube is grounded through the resistor; The output end of the K-bit current source array circuit is connected to the input end of the delay unit, and the output end of the delay unit serves as the output end of the power supply noise suppression voltage-controlled oscillator; The inverting input terminal of the operational amplifier receives the output of the loop filter; The K-bit current source array circuit receives the code K output by the self-calibration frequency circuit and switches the band of the VCO; The delay unit outputs a clock signal.

2. The phase-locked loop circuit with high power supply noise rejection ratio according to claim 1, characterized in that: The self-calibration frequency circuit comprises: a frequency detector and a state machine control unit, The two input ends of the frequency detector receive the feedback clock and the reference clock respectively, and the output end is connected to the input end of the state machine control unit. The output end of the state machine control unit is connected to the second input end of the power supply noise suppression voltage controlled oscillator.

Images