Signal processing method and system thereof

Abstract

The present invention discloses a signal processing system, comprising: a plurality of analog-to-digital converters (ADCs), configured to receive a first sequence and sample the received first sequence to generate a plurality of second sequences, each of the plurality of second sequences corresponding to each of the plurality of ADCs; a sampling point delay compensation module, configured to perform sampling point delay compensation on the plurality of ADCs based on the plurality of second sequences; and a plurality of phase delay compensation modules, configured to perform phase delay compensation on the plurality of ADCs based on the plurality of second sequences.

Description

Technical Field

[0001] The present invention relates to signal processing technology, and more specifically, to a signal processing method and system for simultaneously collecting multi-channel analog signals by multiple analog-digital converters (ADCs). Background Art

[0002] With the rapid development of information technology, people's demand for information is increasing, and the requirements for the speed and accuracy of signal acquisition and processing are also increasing. Today, signal processing systems containing multi-channel ADCs have been widely used in various fields such as radar, missiles, and remote sensing to achieve high-speed data acquisition. However, in such a system, due to the simultaneous use of multiple ADCs, the synchronization between each ADC becomes a crucial factor affecting the accuracy of data acquisition. The more ADCs are used, the greater the challenge of achieving accurate synchronization.

[0003] Existing methods for ADC sampling synchronization include: performing symmetrical complex sampling on a symmetrical channel sequence of analog signal channels; using an ultra-low jitter synchronization clock for sampling synchronization; using the ADC's own synchronization signal plus a delay chip to compensate for the corresponding delay; performing sampling synchronization on the ADC based on a clock distribution chip; etc. However, the degree of synchronization that can be achieved by these synchronization methods is often limited, or only synchronization at the sampling point level, or only synchronization at the phase level, or only synchronization for multiple sampling channels within a single ADC.

[0004] Therefore, there is a need for a signal processing method that can achieve synchronization at both the sampling point level and the phase level, and this method can be applicable to a signal processing system that uses multiple ADCs for sampling to achieve system-level synchronization. Summary of the invention

[0005] In view of the above situation, the present disclosure provides a signal processing method and system for simultaneously acquiring multi-channel analog signals by multiple ADCs.

[0006] On the one hand, according to an embodiment of the present disclosure, a signal processing system is provided, comprising: a plurality of ADCs, configured to receive a first sequence and sample the received first sequence to generate a plurality of second sequences, each of the plurality of second sequences corresponding to each of the plurality of ADCs; a sampling point delay compensation module, configured to perform sampling point delay compensation on the plurality of ADCs based on the plurality of second sequences; and a plurality of phase delay compensation modules, configured to perform phase delay compensation on the plurality of ADCs based on the plurality of second sequences.

[0007] In addition, according to the signal processing system of the embodiment of the present disclosure, the multiple ADCs are further configured to sample multiple analog signals from multiple signal sources respectively.

[0008] In addition, according to an embodiment of the present disclosure, the signal processing system further includes: a first sequence generator configured to generate a first sequence.

[0009] In addition, according to an embodiment of the present disclosure, the signal processing system further includes: a first distributor configured to provide the first sequence to the plurality of ADCs respectively; and a second distributor configured to provide the sampling clock to the plurality of ADCs respectively.

[0010] In addition, according to an embodiment of the present disclosure, the signal processing system further includes: a plurality of switches, each of the plurality of switches corresponding to each of the plurality of ADCs, and configured to select the first sequence from the first distributor or the analog signals from the plurality of signal sources to be provided to a corresponding one of the plurality of ADCs.

[0011] In addition, according to the signal processing system of an embodiment of the present disclosure, the distance from the output port of the first distributor to the input port of each of the multiple ADCs is the same, and the distance from the output port of the second distributor to the input port of each of the multiple ADCs is the same.

[0012] In addition, according to an embodiment of the present disclosure, the signal processing system further includes: a sampling point delay calculation module configured to obtain a sampling point delay corresponding to each of the plurality of ADCs, and provide the obtained sampling point delay to the sampling point delay compensation module.

[0013] In addition, according to the signal processing system of an embodiment of the present disclosure, the sampling point delay calculation module is further configured to: determine one of the multiple second sequences as a reference second sequence; and perform correlation operations on the sampling points of the remaining second sequences except the reference second sequence in the multiple second sequences with the reference second sequence respectively, so as to obtain a sampling point delay corresponding to each of the multiple ADCs, and provide the obtained sampling point delay to the sampling point delay compensation module.

[0014] In addition, according to the signal processing system of the embodiment of the present disclosure, the sampling point delay calculation module is further configured to: determine one of the multiple second sequences as a reference second sequence; estimate the overall sampling point delay of the multiple ADCs; based on the overall sampling point delay, delay the reference second sequence with respect to the sampling point; and perform correlation operations with respect to the sampling points on the remaining second sequences except the reference second sequence in the multiple second sequences and the delayed reference second sequence, respectively, to obtain a sampling point delay corresponding to each of the multiple ADCs, and provide the obtained sampling point delay to the sampling point delay compensation module.

[0015] In addition, according to the signal processing system of an embodiment of the present disclosure, the sampling point delay compensation module is further configured to perform sampling point delay compensation on multiple second sequences based on the obtained sampling point delay to obtain multiple third sequences, each of the multiple third sequences corresponds to each of the multiple ADCs.

[0016] In addition, according to an embodiment of the present disclosure, the signal processing system further includes: a phase delay calculation module configured to obtain a phase delay corresponding to each of the plurality of ADCs, and provide the obtained phase delay to the corresponding phase delay compensation module respectively.

[0017] In addition, according to the signal processing system of an embodiment of the present disclosure, the phase delay calculation module is further configured to: determine one of the multiple third sequences as a reference third sequence; and perform correlation operations on the remaining third sequences of the multiple third sequences except the reference third sequence with the reference third sequence regarding sampling points, so as to obtain a phase delay corresponding to each of the multiple ADCs.

[0018] In addition, according to the signal processing system of an embodiment of the present disclosure, the remaining third sequences in multiple third sequences except the reference third sequence are respectively correlated with the reference third sequence about the sampling point to obtain a phase delay corresponding to each of the multiple ADCs, including: for a corresponding third sequence in the remaining third sequences except the reference third sequence in the multiple third sequences, delaying the corresponding third sequence by different phase amounts to obtain multiple fourth sequences; each of the multiple fourth sequences is respectively correlated with the reference third sequence about the sampling point to obtain multiple correlation peaks; searching for the maximum correlation peak among the multiple correlation peaks, determining the phase amount by which the fourth sequence corresponding to the maximum correlation peak is delayed relative to the corresponding third sequence as the corresponding phase delay; and providing the corresponding phase delay to the corresponding phase delay compensation module.

[0019] In addition, according to the signal processing system of the embodiment of the present disclosure, a corresponding phase delay compensation module delays a corresponding third sequence by different phase amounts to obtain multiple fourth sequences.

[0020] On the other hand, according to an embodiment of the present disclosure, a signal processing method is provided, including: receiving a first sequence; sampling the received first sequence using multiple analog-to-digital converters ADCs to generate multiple second sequences, each of the multiple second sequences corresponding to each of the multiple ADCs; performing sampling point delay compensation on the multiple ADCs based on the multiple second sequences; and performing phase delay compensation on the multiple ADCs based on the multiple second sequences.

[0021] In addition, according to an embodiment of the present disclosure, the signal processing method further includes: using multiple ADCs to sample multiple analog signals from multiple signal sources respectively.

[0022] In addition, according to the signal processing method of an embodiment of the present disclosure, performing sampling point delay compensation on multiple ADCs based on multiple second sequences includes: obtaining a sampling point delay corresponding to each of the multiple ADCs based on the multiple second sequences, and performing sampling point delay compensation on each of the multiple ADCs based on the obtained sampling point delay.

[0023] In addition, according to the signal processing method of an embodiment of the present disclosure, obtaining the sampling point delay corresponding to each of the multiple ADCs includes: determining one of the multiple second sequences as a reference second sequence; and performing correlation operations on the sampling points on the remaining second sequences except the reference second sequence in the multiple second sequences and the reference second sequence respectively, so as to obtain the sampling point delay corresponding to each of the multiple ADCs.

[0024] In addition, according to the signal processing method of an embodiment of the present disclosure, alternatively, obtaining the sampling point delay corresponding to each of the multiple ADCs includes: determining one of the multiple second sequences as a reference second sequence; estimating the overall sampling point delay of the multiple ADCs; delaying the reference second sequence with respect to the sampling point based on the overall sampling point delay; and performing correlation operations on the sampling points on the remaining second sequences except the reference second sequence in the multiple second sequences and the delayed reference second sequence, respectively, to obtain the sampling point delay corresponding to each of the multiple ADCs.

[0025] In addition, according to the signal processing method of an embodiment of the present disclosure, performing phase delay compensation on multiple ADCs based on multiple second sequences includes: based on the obtained sampling point delay, performing sampling point delay compensation on the multiple second sequences respectively to obtain multiple third sequences, each of the multiple third sequences corresponding to each of the multiple ADCs.

[0026] In addition, according to the signal processing method of an embodiment of the present disclosure, performing phase delay compensation on multiple ADCs based on multiple second sequences further includes: obtaining a phase delay corresponding to each of the multiple ADCs based on multiple third sequences, and performing phase delay compensation on each of the multiple ADCs based on the obtained phase delay.

[0027] In addition, according to an embodiment of the present disclosure, obtaining a phase delay corresponding to each of a plurality of ADCs includes: determining one of a plurality of third sequences as a reference third sequence; and performing correlation operations on the remaining third sequences of the plurality of third sequences except the reference third sequence with the reference third sequence regarding sampling points, so as to obtain a phase delay corresponding to each of the plurality of ADCs.

[0028] In addition, according to the signal processing method of an embodiment of the present disclosure, the remaining third sequences in multiple third sequences except the reference third sequence are respectively correlated with the reference third sequence about the sampling point to obtain a phase delay corresponding to each of the multiple ADCs, including: for a corresponding third sequence in the remaining third sequences except the reference third sequence in the multiple third sequences, delaying the corresponding third sequence by different phase amounts to obtain multiple fourth sequences; each of the multiple fourth sequences is respectively correlated with the reference third sequence about the sampling point to obtain multiple correlation peaks; and searching for the maximum correlation peak among the multiple correlation peaks, and determining the phase amount by which the fourth sequence corresponding to the maximum correlation peak is delayed relative to the corresponding third sequence as the corresponding phase delay.

[0029] The method and system according to the embodiments of the present disclosure are simple and effective, and can simultaneously solve the synchronization problems of the sampling point level and the phase level among multiple ADCs used to collect data, without requiring special functional requirements for the ADC or FPGA.

[0030] Specifically, the method and system according to the embodiment of the present disclosure can calculate the sampling point delay amount through an algorithm, and then compensate the sampling point delay through the algorithm. For phase delay, both the algorithm and the algorithm combined with hardware such as a delay line can be used. On the one hand, if the algorithm (for example, time domain cross-correlation operation or FFT-based correlation operation) is fully used to calculate and compensate the phase delay, the calculation and compensation of the sampling point delay and the phase delay can be implemented at the software level, which is convenient and direct. Then the accuracy of the calculation and compensation is mainly limited by the accuracy of the computing device that implements the algorithm or software. On the other hand, if software and hardware (for example, an adjustable delay line) are combined to calculate and compensate the phase delay, the advantages of both can be brought into play at the same time. It can avoid using FFT when calculating the phase delay, reduce the accuracy loss caused by FFT, improve the accuracy of the calculated phase delay, and reduce the ability requirements for the computing device. At the same time, it can also achieve direct high-precision phase delay compensation through the adjustable delay line that can now achieve a fairly high-precision phase delay operation when performing phase delay compensation. Those skilled in the art can freely choose the implementation scheme as needed. Therefore, using the system and method according to the present disclosure, even when multiple ADCs are used, there is benefit in improving synchronization precision and accuracy.

[0031] Therefore, no matter from the software level or the hardware level, the method and system according to the embodiments of the present disclosure have good scalability.

[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Embodiments of the present invention will be better understood from the following detailed description with reference to the accompanying drawings, in which:

[0034] Figure 1 An example of a signal processing system according to an embodiment of the present disclosure is shown;

[0035] Figure 2 An example of a portion for sampling point delay calculation and compensation in a signal processing system according to an embodiment of the present disclosure is shown;

[0036] Figure 3 An example of a portion for phase delay calculation and compensation in a signal processing system according to an embodiment of the present disclosure is shown;

[0037] Figure 4 An example of a portion of a signal processing system operating in a normal operating mode according to an embodiment of the present disclosure is shown;

[0038] Figure 5 An example flow chart of a signal processing method according to an embodiment of the present disclosure is shown;

[0039] Figure 6 An example flow chart of operating mode switching according to an embodiment of the present disclosure is shown;

[0040] Figure 7 An example flow chart showing steps for obtaining sampling point delay according to an embodiment of the present disclosure;

[0041] Figure 8 Another example flow chart showing steps for obtaining sampling point delay according to an embodiment of the present disclosure;

[0042] Fig. 9 An example flow chart showing steps for obtaining phase delay according to an embodiment of the present disclosure;

[0043] Fig.10 An exemplary flow chart showing steps for obtaining the phase delay of each ADC according to an embodiment of the present disclosure; and

[0044] Fig.11An example flow chart of steps for obtaining phase delay in an iterative manner according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0046] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present disclosure, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0047] The present disclosure provides a signal processing system and a method thereof. The system and the method thereof according to the present disclosure can at least bring the following advantages: 1) wide practicability or flexible application, the system and the method thereof according to the present disclosure can be deployed inside a printed circuit board PCB, so that multiple ADCs on the same PCB can be synchronized, and can also be deployed between multiple PCBs, so that multiple ADCs respectively arranged on multiple PCBs can be synchronized; 2) high synchronization accuracy, the synchronization accuracy can depend on the performance of the ADC sampling clock adjustable delay line used in the phase-level synchronization process, the existing commercial adjustable delay line can already use voltage control, and its performance mainly depends on the jitter of the delay line, which can be as low as 0.5ps or less, that is, the synchronization accuracy can reach 0.5ps or better; 3) wide synchronization range, the synchronization adjustment range can depend on the sampling point adjustable delay device (hereinafter referred to as the sampling point delay compensation module) for sampling point-level synchronization, which is only limited by the data buffer size and the repetition period of the test code stream used.

[0048] Figure 1 An example of a signal processing system 10 according to an embodiment of the present disclosure is shown.

[0049] The signal processing system 10 can be configured to calculate the system delay in the synchronous mode, and sample the analog signal based on the calculated system delay in the normal working mode. It can switch between the synchronous mode and the normal working mode. The system delay may include the sampling point delay and phase delay of the digital signal output by the ADC.

[0050] Generally, if Figure 1 As shown, the signal processing system 10 may include a computing device 100 and ADCs 101-1 to 101-X, where X is an integer greater than or equal to 2. The computing device 100 may be used to analyze or process digital signals, etc. For example, the computing device 100 may be configured to calculate sampling point delay and phase delay in a synchronous mode to compensate for the delay, and further configured to further process the acquired digital signals in a normal working mode, etc. The ADCs 101-1 to 101-X may be used to sample input signals for further processing by the computing device 100, such as calculation, analysis, communication, etc. For example, the ADCs 101-1 to 101-X may be used to sample test signals in a synchronous mode, and provide the sampling results to the computing device 100, so that the computing device 100 can analyze the acquired test signals to obtain delay information. For example, ADCs 101-1 to 101-X may also be used to sample analog signals from signal sources 103-1 to 103-X (i.e., analog-to-digital conversion) in a normal operating mode, and provide digital signals converted from the analog signals to computing device 10 for further processing.

[0051] Generally, since multiple ADCs are used at the same time, the synchronization problem between multiple ADCs directly affects the accuracy of multiple digital signals converted from multiple analog signals. In addition, a unified sampling clock can be used to control the sampling synchronization of multiple ADCs. However, due to various factors in time or space, there may be asynchronism when multiple analog signals arrive at multiple ADCs respectively, and asynchronism when sampling clocks arrive at multiple ADCs respectively. This synchronization may not only be in time, but also in space. Therefore, when sampling the analog signals from signal sources 103-1 to 103-X or before sampling the analog signals, ADCs 101-1 to 101-X can be synchronized. The synchronization operation can include compensating for the sampling point asynchronism and phase asynchronism between ADCs 101-1 to 101-X, that is, sampling point delay compensation and phase delay compensation, so that ADCs 101-1 to 101-X reach a synchronized state at both the sampling point level and the phase level.

[0052] refer to Figure 1In one embodiment, the signal processing system 10 may further include a sampling point delay calculation module 1001 , a phase delay calculation module 1002 , a sampling point delay compensation module 1003 and a phase delay compensation module 102 .

[0053] One or more of the sampling point delay calculation module 1001, the phase delay calculation module 1002, the sampling point delay compensation module 1003, and the phase delay compensation module 102 may be implemented by the computing device 100. For example, the computing device 100 may be an integrated circuit such as an FPGA or an ASIC. For example, the computing device 100 may also be a computing device with a processor such as a computer, including but not limited to a personal computer, a tablet computer, a laptop computer, etc. For example, the computing device 100 may also be implemented as a combination of one or more of the various components or devices described above, and may be implemented in a centralized manner or in a distributed manner.

[0054] The sampling point delay calculation module 1001 can be used to calculate the sampling point delay in the synchronization mode, obtain the sampling point delay between the ADCs 101-1 to 101-X caused by various reasons, and provide the obtained sampling point delay to the sampling point delay compensation module 1003. The sampling point delay compensation module 1003 can be used to compensate the sampling point delay of the ADCs 101-1 to 101-X based on the obtained sampling point delay in the normal working mode, so that the sampling point delay of the collected signal is compensated for use in normal working.

[0055] The phase delay calculation module 1002 can be used to calculate the phase delay in the synchronous mode, obtain the phase delay between the ADCs 101-1 to 101-X caused by various reasons, and provide the obtained phase delay to the phase delay compensation module 102. The phase delay compensation module 102 can be used to compensate the phase delay of the ADCs 101-1 to 101-X based on the obtained phase delay in the normal working mode, so that the collected signal does not have a phase delay for normal working. In addition, the sampling point delay compensation module 1003 and the phase delay compensation module 102 can also be used to process the test signal in the synchronous mode so that the phase delay calculation module 1002 calculates the phase delay.

[0056] refer to Figure 1In one embodiment, the signal processing system 10 may further include a clock CLK 107. CLK 107 may be used as a sampling clock for ADCs 101-1 to 101-X in a synchronous mode or a normal working mode. For example, CLK 107 may be generated using an FPGA / ASIC. For example, a dedicated clock source may be used to implement CLK 107, because the jitter performance of the clock generated by FPGA / ASIC is generally large, which may reduce the performance of the ADC. Due to various factors, there may be differences in CLK 107 when it reaches each ADC, so that the sampling of each ADC cannot be strictly synchronized.

[0057] refer to Figure 1 In one embodiment, the signal processing system 10 may further include a test sequence generator, for example, a first sequence generator 1004, for generating a digital signal for testing in a synchronous mode. The digital signal for testing may be received by the ADCs 101-1 to 101-X and converted into a digital signal for processing by the computing device 100. For example, the digital signal for processing by the computing device 100 may be referred to as a second sequence. By analyzing the digital signal converted into the digital signal for processing by the computing device 100, information about the delay of the entire signal processing system 10, including sampling point delay and phase delay, may be obtained. In this way, the sampling point delay and phase delay of the system may be compensated the next time the signal processing system 10 works normally to obtain the required analog signal, so that the obtained digital signal converted from the required analog signal reaches a certain precision and accuracy, and can more truly reflect the characteristics of the analog signal.

[0058] For example, the digital signal used for the test, i.e., the first sequence, can be a PRBS (pseudo-random binary sequence). PRBS is a pseudo-random sequence that contains only 0 and 1. On the one hand, it can be predetermined, and on the other hand, it has the random characteristics (i.e., statistical characteristics) of a certain random sequence. The frequency of CLK 107 and the code rate of the first sequence do not need to be strictly specified. Preferably, for example, the frequency of CLK 107 and the code rate of the first sequence can be set to differ within a range of several times, so that the sampling points have rich waveform jump information, which is convenient for measuring the delay of the system.

[0059] refer to Figure 1In one embodiment, the signal processing system 10 may further include a first distributor 105 and a second distributor 106. The first distributor 105 may be configured to provide the first sequence to the ADCs 101-1 to 101-X, respectively. The second distributor 106 may be configured to provide the sampling clock to the ADCs 101-1 to 101-X, respectively. For example, the first distributor 105 and the second distributor 106 may be implemented by a device such as an RF Power Splitter or a Clock Fanout.

[0060] In one example, the distance from the output port of the first distributor 105 to the input port of each of the ADCs 101-1 to 101-X can be set to be the same, and the distance from the output port of the second distributor 106 to the input port of each of the ADCs 101-1 to 101-X can be set to be the same. In this way, the delay problem caused by hardware settings can be minimized. In this way, at least the delay caused by the physical layout between the first distributor 105, the second distributor 106, and the ADCs 101-1 to 101-X can be reduced, and the phase offset of the sampling clock of each ADC can be made as small as possible, and the time delay between each ADC caused by the difference in physical routing can be avoided.

[0061] refer to Figure 1 In one embodiment, the signal processing system 10 may further include a plurality of switches 104-1 to 104-X. Each of the plurality of switches 104-1 to 104-X is respectively coupled to the first distributor 105 and a corresponding one of the plurality of signal sources 103-1 to 103-X at the same time. For example, each of the plurality of switches 104-1 to 104-X may be configured to select the first sequence from the first distributor 105 or the analog signal from the corresponding signal source to provide to a corresponding one of the ADCs 101-1 to 101-X. For example, the switch may be implemented by a device such as an RF switch, an analog switch, or a relay.

[0062] In one example, multiple switches 104-1 to 104-X can be controlled to simultaneously enable the first sequence, so that the signal processing system 10 enters a synchronous mode to obtain the delay of the signal processing system 10 so as to perform corresponding delay compensation. In another example, multiple switches 104-1 to 104-X can be controlled to simultaneously enable analog signals, so that the signal processing system 10 enters a normal working mode. That is, through the coordinated operation of multiple switches 104-1 to 104-X, the signal processing system 10 can be flexibly switched between a synchronous mode for obtaining system delay and a normal working mode for sampling analog signals. For example, multiple switches 104-1 to 104-X can be controlled by the computing device 100.

[0063] Continue to refer Figure 1 As mentioned above, the sampling point delay calculation module 1001 can be used to calculate the sampling point delay in the synchronous mode, the sampling point delay compensation module 1003 can be used to perform sampling point delay compensation in the normal working mode, the phase delay calculation module 1002 can be used to calculate the phase delay in the synchronous mode, the phase delay compensation module 1002 can be used to perform phase delay compensation in the normal working mode, and the sampling point delay compensation module 1003 and the phase delay compensation module 1002 can also be used to process the test signal in the synchronous mode so that the phase delay calculation module 1002 calculates the phase delay. The functions that can be implemented by each module in different modes are described in detail below.

[0064] As mentioned above, the sampling point delay calculation module 1001 can be used to calculate the sampling point delay of the signal processing system 10 in the synchronous mode.

[0065] Specifically, in the synchronous mode, after the digital signal for testing (i.e., the first sequence) is converted into a digital signal (i.e., the second sequence) for processing by the computing device 100 via the first distributor 105, the corresponding switch 104, and the corresponding ADC 101, the sampling point delay calculation module 1001 can analyze the multiple second sequences to obtain the corresponding sampling point delay. The number of the multiple second sequences is consistent with the number of ADCs, and the multiple second sequences correspond to the ADCs 101-1 to 101-X one by one. Moreover, each of the multiple second sequences corresponds to the delay characteristics of a corresponding ADC among the ADCs 101-1 to 101-X.

[0066] In one example, the sampling point delay calculation module 1001 may be configured to obtain the sampling point delays corresponding to the ADCs 101-1 to 101-X by correlation operations. Specifically, the sampling point delay calculation module 1001 may be configured to: receive multiple second sequences; determine one of the multiple second sequences as a reference second sequence; and perform correlation operations on the sampling points on the remaining second sequences except the reference second sequence in the multiple second sequences with the reference second sequence, that is, calculate the time delays between the multiple second sequences. Through such operations, the sampling point delays corresponding to each of the ADCs 101-1 to 101-X may be obtained.

[0067] In this example, one of the multiple second sequences is determined as the benchmark second sequence for correlation operation. Compared with generating a new sequence as the benchmark sequence, or compared with taking the first sequence as the benchmark, selecting one of the existing multiple second sequences as the benchmark for correlation operation has the advantage of not consuming additional resources, relatively small amount of calculation, and relatively fast calculation speed.

[0068] Continuing with this example, more specifically, the plurality of second sequences may be represented as P1 to P X , P1 to P X The second sequence P1 output by the first ADC can be determined as the reference second sequence, and then the second sequences P2 to P3 output by the second to Xth ADCs can be determined as the reference second sequence. X (The second sequence except P1) performs correlation operations with P1 on the sampling points in sequence (i.e., from P2 to P1 to P X with P1).

[0069] In this X In the correlation operation with P1, for example, if the result of the correlation operation does not show a correlation peak, P X Delay one sampling point. Then, compare P1 with P after delaying one sampling point. X The correlation operation about the sampling point is performed again. And so on, until the correlation peak appears. According to the principle of correlation operation, the appearance of the correlation peak indicates that P1 and P X The same or close to the same. Therefore, when the correlation peak appears, P X The number of delayed sampling points (for example, the number of delayed sampling points is Y, where Y is a positive integer) is P X The sampling point delayed relative to P1. In other words, the sampling point of the Xth ADC is delayed by Y relative to the sampling point of the 1st ADC.

[0070] However, in the above-mentioned correlation operation on the sampling point, there may be such a situation that the selected reference second sequence, for example, P1 output by the first ADC, is not included in all the second sequences P1 to P X The fastest one is the second sequence P2 to P2 relative to other ADC outputs. X There is no delay. Then, in this case, when the correlation operation is performed, the second sequence P2 to P X No matter how many sampling points are delayed, the correlation operation result cannot produce a correlation peak. Therefore, the selected reference second sequence P1 can be delayed appropriately in time (i.e., delayed with respect to sampling points) before performing the correlation operation to effectively avoid the situation where no correlation peak can be obtained.

[0071] Therefore, for the above situation, alternatively, the sampling point delay calculation module 1001 can obtain the sampling point delay corresponding to the corresponding ADC 101 in the following manner in the synchronous mode. Specifically, the sampling point delay calculation module 1001 can be configured in the synchronous mode to: receive a plurality of second sequences P1 to P X ; Multiple second sequences P1 to P X one of the plurality of second sequences P1 to P1 is determined as a reference second sequence; estimating the overall sampling point delay of ADCs 101-1 to 101-X; delaying the reference second sequence with respect to the sampling point based on the overall sampling point delay; and X The second sequences except the reference second sequence in the above embodiment are respectively correlated with the delayed reference second sequence about the sampling points, that is, a plurality of second sequences P1 to P X Through such operation, the sampling point delay corresponding to each of the ADCs 101-1 to 101-X can be obtained.

[0072] Regarding the overall sampling point delay, on the one hand, the overall sampling point delay can be a system-level sampling point delay attributed to various factors related to various aspects of the entire system. For example, the overall sampling point delay can be represented by the maximum sampling point delay that differs between various ADCs. Alternatively, the overall sampling point delay can be represented by the average sampling point delay that differs between various ADCs. In addition, the order of magnitude of the overall sampling point delay can be the same as the order of magnitude of the actual ADC sampling point delay, and the present invention is not limited thereto. In this way, after the reference second sequence is subjected to the overall sampling point delay, the above-mentioned situation in which the correlation peak cannot be obtained hardly occurs or does not occur.

[0073] On the other hand, the factors that affect the overall sampling point delay may be hardware factors, software factors, or other factors such as environmental factors. For example, the delay may be caused by the different aging degrees of each ADC, or by the different models of each ADC. For example, the delay may be caused by the cables connecting the various components in the system or by the routing of the printed circuit board (PCB). In other words, the delay may be related to the layout of the system, which depends on the specific implementation of the system. For another example, the delay may be caused by the non-uniformity of environmental changes, including various factors such as temperature and humidity that can affect the characteristics of each hardware constituting the system. Environmental factors may be more obvious when the various components constituting the system are distributed. Therefore, the overall sampling point delay can be estimated based on an empirical model or empirical values ​​containing the above-mentioned various factors.

[0074] In one example, when calculating the sampling point delay, the selection of the reference second sequence may be a fixed selection (eg, a selection based on a certain fixed condition). In another example, when calculating the sampling point delay, the selection of the reference second sequence may be a random selection.

[0075] As mentioned above, the sampling point delay calculation module 1001 can provide the calculated sampling point delay to the sampling point delay compensation module 1003 in the synchronous mode.

[0076] The sampling point delay calculated by the sampling point delay calculation module 1001 corresponds to each of the ADCs 101-1 to 101-X one by one. For example, the sampling point delay calculation module 1001 can generate a table or any other form of data structure that records the mapping relationship between the sampling point delay and the address (or mark such as ID) of each ADC, and store it in, for example, a memory or storage unit.

[0077] Furthermore, the sampling point delay calculation module 1001, for example, can also perform standardization processing on each sampling point delay, and then store it or directly use it to compensate for the sampling point delay. In one example, taking P1 as the reference, it is stipulated that negative numbers are advanced and positive numbers are lagging, and the calculated sampling point delays of P1 to P4 are 0, -1, +1, and +2 respectively. Now, the output of the 4th ADC with the largest delay (i.e., P4) is used as the reference for standardization processing, and the standardized sampling point delays of P1 to P4 are -2, -3, -1, and 0 respectively. In this way, it is only necessary to perform corresponding delay operations on the remaining ADCs (without the need for sampling point advance operations) to compensate for the corresponding sampling point delays, and a single delay operation is simple and easy to implement. In this example, the sampling point delay compensation can be completed after the 1st ADC to the 4th ADC corresponding to P1 to P4 are delayed by +2, +3, +1, and 0 sample points respectively.

[0078] As mentioned above, the sampling point delay compensation module 1003 can be used to compensate the sampling point delays of the ADCs 101-1 to 101-X based on the sampling point delays obtained from the sampling point delay calculation module 1001 in the normal working mode.

[0079] Specifically, based on the sampling point delay calculation module 1001 having obtained the sampling point delay, the sampling point delay compensation module 1003 can be configured to, in the normal working mode, retrieve the corresponding sampling point delay from the memory or storage unit according to the address of the ADC each time after receiving the digital signal converted from the analog signal from the signal source from each of the ADCs 101-1 to 101-X, and use the corresponding sampling point delay to compensate the received digital signal. For example, such compensation can be implemented by calculation and can be implemented by the computing device 100. In other words, the sampling point delay compensation can be performed at the output end of the ADC (e.g., the computing device 100 at the output end of the ADC).

[0080] As described above, the phase delay calculation module 1002 can be used to calculate the phase delay of the signal processing system 10 in the synchronous mode. In addition, the sampling point delay compensation module 1003 and the phase delay compensation module 102 can be used to process the test signal in the synchronous mode so that the phase delay calculation module 1002 calculates the phase delay. That is, in the synchronous mode, the phase delay calculation module 1002 cooperates with the sampling point delay compensation module 1003 and the phase delay calculation module 1002 to calculate the phase delay.

[0081] Specifically, in the synchronous mode, after the digital signal for testing (i.e., the first sequence) is converted into a digital signal (i.e., the second sequence) for processing by the computing device 100 via the first distributor 105, the corresponding switch 104, and the corresponding ADC 101, the computing device 100 can analyze the multiple second sequences to obtain the corresponding phase delays. X There is a one-to-one correspondence between ADCs 101-1 to 101-X. Also, a plurality of second sequences P1 to P X Each of corresponds to the delay characteristic of a corresponding one of the ADCs 101 - 1 to 101 -X.

[0082] In one example, the phase delay calculation module 1002 may obtain the phase delay corresponding to the corresponding ADC 101 through a correlation operation.

[0083] In this example, the sampling point delay compensation module 1003 may be configured to compensate the plurality of second sequences P1 to P2 based on the obtained sampling point delay in the synchronization mode. XSampling point delay compensation is performed respectively to obtain corresponding multiple third sequences T1 to T X . A plurality of third sequences T1 to T X The sampling point delays between each other are eliminated, and synchronization at the sampling point level is achieved. Next, the phase delay calculation module 1002 can calculate the phase delay of the plurality of third sequences T1 to T X A phase correlation operation is performed to obtain information about the phase delay of the signal processing system. In addition, in the synchronous mode, in order to calculate the phase delay, each time the test signal is processed by the ADC, the sampling point delay compensation module 1003 can be used to compensate the test signal so that the compensated test signal basically only has a phase delay, so that the phase delay calculation module 1002 can calculate or analyze the phase.

[0084] In this example, the phase delay calculation module 1002 may be configured to obtain the respective phase delays corresponding to the ADCs 101-1 to 101-X by correlation operation. Specifically, the phase delay calculation module 1002 may be configured to receive a plurality of third sequences T1 to T2 in the synchronization mode. X ; Multiple third sequences T1 to T X One of the plurality of third sequences T1 to T X The remaining third sequences except the reference third sequence are respectively subjected to phase correlation operation with the reference third sequence, that is, the respective phase delays between the plurality of third sequences are calculated. Through such operation, the phase delay corresponding to each of the ADCs 101-1 to 101-X can be obtained.

[0085] Specifically, the phase delay calculation module 1002 can implement the above-mentioned phase-related operations in different ways.

[0086] In one example, in the synchronization mode, the phase delay calculation module 1002 can calculate the phase delay of the plurality of third sequences T1 to T X Perform FFT operation to extract the phase information of its frequency, and then perform FFT operation on multiple third sequences T1 to T X A phase-related operation is performed to obtain a corresponding phase delay. For example, this operation can be implemented by a computing device at the ADC output. The phase can be directly analyzed using an FFT operation. In this way, the phase delay calculation module 1002 does not need to cooperate with other modules or hardware.

[0087] In another example, the phase delay calculation module 1002 can cooperate with other hardware (eg, the phase delay compensation module 102) in a synchronous mode to directly calculate the phase delay of the plurality of third sequences T1 to T2 by using other hardware. XThe phase delay of the phase-controlled third sequence T1 to T is physically controlled, so that the phase delay calculation module 1002 can calculate the phase delay of the third sequence T1 to T X The above phase delay calculation implemented by hardware can reduce the amount of calculation of the computing device 100 and distribute the pressure of the hardware capability requirement to other parts of the signal processing system 10.

[0088] Generally, the phase delay compensation module 102 can be connected between the computing device 100 and the ADC 101 to adjust the phase delay of the plurality of sampling clocks CLK 107 received from the second distributor 106. This adjustment can be the control of the CLK 107 at the ADC input end, because the reference Figure 1 It can be known that the phase asynchrony between ADC 101-1 to 101-X is mainly caused by the difference in the transmission path from CLK 107 to ADC 101-X and the individual differences of each component. Further, the phase delay compensation module 102 can be composed of X phase delay compensation submodules 102-1 to 102-X corresponding to ADC 101-1 to 101-X. Further, the phase delay compensation submodules 102-1 to 102-X can be implemented as adjustable delay lines. The adjustable delay line can achieve a phase delay operation with a relatively high precision. In addition, the adjustable delay line can achieve high-precision program control, so that the accuracy of the control of the phase delay can also reach a very high level.

[0089] In one example, the phase delay calculation module 1002 may be configured to obtain a plurality of third sequences T1 to T2 from the sampling point delay compensation module 1003 in a synchronous mode. X , then: multiple third sequences T1 to T X One of the plurality of third sequences T1 to T X The remaining third sequences except the reference third sequence in the above embodiment respectively perform correlation operation on the sampling points with the reference third sequence to obtain the phase delay corresponding to each of the ADCs 101-1 to 101-X. Here, the principle of the correlation operation on the sampling points may be the same as the principle of the correlation operation for calculating the sampling point delays described above.

[0090] Specifically, combined Figure 1 , multiple third sequences T1 to T X The third sequences except the reference third sequence in the above embodiment respectively perform correlation operations on the sampling points with the reference third sequence to obtain a phase delay corresponding to each of the ADCs 101-1 to 101-X, which may further include: for the plurality of third sequences T1 to T XA corresponding third sequence among the remaining third sequences except the reference third sequence is sent to a corresponding phase delay compensation submodule to obtain a plurality of fourth sequences F1 to F N . The fourth sequence F1 to F N The third sequence corresponds to the phases delayed by 1, 2, ..., N units respectively by the phase delay compensation submodule, wherein N is an integer greater than or equal to 2, and the phase delayed by N units is equal to delaying one cycle (ie, 360°).

[0091] Then, the phase delay calculation module 1002 may calculate the phase delay of the plurality of fourth sequences F1 to F N Specifically, the phase delay calculation module 1002 can calculate each of the plurality of fourth sequences F1 to F N A correlation operation is performed on the sampling points with the reference third sequence to obtain a plurality of correlation peaks.

[0092] Alternatively, refer to Figure 1 As described above, a corresponding phase delay compensation submodule processes a corresponding third sequence to obtain a plurality of fourth sequences F1 to F N Afterwards, a plurality of fourth sequences F1 to F N The sampling point delay compensation module 1003 may be configured to convert the received plurality of fourth sequences F1 to F1 based on the sampling point delay obtained by the previous calculation. N The corresponding sampling point delay compensation is performed so that the plurality of fourth sequences F1 to F N The sampling point delay generated by the ADC processing is compensated. In this case, the phase delay calculation module 1002 can be configured to receive a plurality of fourth sequences F1 to F1 after sampling point delay compensation from the sampling point delay compensation module 1003. N Then, the compensated fourth sequences F1 to F N Correlation operations on sampling points are performed respectively with the reference third sequence to obtain multiple correlation peaks.

[0093] Based on the multiple correlation peaks obtained, the phase delay calculation module 1002 can also be configured to search for the maximum correlation peak among the multiple correlation peaks, determine the phase amount by which the fourth sequence corresponding to the maximum correlation peak is delayed relative to a corresponding third sequence as the corresponding phase delay, and provide the corresponding phase delay to a corresponding one of the phase delay compensation sub-modules 102-1 to 102-X.

[0094] The above correlation operation for obtaining phase delay is essentially the same as the correlation operation for obtaining sampling points described in detail above, but in terms of implementation, it is implemented with the help of the phase delay compensation module 102 (e.g., an adjustable delay line) as hardware. In this regard, when calculating the phase delay, it is necessary to calculate the correlation between the same sequence (e.g., the third sequence) and the reference sequence (e.g., the reference third sequence) at different phase points within a cycle. On the basis of compensating the sampling point delay, the reference sequence (e.g., the reference third sequence) and the sequences corresponding to each ADC with different phase delays (e.g., the multiple fourth sequences corresponding to each of the remaining third sequences) are correlated about the sampling point, and the result must have a correlation peak. In other words, the correlation operation can reflect the degree of correlation between the sequences corresponding to different phase features and the reference sequence. The values ​​of each correlation peak obtained by the correlation operation within a cycle are recorded, and each correlation peak corresponds to each phase point within a cycle. Among them, the phase delayed at the maximum correlation peak is the phase delay of the ADC of this ADC relative to the ADC of the reference third sequence. In short, this method requires that the synchronization at the sampling point level has been completed before the synchronization at the phase level is performed. The premise of phase-level synchronization calculation and compensation operation is that the synchronization at the sampling point level has been achieved. In other words, phase-level synchronization requires knowing the relevant information of the sampling point delay.

[0095] In one example, the determination of the reference third sequence may be random. The present invention is not limited thereto.

[0096] In order to more specifically describe the situation where the phase delay calculation module 1002 cooperates with the sampling point delay compensation module 1003 and the phase delay calculation module 1002 to calculate the phase delay, another example is introduced. For example, the third sequence T1 generated by performing sampling point delay compensation on the second sequence P1 output by the 1st ADC can be determined as the reference third sequence, and then the third sequences T2 to T3 corresponding to the 2nd to Xth ADC outputs can be used as the reference third sequence. X (The third sequence except T1) performs correlation operations with T1 on sampling points respectively.

[0097] Specifically, for example, for the third sequence T except the reference third sequence T1 X , you can use T X is sent to the corresponding phase delay compensation submodule 102-X to process T X Thus, the phase T is delayed by 1, 2, ..., N units. X , that is, multiple fourth sequences F 1X To F NX In other words, multiple fourth sequences F 1X To F NX T with a phase delay of 1, 2, ..., N units respectivelyX Correspondingly, in addition, multiple fourth sequences F 1X To F NX Corresponding to the X-th compensation submodule 102-X, and corresponding to the X-th ADC 101-X. For simplicity, F 1X To F NX Writing F1 to F N Where N is an integer greater than or equal to 2, and a phase delay of N units is equal to a phase delay of one cycle.

[0098] The phase delay compensation submodule 102-X generates F1 to F N After that, F1 to F N After being received by the sampling point delay compensation module 1003 through the ADC 101-X, the sampling point delay compensation module 1003 then compensates the F1 to F N Then, the phase delay calculation module 1002 calculates the sampling point delay of F1 to F N The correlation operation about the sampling points is performed with the third reference sequence T1 to obtain a plurality of corresponding correlation peaks A1 to A N Next, we can use the search algorithm to go from A1 to A N Find the maximum value A among them MAX The larger the correlation peak value obtained by the correlation operation, the higher the similarity of the two sequences. The fourth sequence with the largest correlation peak value (for example, F N ) is the phase delay Δθ of the ADC (i.e., the Xth ADC). X For example, the F corresponding to the maximum correlation peak N is the phase T delayed by Z units X , then the phase delay of the X-th ADC is Δθ X For Z.

[0099] In one example, Δθ is obtained X Afterwards, Δθ can be X The phase delay is sent to the corresponding phase delay compensation submodule 102-X to compensate for the phase delay of the ADC 101-X.

[0100] Figure 2 An example of a portion used for sampling point delay calculation and compensation in the signal processing system 10 according to an embodiment of the present disclosure is shown.

[0101] refer to Figure 2, Path 1 (represented as a solid line) shows the functional modules through which the test sequence (i.e., the first sequence) flows in the process of obtaining the sampling point delay in the system in the synchronous mode. Specifically, the system enters the synchronous mode, and the first sequence can be converted into a second sequence through the corresponding ADC 201-X. Then, the second sequence can be received by the sampling point delay calculation module 2001, and can be analyzed by the sampling point delay calculation module 2001 together with the second sequence received by other ADCs to obtain the sampling point delay. The obtained sampling point delay can be stored in the sampling point delay compensation module 2003.

[0102] Refer to Figure 2 , Path 2 (represented as a dotted line) shows the functional modules through which the received analog signal flows when the system receives the analog signal from the signal source for processing by the computing device 10 in the normal working mode. Specifically, when the system switches from the synchronous mode to the normal working mode, the analog signal can be converted into a digital signal through the corresponding ADC 201-X. The digital signal can be directly received by the sampling point delay compensation module 2003. Then, the sampling point delay compensation module 2003 can compensate the received digital signal according to the stored sampling point delay. Generally, the sampling point delay compensation can be implemented by software or programming language.

[0103] Figure 3 An example of a portion for phase delay calculation and compensation in the signal processing system 10 according to an embodiment of the present disclosure is shown.

[0104] refer to Figure 3, Path 1' (represented as a solid line) shows the functional modules through which the test sequence (i.e., the third sequence converted from the first sequence) flows during the process of calculating the phase delay of the system in the synchronous mode. Specifically, the system enters the synchronous mode, starting from the phase delay calculation module 3002. The third sequence corresponding to the ADC 301-X for which the phase delay needs to be calculated can be sent to the phase delay compensation module 302-X for phase delay operation, and it is usually preferred to delay the phase by one unit to obtain the third sequence after the phase is delayed by one unit, that is, the first fourth sequence. The first fourth sequence can be received by the sampling point delay compensation module 3003 through the ADC 301-X, and can be sent back to the phase delay calculation module 3002 after the sampling point delay compensation. Then, the phase delay calculation module 3002 can perform a correlation operation on the sampling point with the previously determined reference third sequence to obtain a correlation peak. And, the correlation peak can be stored in the phase delay calculation module 3002. Then, the first fourth sequence is used as the starting input, and the process of path 1' is repeated from the phase delay calculation module 3002 until the Nth fourth sequence is obtained. The Nth fourth sequence is a third sequence with a phase delayed by N units, wherein N is an integer greater than or equal to 2 and corresponds to a delay of one cycle, and one cycle corresponds to a phase range of 360°. That is, by repeating the process of path 1', each phase delay point of the third sequence within one cycle can be traversed, and the third sequence (i.e., each fourth sequence) delayed by each different phase amount can be correlated with the reference sequence to find the phase delay relative to the reference third sequence. After traversing each third sequence with different phase delays, the process of repeating path 1' can be stopped, and the maximum value can be found among all the correlation peaks stored in the phase delay calculation module 3002 to determine the phase delay corresponding to the Xth ADC 301-X.

[0105] Refer to Figure 3 , path 2' (represented as a dotted line) shows the functional modules through which the received analog signal flows when the system receives the analog signal from the signal source for processing by the computing device 10 in the normal working mode. Specifically, the system switches from the synchronous mode to the normal working mode, and the analog signal can be received by the corresponding ADC 301-X. The phase delay compensation module 302-X can perform phase delay compensation on the analog-to-digital conversion function of the ADC 301-X by performing phase delay compensation on the sampling clock provided to the ADC 301-X, so that the converted digital signal has no phase delay. The digital signal after phase delay compensation can then reach the computing device, such as the sampling point delay compensation module 3003 included in the computing device, for further processing. Here, for example, the phase delay compensation can be implemented by hardware (e.g., an adjustable delay line).

[0106] Figure 4 An example of a portion of a signal processing system 10 operating in a normal operating mode according to an embodiment of the present disclosure is shown.

[0107] according to Figure 4 The signal processing system includes an ADC 401-X, a phase delay compensation module 402 and a sampling point delay compensation module 4003. In combination with the description of any one or more of the above embodiments, Figure 4 FIG. 4 is a block diagram showing the basic functional modules of the signal processing system 10 in a normal working mode. The phase delay compensation module 402 may store Figure 3 The sampling point delay compensation module 4003 may store information about the phase delay obtained by the process of Figure 2 The information about the sampling point delay is obtained through the process of

[0108] In this part of the system, ADC 401-X can receive an analog signal from a signal source 403-X. In one example, ADC 401-X can convert the received analog signal into a digital signal required by computing device 100 according to the sampling clock CLK after the phase delay compensation module 402 performs corresponding phase delay compensation. The phase delay of the digital signal is thereby compensated. The digital signal after phase delay compensation can reach sampling point delay compensation module 4003, and then sampling point delay compensation module 4003 can further perform sampling point delay compensation.

[0109] pass Figure 4 The two-stage compensation method shown in FIG. 1 , i.e., the method including sampling point level synchronization compensation and phase level synchronization compensation, enables the sampling point delay and phase delay of each ADC to be compensated, thus achieving synchronization in a wider range. Figure 4 As shown, the synchronization of the phase level can be performed when the ADC performs conversion or before the conversion. Specifically, it can be achieved by the phase delay compensation module 402 compensating the phase delay of the sampling clock CLK.

[0110] Figure 5 An example flow chart of a signal processing method according to an embodiment of the present disclosure is shown. The process may be implemented by a signal processing system 10 including a computing device 100 .

[0111] In step S501, a first sequence as a test sequence is received.

[0112] In step S502, a plurality of ADCs are used to sample the received first sequence to generate a plurality of corresponding second sequences, wherein each of the plurality of second sequences corresponds to each of the plurality of ADCs.

[0113] In step S503, sampling point delay compensation is performed on multiple ADCs based on the multiple second sequences.

[0114] In step S504, phase delay compensation is performed on multiple ADCs based on the multiple second sequences.

[0115] Figure 6 An example flow chart of the working mode switching according to an embodiment of the present disclosure is shown. The process can be implemented by a signal processing system 10 including a computing device 100.

[0116] In step S601, the synchronization mode is entered to complete synchronization at the sampling point level and synchronization at the phase level.

[0117] In step S602, the normal working mode is entered to sample and process the required analog signal.

[0118] In one embodiment, the synchronous mode can be performed before each time the analog signal needs to be sampled, i.e., the normal working mode. In one embodiment, the synchronous mode can also be performed regularly depending on the situation. In another embodiment, the synchronous mode can be performed regularly alternately with the normal working mode.

[0119] Figure 7 An example flow chart of the steps for obtaining the sampling point delay according to an embodiment of the present disclosure is shown. Figure 5 It corresponds to step S503 in , and can be implemented by the signal processing system 10 including the computing device 100.

[0120] In step S701, one of a plurality of second sequences is determined as a reference second sequence.

[0121] In step S702, the remaining second sequences except the reference second sequence in the plurality of second sequences are respectively subjected to correlation operations on sampling points with the reference second sequence to obtain sampling point delays corresponding to each of the plurality of ADCs.

[0122] In step S703 , based on the obtained sampling point delay, sampling point delay compensation is performed on each of the plurality of ADCs.

[0123] Figure 8 Another example flow chart of the steps for obtaining the sampling point delay according to an embodiment of the present disclosure is shown. Figure 5 It corresponds to step S503 in , and can be implemented by the signal processing system 10 including the computing device 100.

[0124] As mentioned earlier, Figure 8 The steps shown can avoid ineffective correlation operations.

[0125] In step S801, one of a plurality of second sequences is determined as a reference second sequence.

[0126] In step S802, the overall sampling point delay of multiple ADCs is estimated.

[0127] In step S803, based on the overall sampling point delay, the reference second sequence is delayed with respect to the sampling points.

[0128] In step S804, the second sequences except the reference second sequence in the plurality of second sequences are respectively correlated with the delayed reference second sequence in terms of sampling points to obtain sampling point delays corresponding to each of the plurality of ADCs.

[0129] In step S805 , based on the obtained sampling point delay, sampling point delay compensation is performed on each of the plurality of ADCs.

[0130] The estimation of the overall sampling point delay in step S802 may be performed in advance and the estimated overall sampling point delay may be stored in the computing device 100 for use in step S803. Alternatively, step S802 may be performed between S801 and S803 as described above. However, the present invention is not limited thereto.

[0131] Fig. 9 An example flow chart of steps for obtaining phase delay according to an embodiment of the present disclosure is shown.

[0132] According to an embodiment of the present disclosure, after step S703 or step S805, sampling point delay compensation may be performed on multiple second sequences based on the obtained sampling point delay to generate multiple corresponding third sequences, and then the step goes to S901. Fig. 9 The process is implemented by a signal processing system 10 including a computing device 100 .

[0133] In step S901, one of a plurality of third sequences is determined as a reference third sequence.

[0134] In step S902, correlation operations on sampling points are performed on the remaining third sequences except the reference third sequence in the plurality of third sequences respectively with the reference third sequence to obtain a phase delay corresponding to each of the plurality of ADCs.

[0135] In step S903 , based on the obtained phase delay, phase delay compensation is performed on each of the plurality of ADCs.

[0136] Compare Figure 7 and Fig. 9 It can be seen that the basic principle of the method for obtaining phase delay is similar to that of the method for obtaining sampling point delay.

[0137] Fig.10 An example flow chart of the steps for obtaining the phase delay of each ADC according to an embodiment of the present disclosure is shown. Fig. 9 The process corresponds to step S902 in the process and can be implemented by the signal processing system 10 including the computing device 100.

[0138] In step S1001, for a corresponding one of the remaining third sequences except the reference third sequence in the plurality of third sequences, a corresponding one of the third sequences is delayed by different phase amounts to obtain a plurality of fourth sequences. The plurality of fourth sequences correspond to the third sequences delayed by 1, 2, ..., N units of phase, respectively. N can take a value greater than or equal to 2, and delaying the third sequence by N units of phase means delaying the third sequence by a full cycle.

[0139] In step S1002, correlation operation is performed on each of the plurality of fourth sequences and the reference third sequence about sampling points to obtain a plurality of correlation peaks.

[0140] In step S1003, a maximum correlation peak value among a plurality of correlation peak values ​​is searched.

[0141] In step S1004, the phase amount by which the fourth sequence corresponding to the maximum correlation peak is delayed relative to a corresponding one of the third sequences is determined as a corresponding phase delay.

[0142] Fig.11 An example flow chart of the steps for iteratively obtaining phase delay according to an embodiment of the present disclosure is shown. Fig. 9 The process corresponds to step S902 in FIG. 1 and can be implemented by the signal processing system 10 including the computing device 100. The process is based at least on Figure 3 Reference Figure 1 , Figure 3 and about Figure 3 The process will become clearer with the description of

[0143] In step S1101, a corresponding third sequence after sampling point delay compensation is received, and a cycle count is initialized. Generally, the cycle count is initially 0. The cycle count can indicate whether the third sequence is delayed for a full cycle. Here, the delayed third sequence is referred to as a fourth sequence to distinguish it from the original corresponding third sequence that has not been delayed.

[0144] In step S1102, the corresponding third sequence is delayed by 1 unit of phase to obtain a fourth sequence.

[0145] In step S1103, the fourth sequence is sampled using the ADC.

[0146] In step S1104, the sampling point delay that has been obtained is used to perform sampling point delay compensation on the fourth sequence after analog-to-digital conversion by the ADC. In this way, the fourth sequence obtained in step S1104 only includes phase delay, but no sampling point delay.

[0147] In step S1105, a correlation operation is performed between the fourth sequence obtained in step S1104 and a reference third sequence previously determined from a plurality of third sequences.

[0148] In step S1106, the correlation peak value obtained from the correlation operation in step S1105 is recorded, and the cycle count is incremented by 1.

[0149] In step S1107, based on the cycle count, it is determined whether the fourth sequence is delayed by one cycle relative to the original corresponding third sequence.

[0150] If the delay is not yet one full cycle, the process goes from step S1107 to step S1102 , taking the fourth sequence as input of S1102 , and repeating steps S1102 to S1107 for the fourth sequence.

[0151] If the delay is a full cycle, that is, the cycle count indicates that the third sequence has been delayed for a full cycle, then go to step S1108.

[0152] In step S1108, the maximum value is found from all the recorded correlation peaks. When one cycle is delayed, multiple correlation peaks should have been recorded, for example, N correlation peaks. Where N is an integer greater than or equal to 2, and a phase delay of N units is equivalent to a phase delay of one cycle, and the cycle count should also be N at this time.

[0153] In step S1109, the corresponding phase delay is determined based on the cycle count corresponding to the maximum correlation peak. For example, if the cycle count corresponding to the maximum correlation peak is B and the delayed phase of 1 unit is d°, the corresponding phase delay is (B×d)°.

[0154] Through the above iterative process, the computing device 100 does not need to store the fourth sequence corresponding to multiple phase delays at the same time, thereby saving storage space and further reducing the requirements on hardware capabilities.

[0155] Fig.10 or Fig.11 The process can obtain the phase delay of one ADC in the plurality of ADCs relative to the reference ADC corresponding to the reference third sequence, and the remaining ADCs except the reference ADC need to be respectively performed Fig.10 or Fig.11 Only through the process of , can the corresponding phase delays be obtained.

[0156] Figures 5 to 11 Any method or process shown in can be implemented in real-time, offline or near real-time. The real-time method does not require the use of a processor, which may save costs, but the development workload of FPGA logic will be slightly larger; the offline and near real-time methods require the use of a processor, which may increase costs, but the software development will be simpler.

[0157] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0158] In several embodiments provided in the present application, it should be understood that each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0159] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code. It should be noted that, in this article, relational terms such as first and third are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but further includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0160] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0161] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the attached claims and their equivalents.

Claims

1. A signal processing system, comprising: a plurality of analog-to-digital converters ADC configured to receive the first sequence in parallel and sample the received first sequence to generate a plurality of second sequences, each of the plurality of second sequences corresponding to each of the plurality of ADCs; a sampling point delay compensation module, configured to perform sampling point delay compensation on the plurality of ADCs based on the plurality of second sequences, wherein performing sampling point delay compensation comprises: obtaining a sampling point delay corresponding to each of the plurality of ADCs based on the plurality of second sequences; and the sampling point delay compensation module is further configured to: perform sampling point delay compensation on the plurality of second sequences respectively based on the obtained sampling point delay to obtain a plurality of third sequences, each of the plurality of third sequences corresponding to each of the plurality of ADCs; and The plurality of phase delay compensation submodules are configured to perform phase delay compensation on the plurality of ADCs based on the plurality of third sequences. 2 . The signal processing system of claim 1 , wherein the plurality of ADCs are further configured to sample a plurality of analog signals from a plurality of signal sources, respectively.

3. The signal processing system of claim 1, further comprising: The first sequence generator is configured to generate the first sequence.

4. The signal processing system of claim 1, further comprising: A first distributor configured to provide the first sequence to the plurality of ADCs respectively; and The second distributor is configured to provide sampling clocks to the plurality of ADCs respectively.

5. The signal processing system of claim 4, further comprising: A plurality of switches, each of the plurality of switches corresponds to each of the plurality of ADCs and is configured to select the first sequence from the first distributor or the analog signals from the plurality of signal sources to be provided to a corresponding one of the plurality of ADCs.

6. The signal processing system according to claim 4, wherein: The distance from the output port of the first distributor to the input port of each of the plurality of ADCs is the same, and The distances from the output port of the second distributor to the input port of each of the plurality of ADCs are the same.

7. The signal processing system of claim 1, further comprising: The sampling point delay calculation module is configured to obtain the sampling point delay corresponding to each of the plurality of ADCs and provide the obtained sampling point delay to the sampling point delay compensation module.

8. The signal processing system according to claim 7, wherein the sampling point delay calculation module is further configured to: determining one of the plurality of second sequences as a reference second sequence; and The remaining second sequences among the plurality of second sequences except the reference second sequence are respectively subjected to correlation operations with the reference second sequence regarding sampling points to obtain sampling point delays corresponding to each of the plurality of ADCs, and the obtained sampling point delays are provided to the sampling point delay compensation module.

9. The signal processing system according to claim 7, wherein: The sampling point delay calculation module is further configured to: determining one of the plurality of second sequences as a reference second sequence; estimating an overall sampling point delay of the plurality of ADCs; Delaying the reference second sequence with respect to sampling points based on the overall sampling point delay; and The remaining second sequences among the plurality of second sequences except the reference second sequence are respectively subjected to correlation operations on sampling points with the delayed reference second sequence to obtain sampling point delays corresponding to each of the plurality of ADCs, and the obtained sampling point delays are provided to the sampling point delay compensation module.

10. The signal processing system of claim 1, further comprising: The phase delay calculation module is configured to obtain the phase delay corresponding to each of the multiple ADCs, and provide the obtained phase delay to the corresponding phase delay compensation submodule.

11. The signal processing system according to claim 10, wherein: The phase delay calculation module is further configured to: determining one of the plurality of third sequences as a reference third sequence; and The remaining third sequences of the plurality of third sequences except the reference third sequence are respectively correlated with the reference third sequence with respect to sampling points to obtain a phase delay corresponding to each of the plurality of ADCs.

12. The signal processing system according to claim 11, wherein: The method further comprises: performing correlation operations on the sampling points of the remaining third sequences except the reference third sequence in the plurality of third sequences and the reference third sequence respectively, so as to obtain a phase delay corresponding to each of the plurality of ADCs, comprising: For a corresponding one of the remaining third sequences except the reference third sequence among the plurality of third sequences, delay the corresponding one of the third sequences by different phase amounts to obtain a plurality of fourth sequences; Performing correlation operations on sampling points on each of the plurality of fourth sequences and the reference third sequence to obtain a plurality of correlation peaks; Searching for a maximum correlation peak value among the plurality of correlation peak values, determining a phase amount by which a fourth sequence corresponding to the maximum correlation peak value is delayed relative to the corresponding one of the third sequences as a corresponding phase delay; and The corresponding phase delay is provided to the corresponding phase delay compensation submodule.

13. The signal processing system according to claim 12, wherein: The corresponding phase delay compensation submodule delays the corresponding third sequence by different phase amounts to obtain multiple fourth sequences.

14. A signal processing method, comprising: receiving a first sequence; sampling the first sequence received in parallel using a plurality of analog-to-digital converters (ADCs) to generate a plurality of second sequences, each of the plurality of second sequences corresponding to each of the plurality of ADCs; Based on the multiple second sequences, performing sampling point delay compensation on the multiple ADCs, wherein performing sampling point delay compensation comprises: obtaining a sampling point delay corresponding to each of the multiple ADCs based on the multiple second sequences; Based on the obtained sampling point delay, respectively perform sampling point delay compensation on the plurality of second sequences to obtain a plurality of third sequences, each of the plurality of third sequences corresponding to each of the plurality of ADCs; and Based on the plurality of third sequences, phase delay compensation is performed on the plurality of ADCs.

15. The signal processing method according to claim 14, further comprising: The plurality of ADCs are used to sample a plurality of analog signals from a plurality of signal sources respectively.

16. The signal processing method according to claim 14, wherein: Obtaining a sampling point delay corresponding to each of the plurality of ADCs comprises: determining one of the plurality of second sequences as a reference second sequence; and The remaining second sequences of the plurality of second sequences except the reference second sequence are respectively subjected to correlation operation with the reference second sequence regarding sampling points to obtain sampling point delays corresponding to each of the plurality of ADCs.

17. The signal processing method according to claim 14, wherein: Obtaining a sampling point delay corresponding to each of the plurality of ADCs comprises: determining one of the plurality of second sequences as a reference second sequence; estimating an overall sampling point delay of the plurality of ADCs; Based on the overall sampling point delay, delaying the reference second sequence with respect to the sampling points; and The remaining second sequences of the plurality of second sequences except the reference second sequence are respectively subjected to correlation operation on sampling points with the delayed reference second sequence to obtain sampling point delays corresponding to each of the plurality of ADCs.

18. The signal processing method according to claim 14, wherein: Based on the multiple third sequences, performing phase delay compensation on the multiple ADCs includes: Based on the plurality of third sequences, a phase delay corresponding to each of the plurality of ADCs is obtained, and Based on the obtained phase delay, phase delay compensation is performed on each of the plurality of ADCs.

19. The signal processing method according to claim 18, wherein: Obtaining a phase delay corresponding to each of the plurality of ADCs comprises: determining one of the plurality of third sequences as a reference third sequence; and The remaining third sequences of the plurality of third sequences except the reference third sequence are respectively correlated with the reference third sequence with respect to sampling points to obtain a phase delay corresponding to each of the plurality of ADCs.

20. The signal processing method according to claim 19, wherein: The method further comprises: performing correlation operations on the sampling points of the remaining third sequences except the reference third sequence in the plurality of third sequences and the reference third sequence respectively, so as to obtain a phase delay corresponding to each of the plurality of ADCs, comprising: For a corresponding one of the remaining third sequences except the reference third sequence among the plurality of third sequences, delay the corresponding one of the third sequences by different phase amounts to obtain a plurality of fourth sequences; Performing correlation operations on sampling points on each of the plurality of fourth sequences and the reference third sequence to obtain a plurality of correlation peaks; and A maximum correlation peak value among the plurality of correlation peak values ​​is searched for, and a phase amount by which the fourth sequence corresponding to the maximum correlation peak value is delayed relative to the corresponding one of the third sequences is determined as a corresponding phase delay.

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