System and method for reference stabilization

Abstract

The present invention is entitled "System and Method for Reference Stabilization." An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to a column readout circuit via a corresponding column line. The column readout circuit may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors selectively coupled to the coarse reference voltage.

Description

Technical Field

[0001] The present invention generally relates to reference stabilization in circuits and is applicable to digital-to-analog converters implemented within analog-to-digital converters in image sensors. Background Art

[0002] Modern electronic devices, such as cell phones, cameras, and computers, often use image sensors. Image sensors can be formed from a two-dimensional array of image pixels. The image pixel array is typically arranged in rows and columns. Each image pixel includes a photosensitive layer that receives incident photons (i.e., light) and converts the photons into an electrical charge. Column readout circuitry is typically coupled to each column of image pixels to read out image signals from the image pixels.

[0003] Conventional image sensors typically include an analog-to-digital converter (ADC) to convert the analog signals generated by image pixels into digital signals. In image sensors with large arrays, most types of these ADCs require reference stabilization in the capacitive DAC for each bit iteration of a complete conversion cycle. Typical reference buffers, which provide the reference voltage for reference stabilization, can result in slow reference stabilization, undesirably limiting conversion time and bandwidth.

[0004] Therefore, it is desirable to provide a reference buffer that supports high slew rates and high bandwidth with varying capacitive loads and provides a circuit with other desirable characteristics. It is against this background that the embodiments herein arise. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of an exemplary electronic device according to some embodiments.

[0006] Figure 2 is a schematic diagram of an exemplary image pixel array in an image sensor according to some embodiments.

[0007] Figure 3 is a schematic diagram of an exemplary analog-to-digital converter (ADC), according to some embodiments.

[0008] Figure 4 is a schematic diagram of an exemplary digital-to-analog converter (DAC) according to some embodiments.

[0009] Figure 5 is an exemplary timing diagram for operating a signal conversion circuit according to some embodiments.

[0010] Figures 6A to 6C is a schematic diagram of an exemplary reference signal generation circuit according to some embodiments. DETAILED DESCRIPTION

[0011] Embodiments of the present invention relate to reference stabilization in circuits, and more particularly to signal conversion circuits within imaging systems (e.g., a DAC in an ADC for an image sensor). If desired, the signal conversion circuits may be implemented in any suitable system. Those skilled in the art will recognize that the exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known circuits and operations have not been described in detail to avoid unnecessarily obscuring the embodiments of the present invention.

[0012] To provide high conversion rates and support high bandwidth with varying capacitive loads, a reference signal generation circuit can provide a coarse reference voltage signal (e.g., a coarse reference) and a fine reference voltage signal (e.g., a fine reference). The coarse reference voltage signal in the MSB (most significant bit or bits) group of a split SAR (successive approximation register) DAC can be used to provide conversion (e.g., a high conversion rate). The same coarse reference voltage signal can be used as a reference for the LSB (least significant bit or bits) group of a split SAR DAC, as the reference accuracy requirement for the LSB group can be relaxed to m (i.e., the number of least significant bits) + 1 bit accuracy. In addition, the fine reference voltage signal (and the coarse reference voltage signal) can be provided to the MSB group of the split SAR DAC. The fine reference voltage signal can provide a final setting for fine-tuning after conversion using the coarse reference voltage signal. For example, the SAR DAC can be provided in an ADC. These exemplary features of the present invention are described in more detail herein.

[0013] Figure 1 is a schematic diagram of an exemplary electronic device according to one embodiment of the present invention. Figure 1 As shown, imaging system 10 can be a portable imaging system, such as a camera, an automotive imaging system, a mobile phone, a video camera, a video surveillance system, or any other imaging device that captures digital image data as desired. System 10 can include a camera module 12 for converting incident light into digital image data. Camera module 12 can include one or more lenses 14 and / or one or more image sensors 16. One or more lenses 14 and one or more image sensors 16 can be mounted in the same package and can provide image data to processing circuitry 18. For example, one or more lenses 14 can be arranged as a lens array 14 and / or one or more image sensors 16 can be arranged as an image sensor array 16.

[0014] Processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, storage devices such as random access memory and non-volatile memory, etc.) and may be implemented using components that are separate from and / or form part of camera module 12 (e.g., circuitry that forms part of an integrated circuit that includes one or more image sensors 16 or an integrated circuit within module 12 associated with one or more image sensors 16). If desired, image data captured and processed by camera module 12 may be further processed and stored using processing circuitry 18. If desired, the processed image data may be provided to an external device (e.g., a computer or other device) using a wired and / or wireless communication path coupled to processing circuitry 18.

[0015] One or more image sensors 16 may include image pixels. Each image pixel in one or more image sensors 16 may receive light of a given color by providing a color filter for the corresponding image pixel. The color filters used for the image pixels in one or more image sensors 16 may be, for example, a red filter, a blue filter, and a green filter. Other color filters may also be used, such as a white filter, a dual-band IR-cut filter (e.g., a filter that allows transmission of visible light as well as a certain range of infrared light emitted by an LED light), or any suitable color filter.

[0016] Figure 2 is an image sensor (e.g. Figure 1 Schematic diagram of an exemplary image pixel array in an image sensor 16). Figure 2 As shown, image sensor 16 may include an image pixel array 202 having a plurality of pixels 201 (sometimes referred to herein as image pixels 201 or image sensor pixels 201). Row control circuitry 204 may be coupled to image pixel array 202. Row control circuitry 204 may provide pixel control signals (e.g., row select signals, pixel reset signals, charge transfer signals, etc.) to pixels 201 via corresponding row control lines 203 to control the capture and readout of images using pixels 201 in image pixel array 202.

[0017] Image sensor 16 may include column control and readout circuitry 212 (sometimes referred to herein as column readout circuitry 212, readout circuitry 212, column circuitry 212, or column control circuitry 212), and may include control and processing circuitry 208 (sometimes referred to herein as control circuitry 208) coupled to row control circuitry 204 and column readout circuitry 212. Column readout circuitry 212 may be coupled to image pixel array 202 via a plurality of column lines 211 (sometimes referred to herein as output lines 211 or pixel output lines 211). For example, each column of pixels 201 in image pixel array 202 may be coupled to a corresponding column line 211. A corresponding analog-to-digital converter (ADC) 214 (sometimes referred to herein as analog-to-digital conversion circuitry 214, ADC circuitry 214, or conversion circuitry 214) and (column) amplifier circuitry 216 may be coupled to each column line 211 (e.g., interposed on the column lines) for amplifying analog image signals captured by image pixel array 202 and converting the captured analog image signals (e.g., analog pixel signals) into corresponding digital image data (e.g., digital pixel data). Column control and readout circuitry 212 may be coupled to external hardware, such as processing circuitry (e.g., processing circuitry 208 external to column circuitry 212, Figure 1 16 ). For example, column control and readout circuitry 212 may perform column readout operations based on (analog) signals and / or (digital) signals received from control and processing circuitry 208. In some examples, column control and readout circuitry 212 may be described herein as including column ADC circuitry 214 and column amplifier 216.

[0018] One or more amplifiers 216 may be configured to receive analog image signals (e.g., analog reset level signals and / or image level signals) from image pixel array 202 and amplify the analog image signals. Depending on the application and the configuration of image sensor 16, the analog image signals may include data from a single column of pixels 201 or from multiple columns of pixels 201. Conversion circuitry 214 may receive the amplified analog image signals from amplifier circuitry 216 and may perform analog-to-digital conversion operations on the analog image signals to generate digital image data. The digital image data may be transmitted to (other portions of) column control and readout circuitry 212 for processing and / or readout operations.

[0019] Figure 3 is a schematic diagram of an exemplary analog-to-digital conversion circuit (e.g., an analog-to-digital converter ADC) configured to convert an analog input signal Vin into digital output data Dout. For example, an analog-to-digital converter (ADC) (e.g., Figure 2 ADC 214 in image sensor 16). Although described herein in the context of an image sensor and / or imaging system, Figure 3 ADC 214 in the embodiment of the present invention may be implemented in any other suitable device or system. In the illustrative example of an imaging system, ADC 214 may receive an analog signal from image pixel array 202. ADC 214 may receive the analog image signal as an input analog signal Vin. Input signal Vin may be one or more analog signals (e.g., signals received via one or more column lines 211) from one or more pixels 201 in image pixel array 202 (e.g., generated by one or more pixels in the image pixel array). ADC 214 may convert the input analog image signal Vin into digital image data Dout, which may be provided to downstream readout and / or processing circuitry.

[0020] exist Figure 3 In the example of , ADC 214 can be a successive approximation register (SAR) ADC. The SAR ADC can use a binary search algorithm implemented using a digital-to-analog converter (DAC) 302, a comparator 304, and a successive approximation register (SAR) control logic 306.

[0021] DAC 302 (sometimes referred to herein as conversion circuit 302) can function (e.g., may include) as a sample and hold circuit for input signal Vin (using switch 308). In other words, DAC 302 can receive signal Vin and output signal Vdac (sometimes referred to herein as voltage Vdac) generated based on the sampled input signal Vin. To generate analog signal Vdac based on input voltage Vin, the DAC can use one or more reference voltages VREF (sometimes referred to herein as one or more reference voltage signals VREF) and one or more control signals from SAR control logic circuit 306. Comparator 304 (sometimes referred to herein as comparison circuit 304) can be used to compare analog signal Vdac with a reference voltage VCM (such as a reference ground voltage). The voltage output by DAC 302 (e.g., signal Vdac) can vary, allowing for successive comparisons with reference voltage VCM. Each comparison can further narrow the range of possible values ​​for Vin, with the number of comparisons determining the conversion resolution.

[0022] Comparator 304 may receive a voltage (signal) Vdac at a first input and a voltage (signal) VCM at a second input. The comparator may compare the magnitude of voltage Vdac with the magnitude of voltage VCM. The output of comparator 304 may be a signal provided to SAR control logic 306 (sometimes referred to herein as register 306). The output signal of comparator 304 may have a value indicating which signal has the higher voltage (e.g., if voltage signal Vdac is greater than voltage signal VCM, the comparator output may be asserted at a logic high level "1," whereas if voltage signal Vdac is greater than voltage signal VCM, the comparator output may be driven to a logic low level "0," and vice versa).

[0023] Figure 3 The SAR control logic 306 in FIG3 is sometimes referred to as a processing circuit. The processing circuit 306 can track the comparison result of the comparator 304 and adjust the output of the DAC 302 accordingly (using a control path that couples the SAR control logic 306 to the DAC 302). The processing circuit 306 can also output the result of the analog-to-digital conversion (e.g., digital data Dout, which is a digital representation of the analog signal Vin).

[0024] Figure 3 The configuration of ADC 214 in FIG is merely exemplary. If desired, ADC 214 may have any other suitable configuration. If desired, the output of DAC 203 may be provided to a first input of comparator 304, and signal Vin may be provided to a second input of comparator 304. If desired, voltage VCM may be implemented as a non-ground voltage. If desired, DAC 302, comparator 304, and / or register 306 may be implemented in any suitable configuration (e.g., coupled to each other) to perform analog-to-digital conversion operations.

[0025] If desired, DAC 302 can be any desired type of digital-to-analog converter. In one illustrative example, DAC 302 can be a capacitive DAC, such as a split-capacitor DAC having an n-bit MSB (capacitor) bank and an m-bit LSB (capacitor) bank. Generally, SAR ADCs with split-capacitor DACs have a single reference voltage (e.g., a single high reference voltage relative to a low reference voltage, a single reference voltage above ground). However, when implemented in a large-format array, the reference voltage may be required to drive a load on the order of nF (nanofarads) within the capacitive DAC, which is undesirable. Furthermore, this results in a long reference settling time in the capacitive DAC, thus limiting the conversion time in the ADC.

[0026] Figure 4An exemplary DAC (e.g., a capacitive DAC that receives two reference voltages (e.g., two reference voltage signals higher than ground) that overcome the above-mentioned problems is shown. As an exemplary example, Figure 4 The DAC 302 can be used in Figure 2 and / or Figure 3 Although described herein in the context of an imaging sensor or system and analog-to-digital conversion circuitry, Figure 4 The DAC 302 in FIG. 3 may be implemented in any other suitable circuit, device, and / or system.

[0027] like Figure 4 As shown, DAC 302 may include an MSB (capacitor) bank 402 and an LSB (capacitor) bank 404 coupled by an intervening capacitor 406 (sometimes referred to as a split capacitor 406). Capacitor 406 may have a first terminal coupled to a path 408 to which MSB bank 402 is coupled. Capacitor 406 may have a second terminal coupled to a path 410 to which LSB bank 404 is coupled. An input signal Vin may be provided to path 408 via sampling switch 308. A control signal Vsamp may be used to control switch 308. A DAC output signal Vdac may be coupled to path 408.

[0028] MSB group 402 may include a suitable number of capacitors 412-1 to 412-n coupled in parallel to path 408. For reference, capacitors 412 are labeled 1, 2, ..., n. If desired, the actual number of capacitors may be, for example, n+1 or any other suitable number. Capacitors 412 may include capacitors having different capacitance values. For example, MSB group 402 may include capacitors having capacitances C, C*2, and C*3, respectively. 1 ,...,C*2 (n-1) If desired, the MSB group 402 may have any other set of capacitance values ​​for the capacitors 412. The number of capacitors 412 may indicate the number of bits associated with the MSB group 402 (e.g., the conversion resolution of the most significant bit). Each of these capacitors 412 may have a first terminal coupled to line 408 (e.g., Figure 4 Each of these capacitors 412 may have a second terminal (e.g., one or more voltage sources supplying the multiple reference voltages) coupled via a switch to multiple reference voltages (e.g., one or more voltage sources supplying the multiple reference voltages). Figure 4 (bottom plate in the).

[0029] Specifically, the corresponding switch 414 can couple the second terminal of the corresponding capacitor 412 to the reference voltage Vreflo. The corresponding switches 415 and 416 can couple the second terminal of the corresponding capacitor 412 to the reference voltage Vrefcoarse. The corresponding switches 415 and 417 can couple the second terminal of the corresponding capacitor 412 to the reference voltage Vreffine.

[0030] SAR control logic 306 and / or any other control circuitry can provide control signals to each set of switches 414, 415, 416, and 417. For example, control logic 306 (which can include a set of latches) can provide control bits (latch bits) to control one or more of switches 414 and 415 in MSB group 402. The control signal (bit) provided to switch 414 can be the inverse (e.g., an inverted version) of the control signal for switch 415. Additionally, control circuitry (e.g., control logic 306) can selectively activate switches 416 and 417 to electrically connect one of voltages Vrefcoarse and Vreffine to switch 415 to perform faster settling while also reducing power consumption and accurately settling to a precise voltage.

[0031] For example, the control circuit can be Figure 4 The control signal bit q is provided to the corresponding switch 415. <m>,q<m+1> ,. ...,q<m+n-1> The control circuit can be as follows Figure 4 The control signal bit q is provided to the corresponding switch 414. <m>,q<m+1> 、...。、q<m+n-1> Inverted version of . (For example, in Figure 4 median q <m>,q<m+1> ,...,q<m+n-1> The control circuit can also be Figure 4 The control signal cen is provided to the corresponding switch 416. <m>,cen<m+1> ,. ...,cen<m+n-1> , and as Figure 4 The control signal bit fen is provided to the corresponding switch 417. <m>、fen<m+1> 、. ...、fen<m+n-1> For example, each bit of the control signals q, cen, and fen can be provided along parallel bit lines. By providing these control bits, the control circuit can control the MSB group 402 to couple (e.g., electrically connect) the corresponding bottom plate of any capacitor 412 to one of three voltages (e.g., voltages Vreflo, Vrefcoarse, and Vreffine).

[0032] LSB group 404 may include a suitable number of capacitors 422-1 to 422-m coupled in parallel to path 410. For reference, capacitors 422 are labeled 1, 2, ..., m. If desired, the actual number of capacitors may be, for example, m+1 or any other suitable number. Capacitors 422 may include capacitors having different capacitance values. For example, LSB group 404 may include capacitors having capacitances C, C*2, and C*3, respectively. 1 ,...,C*2 m If desired, the LSB group 404 may have any other set of capacitance values ​​for the capacitors 422. In some configurations, the capacitance C of the capacitor 412-1 in the MSB group 402 may be different from the capacitance C of the capacitor 422-1 in the LSB group 404. The number of capacitors 422 may indicate the number of bits associated with the LSB group 404 (e.g., the conversion resolution of the least significant bit). Each of these capacitors 422 may have a first terminal coupled to the line 410 (e.g., Figure 4 Each of these capacitors 422 may have a second terminal (e.g., one or more voltage sources supplying the multiple reference voltages) coupled via a switch. Figure 4 (bottom plate in the).

[0033] Specifically, the corresponding switch 424 may couple the second terminal of the corresponding capacitor 422 to the reference voltage Vreflo. The corresponding switch 425 may couple the second terminal of the corresponding capacitor 422 to the reference voltage Vrefcoarse.

[0034] SAR control logic 306 and / or any other control circuitry can provide control signals to each set of switches 424 and 425. For example, control logic 306 (which may include a set of latches) can provide control bits (latch bits) to control one or more of switches 424 and 425 in LSB set 404. The control signal (bit) provided to switch 424 can be an inverted version of the control signal (bit) provided to switch 425. In addition, control circuitry (e.g., control logic 306) can selectively activate switch 425 to electrically connect voltage Vrefcoarse to switch 415 to utilize at least one of the same reference voltages as in MSB set 402, thereby effectively simplifying the design without adversely affecting voltage stability in LSB set 404.

[0035] For example, the control circuit can be Figure 4 The control signal bit q is provided to the corresponding switch 425. <0> ,q <1> ,. ...,q <m-1>The control circuit can be as follows Figure 4 The control signal bit q is provided to the corresponding switch 424. <0> ,q <1> 、...。、q <m-1>Inverted version of . (For example, in Figure 4 median q <0> ,q <1> ,...,q <m-1>For example, bit q of control signal q <0> ,q <1> 、...。、q <m-1>By providing these control bits, the control circuitry can control the LSB group 404 to couple (eg, electrically connect) the corresponding bottom plate of any capacitor 412 to one of two voltages (eg, voltages Vreflo and Vrefcoarse).

[0036] In some configurations, the voltage Vreflo can be a ground voltage (eg, 0V). The voltages Vrefcoarse and Vreffine can be non-ground voltages (eg, positive voltages higher than or greater than the voltage Vreflo). Figure 3 A reference voltage signal VREF is shown provided to DAC 302, but according to some embodiments, reference voltage signal VREF may represent multiple reference voltage signals. Specifically, DAC 302 may receive two reference voltage signals Vrefcoarse and Vreffine, and a ground reference voltage (signal) such as voltage Vreflo.

[0037] Figure 5 shows how an exemplary DAC and / or ADC circuit such as Figure 3 and Figure 4 Specifically, each conversion cycle may include a sampling time period SAMP, an MSB conversion time period MSBCONV, and an LSB conversion time period LSBCONV. During the time period SAMP, the switch control signal Vsamp such as Figure 3 and Figure 4 The control signal of the switch 308 in may be asserted (at assertion Z) to activate or close the switch 308 to sample the input (image) signal.

[0038] Then, during the MSB CONV cycle, different switch groups can be activated or closed to perform the conversion operation on the most significant bit. Figure 5 As shown, during the MSB conversion operation, the combination of the control bits of the control signals cen and fen (e.g., at bit <m>、<m+1> 、...、<m+n-4> 、<m+n-4> 、<m+n-3> 、<m+n-2> and<m+n-1> ) can be activated or closed Figure 4 In other words, each bit of the signals cen and fen may correspond to a capacitor coupled to the capacitor associated with the bit.

[0039] Although Figure 5 It is not explicitly shown in FIG, but during the MSB conversion operation, the control circuit can also make the combination of control bits of the control signal q associated with capacitors 414 and 415 (for example, at bit <m>、<m+1> 、...、<m+n-4> 、<m+n-4> 、<m+n-3> 、<m+n-2> ,as well as<m+n-1> For example, when a capacitor associated with a given bit is used in an MSB conversion operation (e.g., Figure 4 When the capacitor 412-n is used for the control signal fen or for a given bit (e.g., bit 1) of the control signal cen,<m+n-1> ) is effective, the given bit (for example, bit<m+n-1> ) can be effective. This can provide an appropriate connection from the second terminal (e.g., bottom plate) of the corresponding capacitor 412 to one of the voltages Vreffine and Vrefcoarse. For another example, when compared to a given position (e.g., position <m>) associated capacitors (e.g., Figure 4 When the capacitor 412-1 in FIG. 1 is not used for the MSB conversion operation, such as when a given bit (e.g., bit 1) is used for the control signal fen or for the control signal cen, <m>) are not valid, the given bit (for example, bit <m>) may become invalid.

[0040] For each comparator cycle during the MSB conversion operation (e.g., Figure 3 As shown in FIG1 , a coarse reference voltage (e.g., voltage Vrefcoarse) may be used first, and a fine reference voltage (e.g., voltage Vreffine) may be used later. This may support high conversion rates, high bandwidths, and thus improve conversion times.

[0041] For example, during the MSB(n)th bit transition, the reference driver may supply a current approximately equal to Y*(C*2 n / 2+C pn )*Vreffine, where Y is the number of column-parallel ADCs, C is the unit capacitance of DAC 302, and C pn is the bottom plate parasitic of the nth capacitor (e.g., capacitor 412-n). The effective capacitance obtained at the bottom plate of the MSB group may be approximately C eq =Y*(C*2 n / 2+C pn ).

[0042] Charge to C eq *Vreffine causes the reference driver to switch to a voltage of Vreffine*C vrefdrv / (C vrefdrv + Ceq), where C vrefdrv is the output and routing capacitance of the reference driver. To reduce the slew rate on the reference driver to 50%, C vrefdrv =Ceq / 2. For several clock cycles, the required conversion current can be on the order of several 100mA. This large conversion current can result in very high power dissipation in the reference driver. The conversion requirement can be addressed by charging one or more DAC capacitor bottom plates to voltage Vrefcoarse for one, two, or any other suitable number of clock cycles, and then charging to voltage Vreffine.

[0043] For the MSB(n-1)th bit conversion, if the MSB(n)th bit is connected to Vreffine (for Vin>Vreffine / 2), then the fine reference driver may have to supply approximately equal to C*2 n *Vrefcoarse / 8+C pn *Vrefcoarse / 8, where C is the unit capacitance of the DAC, and C pn It is the parasitic of the bottom plate of the nth bit. Since the signal Vdac is at the MSB bottom plate<n+m-1> The effective voltage change obtained by changing Vrefcoarse / 4 is Vrefcoarse / 8. This additional charge can introduce transitions into the fine reference driver.

[0044] To avoid transitions on the fine reference driver during the MSB(n-1)th bit transition, the MSB(n-1)th bit capacitor (e.g., capacitor 412-(n-1)) can be connected to voltage Vrefcoarse while the MSB(n-1)th bit is charging to voltage Vrefcoarse. Depending on the design routing of the RC (resistor-capacitor circuit), charging to voltage Vrefcoarse can take one, two, or any suitable number of clock cycles. After charging the backplane to voltage Vrefcoarse, the control circuit can switch to fine reference voltage Vreffine to accurately determine the bit value.

[0045] To avoid transitions on the fine reference buffer, for each bit transition, all bits can be switched to voltage Vrefcoarse for one, two, or any suitable number of clock cycles. Then, all bits can be switched back to voltage Vreffine.

[0046] exist Figure 5 In the example, the most significant bit transition (e.g., MSB group nth bit or bit<m+n-1> During the conversion), at the effective A1, the control circuit can make the control signal cen<m+n-1> (and control signal bit q<m+n-1> ) takes effect to Figure 4 The bottom plate of capacitor 412-n in is connected to voltage Vrefcoarse. This can provide for reference stabilization (e.g., for changing Figure 3 and Figure 4 After a suitable amount of time, at assertion B1, the control circuit may cause the control signal to be fen<m+n-1> (and control signal bit q<m+n-1> ) takes effect to Figure 4 The bottom plate of capacitor 412-n in is connected to voltage Vreffine. This can provide for reference stabilization (e.g., for changing Figure 3 and Figure 4 When the bottom plate of capacitor 412-n is connected to voltage Vreffine, output signal Vdac can flip the output of comparator 304, causing Y1 to be asserted. This can complete a single-bit conversion.

[0047] On subsequent bit transitions (e.g., bit n-1 of the MSB group or bit<m+n-2> During the conversion), when A2 and C1 are valid, the control circuit can make the control signal cen<m+n-1> and cen<m+n-2> (and control signal bit q<m+n-1> and q<m+n-2> ) takes effect to Figure 4 The bottom plates of capacitors 412-n and capacitor 412-(n-1) (eg, the capacitor associated with the second most significant bit) are connected to voltage Vrefcoarse. After a suitable amount of time, at assertion B2 and D1, the control circuitry may cause the control signal bit fen to<m+n-1> and fen<m+n-2> (and control signal bit q<m+n-1> and q<m+n-2> ) asserts to connect the bottom plates of capacitors 412-n and 412-(n-1) to voltage Vreffine. When the bottom plates of capacitors 412-n and 412-(n-1) are connected to voltage Vreffine, output signal Vdac may flip the output of comparator 304, causing Y2 to assert. This may complete another bit transition.

[0048] for Figure 4 The combination of capacitors in the MSB group 402 in FIG. 4 can be similarly operated. Figure 5 In the example, the MSB conversion can control the most significant bit of the signal (for example, the bits of the control signals q, cen, and fen).<m+n-1> ) and may proceed to the less significant bits in the MSB group 402.

[0049] The least significant bit in the MSB group 402 is converted (e.g., with Figure 5 After the LSB conversion time period is started (associated with Y5 in the figure for illustration), a coarse reference voltage can be used instead of a fine reference voltage during the LSB conversion because the accuracy requirement of the reference voltage is less stringent. Specifically, the accuracy can be relaxed to m (the number of least significant bits) + 1 bit. By closing a switch such as Figure 4 By switching switch 425 in the LSB group 404, the bottom plate of capacitor 422 in the LSB group 404 can be charged. A combination of capacitors 422-m (starting with the capacitor associated with the most significant bit) can be used for LSB bit conversion. After performing the LSB conversion, a full conversion cycle can be completed and subsequent signals can be sampled during subsequent sampling cycles.

[0050] Figures 6A to 6C 1 shows a portion of an exemplary reference signal generating circuit (sometimes referred to herein as a reference buffer or reference driver) for generating two reference signals using a base reference signal. Figure 6A As shown, the portion 602-1 of the reference signal generating circuit 602 may receive an initial voltage V1. Based on the initial voltage V1, the portions 602-2 and 602-3 of the reference signal generating circuit 602 may generate voltages Vreffine and Vrefcoarse, respectively (at Figure 6B and Figure 6C middle).

[0051] Re-reference Figure 6A , the initial voltage V1 may be a bandgap reference voltage. Amplifier circuit 604 (sometimes referred to herein as amplifier 604) may have a first (non-inverting) input terminal, a second (inverting) input terminal, and an output terminal. For example, amplifier circuit 604 may be an operational transconductance amplifier. Amplifier circuit 604 may receive voltage V1 at its non-inverting input and may be coupled to transistors 606 and 608 at its output terminal.

[0052] Transistor 606, variable resistor 610, and resistor 614 may be coupled in series between terminal 618 and terminal 620. The node between variable resistor 610 and resistor 614 may be coupled to the inverting input terminal of amplifier circuit 604 as a feedback path. Transistor 608, variable resistor 612, and resistor 616 may be coupled in series between terminal 618 and terminal 620. For example, voltage terminal 618 may supply power supply voltage Vs and may be set to ground voltage.

[0053] The node between the transistor 606 and the variable resistor 610 may be an intermediate node VF for generating the voltage Vreffine. Figure 6B , the intermediate node VF can be coupled to the non-inverting input terminal of the amplifier circuit 650. The inverting input terminal of the amplifier circuit 650 can be coupled to its output terminal in a feedback path. The output terminal of the amplifier circuit 650 can provide a voltage Vreffine, which can be supplied to a DAC circuit, an ADC circuit, etc. (for example, supplied to Figure 3 and Figure 4 The voltage Vreffine can be generated using a high-bandwidth amplifier to provide fast settling.

[0054] The node between the transistor 608 and the variable resistor 612 may be an intermediate node VC for generating the voltage Vrefcoarse. Figure 6C , the intermediate node VC can be coupled to the non-inverting input terminal of the amplifier circuit 660. The inverting input terminal of the amplifier circuit 660 can be coupled to its output terminal in a feedback path. The output terminal of the amplifier circuit 660 can be coupled to the capacitor 662. The output terminal of the amplifier circuit 660 can generate a voltage Vrefcoarse, which can be supplied to a DAC circuit, an ADC circuit, etc. (for example, supplied to Figure 3 and Figure 4 ). For example, voltage Vrefcoarse can be supplied (e.g., generated) by an internal on-chip LDO (low dropout regulator) with a 1uF to 4uF decoupling capacitor. As another example, voltage Vrefcoarse can be generated for each (pixel) column using a unity-gain buffer without requiring additional pads for the decoupling capacitor. Voltage Vrefcoarse can be adjusted to be close to voltage Vreffine using trimming. Voltages Vreffine and Vrefcoarse can be trimmed to match a desired reference voltage (e.g., voltage V1).

[0055] The systems and methods described herein use a coarse reference (voltage) to charge the DAC capacitor plates to the coarse reference for high conversion rates, and a fine reference (voltage) to charge the DAC capacitor plates for accurate settling. In effect, the coarse reference is trimmed to closely match the fine reference, allowing the same coarse reference to be used as a similar fine reference voltage in the LSB group for faster conversions. In other words, the same coarse reference is used to charge the DAC capacitor plates. In other words, the coarse reference can be used to provide conversions, while the fine reference can be used to support high bandwidth. If desired, the same coarse reference can be used as the reference for the LSB group of a split-SAR ADC, as the reference accuracy requirement for the LSB group can be relaxed to m (the number of least significant bits) + 1 bit of accuracy.

[0056] According to one embodiment, a digital-to-analog conversion circuit may include a first plurality of capacitors associated with a first capacitor bank. The first plurality of capacitors may be configured to selectively couple to a selected one of a coarse reference voltage and a fine reference voltage. The digital-to-analog conversion circuit may include a second plurality of capacitors associated with a second capacitor bank. The second plurality of capacitors may be configured to selectively couple to the coarse reference voltage.

[0057] According to another embodiment, the first plurality of capacitors may be configured to be selectively coupled to a selected one of the coarse reference voltage, the fine reference voltage, and ground.

[0058] According to another embodiment, the second plurality of capacitors may be configured to be selectively coupled to a selected one of the coarse reference voltage and the ground voltage.

[0059] According to another embodiment, the coarse reference voltage and the fine reference voltage may be voltages greater than ground.

[0060] According to another embodiment, the coarse reference voltage and the fine reference voltage may be generated based on the same initial reference voltage.

[0061] According to another embodiment, a first capacitor in the first plurality of capacitors may have a first terminal and a second terminal, the first terminal being configured to receive an input voltage, and the second terminal being configured to selectively receive the coarse reference voltage using the first switch and the second switch and to selectively receive the fine reference voltage using the first switch and the third switch.

[0062] According to another embodiment, the second terminal of the first capacitor may be configured to receive a ground voltage using a fourth switch.

[0063] According to another embodiment, the second capacitor of the second plurality of capacitors may have a third terminal and a fourth terminal, the third terminal configured to receive the coarse reference voltage using a fifth switch, and the fourth terminal configured to receive the ground voltage using a sixth switch.

[0064] According to another embodiment, the digital-to-analog conversion circuit may include an additional capacitor having a first terminal and a second terminal, the first terminal coupled to the first capacitor bank and the second terminal coupled to the second capacitor bank.

[0065] According to another embodiment, the digital-to-analog conversion circuit may include an input sampling switch coupled to the first terminal of the additional capacitor, the first terminal configured to receive an input voltage using the input sampling switch and configured to provide an output voltage.

[0066] According to one embodiment, an analog-to-digital conversion circuit may include a digital-to-analog conversion circuit; a comparator having an input terminal coupled to the digital-to-analog conversion circuit and an output terminal; and a control circuit coupled to the output terminal and to the digital-to-analog conversion circuit. The digital-to-analog conversion circuit may be configured to receive a first reference voltage, a second reference voltage, and a ground voltage.

[0067] According to another embodiment, the digital-to-analog conversion circuit may include a plurality of capacitors coupled to the first reference voltage, the second reference voltage, and a ground voltage using a plurality of switches.

[0068] According to one embodiment, the analog-to-digital conversion circuit may include a switch through which the digital-to-analog conversion circuit receives an input signal. The plurality of capacitors may each have a first terminal and a second terminal, the first terminal being coupled to the switch, and the second terminal being coupled to the first reference voltage, the second reference voltage, and the ground voltage using a set of switches among the plurality of switches.

[0069] According to another embodiment, the control circuit may be configured to provide control signals to the plurality of switches.

[0070] According to another embodiment, the control circuit may be configured to provide a corresponding bit of the control signal to each of the plurality of switches.

[0071] According to another embodiment, the control circuit may include a successive approximation register.

[0072] According to another embodiment, the digital-to-analog conversion circuit may include a split-capacitor digital-to-analog converter.

[0073] According to one embodiment, an imaging system may include an image sensor pixel array arranged in columns and rows; an analog-to-digital conversion circuit coupled to the image sensor pixel array via a plurality of pixel output lines; and a reference signal generation circuit coupled to the analog-to-digital conversion circuit, operable to generate a first reference voltage and a second reference voltage based on a target voltage, and operable to provide the first reference voltage and the second reference voltage to the analog-to-digital conversion circuit.

[0074] According to another embodiment, the image sensor pixels in the image sensor pixel array are operable to generate analog image signals, and the analog-to-digital conversion circuit is operable to convert the analog image signals into digital image data using the first reference voltage and the second reference voltage.

[0075] According to another embodiment, the first reference voltage and the second reference voltage may be greater than a ground voltage.

[0076] The foregoing is merely an illustrative description of the principles of the present invention, and those skilled in the art may make various modifications. The above embodiments may be implemented individually or in any combination.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m>

Claims

1. A digital-to-analog conversion circuit, the digital-to-analog conversion circuit receiving an input signal, the digital-to-analog conversion circuit comprising: a first plurality of capacitors associated with a first capacitor bank, wherein each capacitor of the first plurality of capacitors is configured to sample the input signal at a first terminal and receive a selected one of a coarse reference voltage, a fine reference voltage, and an additional reference voltage at a second terminal, and wherein the first terminal of a given capacitor of the first plurality of capacitors is configured to receive the input voltage of the input signal using a sampling switch, and the second terminal of the given capacitor of the first plurality of capacitors is configured to selectively receive the coarse reference voltage using a first switch and a second switch and selectively receive the fine reference voltage using the first switch and a third switch; and A second plurality of capacitors is associated with a second capacitor bank, wherein each capacitor of the second plurality of capacitors is configured to sample the input signal at a first terminal and receive a selected one of the coarse reference voltage and the additional reference voltage at a second terminal.

2. The digital-to-analog conversion circuit according to claim 1, wherein: The additional reference voltage is a ground voltage.

3. The digital-to-analog conversion circuit according to claim 1, wherein: The coarse reference voltage and the fine reference voltage are voltages greater than a ground voltage.

4. The digital-to-analog conversion circuit according to claim 1, wherein: The coarse reference voltage and the fine reference voltage are generated based on the same initial reference voltage.

5. The digital-to-analog conversion circuit according to claim 1, wherein: A second terminal of a given capacitor of the first plurality of capacitors is configured to receive the additional reference voltage using a fourth switch, and wherein a second terminal of a given capacitor of the second plurality of capacitors is configured to receive the coarse reference voltage using a fifth switch, and a second terminal of a given capacitor of the second plurality of capacitors is configured to receive the additional reference voltage using a sixth switch.

6. The digital-to-analog conversion circuit according to claim 1, further comprising: an additional capacitor having a first terminal and a second terminal, wherein the first terminal of the additional capacitor is coupled to the first capacitor bank and the second terminal of the additional capacitor is coupled to the second capacitor bank; and The sampling switch is coupled to a first terminal of the additional capacitor, and the first terminal of the additional capacitor is configured to provide an output voltage of the digital-to-analog conversion circuit.

7. An analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit include: The digital-to-analog conversion circuit according to claim 1; a comparator having an input terminal coupled to the digital-to-analog conversion circuit and having an output terminal; and A control circuit is coupled to the output terminal and to the digital-to-analog conversion circuit.

8. The analog-to-digital conversion circuit according to claim 7, wherein: The control circuit is configured to provide control signals to the first switch, the second switch, and the third switch.

9. The analog-to-digital conversion circuit according to claim 7, wherein: The control circuit includes a successive approximation register, and wherein the digital-to-analog conversion circuit includes a split-capacitor digital-to-analog converter.

10. An imaging system comprising: an array of image sensor pixels arranged in columns and rows; The analog-to-digital conversion circuit according to claim 7, wherein the analog-to-digital conversion circuit is coupled to the image sensor pixel array via a plurality of pixel output lines; and a reference signal generating circuit coupled to the analog-to-digital conversion circuit, the reference signal generating circuit operable to generate the coarse reference voltage and the fine reference voltage based on the same initial voltage, and operable to provide the coarse reference voltage and the fine reference voltage to the analog-to-digital conversion circuit.

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