Display device and method of manufacturing the same

Abstract

A display device includes: a substrate including a display area and a non-display area disposed near the display area; a plurality of pixels disposed in the display area; a plurality of signal lines disposed on the substrate and connected to the plurality of pixels; and a pad portion disposed in the non-display area and including a plurality of pads. The plurality of signal lines include: a first crack detection line connected to a first test voltage pad and a first pad at a first node, connected to a second pad at a second node, and extending along the non-display area between the first node and the second node; and a first data line including one end connected to a first transistor connected to the first crack detection line at the second node and the other end connected to a corresponding pixel among the plurality of pixels.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a display device and a method of manufacturing the same. Background Art

[0002] As display devices become smaller, lighter, and thinner, it is desirable to improve the durability of the display devices against cracks, scratches, and the like that may occur due to external impacts.

[0003] The display device includes a display panel including pixels for displaying an image. When the display panel is cracked, foreign matter such as moisture may penetrate into a display area of ​​the display panel, thereby causing defects.

[0004] A crack test of a display panel may be performed after an integrated circuit (IC) is mounted on the display panel. However, in a cell state, such a crack test may not be able to determine whether a crack exists in the display panel. Summary of the invention

[0005] Exemplary embodiments of the present invention are directed to a display device and a method for manufacturing the same that can detect whether a crack is generated in a display panel before and after an integrated circuit (IC) is mounted on the display panel. Exemplary embodiments further provide effective detection of the location of a crack generated in the display panel.

[0006] According to an exemplary embodiment, a display device includes: a substrate including a display area and a non-display area disposed near the display area; a plurality of pixels disposed in the display area; a plurality of signal lines disposed on the substrate and connected to the pixels; and a pad portion disposed in the non-display area and including a plurality of pads. The signal line includes a first crack detection line connected to a first test voltage pad and a first pad at a first node, connected to a second pad at a second node, and extending around the non-display area between the first node and the second node. The signal line further includes a first data line including one end connected to a first transistor connected to the first crack detection line at a second node and the other end connected to a corresponding pixel among the plurality of pixels.

[0007] In an exemplary embodiment, the signal line further includes a plurality of second data lines, each of the second data lines including one end connected to the first crack detection line through a corresponding one of the plurality of second transistors and the other end connected to a corresponding pixel of the plurality of pixels.

[0008] In an exemplary embodiment, the signal line further includes a control line connected to gates of the first transistor and the second transistor.

[0009] In an exemplary embodiment, the crack of the first crack detection line is detected by applying an enable level voltage to the control line and applying a black gray voltage to the first test voltage pad.

[0010] In an exemplary embodiment, the display device further includes a first additional pad connected to the first pad and a second additional pad connected to the second pad. The first additional pad and the second additional pad are disposed in the non-display area. When a disable level voltage is applied to the control line, the resistance of the first crack detection line is measured using the first additional pad and the second additional pad.

[0011] In an exemplary embodiment, the display device further includes a data driving integrated circuit (IC) connected to the pad portion. The first test voltage pad, the first additional pad, and the second additional pad are in a floating state.

[0012] In an exemplary embodiment, the signal line further includes a first test voltage line including one end connected to the first test voltage pad at the first node and another end connected to the second transistor. The first test voltage line has a resistance corresponding to a line resistance of the first crack detection line.

[0013] In an exemplary embodiment, the resistance of the first test voltage line is proportional to the magnitude of the line resistance.

[0014] In an exemplary embodiment, the non-display area includes a bendable area, and the signal line includes a second crack detection line and a second data line. The second crack detection line is connected to the second test voltage pad and the third pad at a third node, connected to the fourth pad at a fourth node, and extends around the bendable area between the third node and the fourth node. The second data line includes one end connected to the second transistor connected to the second crack detection line at the third node and the other end connected to a corresponding pixel among the plurality of pixels.

[0015] In an exemplary embodiment, the first crack detection line and the second crack detection line respectively include lines reciprocating in a zigzag pattern along at least one side of the display area.

[0016] According to an exemplary embodiment, a method for manufacturing a display device includes: manufacturing a display panel; testing a crack in the display panel before mounting a driver integrated circuit (IC) to the display panel; mounting the driver IC to the display panel; and after mounting the driver IC to the display panel, testing the crack in the display panel again using the driver IC.

[0017] In an exemplary embodiment, manufacturing a display panel includes: forming a plurality of pixels in a display area of ​​a substrate, wherein the substrate includes a display area and a non-display area disposed near the display area; forming a plurality of signal lines on the substrate, wherein the signal lines are connected to the pixels; and forming a pad portion in the non-display area, wherein the pad portion includes a plurality of pads. The signal line includes a first crack detection line, the first crack detection line is connected to a first test voltage pad and a first pad at a first node, is connected to a second pad at a second node, and extends around the non-display area between the first node and the second node. The signal line further includes a first data line, the first data line includes one end connected to a first transistor connected to the first crack detection line at a second node and the other end connected to a corresponding pixel among a plurality of pixels. The signal line further includes a plurality of second data lines, each of the second data lines includes one end connected to the first crack detection line through a corresponding one of the plurality of second transistors and the other end connected to a corresponding pixel among a plurality of pixels. The signal line further includes a control line connected to gates of the first transistor and the second transistor.

[0018] In an exemplary embodiment, the method further includes measuring a resistance of the first crack detection line when retesting the crack in the display panel using the driving IC indicates that the crack has been detected.

[0019] In an exemplary embodiment, measuring the resistance of the first crack detection line includes: applying a disable level voltage to the control line; and measuring the resistance of the first crack detection line using a first additional pad and a second additional pad while applying the disable level voltage to the control line. The first additional pad is connected to the first pad, and the second additional pad is connected to the second pad. The first additional pad and the second additional pad are disposed in the non-display area.

[0020] In an exemplary embodiment, mounting the driver IC to the display panel includes connecting the data driver IC to the pad portion. When the first test voltage pad, the first additional pad, and the second additional pad are in a floating state, retesting the crack in the display panel using the driver IC is performed.

[0021] In an exemplary embodiment, measuring the resistance of the first crack detection line further includes measuring the resistance of the first crack detection line using the first pad and the second pad by the driving IC.

[0022] In an exemplary embodiment, testing a crack in the display panel includes: applying an enable level voltage to a control line; and applying a black gray voltage to a first test voltage pad.

[0023] According to an exemplary embodiment, a display device includes: a substrate including a display area and a non-display area disposed near the display area, wherein the non-display area includes a bendable area; a plurality of pixels disposed in the display area; and a plurality of signal lines disposed on the substrate and connected to the pixels. The signal lines include: a plurality of data lines connected to the pixels; a first crack detection line connected to a first data line among the plurality of data lines through a first transistor, wherein the first crack detection line is disposed in a portion of the non-display area other than the bendable area; a second crack detection line connected to a second data line among the plurality of data lines through a second transistor, wherein the second crack detection line is disposed in the bendable area; and a control line connected to a gate of the first transistor and a gate of the second transistor. The first crack detection line includes a plurality of lines extending in a first direction, and at least one of the lines is disposed between a line disposed closest to an edge of the substrate and a line disposed farthest from an edge of the substrate.

[0024] In an exemplary embodiment, the display device further includes: a first test voltage pad disposed in the non-display area and connected to the first crack detection line; a second test voltage pad disposed in the non-display area and connected to the second crack detection line; and a data drive IC disposed in the non-display area and connected to the first crack detection line and the second crack detection line. The first test voltage pad and the second test voltage pad are in a floating state.

[0025] In an exemplary embodiment, the data driving IC measures the resistance of the first crack detection line and the resistance of the second crack detection line.

[0026] According to the exemplary embodiment, before and after the IC is mounted on the display panel, it is possible to effectively and accurately detect whether a crack is generated in the display panel. In addition, the location of the crack in the display panel can be effectively found. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 A perspective view showing a display apparatus according to an exemplary embodiment of the present invention.

[0029] Figure 2 A layout diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0030] Figure 3 A flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention.

[0031] Figure 4 A waveform diagram illustrating a signal applied to a display device according to an exemplary embodiment of the present invention.

[0032] Figure 5 A display area of ​​a display device to which a test signal is applied is shown.

[0033] Figure 6 A layout diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0034] Figure 7 Show Figure 6 The first part of the display device.

[0035] Figure 8 Show Figure 6 The second part of the display device.

[0036] Fig. 9 A flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0037] Exemplary embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings.Like reference numerals may refer to the same elements throughout the drawings.

[0038] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0039] For ease of description, spatially relative terms such as "below," "beneath," "under," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another element (other elements) or feature (other features) as shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figure is flipped, an element described as being "below" or "below" or "under" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may encompass both orientations of above and below.

[0040] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0041] Now refer to Figure 1 and Figure 2 A display device according to an exemplary embodiment is described. Figure 1 A perspective view showing a display apparatus according to an exemplary embodiment of the present invention. Figure 2A layout diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0042] refer to Figure 1 The display device includes a display panel, and the display panel includes a substrate 100, a driving circuit part 200, and test voltage pads 120a and 120b.

[0043] The substrate 100 is an insulating substrate including, for example, glass, polymer, or stainless steel. The substrate 100 may be flexible, stretchable, foldable, bendable, or rollable. As a result, the display device may be flexible, stretchable, foldable, bendable, or rollable. For example, the substrate 100 may have a flexible film including a resin such as polyimide.

[0044] exist Figure 1 In the exemplary embodiment shown in , the non-display area NDA surrounds the display area DA. However, the present invention is not limited thereto. For example, in an exemplary embodiment, the non-display area NDA may be disposed on any one side or each side of the display area DA.

[0045] The display panel includes a display area DA in which an image is displayed, and a non-display area NDA disposed adjacent to the display area DA, in which elements and / or signal lines for generating and / or transmitting various signals applied to the display area DA are formed.

[0046] A plurality of pixels and signal lines applying signals for driving the plurality of pixels may be provided in the display area DA.

[0047] The crack detection lines CD1 and CD2, the test controller 110 detecting defects of the crack detection lines, and the driving circuit part 200 driving a plurality of pixels may be disposed in the non-display area NDA. The pixels are not disposed in the non-display area NDA.

[0048] The driving circuit part 200 may be bonded to the substrate 100 of the display panel by a chip on glass process or a chip on plastic process. Alternatively, the driving circuit part 200 may be formed simultaneously with the plurality of data lines D1 to Dm, the plurality of scan lines, and the plurality of pixels P according to an amorphous silicon TFT gate driver (ASG) scheme or a gate driver on panel (GIP) scheme. The driving circuit part 200 is mounted on a tape carrier package (TCP) or a flexible film, and the tape carrier package (TCP) or the flexible film on which the driving circuit part 200 is mounted may be attached to the substrate 100 of the display panel according to a tape automated bonding (TAB) process.

[0049] like Figure 2As shown in FIG. 1 , the display area DA of the substrate 100 includes a plurality of pixels P, a plurality of data lines D1 to Dm, and a plurality of gate lines G1 to Gn connected to the pixels P. Each pixel P is a minimum unit for displaying an image. The plurality of pixels P may basically have a matrix form and may be arranged in the display area DA.

[0050] Test voltage pads 120a and 120b, test control pads 130, test controller 110, and driving circuit parts 200a and 200b may be disposed in the non-display area NDA of substrate 100. Driving circuit part 200a may be a data driver 200a, and driving circuit part 200b may be a gate driver 200b.

[0051] Test voltage pads 120a and 120b are connected to one end of test transistors T1 to To. The same test voltage or different test voltages can be supplied to test voltage pads 120a and 120b. After the drive circuit portion 200a is assembled (for example, after the drive circuit portion 200a is mounted to the display panel), the test voltage pads 120a and 120b are in a floating state.

[0052] The test control pad 130 is connected to the respective gates of the test transistors T1 to To. A test control signal is supplied to the test control pad 130.

[0053] The test controller 110 includes a plurality of test transistors T1 to To. The test transistors T1 to To may be disposed between the driving circuit part 200a in the display area DA and the non-display area NDA. The test transistors T1 to To are connected between the data lines D1 to Dm and the test voltage pads 120a and 120b.

[0054] The line TG connected to the gates of the test transistors T1 to To is connected to the test control pad 130. The gates of the test transistors T1 to To and the line TG may be a single line. Herein, the line TG may be referred to as a control line.

[0055] Each gate of the test transistors T1 to To is connected to the test control pad 130 through the line TG, one end (e.g., the first end) of the test transistors T1 to To is connected to one of the test voltage pads 120a and 120b, and the other end (e.g., the second end) of the test transistors T1 to To is connected to one of the data lines D1 to Dm.

[0056] The corresponding crack detection lines CD1 and CD2 may be connected between respective one ends of the test transistors T2 and To- 1 among the test transistors T1 to To and the corresponding test voltage pads 120 a and 120 b .

[0057] The first crack detection line CD1 may be connected between one end of the test transistor T2 connected to the data line D2 and the test voltage pad 120a. The second crack detection line CD2 may be connected between one end of the test transistor To-1 connected to the data line Dm-1 and the test voltage pad 120b.

[0058] The first crack detection line CD1 and the second crack detection line CD2 may be disposed in the non-display area NDA disposed outside the display area DA.

[0059] The first crack detection line CD1 and the second crack detection line CD2 may be disposed at a position further outside than the gate driver 200b. For example, the gate driver 200b may be disposed between the first crack detection line CD1 in the display area DA and the non-display area NDA.

[0060] The first crack detection line CD1 and the second crack detection line CD2 may be lines extending around the outside of the display area DA. Figure 2 As shown in , the first crack detection line CD1 may be disposed at the left outer portion of the display area DA, and the second crack detection line CD2 may be disposed at the right outer portion of the display area DA. For example, the first crack detection line CD1 may be disposed so that it extends around the left outer portion of the display area DA, and the second crack detection line CD2 may be disposed so that it extends around the right outer portion of the display area DA.

[0061] Between one ends of the test transistors T1, T3 to To-2 and To not connected to the first and second crack detection lines CD1 and CD2 and the test voltage pads 120a and 120b, corresponding test voltage lines ML1 and ML2 may be connected at nodes N1 and N3.

[0062] In an exemplary embodiment, the first crack detection line CD1 may be connected to the test voltage pad 120a and the pad 140a at a node N1, and connected to the pad 140b at a node N2. Figure 2 As shown in , the first crack detection line CD1 may extend around the non-display area NDA between the node N1 and the node N2.

[0063] The driving circuit part may include a data driver 200a connected to a data pad connected to the plurality of data lines D1 to Dm and supplying a data voltage, and a gate driver 200b supplying a gate signal to the plurality of gate lines G1 to Gn.

[0064] In the exemplary embodiments described herein, the data driver 200a will be described as being mounted on a substrate as a data driver IC. The data driver IC 200a may be connected to the pads 140a to 140d to supply a voltage and / or current for performing a crack test to the crack detection lines CD1 and CD2.

[0065] The data drive IC 200a may be connected to lines L1 to L4 connected to the first and second crack detection lines CD1 and CD2 through pads 140a to 140d. The lines L1 to L4 are connected to the first and second crack detection lines CD1 and CD2 at corresponding nodes N1 to N4.

[0066] In reference Figure 2 The exemplary embodiment described has described that the gate driver 200b is disposed on the left side of the non-display area NDA, and the data driver IC 200a, the test transistors T1 to To, the test voltage pads 120a and 120b, and the test control pad 130 are disposed on the lower side of the non-display area NDA. However, the arrangement of the signal lines, pad portions, transistors, and drivers in the non-display area NDA is not limited thereto.

[0067] Now refer to Figures 3 to 5 Description for detection Figure 2 A method of displaying defects of a device.

[0068] Figure 3 A flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention. Figure 4 A waveform diagram illustrating a signal applied to a display device according to an exemplary embodiment of the present invention. Figure 5 A display area of ​​a display device to which a test signal is applied is shown.

[0069] refer to Figure 3 and Figure 4 , manufacturing a display panel (S100). The manufactured display panel may be, for example, Figure 2 . Therefore, manufacturing the display panel includes, for example, forming pixels P in a display area DA of a substrate 100, forming a signal line described herein on the substrate 100, and forming a pad portion including a pad described herein in a non-display area NDA. The defect of the crack line is tested by applying a predetermined voltage to the test voltage pads 120a and 120b (S110).

[0070] When the test control signal TS applied to the test control pad 130 is at an enable level L (e.g., when the test control signal TS is an enable level voltage), the test transistors T1 to To may be turned on. The test control signal TS may be applied to the transistors T1 to To via the control line TG. The test voltage Vtest applied to the test voltage pads 120a and 120b may have a voltage level corresponding to a black grayscale. It will be assumed that the test voltage is at a disable level H. The test voltage may then be supplied to the data lines D1 to Dm through the turned-on test transistors T1 to To.

[0071] The gate signals G[1] to G[n] may be sequentially changed to the enable level L in the time period t1 to tn in which the test control signal TS is at the enable level L. For example, the gate signal G[1] is changed to the enable level L at t1, and is changed to the disable level H at t2. The gate signal G[2] is changed to the enable level L at t2.

[0072] Although the enable level in the exemplary embodiment described herein is a low level L, and the disable level in the exemplary embodiment described herein is a high level H, the present invention is not limited thereto. For example, in an exemplary embodiment, the enable level may be a high level H, and the disable level may be a low level L.

[0073] When the gate signals G[1] to G[n] are applied to the pixel P, the test voltage may be written to the pixel P. The pixel P represents a black grayscale by the test voltage written to the pixel P.

[0074] However, when a crack is generated in the display panel, the data lines D1 to Dm or the first and second crack detection lines CD1 and CD2 may be disconnected or line resistance of the data lines D1 to Dm or the first and second crack detection lines CD1 and CD2 may increase.

[0075] For example, when a crack in which the data line D2 or the first crack detection line CD1 is disconnected is generated in the display panel, the test voltage is not applied to the data line D2.

[0076] As another example, when a crack is generated in the display device and the line resistance of the data line D2 or the first crack detection line CD1 increases, the test voltage applied to the data line D2 has a predetermined level lower than the disable level H due to a voltage drop caused by the increase in line resistance.

[0077] Therefore, the voltage supplied to the pixel connected to the data line D2 has a level lower than the disable level H. The pixel connected to the data line D2 exhibits a white gray to a gray gray that is brighter than a black gray due to the voltage having a lower level. That is, a bright line can be exhibited by the pixel connected to the data line D2.

[0078] like Figure 5 As shown in FIG. 1 , the pixel PC2 connected to the data line D2 for receiving the test voltage exhibits a white grayscale to a gray grayscale through the first crack detection line CD1. As a result, Figure 5 The bright line shown in FIG. 1 may be visible. Therefore, it may be determined that a crack is generated in the area where the first crack detection line CD1 is disposed in the non-display area NDA.

[0079] The bright line may be represented by the pixel PCi connected to the data line Di connected to the test transistor Ti which is not connected to the first crack detection line CD1 and the second crack detection line CD2. It may be determined that this is not generated by a crack in the display device but by another factor.

[0080] The pixel PCm-1 refers to the pixel P connected to the data line Dm-1 (see Figure 2 ). The pixel PCm-1 connected to the data line Dm-1 for receiving the test voltage shows a black grayscale through the second crack detection line CD2, so the dark line may be visible. It can be determined that this is because no crack is generated in the area where the second crack detection line CD2 is set in the non-display area NDA.

[0081] As described above, whether the display device is cracked can be determined in S110 by a bright line seen according to a disconnection state or a change in line resistance of the data lines D1 to Dm and a disconnection state or a change in line resistance of the crack detection lines CD1 and CD2 formed outside the display area DA. Further, the location where the crack is generated can be checked according to the location where the bright line is seen.

[0082] When a bright line is represented by the pixel PC2 or PCm-2 respectively connected to the data line D2 or Dm-2 for receiving the test voltage from the crack detection lines CD1 and CD2, it is determined that a crack is generated in the display panel (S150).

[0083] When no bright line is seen in S110 , the display panel is determined to be a good product (eg, no crack is detected), and a module process for mounting the data drive IC 200 a on the display panel is performed ( S120 ).

[0084] After the module process is performed, the resistance of the crack detection lines CD1 and CD2 is tested by the data driving IC 200a (S130). When the resistance of the crack detection lines CD1 and CD2 is tested, the test control signal TS at the disable level H is applied to the test control pad 130, and the test transistors T1 to To are turned off.

[0085] The data driving IC 200 a may measure the resistance of the crack detection line CD1 using the lines L1 and L2 connected to the crack detection line CD1 , and may measure the resistance of the crack detection line CD2 using the lines L3 and L4 connected to the crack detection line CD2 .

[0086] In an exemplary embodiment, the data driving IC 200a includes a variable resistor, and the resistance of the crack detection lines CD1 and CD2 may be measured by comparing the resistance of the crack detection lines CD1 and CD2 with the resistance of the variable resistor. However, the method for measuring resistance according to the exemplary embodiment is not limited thereto.

[0087] When the measured resistance is within the predetermined range, it is determined that no crack is generated in the crack detection lines CD1 and CD2 (S140). That is, the display panel is determined to be a good product again.

[0088] When the measured resistance exceeds the predetermined range, it is determined that cracks are generated in the crack detection lines CD1 and CD2 (S150).

[0089] As described above, the exemplary embodiments provide a display device and a method for manufacturing the same, in which whether a crack is generated in a display panel can be effectively detected before and after a driver IC is mounted on the display panel. Figure 3 In S120, the display device is first determined to be free of defects before the data driver IC 200a is installed, and in S140, the display device is again determined to be free of defects after the data driver IC 200a is installed. Further, the exemplary embodiment provides a display device and a method for manufacturing the same, in which the location of a crack in a display panel can be effectively determined.

[0090] Now refer to Figures 6 to 9 A display device and a method of manufacturing the same according to exemplary embodiments are described.

[0091] Figure 6 A layout diagram of a display device according to an exemplary embodiment of the present invention is shown. Figure 7 Show Figure 6 The first part of the display device. Figure 8 Show Figure 6 The second part of the display device.

[0092] For ease of explanation, when describing Figure 6 When displaying devices as shown in , the previous references are omitted. Figure 2 Further description of the same or similar configurations and elements described in the display device shown in .

[0093] The non-display area NDA may include a bendable area BA. Figure 6, the bendable area BA is shown to be disposed at the lower side of the display area DA. However, the position and number of the bendable area BA are not limited thereto. The bendable area BA refers to an area that is bent and an area that will be bent in a subsequent process.

[0094] Test voltage pads 120a, 120b, 120c, and 120d are connected to one end of test transistors T1 to To. The same test voltage or different test voltages may be supplied to the test voltage pads 120a, 120b, 120c, and 120d. The periods during which the test voltages are applied to the test voltage pads 120a, 120b, 120c, and 120d may be the same or different.

[0095] The test transistors T1 to To are connected between the data lines D1 to Dm and the test voltage pads 120 a , 120 b , 120 c , and 120 d .

[0096] The respective gates of the test transistors Tl to To can be connected to the test control pad 130 through the line TG, one end of the test transistors Tl to To can be connected to one of the test voltage pads 120a, 120b, 120c and 120d, and the other end of the test transistors T1 to To can be connected to a corresponding one of the data lines D1 to Dm.

[0097] The corresponding crack detection lines CD1 and CD2 may be connected between respective one ends of some of the test transistors T2 , T4 , and To- 1 among the test transistors T1 to To and the corresponding test voltage pads 120 a and 120 b .

[0098] The corresponding crack detection lines CD3 and CD4 may be connected between respective one ends of some of the test transistors T3 and To-2 among the test transistors T1 to To and the corresponding test voltage pads 120 c and 120 d .

[0099] The first crack detection line CD1 may be connected between one end of the test transistor T2 connected to the data line D2, one end of the test transistor T4 connected to the data line D4, and the test voltage pad 120a. The second crack detection line CD2 may be connected between one end of the test transistor To-1 connected to the data line Dm-1 and the test voltage pad 120b.

[0100] The third crack detection line CD3 may be connected between one end of the test transistor T3 connected to the data line D3 and the test voltage pad 120c. The fourth crack detection line CD4 may be connected between one end of the test transistor To-2 connected to the data line Dm-2 and the test voltage pad 120d.

[0101] The first crack detection line CD1 and the second crack detection line CD2 may be respectively disposed in a non-display area NDA disposed outside the display area DA. The first crack detection line CD1 and the second crack detection line CD2 may extend along both sides of the display area, respectively.

[0102] The first crack detection line CD1 may be a line that reciprocates (e.g., moves back and forth alternately) in a zigzag pattern along one side of the display area DA. The second crack detection line CD2 may be a line that reciprocates (e.g., moves back and forth alternately) in a zigzag pattern along one side of the display area DA. The first crack detection line CD1 and the second crack detection line CD2 may be lines that reciprocate (e.g., move back and forth alternately) in a zigzag pattern in the non-display area NDA except the bendable area BA. The first crack detection line CD1 and the second crack detection line CD2 may be single lines and may be arranged so that they extend along the circumference of the display area DA. However, the arrangement of the first crack detection line CD1 and the second crack detection line CD2 is not limited thereto.

[0103] Now refer to Figure 7 Describe the position and form of the first crack detection line CD1 and the second crack detection line CD2, Figure 7 yes Figure 6 Magnified view of area A1 in FIG.

[0104] The first crack detection line CD1 is disposed in the area A1. The first crack detection line CD1 includes a plurality of lines CD11, CD12, CD13, and CD14 extending in different directions.

[0105] Each of the lines CD11, CD12, CD13, and CD14 extends in the X-axis direction. For example, the lines CD11 and CD13 extend in the positive X-axis direction, and the lines CD12 and CD14 extend in the negative X-axis direction.

[0106] Further, the plurality of lines CD11, CD12, CD13, and CD14 are disposed so that they may have different shortest distances from the edge 101 of the substrate 100. For example, the line CD11 is disposed to be spaced apart from the edge 101 of the substrate 100 by a length L1 in the Y-axis direction, and the line CD14 is disposed to be spaced apart from the edge 101 of the substrate 100 by a length L2 in the Y-axis direction.

[0107] In this case, at least one line CD12 and / or CD13 may be disposed between a line CD11 disposed closest to an edge 101 of the substrate 100 and a line CD14 disposed farthest from an edge 101 of the substrate 100, and the third crack detection line CD3 and the fourth crack detection line CD4 may be disposed in the bendable area BA of the non-display area NDA, respectively. The third crack detection line CD3 may be a line that reciprocates (e.g., moves back and forth alternately) in a zigzag pattern in the bendable area BA. The fourth crack detection line CD4 may be a line that reciprocates (e.g., moves back and forth alternately) in a zigzag pattern in the bendable area BA. The third crack detection line CD3 and the fourth crack detection line CD4 may be single lines and may be disposed so that they extend along the circumference of the display area DA. However, the arrangement of the third crack detection line CD3 and the fourth crack detection line CD4 is not limited thereto.

[0108] Now refer to Figure 8 Describe the position and form of the third crack detection line CD3 and the fourth crack detection line CD4, Figure 8 yes Figure 6 2 is an enlarged view of the area A2 in FIG. The third crack detection line CD3 is set in the area A2. The third crack detection line CD3 includes a plurality of lines CD31, CD32, CD33 and CD44 extending in different directions.

[0109] Each of the lines CD31 , CD32 , CD33 , and CD34 extends in the Y-axis direction. For example, the lines CD31 and CD33 extend in the positive Y-axis direction, and the lines CD32 and CD34 extend in the negative Y-axis direction.

[0110] The plurality of lines CD31, CD32, CD33, and CD34 are disposed so that they may have different shortest distances from the edge 102 of the substrate 100. For example, the line CD31 is disposed to be spaced apart from the edge 102 of the substrate 100 by a length L3 in the X-axis direction, and the line CD34 is disposed to be spaced apart from the edge 102 of the substrate 100 by a length L4 in the X-axis direction.

[0111] In this case, at least one line CD32 and / or CD33 may be disposed between the line CD31 disposed closest to the edge 102 of the substrate 100 and the line CD34 disposed farthest from the edge 102 of the substrate 100 .

[0112] When the first crack detection line CD1 and the third crack detection line CD3 are arranged on the same side (e.g., the left side) in the non-display area NDA, they are arranged in different areas. As a result, the position where the crack is generated in the display panel can be detected more accurately. The second crack detection line CD2 and the fourth crack detection line CD4 also have the same effect.

[0113] Between one end of the test transistors T1, Ti-1 to Ti+1, To, etc. not connected to the first to fourth crack detection lines CD1 to CD4 and the test voltage pads 120a and 120b, corresponding test voltage lines ML1 and ML2 may be connected at nodes N1 and N3.

[0114] Resistors R1 and R2 may be further disposed in the non-display area NDA. The resistors R1 and R2 may be formed by the first test voltage line ML1 or the second test voltage line ML2. The resistor R1 may be disposed between the first node N1 and one end of the test transistor T1.

[0115] The resistors R1 and R2 may be formed to compensate for a voltage difference between a test voltage value applied to the data lines D2, D4, and Dm-1 and a test voltage applied to the data lines D1, Di-1 to Di+1, Dm, etc., through line resistance of the first and second crack detection lines CD1 and CD2.

[0116] That is, the resistor R1 and the resistor R2 can be connected between one end of the test transistors T1, Ti-1 to Ti+1, To, etc. that are not connected to the first to fourth crack detection lines CD1 to CD4 and the first test voltage line ML1 and the second test voltage line ML2 for connecting the test voltage pads 120a and 120b.

[0117] In this case, the deviation of the test voltage caused by the line resistance of the crack detection line CD1 may be minimized or reduced by designing the resistance of the resistor R1 using the line resistance of the crack detection line CD1. For example, the resistance of the resistor R1 may be designed according to Equation 1.

[0118] (Equation 1)

[0119]

[0120] Here, R is the resistance of resistor R1, R CD is the line resistance of the crack detection line CD1, k is the number of data lines connected to the first test voltage line ML1, and T is the number of data lines connected to the crack detection line CD1. In this case, 1.25 is a modifiable constant, which is a positive integer greater than 0.

[0121] The resistor R1 may be designed by changing the form of the first test voltage line ML1 in the region where the first test voltage line ML1 is provided. For example, the resistor R1 satisfying the resistance calculated by Equation 1 may be formed by controlling the thickness, length or width of the first test voltage line ML1.

[0122] The first test voltage line ML1 may be disposed in a region disposed between a region where the test voltage pad 120 a is disposed and a region where one end of the test transistor T1 is disposed, and thus a region where a line for the resistor R1 is disposed may be obtained.

[0123] According to an exemplary embodiment, the resistance of the first test voltage line ML1 may be proportional to the size of the line resistance.

[0124] A method for designing the resistance of resistor R1 can be described. The resistance of resistor R2 can be designed in a similar manner.

[0125] The pads 140a to 140h are connected to the crack detection lines CD1 to CD4. For example, one end of the crack detection line CD1 is connected to the pad 140a, and the other end is connected to the pad 140b. One end of the crack detection line CD3 is connected to the pad 140e, and the other end is connected to the pad 140f.

[0126] The data driving IC 200a may be connected to the pads 140a to 140h. The data driving IC 200a may supply a voltage and / or a current for testing a crack to the crack detection lines CD1 to CD4 through the pads 140a to 140h.

[0127] Additional pads 121a to 121h connected to the pads 140a to 140h are provided in the non-display area NDA. Before the connection of the data drive IC 200a, a voltage and / or current for testing a crack may be supplied to the crack detection lines CD1 to CD4 through the additional pads 121a to 121h. The additional pads 121a to 121h are combined with the data drive IC 200a and then in a floating state.

[0128] The data drive IC 200a may be connected to lines L1 to L4 connected to the first and second crack detection lines CD1 and CD2 through pads 140a to 140d. The lines L1 to L4 are connected to the first and second crack detection lines CD1 and CD2 at corresponding nodes N1 to N4.

[0129] For example, the line L1 is connected to the node N1, at which the test voltage line ML1 is connected to the first crack detection line CD1. The resistor R1 is connected between the node N1 and one end of the test transistor T1. The line L2 is connected to the node N2 provided between the first crack detection line CD1 and one end of the test transistor T2. That is, the lines L1 and L2 are connected to the node N1 at which the first crack detection line CD1 extends from the test voltage pad 120a to the outside of the display area DA and the node N2 at which the first crack detection line CD1 is led out from the outside of the display area DA to the test transistor T2.

[0130] In a similar manner, line L3 is connected to the test voltage line ML2 to the node N3 where the second crack detection line CD2 is located. Resistor R2 is connected between the node N3 and one end of the test transistor To. Line L4 is connected to a node N4 disposed between the second crack detection line CD2 and one end of the test transistor To-1. That is, lines L3 and L4 are connected to the node N3 where the second crack detection line CD2 extends from the test voltage pad 120b to the outside of the display area DA and the second crack detection line CD2 is led out from the outside of the display area DA to the node N4 where the test transistor To is located.

[0131] The data drive IC 200a may be connected to lines L5 to L8 connected to the third and fourth crack detection lines CD3 and CD4 through pads 140e to 140h. The lines L5 to L8 are connected to the third and fourth crack detection lines CD3 and CD4 at corresponding nodes N5 to N8.

[0132] For example, line L5 is connected to the third crack detection line CD3 and extends from the test voltage pad 120c to the node N5 outside the display area DA. Line L6 is connected to the third crack detection line CD3 and leads from the outside of the display area DA to the node N6 where the test transistor T3 is located.

[0133] In a similar manner, line L7 is connected to the fourth crack detection line CD4 extending from the test voltage pad 120d to the node N7 outside the display area DA. Line L8 is connected to the fourth crack detection line CD3 extending from the outside of the display area DA to the node N8 where the test transistor To-2 is located.

[0134] In reference Figure 6 In the described exemplary embodiment, it is shown that the gate driver 200b is disposed on the left side of the non-display area NDA, and the data driver IC 200a, the test transistors T1 to To, the test voltage pads 120a to 120d, and the test control pad 130 are disposed on the lower side of the non-display area NDA. However, the arrangement of the signal lines, pad portions, transistors, and drivers of the non-display area NDA is not limited thereto.

[0135] Now refer to Fig. 9 Description for detection Figure 6 A method of displaying defects of a device.

[0136] Fig. 9 A flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention.

[0137] The display panel is manufactured (S200). The manufactured display panel may be, for example, Figure 6 The display panel shown in .

[0138] A predetermined voltage is applied to the test voltage pads 120a to 120d to test whether the crack line has a defect (S210). Figure 3 In a manner similar to that of S110 , the bright line may be represented by pixels connected to the data line connected to the crack detection line.

[0139] In S210, when bright lines are represented by pixels connected to data lines D2 and D4, D3, Dm-2 or Dm-1 for receiving a test voltage through the crack detection lines CD1 to CD4, resistances of the crack detection lines CD1 to CD4 are tested (S240).

[0140] In S240 , when the resistances of the crack detection lines CD1 to CD4 are tested, the test control signal TS at the disable level H is applied to the test control pad 130 so that the test transistors T1 to To are in a turned-off state.

[0141] The resistance may be measured, for example, by applying a current to an additional pad connected to a crack detection line corresponding to a bright line among the additional pads 121a to 121h. When the bright line is represented by a pixel connected to the data line Dm-1, the resistance of the crack detection line CD2 may be measured by the additional pads 121c and 121d connected to the crack detection line CD2 corresponding to the data line Dm-1.

[0142] In S210, when bright lines caused by pixels connected to the data lines D2 and D4, D3, Dm-2 or Dm-1 for receiving a test voltage through the crack detection lines CD1 to CD4 are not seen, the display panel is determined to be a good product, and a module process for mounting the data driver IC 200a on the display panel is performed (S220).

[0143] After the module process is performed, whether the crack detection lines CD1 to CD4 have defects is tested by the data driver IC 200a (S230). The data driver IC 200a may test defects of the crack detection lines CD1 to CD4 by applying a test voltage to the pads 140a, 140e, 140c, and 140g.

[0144] In S230, when bright lines are represented by pixels connected to data lines D2 and D4, D3, Dm-2 or Dm-1 for receiving a test voltage from the crack detection lines CD1 to CD4, resistances of the crack detection lines CD1 to CD4 are tested by the data driving IC 200a (S240).

[0145] In S230, when the bright line is seen, the data drive IC 200a may measure the resistance of the crack detection line CD1 using the line L1 and the line L2 connected to the crack detection line CD1, and may measure the resistance of the crack detection line CD2 using the line L3 and the line L4 connected to the crack detection line CD2. The data drive IC 200a may measure the resistance of the crack detection line CD3 using the line L5 and the line L6 connected to the crack detection line CD3, and may measure the resistance of the crack detection line CD4 using the line L7 and the line L8 connected to the crack detection line CD4.

[0146] In S240 , when the measured resistance is within the predetermined range, it is determined that no crack is generated in the crack detection lines CD1 to CD4 , and a defect is generated in a line (eg, a data line or a gate line) in the display panel ( S242 ).

[0147] In S240 , when the measured resistance exceeds the predetermined range, it is determined that cracks are generated in the crack detection lines CD1 to CD4 ( S244 ).

[0148] In S230, when the bright line is not visible, it is determined that no cracks are generated in the crack detection lines CD1 to CD4, and no defects are generated in the lines (eg, data lines and gate lines) in the display panel (S250). That is, the display panel is determined to be a good product again.

[0149] As described above, according to the display device and the manufacturing method thereof according to the exemplary embodiment, it is possible to effectively detect whether a crack is generated in the display panel before and after the driver IC is mounted on the display panel. Further, according to the display device and the manufacturing method thereof according to the exemplary embodiment, it is possible to accurately determine whether a crack is generated in the display panel or whether a defect is generated in the line (e.g., data line and gate line) in the display panel. In addition, according to the display device and the manufacturing method thereof according to the exemplary embodiment, the position of the crack in the display panel can be effectively detected.

[0150] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area arranged near the display area; A plurality of pixels are arranged in the display area; A plurality of signal lines, disposed on the substrate and connected to the pixels; as well as a pad portion, disposed in the non-display area and comprising a plurality of pads, The signal line includes: a first crack detection line, directly electrically connected to the first test voltage pad and the first pad at a first node, directly electrically connected to the second pad at a second node, and extending around the non-display area between the first node and the second node; as well as a first data line including one end connected to the first transistor connected to the first crack detection line at the second node and another end connected to a corresponding pixel among the plurality of pixels, and The first pad and the second pad supply a voltage and / or a current for performing a crack test to the first crack detection line.

2. The display device according to claim 1, wherein the signal line further comprises: A plurality of second data lines, each of the second data lines including one end connected to the first crack detection line through a corresponding one of the plurality of second transistors and another end connected to a corresponding pixel among the plurality of pixels.

3. The display device according to claim 2, wherein the signal line further comprises: A control line is connected to the gates of the first transistor and the second transistor. 4 . The display device of claim 3 , wherein the crack of the first crack detection line is detected by applying an enable level voltage to the control line and applying a black gray voltage to the first test voltage pad.

5. The display device according to claim 3, further comprising: a first additional pad connected to the first pad; as well as a second additional pad connected to the second pad, wherein the first additional pad and the second additional pad are disposed in the non-display area, Wherein, when a disable level voltage is applied to the control line, the resistance of the first crack detection line is measured using the first additional pad and the second additional pad.

6. The display device according to claim 5, further comprising: A data driving integrated circuit connected to the pad portion, The first test voltage pad, the first additional pad and the second additional pad are in a floating state.

7. The display device according to claim 2, wherein the signal line further comprises: a first test voltage line including one end connected to the first test voltage pad at the first node and another end connected to the second transistor, The first test voltage line has a resistance corresponding to a line resistance of the first crack detection line. 8 . The display device according to claim 7 , wherein the resistance of the first test voltage line is proportional to a magnitude of the line resistance.

9. The display device according to claim 1, wherein the non-display area includes a bendable area, and the signal line includes: a second crack detection line connected to the second test voltage pad and the third pad at a third node, connected to the fourth pad at a fourth node, and extending around the bendable region between the third node and the fourth node; as well as a second data line including one end connected to the second transistor connected to the second crack detection line at the third node and the other end connected to a corresponding pixel among the plurality of pixels, and The third pad and the fourth pad supply the voltage and / or the current for performing the crack test to the second crack detection line. 10 . The display device of claim 9 , wherein the first crack detection line and the second crack detection line respectively comprise lines reciprocating in a zigzag pattern along at least one side of the display area.

11. A method for manufacturing a display device, comprising: Manufacturing display panels; testing cracks in the display panel using a first set of pads before mounting a driver integrated circuit to the display panel; Mounting the driver integrated circuit on the display panel; as well as After mounting the driver integrated circuit to the display panel, testing the display panel for cracks again using the driver integrated circuit and the second set of pads, The manufacturing of the display panel comprises: forming a plurality of pixels in a display area of ​​a substrate, wherein the substrate includes the display area and a non-display area disposed near the display area; forming a plurality of signal lines on the substrate, wherein the signal lines are connected to the pixels; and forming a pad portion in the non-display area, wherein the pad portion includes a plurality of pads including the first group of pads and the second group of pads, The signal line includes: a first crack detection line, directly electrically connected to the first test voltage pad and a first pad among the second group of pads at a first node, directly electrically connected to a second pad among the second group of pads at a second node, and extending around the non-display area between the first node and the second node; a first data line including one end connected to the first transistor connected to the first crack detection line at the second node and another end connected to a corresponding pixel among the plurality of pixels; a plurality of second data lines, each of the second data lines including one end connected to the first crack detection line through a corresponding one of the plurality of second transistors and another end connected to a corresponding pixel among the plurality of pixels; and a control line connected to the gates of the first transistor and the second transistor, and The first pad and the second pad supply a voltage and / or a current for performing a crack test to the first crack detection line.

12. The method according to claim 11, further comprising: When the crack in the display panel is tested again using the driving integrated circuit, indicating that a crack has been detected, the resistance of the first crack detection line is measured.

13. The method of claim 12, wherein measuring the resistance of the first crack detection line comprises: applying a disable level voltage to the control line; as well as while applying the disable level voltage to the control line, measuring the resistance of the first crack detection line using a first additional pad and a second additional pad, wherein the first additional pad is connected to the first pad, and the second additional pad is connected to the second pad, The first additional pad and the second additional pad are disposed in the non-display area.

14. The method according to claim 13, wherein mounting the driver integrated circuit to the display panel comprises: connecting a data driving integrated circuit to the pad portion, Wherein when the first test voltage pad, the first additional pad and the second additional pad are in a floating state, retesting the crack in the display panel using the driving integrated circuit is performed.

15. The method of claim 14, wherein measuring the resistance of the first crack detection line further comprises: The resistance of the first crack detection line is measured by the driving integrated circuit using the first pad and the second pad.

16. The method of claim 11, wherein testing the display panel for cracks comprises: applying an enable level voltage to the control line; as well as A black grayscale voltage is applied to the first test voltage pad.

17. A display device comprising: A substrate, comprising a display area and a non-display area disposed near the display area, wherein the non-display area comprises a bendable area; A plurality of pixels are arranged in the display area; as well as A plurality of signal lines are arranged on the substrate and connected to the pixels, The signal line includes: a plurality of data lines connected to the pixels; a first crack detection line, directly electrically connected to the first pad at a first node, directly electrically connected to the second pad at a second node, and connected to a first data line among the plurality of data lines through a first transistor, wherein the first crack detection line is disposed in a portion of the non-display area excluding the bendable area; a second crack detection line directly electrically connected to the third pad at a third node, directly electrically connected to the fourth pad at a fourth node, and connected to a second data line among the plurality of data lines through a second transistor, wherein the second crack detection line is disposed in the bendable region; and a control line connected to a gate of the first transistor and a gate of the second transistor, wherein the first crack detection line comprises a plurality of lines extending in a first direction, and at least one of the lines is disposed between a line disposed closest to an edge of the substrate and a line disposed farthest from the edge of the substrate, wherein the first pad and the second pad supply a voltage and / or a current for performing a crack test to the first crack detection line, and The third pad and the fourth pad supply the voltage and / or the current for performing the crack test to the second crack detection line.

18. The display device according to claim 17, further comprising: a first test voltage pad, disposed in the non-display area and connected to the first crack detection line; a second test voltage pad, disposed in the non-display area and connected to the second crack detection line; as well as a data driving integrated circuit disposed in the non-display area and connected to the first crack detection line and the second crack detection line, The first test voltage pad and the second test voltage pad are in a floating state.

19. The display device of claim 18, wherein the data driving integrated circuit measures a resistance of the first crack detection line using the first pad and the second pad, and measures a resistance of the second crack detection line using the third pad and the fourth pad.

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