A Central Processing Unit Physical Signal Electrical Characteristics Testing Device, System and Method

Abstract

Embodiments of the present invention disclose a central processing unit physical signal electrical characteristic testing device, system and method, which relate to the technical field of physical signal measurement and can obtain the output capability of the pins of the high-speed input / output interface of the central processing unit. The testing device includes a test board, on which a fan-out link is arranged. The first end of the fan-out link is used to be connected to the high-speed input / output interface of the central processing unit, and the second end is used to be connected to a first testing device. A de-embedding link corresponding to the fan-out link is also arranged on the test board. The de-embedding link has the same structure as the fan-out link, and both ends of the de-embedding link are respectively used to be connected to both ends of a second testing device. The present invention is applicable to testing the electrical characteristics of the physical signals of the central processing unit.

Description

Technical Field

[0001] The present invention relates to the technical field of physical signal measurement, and in particular, to a test device, system and method for the electrical characteristics of the physical signals of a central processing unit. Background Art

[0002] Currently, the high-speed input / output interfaces of a central processing unit (CPU) mainly include PCIE / SATA / USB. PCIE (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, SATA (Serial Advanced Technology Attachment) is an industry-standard serial hardware drive interface, and USB (Universal Serial Bus) is an external bus standard for standardizing the connection and communication between a computer and external devices.

[0003] As Figure 1 shown, the electrical characteristic verification of traditional CPU high-speed input / output interfaces is based on an actual product board (an actual product developed for market applications). The test points of the signal test device 104 are all tested at the end (102) of the entire link, and the output capabilities of the pins 101 of the CPU chip cannot be tested. The test results include the losses of the entire main board link 103. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a test device, system and method for the electrical characteristics of the physical signals of a central processing unit, which can obtain the output capabilities of the pins of the high-speed input / output interfaces of the central processing unit.

[0005] In a first aspect, an embodiment of the present invention provides a test device for the electrical characteristics of the physical signals of a central processing unit, including a test board. A fan-out link is provided on the test board. The first end of the fan-out link is used to be connected to the high-speed input / output interface of the central processing unit, and the second end is used to be connected to a first test device. A de-embedding link corresponding to the fan-out link is also provided on the test board. The de-embedding link has the same structure as the fan-out link, and both ends of the de-embedding link are respectively used to be connected to both ends of a second test device.

[0006] Optionally, the number of the fan-out links is at least two. Each fan-out link corresponds to a de-embedding link, and the de-embedding link has the same structure as the corresponding fan-out link. The first ends of the fan-out links are respectively used to be connected to different high-speed input / output interfaces of the central processing unit.

[0007] Optionally, the number of the fan-out links is two. The first end of one of the fan-out links is used to connect to the SATA interface or the PCIE interface of the central processing unit, and the first end of the other fan-out link is used to connect to the USB interface of the central processing unit.

[0008] Optionally, an SMP or SMA connector is connected to the second end of the fan-out link, and the fan-out link is connected to the first test device through the SMP or SMA connector; SMP or SMA connectors are respectively connected to both ends of the de-embedding link, and both ends of the de-embedding link are respectively connected to the second test device through the SMP or SMA connectors.

[0009] Optionally, a to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is further provided on the test board, and the link length of the to-be-tested topology limit link is determined according to the link loss value of the high-speed input / output interface protocol standard, or is jointly determined according to the link loss value of the high-speed input / output interface protocol standard and the output capability of the high-speed input / output interface.

[0010] Optionally, at least one to-be-tested topology limit link is respectively provided on the test board corresponding to each of the high-speed input / output interfaces.

[0011] Optionally, the test board is provided with at least one of the following to-be-tested topology limit links of high-speed input / output interfaces: SATA interface, PCIE interface, USB interface;

[0012] When the test board is provided with a to-be-tested topology limit link of the SATA interface, the to-be-tested topology limit link of the SATA interface at least includes one of the following: SATA connector + cable to-be-tested limit link, SATA Slimline connector + cable + backplane to-be-tested limit link, SATA MiniSAS connector + cable + backplane to-be-tested limit link, SATA M.2 connector to-be-tested limit link;

[0013] When the test board is provided with a to-be-tested topology limit link of the PCIE interface, the to-be-tested topology limit link of the PCIE interface at least includes one of the following: PCIE on-board chip to-be-tested limit link, PCIE standard connector to-be-tested limit link, PCIE on-board standard connector + adapter card + standard card to-be-tested limit link, PCIE M.2 connector to-be-tested limit link, PCIE Slimline connector + cable + backplane + solid-state drive to-be-tested limit link;

[0014] When the to-be-tested topology limit link with a USB interface is provided on the test board, the to-be-tested topology limit link of the USB interface includes at least one of the following: the to-be-tested limit link of the USB standard Type-A connector, the to-be-tested limit link of the USB cable + Type-A connector, and the to-be-tested limit link of the USB cable + backplane + Type-A connector.

[0015] In a second aspect, an embodiment of the present invention provides a central processing unit physical signal electrical characteristic test system, including the device described in any of the above embodiments. The system further includes: a first test device connected to the second end of the fan-out link for obtaining the physical signal output by the high-speed input / output interface of the central processing unit through the fan-out link; and a second test device connected to both ends of the de-embedding link for extracting the electrical characteristic parameters of the de-embedding link.

[0016] Optionally, the second test device is further configured to send the electrical characteristic parameters to the first test device; and the first test device is further configured to: perform a de-embedding operation on the physical signal based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signal output by the high-speed input / output interface of the central processing unit.

[0017] Optionally, when the to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is further provided on the test board, the test system further includes: a third test device connected to the terminal of the to-be-tested topology limit link for performing physical signal measurement at the terminal of the to-be-tested topology limit link.

[0018] In a third aspect, a method for testing the electrical characteristics of a central processing unit physical signal is characterized in that, based on the device described in any of the above embodiments, the method includes: extracting the electrical characteristic parameters of the de-embedding link by using a second test device; obtaining the physical signal output by the central processing unit through the fan-out link by using a first test device; and performing a de-embedding operation on the physical signal based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signal output by the high-speed input / output interface of the central processing unit.

[0019] Optionally, when the to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is further provided on the test board, the method further includes: performing physical signal measurement at the terminal of the to-be-tested topology limit link by using a third test device; and verifying the link output limit ability of the high-speed input / output interface corresponding to the to-be-tested topology limit link according to the physical signal.

[0020] Optionally, verifying the link output limit capability of the high-speed input / output interface corresponding to the to-be-tested topological limit link according to the physical signal includes: determining whether the physical signal meets the output requirements; if so, using the link length of the to-be-tested topological limit link as the link limit length of the high-speed input / output interface.

[0021] An electrical characteristic testing device for a central processing unit physical signal provided by an embodiment of the present invention includes a test board. A fan-out link is arranged on the test board. The first end of the fan-out link is used to be connected to the high-speed input / output interface of the central processing unit, and the second end is used to be connected to a first test device. A de-embedding link corresponding to the fan-out link is also arranged on the test board. The de-embedding link has the same structure as the fan-out link. Both ends of the de-embedding link are respectively used to be connected to both ends of a second test device. In this way, by designing the fan-out link, the first test device is used to measure the physical signal output by the high-speed input / output interface of the central processing unit through the fan-out link. At the same time, a de-embedding link with the same structure as the fan-out link is designed on the test board. The second test device is used to extract the electrical characteristic parameters of the de-embedding link, and a de-embedding operation is performed on the physical signal measured by the first test device based on the electrical characteristic parameters, so as to obtain the electrical characteristics of the physical signal output by the high-speed input / output interface of the central processing unit, that is, the output capability of the pin end of the high-speed input / output interface of the central processing unit. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 It is a schematic structural diagram of an electrical characteristic verification device for a traditional CPU high-speed input / output interface;

[0024] Figure 2 It is a schematic connection relationship diagram between an electrical characteristic testing device for a central processing unit physical signal provided by an embodiment of the present invention and a central processing unit (CPU);

[0025] Figure 3 It is a schematic connection relationship diagram between an electrical characteristic testing device for a central processing unit physical signal provided by an embodiment of the present invention, a central processing unit, a first test device, and a second test device;

[0026] Figure 4Another schematic diagram of the connection relationship between another central processor physical signal electrical characteristic testing device provided by an embodiment of the present invention and the central processor;

[0027] Figure 5 The first schematic diagram of the structure of the topology limit link to be tested of the PCIE interface provided by an embodiment of the present invention;

[0028] Figure 6 The second schematic diagram of the structure of the topology limit link to be tested of the PCIE interface provided by an embodiment of the present invention;

[0029] Figure 7 The third schematic diagram of the structure of the topology limit link to be tested of the PCIE interface provided by an embodiment of the present invention;

[0030] Figure 8 The fourth schematic diagram of the structure of the topology limit link to be tested of the PCIE interface provided by an embodiment of the present invention;

[0031] Figure 9 The fifth schematic diagram of the structure of the topology limit link to be tested of the PCIE interface provided by an embodiment of the present invention;

[0032] Figure 10 The first schematic diagram of the structure of the topology limit link to be tested of the SATA interface provided by an embodiment of the present invention;

[0033] Figure 11 The second schematic diagram of the structure of the topology limit link to be tested of the SATA interface provided by an embodiment of the present invention;

[0034] Figure 12 The third schematic diagram of the structure of the topology limit link to be tested of the SATA interface provided by an embodiment of the present invention;

[0035] Figure 13 The fourth schematic diagram of the structure of the topology limit link to be tested of the SATA interface provided by an embodiment of the present invention;

[0036] Figure 14 The first schematic diagram of the structure of the topology limit link to be tested of the USB interface provided by an embodiment of the present invention;

[0037] Figure 15 The second schematic diagram of the structure of the topology limit link to be tested of the USB interface provided by an embodiment of the present invention;

[0038] Figure 16 The third schematic diagram of the structure of the topology limit link to be tested of the USB interface provided by an embodiment of the present invention;

[0039] Figure 17Schematic diagram of importing all simulation models into the simulation framework process of simulation software in a specific simulation method provided by an embodiment of the present invention;

[0040] Figure 18 Schematic diagram of a partial connection relationship between another central processor physical signal electrical characteristic testing device provided by an embodiment of the present invention and a central processor with 4 DIEs;

[0041] Figure 19 Schematic flowchart of a central processor physical signal electrical characteristic testing method provided by an embodiment of the present invention;

[0042] Figure 20 Schematic flowchart of another central processor physical signal electrical characteristic testing method provided by an embodiment of the present invention;

[0043] Figure 21 Schematic flowchart of yet another central processor physical signal electrical characteristic testing method provided by an embodiment of the present invention. Detailed implementation manners

[0044] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0046] In a first aspect, an embodiment of the present invention provides a central processor physical signal electrical characteristic testing device, which can obtain the output capability of the high-speed input / output interface pin ends of a central processor.

[0047] As Figure 2 and Figure 3 shown, a central processor physical signal electrical characteristic testing device provided in this embodiment includes a test board 201. A fan-out link 202 is provided on the test board 201. The first end of the fan-out link 202 is used to connect to the high-speed input / output interface of the central processor 301, and the second end is used to connect to a first test device 401. A de-embedding link 203 corresponding to the fan-out link 202 is also provided on the test board 201. The de-embedding link 203 has the same structure as the fan-out link 202, and both ends of the de-embedding link 203 are respectively used to connect to both ends of a second test device 501.

[0048] In this embodiment, the test board may be a printed circuit board (PCB), the fan-out link may be a pair of differential lines arranged on the printed circuit board, and the de-embedding link may be another pair of differential lines arranged on the printed circuit board with the same length, routing method, etc. as the fan-out link.

[0049] The first test device may be an oscilloscope for testing the physical signals output by the high-speed input / output interface of the central processing unit through the fan-out link; the second test device may be a network analyzer for extracting the electrical characteristic parameters of the de-embedding link, and the electrical characteristic parameters are used to describe the electrical characteristics of the de-embedding link. Specifically, the electrical characteristic parameters may be S parameters (S parameter); since the physical structure of the de-embedding link is the same as that of the fan-out link, the electrical characteristic parameters of the fan-out link are the same as those of the de-embedding link. In this way, based on the electrical characteristic parameters extracted by the second test device, a de-embedding operation is performed on the physical signals output by the fan-out link, and the electrical characteristics of the physical signals output at the pin ends of the high-speed input / output interface of the central processing unit can be obtained, that is, the output capability of the pin ends of the high-speed input / output interface of the central processing unit.

[0050] As Figure 3 shown, optionally, in the above embodiment, after the second test device 501 extracts the electrical characteristic parameters of the de-embedding link, it may send the electrical characteristic parameters to the first test device 401, and the first test device 401 performs a de-embedding operation on the physical signals output by the fan-out link based on the electrical characteristic parameters.

[0051] Optionally, in the above embodiment, the number of the fan-out links is at least two, each fan-out link corresponds to a de-embedding link respectively, and the structure of the de-embedding link is the same as that of its corresponding fan-out link; the first ends of the fan-out links are respectively used to be connected to different high-speed input / output interfaces of the central processing unit.

[0052] In this embodiment, corresponding fan-out links are designed for different high-speed input / output interfaces of the central processing unit. In this way, by only connecting the central processing unit to the test board once, the electrical characteristics of the physical signals output by multiple high-speed input / output interfaces of the central processing unit can be tested, improving the test efficiency.

[0053] When the physical structures of the fan-out links are the same, the number of the de-embedding links may be 1, and each fan-out link corresponds to the de-embedding link.

[0054] As Figure 4As shown, optionally, the number of the fan-out links can be two, wherein the first end of one of the fan-out links 2021 is used to connect to the SATA interface or PCIE interface of the central processing unit, and the first end of the other fan-out link 2022 is used to connect to the USB interface of the central processing unit.

[0055] In this embodiment, since the interface protocols of SATA and PCIE are similar, the interface on the central processing unit connected to one of the fan-out links can be configured as a SATA interface or a PCIE interface. In this way, one fan-out link on the test board can test two high-speed input and output interfaces on the central processing unit.

[0056] Through the above two fan-out links, the output capacity test of the three common high-speed input and output interface pins on the current central processing unit can be realized. It solves the problem that the physical signal of the CPU pin of the PCIE interface cannot be measured, and can effectively evaluate the pros and cons of the CPU PICE PHY design; it solves the problem that the physical signal of the CPU pin of the SATA interface cannot be measured, and can effectively evaluate the pros and cons of the SATA PICE PHY design; it solves the problem that the physical signal of the CPU pin of the USB interface cannot be measured, and can effectively evaluate the pros and cons of the USB PICE PHY design.

[0057] like Figure 2 and Figure 3 As shown, optionally, the second end of the fan-out link 11 is connected to an SMP or SMA connector, and the fan-out link 202 is connected to the first test device through the SMP or SMA connector; both ends of the de-embedding link 203 are respectively connected to SMP or SMA connectors, and both ends of the de-embedding link 203 are respectively connected to the second test device through the SMP or SMA connector.

[0058] In this embodiment, the SMP connector and the SMA connector are high-speed connectors, which can be directly connected to the first test device and the second test device, thereby reducing other link losses and making the test results more accurate.

[0059] like Figure 4 As shown, optionally, the test board is also provided with a topological limit link to be tested of at least one high-speed input and output interface of the central processor (see Figure 4 The invention discloses 5 topology limit links 205 to be tested of the PCIE interface, 4 topology limit links 204 to be tested of the SATA interface, and 3 common topology limit links 206 of the USB interface, wherein the link lengths of the topology limit links to be tested are determined according to the link loss values ​​of the high-speed input / output interface protocol standard, or are jointly determined according to the link loss values ​​of the high-speed input / output interface protocol standard and the output capacity of the high-speed input / output interface.

[0060] In this embodiment, each high-speed input / output interface of the central processing unit may respectively correspond to some common topological limit links. For example, the 5 common topological limit links of the PCIE interface: the PCIE on-board chip limit link (see Figure 5 ), the PCIE on-board standard connector limit link (see Figure 6 ), the PCIE on-board standard connector + adapter card + standard card limit link (see Figure 7 ), the PCIE M.2 connector limit link (see Figure 8 ), the PCIE Slimline connector + cable + backplane + solid-state drive limit link (see Figure 9 ); the 4 common topological limit links of the SATA interface: the SATA connector + cable limit link (see Figure 10 ), the SATA Slimline connector + cable + backplane limit link (see Figure 11 ), the SATA MiniSAS connector + cable + backplane limit link (see Figure 12 ), the SATA M.2 connector limit link (see Figure 13 ); the 3 common topological limit links of the USB interface: the USB standard Type-A connector limit link (see Figure 14 ), the USB cable + Type-A connector limit link (see Figure 15 ), the USB cable + backplane + Type-A connector limit link (see Figure 16 ).

[0061] The topological structure of one of the to-be-tested topological limit links of the high-speed input / output interface can be the same as that of one of the common topological limit links of the high-speed input / output interface. The limit length of the link in the to-be-tested topological limit link refers to the length of the actual link on the test board, which can be obtained through simulation. Specifically, the simulation can be carried out according to the link loss value of the high-speed input / output interface protocol standard to obtain the limit length of the link in the to-be-tested topological limit link.

[0062] For example, for the PCIE on-board chip limit link, the simulation is carried out according to the link loss value of the PCIE protocol standard shown in the following table to obtain the limit length of the actual link from the central processing unit to the on-board chip, and complete the design of one of the to-be-tested topological limit links of the PCIE interface (as Figure 5 shown, 2051 represents the length of the actual link on the test board).

[0063]

[0064] The specific simulation process is as follows:

[0065] Step 1: Evaluate the relevant components of the entire link. Figure 5 As shown, for the PCIE onboard chip topology extreme link, there are CPU, PCB motherboard, and onboard chip.

[0066] The second step is to use the CPU simulation model, including the CPU transmitter model, CPU substrate model, and CPU base model; use the PCB motherboard model, including PCB breakout routing, main routing, vias, capacitors, etc.; use the onboard chip model, including the receiver model and substrate model.

[0067] The third step is to import all models into the simulation framework process of the simulation software (see Figure 17 ).

[0068] The fourth step is to determine the actual link limit length according to the link loss value of the PCIE protocol standard, and set the main routing 609 in the motherboard PCB model 604 as a variable, so that the length can be adjusted. Then, the CPU substrate model 602, the CPU base model 603, the motherboard PCB model 604, and the onboard chip substrate model 605 are simulated together for loss, so that the total loss is less than the maximum link loss value of 25db@8Ghz of the PCIE protocol standard, and the maximum value of the main routing 609 is obtained. The total value of the main routing 609, the breakout routing 608, and the capacitor fan out 612 is the actual link limit length of the PCB motherboard (i.e., the test board).

[0069] For the PCIE onboard standard connector limit link, simulation is performed according to the link loss value of the PCIE protocol standard as shown in the table above, and the limit length of the actual link from the central processor to the onboard standard connector is obtained, completing the design of another topology limit link to be tested for the PCIE interface (such as Figure 6 As shown, 2052 represents the actual link length on the test board).

[0070] For the PCIE onboard standard connector + adapter card + standard card extreme link, simulation is performed according to the link loss value of the PCIE protocol standard as shown in the table above, and the actual extreme length of the link from the central processor to the onboard standard connector is obtained, completing another topology extreme link design to be tested for the PCIE interface (such as Figure 7 As shown, 2053 represents the actual link length on the test board).

[0071] The simulation method of the topological extreme link corresponding to other high-speed input and output interfaces is similar to the simulation method of the topological extreme link of the above-mentioned PCIE interface, and will not be repeated here.

[0072] Alternatively, the limit length of the link in the topology limit link to be measured is related not only to the link loss value according to the central processing unit high-speed input / output interface protocol standard, but also to the output capacity of the high-speed input / output interface. Specifically, the limit length of the link in the topology limit link to be measured can also be obtained by simulating according to the output capacity of the high-speed input / output interface; compare the limit length obtained by simulating according to the link loss value of the high-speed input / output interface protocol standard with the limit length obtained by simulating according to the output capacity of the high-speed input / output interface, and take the smaller limit length value as the limit length of the link in the topology limit link to be measured.

[0073] For example, after obtaining the limit length of the actual link of the PCB main board (i.e., the test board) according to the above first to fourth steps, the following operations are performed:

[0074] Step 5: Obtain the limit link length according to the output capacity of the CPU high-speed IO port (obtained by testing the fan-out link and de-embedding link designed in the above embodiments). First, measure the physical signal quality parameters at the chip PIN of the CPU, including the differential voltage magnitude, equalization value magnitude, etc. As Figure 17 shown, import these parameters into the CPU transmitter model 601. At this time, the signal intensity transmitted by the transmitter in the simulation software is the intensity of the actual chip. Then, set the main trace 609 as a variable. After setting, pass the signal transmitted by the CPU transmitter model 601 through the CPU substrate model 602, CPU socket 603, main board PCB model 604, and on-board chip substrate model 605. At the on-board chip receiver model 606, the simulation software will obtain the actual signal quality eye diagram. According to the signal quality specification at the link terminal, taking PCIE as an example, the eye height needs to be greater than 15mv and the eye width needs to be greater than 0.3UI. According to this standard value, a maximum value of the main trace 609 is obtained. The sum of the main trace 609, breakout trace 608, and capacitor fan out 612 is the limit length of the actual link of the main board.

[0075] Step 6: Combine the results of the fourth and fifth steps, and take the smaller value as the final limit length of the actual link of the main board.

[0076] In this embodiment, by setting the topology limit link on the test board, it is possible to verify whether the limit link length obtained by simulation is accurate. In this way, by testing the actual length of the topology limit link of the high-speed input / output interface of the central processing unit, the limit output capacity of the high-speed input / output interface of the central processing unit can be obtained, and then the relevant design parameters for CPU board design guidance can be obtained.

[0077] The problem that the current link verification for high-speed input / output interfaces is all based on the actual product version, and the actual product boards are designed according to actual product requirements, and the actual link length does not reach the link limit length, so the link limit of the actual CPU signal output cannot be measured, the parameters in the CPU design guide cannot be verified, and thus an accurate design guide parameter cannot be given to the customer is solved.

[0078] For a multi-DIE central processing unit, there may be multiple duplicate high-speed input / output interfaces. For example, there are two PCIE interfaces. At this time, corresponding to-be-tested topological limit links can be designed on the test board for each high-speed input / output interface. For example Figure 18 For the central processing unit with 4 DIEs shown in, each DIE has Combo link Type A and Type B. Therefore, the test board can include a larger number of to-be-tested topological limit link designs, but the overall solution can still be classified into the following 5 types: the fan-out link of the PCIE / SATA interface, the fan-out link of the USB interface, 5 to-be-tested topological limit links of the PCIE interface, 4 to-be-tested topological limit links of the SATA interface, and 3 to-be-tested topological limit links of the USB interface.

[0079] Optionally, in the above embodiment, after obtaining the limit length of the actual link of the topological limit link of a certain high-speed input / output interface through simulation, when setting the corresponding to-be-tested topological limit link on the test board, the actual link length on the test board in the to-be-tested topological limit link can be less than the limit length obtained according to the simulation, leaving a certain margin for testing. For example, the actual link length on the test board is about 85% of the limit length obtained by simulation.

[0080] Optionally, in the above embodiment, at least one to-be-tested topological limit link 13 is respectively arranged on the test board 1 corresponding to each high-speed input / output interface.

[0081] In this embodiment, for each high-speed input / output interface, at least one to-be-tested topological limit link is arranged to test the limit output ability of the high-speed input / output interface. In this way, the test result can be more comprehensive, and thus the relevant design parameters for guiding the design of the output CPU board can be more detailed and comprehensive.

[0082] Optionally, the test board is provided with at least one of the following high-speed input and output interface topological limit links to be tested: SATA interface, PCIE interface, USB interface; when the test board is provided with the SATA interface topological limit link to be tested, the SATA interface topological limit link to be tested includes at least one of the following: SATA connector + cable to be tested limit link, SATA Slimline connector + cable + backplane to be tested limit link, SATA MiniSAS connector + cable + backplane to be tested limit link, SATA M.2 connector to be tested limit link; when the test board is provided with the PCIE interface topological limit link to be tested, the PCIE interface topological limit link to be tested includes at least one of the following: PCIE onboard chip to be tested limit link, PCIE standard connector to be tested limit link, PCIE onboard standard connector + adapter card + standard card to be tested limit link, PCIE M.2 connector to be tested limit link, PCIE Slimline connector + cable + backplane + solid state drive extreme link to be tested; when the test board is provided with a USB interface topology extreme link to be tested, the USB interface topology extreme link to be tested includes at least one of the following: USB standard TYPE-A connector extreme link to be tested, USB cable + type-A connector extreme link to be tested, USB cable + backplane + type-A connector extreme link to be tested.

[0083] In this embodiment, the test board can be provided with the tested extreme links of three common high-speed input and output interfaces of the central processing unit, and the topological structure of the tested extreme link corresponding to each high-speed input and output interface can adopt the topological structure of the common topological extreme link of the high-speed input and output interface, that is, the tested extreme link on the test board imitates the extreme application scenario of the high-speed input and output interface on the actual product board, so that the extreme transmission capacity of the CPU PCIE interface, the extreme transmission capacity of the CPU SATA interface, and the extreme transmission capacity of the CPU USB interface can be verified, and the effective output CPU board design guidance can be given to customers.

[0084] In a second aspect, an embodiment of the present invention provides a central processing unit physical signal electrical characteristic testing system, which can obtain the output capability of the central processing unit high-speed input and output interface pin end.

[0085] like Figure 3As shown in the figure, this embodiment provides a test system for the electrical characteristics of the physical signals of a central processing unit, which includes the test device described in any of the above embodiments. The system further includes: a first test device 401, connected to the second end of the fan-out link, for acquiring the physical signals output by the high-speed input / output interface of the central processing unit 301 through the fan-out link; a second test device 501, connected to both ends of the de-embedding link, for extracting the electrical characteristic parameters of the de-embedding link.

[0086] In this embodiment, the first test device can be an oscilloscope, which is used to test the physical signals output by the high-speed input / output interface of the central processing unit through the fan-out link; the second test device can be a network analyzer, which is used to extract the electrical characteristic parameters of the de-embedding link. These electrical characteristic parameters are used to describe the electrical characteristics of the de-embedding link. Specifically, the electrical characteristic parameters can be S parameters (S parameter); since the physical structure of the de-embedding link is the same as that of the fan-out link, the electrical characteristic parameters of the fan-out link are the same as those of the de-embedding link. In this way, based on the electrical characteristic parameters extracted by the second test device, a de-embedding operation is performed on the physical signals output by the fan-out link, and the electrical characteristics of the physical signals output by the pin ends of the high-speed input / output interface of the central processing unit can be obtained, that is, the output ability of the pin ends of the high-speed input / output interface of the central processing unit.

[0087] As Figure 3 shown, optionally, the second test device 501 is further configured to send the electrical characteristic parameters to the first test device 401; the first test device 401 is further configured to: perform a de-embedding operation on the physical signals based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signals output by the high-speed input / output interface of the central processing unit 301. In this embodiment, the first test device can use an oscilloscope with a de-embedding function, so that the electrical characteristics of the physical signals output by the high-speed input / output interface of the central processing unit can be automatically obtained.

[0088] Optionally, when at least one high-speed input / output interface of the central processing unit has a to-be-tested topology limit link on the test board, the test system further includes: a third test device, connected to the terminal of the to-be-tested topology limit link, for performing physical signal measurement at the terminal of the to-be-tested topology limit link.

[0089] In this embodiment, for Figure 5 the to-be-tested topology limit link shown in the figure, the third device is used to test the physical signals output by the test board to the pin ends of the on-board chip; for Figure 6 the to-be-tested limit link shown in the figure, the third device is used to test the physical signals output by the test board to the pin ends of the on-board connector; for Figure 7For the limit link to be measured as shown, a third device is used to test the physical signal output by the adapter card to the pin end of the standard card; for Figure 8 For the limit link to be measured as shown, a third device is used to test the physical signal output by the M.2 connector to the pin end of the solid-state drive; and so on.

[0090] The third test device can be an oscilloscope, and the third test device and the first test device can be the same device. When the third test device and the first test device are the same device and the test device can simultaneously acquire the physical signals output from different output ends, the terminal of the limit link of the topology to be measured and the second end of the fan-out link can be simultaneously connected to the test device; when the test device can only acquire the physical signal output from one output end at a time, the physical signal output from the second end of the fan-out link can be acquired by using the device first, and then the physical signal output from the terminal of the limit link of the topology to be measured can be acquired by using the device.

[0091] In a third aspect, an embodiment of the present invention provides a method for testing the electrical characteristics of the physical signals of a central processing unit. Based on the device described in any of the above embodiments, the output capability of the pin end of the high-speed input / output interface of the central processing unit can be obtained.

[0092] As Figure 19 shown, an embodiment of the present invention provides a method for testing the electrical characteristics of the physical signals of a central processing unit. Based on the device described in any of the above embodiments, the method includes:

[0093] S701. Use a second test device to extract the electrical characteristic parameters of the de-embedding link;

[0094] In this step, the second test device can be a network analyzer, and the electrical characteristic parameters are used to describe the electrical characteristics of the de-embedding link. Specifically, the electrical characteristic parameters can be S parameters.

[0095] S702. Use a first test device to acquire the physical signals output by the central processing unit through the fan-out link;

[0096] In this step, the first test device can be an oscilloscope.

[0097] S703. Perform a de-embedding operation on the physical signals based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signals output by the high-speed input / output interface of the central processing unit.

[0098] In this embodiment, a first test device is used to measure the physical signal output by the high-speed input / output interface of the central processing unit through the fan-out link, and a de-embedding link with the same structure as the fan-out link is designed on a test board. The electrical characteristic parameters of the de-embedding link are extracted by the second test device, and a de-embedding operation is performed on the physical signal measured by the first test device based on the electrical characteristic parameters, so as to obtain the electrical characteristics of the physical signal output by the high-speed input / output interface of the central processing unit, that is, the output capacity of the pin end of the high-speed input / output interface of the central processing unit.

[0099] like Figure 20 As shown, optionally, when the test board is also provided with a topology limit link to be tested of at least one high-speed input and output interface of the central processor, the method may further include:

[0100] S704, using a third test device to perform physical signal measurement at a terminal of the topology limit link to be tested;

[0101] In this step, for Figure 3 For the limit link to be tested shown in , a third device is used to test the physical signal output by the test board to the pin end of the onboard chip; Figure 4 For the limit link to be tested shown in , a third device is used to test the physical signal output by the test board to the pin end of the onboard connector; Figure 5 For the limit link to be tested shown in , a third device is used to test the physical signal output by the adapter card to the pin end of the standard card; Figure 6 The limit link to be tested shown in is tested using a third device to test the physical signal output by the M.2 connector to the pin end of the solid state drive; and so on.

[0102] S705: Verify the link output limit capability of the high-speed input and output interface corresponding to the topology limit link to be tested according to the physical signal.

[0103] In this step, if Figure 21 Specifically, the step of verifying the link output limit capability of the high-speed input and output interface corresponding to the topology limit link to be tested according to the physical signal may include:

[0104] S7051, determining whether the physical signal meets the output requirements;

[0105] In this step, the physical signal can be compared with the protocol standard value. When the physical signal is the same as the protocol standard value, the link length of the to-be-tested topological limit link reaches the limit link length; when the physical signal is lower than the protocol standard value, the link length of the to-be-tested topological limit link exceeds the limit link length; when the physical signal is higher than the protocol standard value, the link length of the to-be-tested topological limit link is less than the limit link length.

[0106] The output requirement can be higher than or equal to the protocol standard value.

[0107] S7052. If so, take the link length of the to-be-tested topological limit link as the link limit length of the high-speed input / output interface.

[0108] In this embodiment, the output requirement can be higher than or equal to the protocol standard value. In this way, when the physical signal meets the output requirement, the link length of the to-be-tested topological limit link can be taken as the link limit length of the high-speed input / output interface, that is, the link output limit ability of the high-speed input / output interface. Specifically, each topological structure of the to-be-tested topological limit link of the high-speed input / output interface represents one of the application scenarios of the high-speed input / output interface. In this way, when the physical signal meets the output requirement, the link length of the to-be-tested topological limit link can be taken as the link limit length corresponding to this topological structure application scenario of the high-speed input / output interface.

[0109] If the to-be-tested topological limit links in common application scenarios are designed for each high-speed input / output interface of the central processor on the test board, through the method provided in this embodiment, the link output limit ability of each high-speed input / output interface of the central processor in common application scenarios can be obtained. In this way, the relevant design parameters for guiding the CPU board design can be further output.

[0110] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0111] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0112] In particular, for the system and method embodiments, since they are basically similar to the device embodiments, the description is relatively simple. For the related parts, reference can be made to the partial description of the device embodiments.

[0113] As mentioned above, the above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A test device for the electrical characteristics of physical signals of a central processing unit, characterized in that, It includes a test board, on which a fan-out link is provided. The first end of the fan-out link is used to connect to the high-speed input / output interface of the central processing unit, and the second end is used to connect to the first test device. The first test device is used to test the physical signals output by the high-speed input / output interface of the central processing unit through the fan-out link. On the test board, a de-embedding link corresponding to the fan-out link is also provided. The de-embedding link has the same structure as the fan-out link, and both ends of the de-embedding link are respectively used to connect to both ends of the second test device. The second test device is used to extract the electrical characteristic parameters of the de-embedding link. On the test board, a to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is also provided. The link length of the to-be-tested topology limit link is determined according to the link loss value of the high-speed input / output interface protocol standard, or jointly determined according to the link loss value of the high-speed input / output interface protocol standard and the output capacity of the high-speed input / output interface. The to-be-tested topology limit link is used for: using a third test device to perform physical signal measurement at the terminal of the to-be-tested topology limit link; judging whether the physical signal meets the output requirements; if so, taking the link length of the to-be-tested topology limit link as the link limit length of the high-speed input / output interface.

2. The test device according to claim 1, wherein The number of the fan-out links is at least two, and each fan-out link corresponds to a de-embedding link, and the de-embedding link has the same structure as the corresponding fan-out link. The first ends of the respective fan-out links are respectively used to connect to different high-speed input / output interfaces of the central processing unit.

3. The test device according to claim 2, wherein The number of the fan-out links is two. The first end of one of the fan-out links is used to connect to the SATA interface or PCIE interface of the central processing unit, and the first end of the other fan-out link is used to connect to the USB interface of the central processing unit.

4. The testing device according to any one of claims 1 to 3, characterized in that, The second end of the fan-out link is connected with an SMP or SMA connector, and the fan-out link is connected to the first test device through the SMP or SMA connector. Both ends of the de-embedding link are respectively connected with an SMP or SMA connector, and both ends of the de-embedding link are respectively connected to the second test device through the SMP or SMA connector.

5. The test device according to claim 1, characterized in that, On the test board, at least one to-be-tested topology limit link is respectively provided corresponding to each high-speed input / output interface.

6. The testing device according to claim 5, characterized in that, On the test board, at least one of the following high-speed input / output interfaces' to-be-tested topology limit links is provided: SATA interface, PCIE interface, USB interface. When the to-be-tested topology limit link of the SATA interface is provided on the test board, the to-be-tested topology limit link of the SATA interface at least includes one of the following: SATA connector + cable to-be-tested limit link, SATA Slimline connector + cable + backplane to-be-tested limit link, SATA MiniSAS connector + cable + backplane to-be-tested limit link, SATA M.2 connector to-be-tested limit link. When a to-be-tested topology limit link with a PCIE interface is provided on the test board, the to-be-tested topology limit link of the PCIE interface includes at least one of the following: a to-be-tested limit link of a PCIE on-board chip, a to-be-tested limit link of a PCIE standard connector, a to-be-tested limit link of a PCIE on-board standard connector + adapter card + standard card, a to-be-tested limit link of a PCIE M.2 connector, a to-be-tested limit link of a PCIE Slimline connector + cable + backplane + solid-state drive; When a to-be-tested topology limit link with a USB interface is provided on the test board, the to-be-tested topology limit link of the USB interface includes at least one of the following: a to-be-tested limit link of a USB standard Type-A connector, a to-be-tested limit link of a USB cable + Type-A connector, a to-be-tested limit link of a USB cable + backplane + Type-A connector.

7. A central processing unit physical signal electrical characteristic testing system, characterized in that Including the device according to any one of claims 1 to 6 above, the system further includes: A first test device, connected to the second end of the fan-out link, for acquiring physical signals output by the high-speed input / output interface of the central processing unit through the fan-out link; A second test device, connected to both ends of the de-embedding link, for extracting electrical characteristic parameters of the de-embedding link.

8. The test system according to claim 7, wherein The second test device is further configured to send the electrical characteristic parameters to the first test device; The first test device is further configured to: Perform a de-embedding operation on the physical signals based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signals output by the high-speed input / output interface of the central processing unit.

9. The test system according to claim 7, wherein When a to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is further provided on the test board, the test system further includes: A third test device, connected to the terminal of the to-be-tested topology limit link, for performing physical signal measurement at the terminal of the to-be-tested topology limit link.

10. A method for testing the electrical characteristics of physical signals of a central processing unit, characterized in that, Based on the device according to any one of claims 1 to 6 above, the method includes: Extracting electrical characteristic parameters of the de-embedding link by using a second test device; Acquiring physical signals output by the central processing unit through the fan-out link by using a first test device; Performing a de-embedding operation on the physical signals based on the electrical characteristic parameters to obtain the electrical characteristics of the physical signals output by the high-speed input / output interface of the central processing unit.

11. The test method according to claim 10, wherein When a to-be-tested topology limit link of at least one high-speed input / output interface of the central processing unit is further provided on the test board, the method further includes: Performing physical signal measurement at the terminal of the to-be-tested topology limit link by using a third test device; Verifying the link output limit ability of the high-speed input / output interface corresponding to the to-be-tested topology limit link according to the physical signals.

12. The test method according to claim 11, characterized in that, The verifying the link output limit ability of the high-speed input / output interface corresponding to the to-be-tested topology limit link according to the physical signals includes: Judging whether the physical signals meet the output requirements; If so, taking the link length of the to-be-tested topology limit link as the link limit length of the high-speed input / output interface.

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