Semiconductor device having high voltage transistor

Abstract

A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first impurity region is disposed in an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is in the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed in the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first blocking insulating pattern is disposed in the first trench.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including high voltage transistors. Background Art

[0002] The semiconductor device may include a memory cell region in which a memory cell is formed and a peripheral region in which a peripheral circuit for driving the memory cell is formed. The peripheral circuit formed in the peripheral region may include a high voltage transistor configured to operate with a voltage ranging from several volts to tens of volts. The high voltage transistor may have excellent operating characteristics and may be formed in a small limited area of ​​a substrate. Summary of the invention

[0003] The semiconductor device includes a gate structure disposed on a substrate. A first impurity region exists in an upper portion of the substrate. A third impurity region is also in an upper portion of the substrate. A first trench is disposed in the substrate, and a first blocking insulating pattern is disposed in the first trench.

[0004] The gate structure may have a first sidewall and a second sidewall opposite to the first sidewall. The first impurity region may be spaced apart from the first sidewall. The third impurity region may be spaced apart from the second sidewall. The first trench may be in the substrate disposed between the first sidewall and the first impurity region. The first trench may be spaced apart from the first sidewall.

[0005] The semiconductor device includes a gate structure formed on a substrate. A first impurity region is formed in the substrate. A second impurity region is formed in the substrate. A third impurity region is formed in the substrate. A fourth impurity region is formed in the substrate.

[0006] The first impurity region may be spaced apart from the first sidewall of the gate structure. The second impurity region may be formed in the substrate between the first sidewall and the first impurity region. The second impurity region may be connected to the first impurity region. The third impurity region may be formed in the substrate. The third impurity region may be spaced apart from the second sidewall of the gate structure opposite to the first sidewall. The fourth impurity region may be formed in the substrate between the second sidewall and the third impurity region. The fourth impurity region may be connected to the third impurity region. The first blocking insulating pattern may fill a first trench formed in the substrate between the first sidewall and the first impurity region. The first blocking insulating pattern may be spaced apart from the first sidewall of the gate structure. The second impurity region may be formed along a surface of the substrate below the first blocking insulating pattern.

[0007] The semiconductor device includes a gate structure formed on a substrate. A first impurity region is formed in an upper portion of the substrate. A second impurity region is formed in the substrate. A third impurity region is formed at an upper portion of the substrate. A fourth impurity region is formed in the substrate. The semiconductor device also includes an insulating interlayer and first and second contact plugs.

[0008] The first impurity region may be spaced apart from the first sidewall of the gate structure. The second impurity region may be formed in the substrate between the first sidewall and the first impurity region. The second impurity region may be connected to the first impurity region. The third impurity region may be formed at an upper portion of the substrate. The third impurity region may be spaced apart from the second sidewall of the gate structure opposite to the first sidewall. The fourth impurity region may be formed in the substrate between the second sidewall and the third impurity region. The fourth impurity region may be connected to the third impurity region. The first blocking insulating pattern may fill the first trench formed in the substrate between the first sidewall and the first impurity region. The insulating interlayer may at least partially cover the gate structure on the substrate. The first and second contact plugs may each pass through the insulating interlayer. The first contact plug and the second contact plug may contact the first impurity region and the third impurity region, respectively. The first blocking insulating pattern may be spaced apart from the first sidewall. The first to fourth impurity regions may be doped with impurities of the same conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete appreciation of the present disclosure and its many attendant aspects will be more clearly appreciated from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0011] Figure 2 It is shown in Figure 1 A cross-sectional view of an example of a memory cell formed in a memory cell region is shown;

[0012] Figure 3 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0013] Figure 4 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0014] Figure 5 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0015] Figure 6 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0016] Figure 7is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0017] Figure 8 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0018] Figures 9 to 17 are cross-sectional views showing various stages of a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0019] Fig.18 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0020] Fig.19 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0021] Fig. 20 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0022] Fig.21 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0023] Fig. 22 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0024] Figure 23 to Figure 27 are cross-sectional views showing various stages of a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0025] Fig.28 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0026] Fig.29 is a plan view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0027] Fig.30 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0028] Figure 31 to Figure 34 are cross-sectional views showing various stages of a method of manufacturing a vertical semiconductor device according to an exemplary embodiment of the present disclosure;

[0029] Fig.35 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0030] Fig.36 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure;

[0031] Figure 37 to Figure 39 are cross-sectional views respectively showing high voltage transistors according to exemplary embodiments of the present disclosure; and

[0032] Fig.40 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In describing the exemplary embodiments of the present disclosure shown in the drawings, specific terminology is employed for the sake of clarity. However, the present disclosure is not intended to be limited to the specific terminology so selected, and it should be understood that each specific element includes all technical equivalents that operate in a similar manner. Figure 1 is a plan view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0034] refer to Figure 1 , the semiconductor device may include a memory cell region MA and a peripheral region PA disposed on at least one side of the memory cell region MA. The memory cells formed in the memory cell region MA may have a three-dimensional structure or a two-dimensional structure. Peripheral circuits such as transistors, resistor structures, capacitors, and inductors may be formed in the peripheral region PA. For example, one of the transistors may include a high voltage transistor configured to operate with a voltage of several volts to tens of volts.

[0035] Figure 2 It is shown in Figure 1 A cross-sectional view of an example of a memory cell formed in a memory cell region is shown.

[0036] In an exemplary embodiment of the present disclosure, the semiconductor device may be a NAND flash memory device, and the memory cell may include a vertical memory cell.

[0037] refer to Figure 2 , the vertical memory cell may include a stack structure 30 formed on a substrate 100 and a channel structure 28 passing through the stack structure 30. The channel structure 28 may include a channel 22. Moreover, an upper insulating layer 40 may be formed on the stack structure 30. In addition, a bit line structure 46 may be formed on the stack structure 30 to be electrically connected to the channel 22 in the channel structure 28. The bit line structure 46 may include a bit line contact 42 and a bit line 44.

[0038] The stack structure 30 may include insulating layers 10 and gate electrodes 12 that are alternately and repeatedly stacked. In an exemplary embodiment of the present disclosure, trenches 32 may be provided between the plurality of stack structures 30 , and the insulating patterns 34 may fill the trenches 32 .

[0039] The gate electrode 12 may function as a gate of a cell transistor.

[0040] The channel structure 28 may pass through the stack structure 30. The channel structure 28 may be formed in a channel hole 14 that passes through the stack structure 30 and extends to the upper surface of the substrate 100.

[0041] In an exemplary embodiment of the present disclosure, the semiconductor pattern 16 may be further formed on the bottom of the channel hole 14, and the semiconductor pattern 16 may contact the upper surface of the substrate 100. In some exemplary embodiments of the present disclosure, the semiconductor pattern 16 may not be formed on the bottom of the channel hole 14.

[0042] The channel structure 28 may include the data storage structure 20, the channel 22, the filling insulating pattern 24, and the upper conductive pattern 26. The upper conductive pattern 26 may be formed at an upper portion of the channel hole 14, and the upper conductive pattern 26 may be electrically connected to the channel 22.

[0043] The data storage structure 20 may include a blocking layer, a charge storage layer, and a tunnel insulating layer, which may be sequentially stacked from a sidewall of the channel hole 14. The blocking layer may contact the gate electrode 12.

[0044] The channel 22 may be electrically connected to the substrate 100 .

[0045] In the above, an example of a memory cell of a vertical NAND flash memory device is shown. However, the structure of the memory cell may be of any known type.

[0046] In addition, the semiconductor device does not have to be a vertical NAND flash memory device. For example, the semiconductor device may be a memory device such as a planar flash memory device, a DRAM device, or an SRAM device. Depending on the semiconductor device, the structure of the memory cell formed in the cell region may be changed.

[0047] Figure 3 and Figure 4 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Figure 3 is along Figure 4 A cross-sectional view taken along line A-A' of FIG. 1 is a ... Figure 1 In the peripheral area shown.

[0048] refer to Figure 3 and Figure 4, a high voltage transistor may be formed on the substrate in the peripheral area PA, and the high voltage transistor may include a gate structure 130, a first blocking insulating pattern 116a, a second blocking insulating pattern 116b, and impurity regions 132a, 132b, 136a, and 136b. An insulating interlayer 140 covering the high voltage transistor may be formed on the substrate 100. A first contact plug 142a and a second contact plug 142b may pass through the insulating interlayer 140, and each of the first contact plug 142a and the second contact plug 142b may contact at least a portion of the impurity regions 132a, 132b, 136a, and 136b.

[0049] Hereinafter, a channel length direction of the high voltage transistor is referred to as a first direction, and a channel width direction of the high voltage transistor is referred to as a second direction.

[0050] An isolation trench 108 may be formed in the substrate 100 in the peripheral area PA, and an isolation pattern 114a may be formed in the isolation trench 108. The isolation pattern 114a may include an insulating material, such as silicon oxide, silicon nitride, etc. The isolation pattern 114a may be used as a field region, and the upper surface of the substrate 100 on which the isolation pattern 114a is not formed may be used as an active region. A high voltage transistor may be formed on the active region.

[0051] The gate structure 130 may be formed on the active region and may be disposed to cross the active region. The gate structure 130 may extend in the second direction.

[0052] The gate structure 130 may include a gate insulating pattern 102b and a gate pattern stacked on the gate insulating pattern 102b. The gate pattern may include one or more layers.

[0053] In an exemplary embodiment of the present disclosure, the gate insulating pattern 102 b may include silicon oxide.

[0054] In an exemplary embodiment of the present disclosure, the gate pattern may include a first gate pattern 104b including lower polysilicon and a second gate pattern 122a including upper polysilicon and metal. The first gate pattern 104b may directly contact the gate insulating pattern 102b. The first gate pattern 104b may include polysilicon doped with impurities.

[0055] In an exemplary embodiment of the present disclosure, the gate pattern may have a structure including a stacked first polysilicon pattern 104b, a second polysilicon pattern 118a, and a metal silicide pattern 120a. In this case, the first polysilicon pattern may be used as the first gate pattern 104b, and the second polysilicon pattern 118a and the metal silicide pattern 120a may be used as the second gate pattern 122a.

[0056] In some exemplary embodiments of the present disclosure, the gate pattern may have a structure including a stacked first polysilicon pattern, a second polysilicon pattern, a barrier metal pattern, and a metal pattern. In some exemplary embodiments of the present disclosure, the gate pattern may have a structure including a stacked first polysilicon pattern, a barrier metal pattern, and a metal pattern.

[0057] In some exemplary embodiments of the present disclosure, the gate insulating pattern 102b may include a metal oxide having a high dielectric constant. When the gate insulating pattern 102b includes a metal oxide having a high dielectric constant, a gate pattern directly contacting the gate insulating pattern 102b may include a metal.

[0058] In an exemplary embodiment of the present disclosure, the sidewall of the gate structure 130 in the first direction may not have a curved portion or a protrusion. For example, the sidewall of the gate structure 130 in the first direction may extend to have a predetermined slope.

[0059] In an exemplary embodiment of the present disclosure, a hard mask pattern 124 may be further formed on the gate pattern. The hard mask pattern 124 may include, for example, silicon oxide or silicon nitride.

[0060] The first trench 110a and the second trench 110b may be formed in the substrate 100. The first trench 110a and the second trench 110b may be spaced apart from the sidewall of the gate structure 130, respectively, in the first direction. Therefore, the upper surface of the substrate 100 between the first trench 110a and the gate structure 130 and the upper surface of the substrate 100 between the second trench 110b and the gate structure 130 may be substantially flat. The first blocking insulating pattern 116a and the second blocking insulating pattern 116b may be formed in the first trench 110a and the second trench 110b, respectively. The first blocking insulating pattern 116a and the second blocking insulating pattern 116b may fill the first trench 110a and the second trench 110b, respectively. The first blocking insulating pattern 116a and the second blocking insulating pattern 116b may include, for example, silicon oxide. Therefore, the gate structure 130 and the first blocking insulating pattern 116a may be spaced apart from each other, and the gate structure 130 and the second blocking insulating pattern 116b may be spaced apart from each other.

[0061] For example, the first blocking insulating pattern 116a may be spaced apart from a first sidewall of the gate structure 130 in the first direction. The second blocking insulating pattern 116b may be spaced apart from a second sidewall of the gate structure 130 opposite to the first sidewall.

[0062] In addition, an active region of the substrate 100 disposed between the first sidewall of the gate structure 130 and the first blocking insulating pattern 116a and an active region of the substrate 100 disposed between the second sidewall of the gate structure 130 and the second blocking insulating pattern 116b may have a substantially flat upper surface. An edge of the gate structure 130 in the first direction (e.g., the first sidewall or the second sidewall) and the first blocking insulating pattern 116a may not overlap each other, and another edge of the gate structure 130 in the first direction (e.g., the second sidewall or the first sidewall) and the second blocking insulating pattern 116b may not overlap each other.

[0063] In an exemplary embodiment of the present disclosure, the bottom of the first trench 110a and the bottom of the second trench 110b may be coplanar with each other. Therefore, the bottom of the first blocking insulating pattern 116a and the bottom of the second blocking insulating pattern 116b may be coplanar with each other.

[0064] The edge of the gate structure 130 and the first blocking insulating pattern 116a may be spaced apart from each other, and the other edge of the gate structure 130 and the second blocking insulating pattern 116b may be spaced apart from each other. Therefore, compared with the case where each of the first blocking insulating pattern and the second blocking insulating pattern may overlap with the gate structure or the case where each of the first blocking insulating pattern and the second blocking insulating pattern and the gate structure may not be spaced apart from each other, the distance between the first blocking insulating pattern 116a and the second blocking insulating pattern 116b in the first direction may be increased. For example, the distance P between the bottom of the first blocking insulating pattern 116a and the bottom of the second blocking insulating pattern 116b in the first direction may be increased.

[0065] In the case of a high voltage transistor, when the distance P between the bottom of the first blocking insulating pattern 116a and the bottom of the second blocking insulating pattern 116b is reduced, an undesirable channel path may be generated at the portion between the second impurity region 132a below the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b below the bottom of the second blocking insulating pattern 116b. Therefore, punch-through may occur. Punch-through is a phenomenon in a transistor when the depletion layers around the drain region and the source region merge into one depletion region. The field under the gate and the drain current become strongly dependent on the drain-source voltage. Punch-through causes a current that increases rapidly with an increase in the drain-source voltage. Punch-through may be undesirable because it increases the output conductance and limits the maximum operating voltage of the transistor.

[0066] As described above, the distance P between the bottom of the first and second blocking insulating patterns 116a and 116b may be increased. Therefore, the distance between the second and fourth impurity regions 132a and 132b disposed at the lower portion of the substrate 100 may be increased, thereby reducing the possibility of punch-through.

[0067] In an exemplary embodiment of the present disclosure, a first distance a1 between a first sidewall of the gate structure 130 and the first blocking insulating pattern 116 a may be substantially the same as a second distance a2 between a second sidewall of the gate structure 130 and the second blocking insulating pattern 116 b .

[0068] In an exemplary embodiment of the present disclosure, the inner widths of the first trench 110a and the second trench 110b may be substantially the same. Therefore, the widths of the first blocking insulating pattern 116a and the second blocking insulating pattern 116b may be substantially the same.

[0069] A first blocking insulating pattern 116 a may be formed between the gate structure 130 and the first contact plug 142 a , and a second blocking insulating pattern 116 b may be formed between the gate structure 130 and the second contact plug 142 b .

[0070] The impurity regions 132a, 132b, 136a, and 136b may include a first impurity region 136a, a second impurity region 132a, a third impurity region 136b, and a fourth impurity region 132b.

[0071] The first impurity region 136a may be formed below the surface of the substrate 100 between the first blocking insulating pattern 116a and the isolation pattern 114a. For example, the first impurity region 136a may be spaced apart from the first sidewall of the gate structure 130.

[0072] The second impurity region 132a may be formed at an upper portion of the substrate along a surface of the first trench 110a. For example, the second impurity region 132a may be formed along a surface of the substrate 100 below the first blocking insulating pattern 116a. In addition, the second impurity region 132a may be formed at an upper portion of the substrate 100 between the first sidewall of the gate structure 130 and the first blocking insulating pattern 116a and at an upper portion of the substrate 100 between the first blocking insulating pattern 116a and the first impurity region 136a. Therefore, the first impurity region 136a and the second impurity region 132a may be connected to each other.

[0073] The third impurity region 136b may be formed below the surface of the substrate 100 between the second blocking insulating pattern 116b and the isolation pattern 114a. For example, the third impurity region 136b may be spaced apart from the second sidewall of the gate structure 130. In addition, the second trench 110b may be disposed between the second sidewall of the gate structure 130 and the third impurity region 136b.

[0074] The fourth impurity region 132b may be formed at an upper portion of the substrate 100 along a surface of the second trench 110b. For example, the fourth impurity region 132b may be formed along the substrate 100 below the second blocking insulating pattern 116b. In addition, the fourth impurity region 132b may be formed at an upper portion of the substrate 100 between the second sidewall of the gate structure 130 and the second blocking insulating pattern 116b and at an upper portion of the substrate 100 between the second blocking insulating pattern 116b and the third impurity region 136b. Therefore, the third impurity region 136b and the fourth impurity region 132b may be connected to each other.

[0075] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be used as a source region, the second impurity region 132a may be used as a source extension region, the third impurity region 136b may be used as a drain region, and the fourth impurity region 132b may be used as a drain extension region.

[0076] Impurities doped in the first to fourth impurity regions 136a, 132a, 136b, and 132b may have the same conductivity type.

[0077] In an exemplary embodiment of the present disclosure, the impurity concentrations of the first impurity region 136a and the second impurity region 132a may be different from each other. For example, the impurity concentration of the first impurity region 136a may be higher than the impurity concentration of the second impurity region 132a. The impurity concentrations of the third impurity region 136b and the fourth impurity region 132b may be different from each other. For example, the impurity concentration of the third impurity region 136b may be higher than the impurity concentration of the fourth impurity region 132b. In addition, the impurity concentrations of the first and third impurity regions 136a and 136b may be higher than the impurity concentrations of the second and fourth impurity regions 132a and 132b.

[0078] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be spaced apart from the first blocking insulating pattern 116a. In an exemplary embodiment of the present disclosure, the first impurity region 136a may contact a portion of the isolation pattern 114a.

[0079] In an exemplary embodiment of the present disclosure, the third impurity region 136b may be spaced apart from the second blocking insulating pattern 116b. In addition, the third impurity region 136b may contact a portion of the isolation pattern 114a.

[0080] The first and second contact plugs 142 a and 142 b may contact the first and third impurity regions 136 a and 136 b , respectively.

[0081] In some exemplary embodiments of the present disclosure, the gate contact plug may contact an upper surface of the second gate pattern 122 a of the gate structure 130 .

[0082] In an exemplary embodiment of the present disclosure, a distance between the first contact plug 142a and the first blocking insulating pattern 116a may be greater than a distance between the first contact plug 142a and the isolation pattern 114a. In addition, a distance b between the second contact plug 142b and the second blocking insulating pattern 116b may be greater than a distance c between the second contact plug 142b and the isolation pattern 114a.

[0083] In an exemplary embodiment of the present disclosure, in the high voltage transistor, the blocking insulating patterns 116 a and 116 b and the impurity regions 136 a , 132 a , 136 b , and 132 b may be symmetrical with respect to the gate structure 130 .

[0084] exist Figure 3 , reference numeral 1 represents the flow of current along the impurity region and the channel when the high voltage transistor operates.

[0085] The high voltage transistor may include the first blocking insulating pattern 116a and the second blocking insulating pattern 116b, so that the effective distance of the source extension region and the effective distance of the drain extension region can be increased. In addition, the effective distance from the first sidewall of the gate structure 130 to the first contact plug 142a and the effective distance from the second sidewall of the gate structure 130 to the second contact plug 142b can be increased.

[0086] The high voltage transistor may have a channel region at the surface of the substrate 100 below the gate structure 130. The effective distance between the channel region and the first contact plug 142a and the effective distance between the channel region and the second contact plug 142b may be increased, so that the resistance between the channel region and the first contact plug 142a and the resistance between the channel region and the second contact plug 142b may be increased. Therefore, the breakdown voltage of the high voltage transistor formed in a limited area of ​​the substrate may be increased.

[0087] In addition, the distance between the first contact plug 142a and the first blocking insulating pattern 116a may be greater than the distance between the first contact plug 142a and the isolation pattern 114a. In addition, the distance between the second contact plug 142b and the second blocking insulating pattern 116b may be greater than the distance between the second contact plug 142b and the isolation pattern 114a. Therefore, the breakdown voltage of the high voltage transistor can be improved.

[0088] In addition, a distance P between the bottom of the first blocking insulating pattern 116 a and the bottom of the second blocking insulating pattern 116 b may be increased, so that the possibility of punch-through of the high voltage transistor may be reduced.

[0089] The high voltage transistor according to the exemplary embodiment of the present disclosure may be used to operate the reference Figure 2 For example, a high voltage transistor may be used as a switching device for supplying a voltage to a gate electrode of a cell transistor.

[0090] Figure 5 and Figure 6 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Figure 5 is along Figure 6 A cross-sectional view taken along line AA'.

[0091] Figure 5 and Figure 6 The high voltage transistor shown with Figure 3 The high voltage transistors shown are substantially identical except for the arrangement of the gate structure.

[0092] refer to Figure 5 and Figure 6 , a first distance a1 between an edge of the gate structure 130 and the first blocking insulating pattern 116 a and a second distance a2 between another edge of the gate structure 130 and the second blocking insulating pattern 116 b may be different from each other.

[0093] For example, in the operation of the high voltage transistor, the distance between the blocking insulating pattern adjacent to the impurity region for supplying the high voltage and the edge of the gate structure may be greater than the distance between the other blocking insulating pattern and the other edge of the gate structure. For example, when the high voltage is supplied to the source region, the first distance a1 may be greater than the second distance a2. For example, when the high voltage is supplied to the drain region, the second distance a2 may be greater than the first distance a1. Therefore, the breakdown voltage at the impurity region for supplying the high voltage may be increased.

[0094] Figure 7 and Figure 8 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Figure 7 is along Figure 8 A cross-sectional view taken along line AA'.

[0095] Figure 7 and Figure 8 The high voltage transistor shown can be used with Figure 3 The high voltage transistors shown are substantially identical except for the arrangement of the impurity regions.

[0096] refer to Figure 7 and Figure 8 , the first impurity region 136a may be formed at the entire upper portion of the substrate 100 between the first blocking insulating pattern 116a and the isolation pattern 114a, and the third impurity region 136b may be formed at the entire upper portion of the substrate 100 between the second blocking insulating pattern 116b and the isolation pattern 114a. For example, the first impurity region 136a and the third impurity region 136b may contact the first blocking insulating pattern 116a and the second blocking insulating pattern 116b, respectively.

[0097] The first contact plug 142a and the second contact plug 142b may be formed at the central portions of the first impurity region 136a and the third impurity region 136b, respectively. In an exemplary embodiment of the present disclosure, the distance between the first contact plug 142a and the first blocking insulating pattern 116a may be substantially the same as the distance between the first contact plug 142a and the isolation pattern 114a. In addition, the distance b between the second contact plug 142b and the second blocking insulating pattern 116b may be substantially the same as the distance c between the second contact plug 142b and the isolation pattern 114a.

[0098] Figures 9 to 17 are cross-sectional views showing various stages of a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0099] refer to Fig. 9 , a gate insulating layer 102 may be formed on the substrate 100 including the memory cell region and the peripheral region. A first gate layer 104 may be formed on the gate insulating layer 102.

[0100] In an exemplary embodiment of the present disclosure, the gate insulating layer 102 may include silicon oxide. In an exemplary embodiment of the present disclosure, the first gate layer 104 may include polysilicon.

[0101] In some exemplary embodiments of the present disclosure, the gate insulating layer 102 may include a metal oxide having a high dielectric constant. In this case, the first gate layer 104 may include a metal.

[0102] A first mask layer 106 may be formed on the first gate layer 104. The first mask layer 106 may include silicon oxide or silicon nitride.

[0103] refer to Fig.10 , the first mask layer 106 may be patterned to form a first mask pattern 106a. The first mask pattern 106a may include openings at regions where the isolation trench 108 and the first and second trenches 110a and 110b may be subsequently formed.

[0104] The first mask pattern 106a may be used as an etching mask to etch the first gate layer 104, the gate insulating layer 102, and the substrate 100 to form an isolation trench 108 and first and second trenches 110a and 110b. In addition, the first gate layer 104 and the gate insulating layer 102 may be patterned by an etching process. Thus, an initial first gate pattern 104a and an initial gate insulating pattern 102a may be formed.

[0105] A plurality of isolation trenches 108 may be formed in the substrate of the isolation region. Thus, an active region may be defined by the isolation trenches 108. A first trench 110a and a second trench 110b may be formed at the active region between the isolation trenches 108. An effective distance between a subsequently formed gate structure and a contact plug may be increased by forming the first trench 110a and the second trench 110b.

[0106] refer to Fig.11 , the second mask pattern 150 may cover the isolation trench 108 and the memory cell region and expose the first trench 110a and the second trench 110b. The second mask pattern 150 may be a photoresist pattern.

[0107] Impurities may be implanted (or doped) along surfaces of the first and second trenches 110a and 110b exposed by the second mask pattern 150 to form initial first impurity regions 112. The impurity implantation process may be performed by an inclined ion implantation process so that impurities may be uniformly doped along surfaces of the first and second trenches 110a and 110b.

[0108] Thereafter, the second mask pattern 150 may be removed.

[0109] refer to Fig.12 , an insulating layer may be formed on the first mask pattern 106a to fill the isolation trench 108 and the first trench 110a and the second trench 110b. The surface of the insulating layer may be planarized until the upper surface of the initial first gate pattern 104a may be exposed, thereby forming the first insulating pattern 114 and the second insulating pattern 116. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0110] The first insulating pattern 114 may fill the isolation trench 108 and a space above the isolation trench 108 between a stack structure including the initial gate insulating pattern 102a and the initial first gate pattern 104a thereon. In addition, the second insulating pattern 116 may fill the first trench 110a and the second trench 110b and a space above the first trench 110a and the second trench 110b between the stack structure including the initial gate insulating pattern 102a and the initial first gate pattern 104a thereon.

[0111] refer to Fig.13 , a second gate layer 122 may be formed on the first and second insulating patterns 114 and 116 and the preliminary first gate pattern 104 a .

[0112] In an exemplary embodiment of the present disclosure, the second gate layer 122 may include a stacked second polysilicon layer 118 and a metal silicide layer 120. Thereafter, a hard mask pattern 124 may be formed on the second gate layer 122.

[0113] The hard mask pattern 124 may be used as an etching mask for forming a gate structure. Therefore, the hard mask pattern 124 may be formed on the active region between the first trench 110a and the second trench 110b. In addition, one end of the hard mask pattern 124 in the first direction may be spaced apart from the first trench 110a, and the other end of the hard mask pattern 124 in the first direction may be spaced apart from the second trench 110b.

[0114] refer to Fig.14 The second gate layer 122 , the initial first gate pattern 104 a , the initial gate insulating pattern 102 a , and the first and second insulating patterns 114 and 116 may be etched using the hard mask pattern 124 as an etching mask to form a gate structure 130 .

[0115] The gate structure 130 may be formed on the active region of the substrate 100 , and the gate structure 130 may include a gate insulating pattern 102 b , a first gate pattern 104 b , a second gate pattern 122 a , and a hard mask pattern 124 , which are stacked.

[0116] In addition, an isolation pattern 114a may be formed in the isolation trench 108, and a first blocking insulating pattern 116a may be formed in the first trench 110a. A second blocking insulating pattern 116b may be formed in the second trench 110b. The first blocking insulating pattern 116a may be spaced apart from the first sidewall of the gate structure 130, and the second blocking insulating pattern 116b may be spaced apart from the second sidewall of the gate structure 130.

[0117] In an exemplary embodiment of the present disclosure, in the patterning process of the gate structure 130, the distance between the gate structure 130 and the first blocking insulating pattern 116a and the distance between the gate structure 130 and the second blocking insulating pattern 116b may be substantially the same. In this case, the gate structure 130 may be manufactured by performing subsequent processes. Figure 3 and Figure 4 The high voltage transistor shown.

[0118] In some exemplary embodiments of the present disclosure, in the patterning process of the gate structure 130, the distance between the gate structure 130 and the first blocking insulating pattern 116a and the distance between the gate structure 130 and the second blocking insulating pattern 116b may be different from each other. In this case, the gate structure 130 may be manufactured by performing subsequent processes. Figure 5 and Figure 6 The high voltage transistor shown.

[0119] refer to Fig.15 , an ion implantation process may be performed on the substrate 100 and the gate structure 130 to form an initial second impurity region 132. Impurities may be doped into the upper portion of the substrate 100 in the region where the gate structure 130 is not formed by the ion implantation process, and the upper portion doped with impurities merges with the initial first impurity region 112 to form the initial second impurity region 132. Therefore, the initial second impurity region 132 may be formed along the surfaces of the first trench 110a and the second trench 110b and the surface of the substrate 100 between the gate structure 130 and the isolation pattern 114a.

[0120] In an exemplary embodiment of the present disclosure, before the doping of impurities, a protective layer may be further formed on the surfaces of the substrate 100 and the gate structure 130. The protective layer may protect the gate structure 130 and the substrate 100 during the ion implantation process. The protective layer may include, for example, silicon oxide.

[0121] The preliminary second impurity region 132 may partially function as the second impurity region and partially function as the fourth impurity region. The preliminary second impurity region 132 may have a first impurity concentration.

[0122] refer to Fig.16 , a third mask pattern 138 may be formed on the substrate 100 and the gate structure 130. The third mask pattern 138 may be used as an ion implantation mask in a doping process of forming the first impurity region 136a and the third impurity region 136b.

[0123] In an exemplary embodiment of the present disclosure, the third mask pattern 138 may selectively expose a portion of the substrate 100 for forming a first contact plug.

[0124] Impurities may be implanted into the substrate 100 using the third mask pattern 138 as a mask to form a first impurity region 136a and a third impurity region 136b. The initial second impurity region 132 connected to the first impurity region 136a may be used as the second impurity region 132a. In addition, the initial second impurity region 132 connected to the third impurity region 136b may be used as the fourth impurity region 132b.

[0125] The impurities doped in the first to fourth impurity regions 136a, 132a, 136b, and 132b may have the same conductivity type. In an exemplary embodiment of the present disclosure, the second impurity concentration of the first impurity region 136a and the third impurity region 136b and the first impurity concentration of the second impurity region 132a and the fourth impurity region 132b may be different from each other. For example, the second impurity concentration may be higher than the first impurity concentration.

[0126] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be spaced apart from the first blocking insulating pattern 116a. In an exemplary embodiment of the present disclosure, the third impurity region 136b may be spaced apart from the second blocking insulating pattern 116b.

[0127] In some exemplary embodiments of the present disclosure, the first impurity region 136a may be formed in the entire upper portion of the substrate between the first blocking insulating pattern 116a and the isolation pattern 114a. The third impurity region 136b may be formed in the entire upper portion of the substrate between the second blocking insulating pattern 116b and the isolation pattern 114a. In this case, the ... Figure 7 and Figure 8 The high voltage transistor shown.

[0128] Then, the third mask pattern 138 may be removed.

[0129] refer to Fig.17 The insulating interlayer 140 may cover the substrate 100 and the gate structure 130 . The first contact plug 142 a and the second contact plug 142 b may be formed through the insulating interlayer 140 .

[0130] The first and second contact plugs 142 a and 142 b may contact upper surfaces of the first and third impurity regions 136 a and 136 b , respectively.

[0131] In an exemplary embodiment of the present disclosure, a gate contact plug may be further formed through the insulating interlayer 140 and the hard mask pattern 124. The gate contact plug may contact an upper surface of the second gate pattern 122a.

[0132] In an exemplary embodiment of the present disclosure, the distance between the first contact plug 142a and the first blocking insulating pattern 116a may be greater than the distance between the first contact plug 142a and the isolation pattern 114a. In addition, the distance between the second contact plug 142b and the second blocking insulating pattern 116b may be greater than the distance between the second contact plug 142b and the isolation pattern 114a.

[0133] In some exemplary embodiments of the present disclosure, Figure 7 and Figure 8 As shown, the distance between the first contact plug 142a and the first blocking insulating pattern 116a may be substantially the same as the distance between the first contact plug 142a and the isolation pattern 114a. In addition, the distance between the second contact plug 142b and the second blocking insulating pattern 116b may be substantially the same as the distance between the second contact plug 142b and the isolation pattern 114a.

[0134] Fig.18 and Fig.19 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Fig.18 is along Fig.19 A cross-sectional view taken along line AA'.

[0135] Fig.18 and Fig.19 There may be a plurality of high voltage transistors electrically connected to each other and formed in the active region. The structure of each high voltage transistor may be similar to that of the reference Figure 3 The structure described is essentially the same.

[0136] refer to Fig.18 and Fig.19 , a plurality of gate structures 130 extending along the second direction may be formed on the substrate 100. The plurality of gate structures 130 may be spaced apart from each other in the first direction.

[0137] The first trench 110a and the second trench 110b may be formed between the plurality of gate structures 130 and between one of the gate structures 130 and the isolation pattern 114a, respectively. In an exemplary embodiment of the present disclosure, the first trench 110a may be spaced apart from a first sidewall of one of the gate structures 130, and the second trench 110b may be spaced apart from a second sidewall of one of the gate structures 130. The first blocking insulating pattern 116a and the second blocking insulating pattern 116b may be formed in the first trench 110a and the second trench 110b, respectively.

[0138] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be used as a common impurity region of two high voltage transistors connected to each other in the first direction. In an exemplary embodiment of the present disclosure, the two high voltage transistors may be symmetrical with respect to a straight line passing through the center of the first impurity region 136a in the second direction. In this case, the first impurity region 136a may be disposed between the first blocking insulating patterns 116a in the two high voltage transistors.

[0139] In an exemplary embodiment of the present disclosure, the third impurity region 136 b may be formed between the second blocking insulating pattern 116 b and the isolation pattern 114 a .

[0140] The first contact plug 142a may be formed on an upper surface of the first impurity region 136a. The second contact plug 142b may be formed on an upper surface of the third impurity region 136b.

[0141] Fig. 20 and Fig.21 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Fig. 22 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Fig. 20 is along Fig.21 A cross-sectional view taken along line AA'.

[0142] Each high voltage transistor is Figure 3 The high voltage transistors shown are substantially the same except for the blocking insulating pattern.

[0143] refer to Fig. 20 and Fig.21 , the high voltage transistor may include a gate structure 130, a first blocking insulating pattern 116a, and impurity regions 136a, 132a, 136b, and 132b. An insulating interlayer 140 may cover the high voltage transistor. A first contact plug 142a and a second contact plug 142b may be formed through the insulating interlayer 140. The first contact plug 142a and the second contact plug 142b may contact at least a portion of the impurity region.

[0144] The substrate 100 may include a first trench 110a spaced apart from a first sidewall of the gate structure 130 in a first direction. A first blocking insulating pattern 116a may be formed in the first trench 110a.

[0145] For example, the first blocking insulating pattern 116a may be spaced apart from one sidewall of the gate structure 130 in the first direction. The second blocking insulating pattern may not be formed on the substrate 100. In particular, the second blocking insulating pattern spaced apart from the second sidewall of the gate structure 130 opposite to the first sidewall may not be formed. Therefore, the first blocking insulating pattern 116a may be asymmetric with respect to the gate structure 130.

[0146] The impurity regions may include a first impurity region 136 a , a second impurity region 132 a , a third impurity region 136 b , and a fourth impurity region 132 b .

[0147] The first impurity region 136a may be formed below the surface of the substrate 100 in the active region between the first blocking insulating pattern 116a and the isolation pattern 114a. The second impurity region 132a may be formed in the substrate 100 along the surface of the first trench 110a in which the first blocking insulating pattern 116a is formed. The first impurity region 136a and the second impurity region 132a may be connected to each other.

[0148] The third impurity region 136b may be spaced apart from the second sidewall of the gate structure 130. The third impurity region 136b may be formed below the surface of the substrate 100 in the active region between the second sidewall of the gate structure 130 and the isolation pattern 114a. The fourth impurity region 132b may be formed below the surface of the substrate 100 in the active region between the second sidewall of the gate structure 130 and the third impurity region 136b. The third impurity region 136b and the fourth impurity region 132b may be formed below the flat top surface of the substrate 100.

[0149] Since the first blocking insulating pattern 116a may be spaced apart from the first sidewall of the gate structure 130, the fourth impurity region 132b and the second impurity region 132a below the bottom of the first blocking insulating pattern 116a may not be located on the same plane. The bottom of the first blocking insulating pattern 116a and the portion of the substrate 100 adjacent to the second sidewall of the gate structure 130 may be arranged in an inclined direction. Therefore, the distance P between the bottom of the first blocking insulating pattern 116a and the portion of the substrate 100 adjacent to the second sidewall of the gate structure 130 may be increased. In addition, the lowermost portion of the second impurity region 132a and the fourth impurity region 132b may be arranged in an inclined direction, so that the distance between the lowermost portion of the second impurity region 132a and the fourth impurity region 132b may be increased. For example, the possibility of generating an unwanted channel path between the second impurity region 132a below the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b adjacent to the second sidewall of the gate structure may be reduced. Therefore, the possibility of punch-through may be reduced.

[0150] Since the first blocking insulating pattern 116a is asymmetrically disposed relative to the gate structure 130, punch-through can be greatly reduced. Fig. 22 As shown, the first sidewall of the gate structure 130 and the first blocking insulating pattern 116 a may not be spaced apart from each other.

[0151] In an exemplary embodiment of the present disclosure, the first blocking insulating pattern 116 a may be disposed adjacent to an impurity region for supplying a high voltage during operation of the high voltage transistor.

[0152] The first contact plug 142a may contact the first impurity region 136a. The second contact plug 142b may contact the third impurity region 136b.

[0153] In an exemplary embodiment of the present disclosure, a distance between the first contact plug 142 a and the first blocking insulating pattern 116 a may be greater than a distance between the first contact plug 142 a and the isolation pattern 114 a .

[0154] In an exemplary embodiment of the present disclosure, a distance between the second contact plug 142 b and the gate structure 130 may be greater than a distance between the second contact plug 142 b and the isolation pattern 114 a .

[0155] As the distance P between the bottom of the first blocking insulating pattern 116 a and the fourth impurity region 132 b increases, the possibility of punch-through of the high voltage transistor may be reduced.

[0156] Figure 23 to Figure 27 are cross-sectional views showing various stages of a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0157] refer to Fig.23 , a gate insulating layer, a first gate layer, and a first mask layer may be formed on the substrate 100 including the memory cell region and the peripheral region.

[0158] The first mask layer may be patterned to form a first mask pattern 106a. The first gate layer, the gate insulating layer, and the substrate 100 may be etched using the first mask pattern 106a as an etching mask to form an isolation trench 108 and a first trench 110a. In addition, the first gate layer and the gate insulating layer may be patterned by an etching process, so that an initial first gate pattern 104a and an initial gate insulating pattern 102a may be formed.

[0159] The isolation trench 108 may be formed in an isolation region of the substrate 100. The first trench 110a may be spaced apart from a first sidewall of a gate structure to be formed subsequently.

[0160] refer to Fig.24 The second mask pattern 150 may cover the isolation trench 108 and the memory cell region and expose the first trench 110a. Impurities may be implanted (or doped) along the surface of the first trench 110a exposed by the second mask pattern 150 to form an initial first impurity region 112. Then, the second mask pattern 150 may be removed.

[0161] refer to Fig.25 , can be executed with reference Figure 12 to Figure 13 The process is the same as described.

[0162] Therefore, the first insulating pattern 114 may fill the isolation trench 108 and a space above the isolation trench 108 between the stacked structure including the initial gate insulating pattern 102a and the initial first gate pattern 104a thereover. In addition, the second insulating pattern 116 may fill the first trench 110a and a space above the first trench 110a between the stacked structure including the initial gate insulating pattern 102a and the initial first gate pattern 104a thereover.

[0163] A second gate layer 122 and a hard mask pattern 124 may be formed on the first and second insulating patterns 114 and 116 and the preliminary first gate pattern 104a. A first sidewall of the hard mask pattern 124 and the first trench 110a may be spaced apart from each other in the first direction.

[0164] refer to Fig.26 The second gate layer 122 , the initial first gate pattern 104 a , the initial gate insulating pattern 102 a , and the first and second insulating patterns 114 and 116 may be etched using the hard mask pattern 124 as an etching mask to form a gate structure 130 .

[0165] Thus, the gate structure 130 may be formed on the substrate 100 in the active region. In addition, an isolation pattern 114a may be formed in each isolation trench 108, and a first blocking insulating pattern 116a may be formed in the first trench 110a.

[0166] An ion implantation process may be performed on the substrate 100 and the gate structure 130 to form an initial second impurity region 132. The initial second impurity region 132 may be formed along a surface of the first trench 110a and a surface of the substrate 100 between the gate structure 130 and the isolation pattern 114a.

[0167] refer to Fig. 27 , a third mask pattern 138 may be formed on the substrate 100 and the gate structure 130. The third mask pattern 138 may be used as an ion implantation mask in a doping process for forming the first impurity region 136a and the third impurity region 136b.

[0168] Impurities may be implanted into the substrate 100 using the third mask pattern 138 to form a first impurity region 136a and a third impurity region 136b. The initial second impurity region 132 connected to the first impurity region 136a may be used as the second impurity region 132a. In addition, the initial second impurity region 132 connected to the third impurity region 136b may be used as the fourth impurity region 132b.

[0169] Reference again Fig. 22The insulating interlayer 140 may cover the substrate 100 and the gate structure 130 . Then, a first contact plug 142 a and a second contact plug 142 b may be formed through the insulating interlayer 140 .

[0170] Fig.28 and Fig.29 2 are a cross-sectional view and a plan view respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0171] exist Fig.28 and Fig.29 In the embodiment, a plurality of high voltage transistors formed on the active region may be electrically connected to each other. The structure of each high voltage transistor may be similar to that of the reference Fig. 20 The structures of the high voltage transistors shown are essentially the same.

[0172] refer to Fig.28 and Fig.29 , a plurality of gate structures 130 extending along the second direction may be formed on the substrate 100. The plurality of gate structures 130 may be spaced apart from each other in the first direction.

[0173] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be a common impurity region of two high voltage transistors connected in the first direction. In an exemplary embodiment of the present disclosure, the two high voltage transistors may be symmetrical with respect to a straight line passing through the center of the first impurity region 136a in the second direction. In this case, the first impurity region 136a may be disposed between the first blocking insulating patterns 116a in the two high voltage transistors.

[0174] In an exemplary embodiment of the present disclosure, the third impurity region 136 b may be formed between the second sidewall of the gate structure 130 and the isolation pattern 114 a .

[0175] The first contact plug 142a may be formed on an upper surface of the first impurity region 136a. The second contact plug 142b may be formed on an upper surface of the third impurity region 136b.

[0176] Fig.30 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0177] Fig.30 The transistor shown can be used with Figure 3 The high voltage transistors shown are substantially the same except for the blocking insulating pattern.

[0178] refer to Fig.30, the high voltage transistor may include a gate structure 130, a first blocking insulating pattern 116a, a second blocking insulating pattern 116b, and impurity regions 136a, 132a, 136b, and 132b. The insulating interlayer 140 may cover the high voltage transistor. The first contact plug 142a and the second contact plug 142b may be formed through the insulating interlayer 140. The first contact plug 142a and the second contact plug 142b may contact at least a portion of the impurity regions 136a, 132a, 136b, and 132b.

[0179] The substrate 100 may include a first trench 110a spaced apart from a first sidewall of the gate structure 130 in a first direction. A first blocking insulating pattern 116a may be formed in the first trench 110a.

[0180] The substrate 100 may include a second trench 110b spaced apart from a second sidewall of the gate structure 130 in the first direction. A second blocking insulating pattern 116b may be formed in the second trench 110b.

[0181] In an exemplary embodiment of the present disclosure, the depth of the second trench 110b may be different from the depth of the first trench 110a. For example, the depth of the second trench 110b may be less than the depth of the first trench 110a. For example, the bottom of the first trench 110a and the bottom of the second trench 110b may not be coplanar with each other. Therefore, the bottom of the first blocking insulating pattern 116a and the bottom of the second blocking insulating pattern 116b may be located on different planes.

[0182] Therefore, the first and second blocking insulating patterns 116 a and 116 b may be asymmetric with respect to the gate structure 130 .

[0183] The impurity regions may include a first impurity region 136 a , a second impurity region 132 a , a third impurity region 136 b , and a fourth impurity region 132 b .

[0184] The first impurity region 136a may be formed below the surface of the substrate 100 in the active region between the first blocking insulating pattern 116a and the isolation pattern 114a. The second impurity region 132a may be formed in the substrate 100 along the surface of the first trench 110a in which the first blocking insulating pattern 116a is formed. The first impurity region 136a and the second impurity region 132a may be connected to each other.

[0185] The third impurity region 136b may be formed below the surface of the substrate 100 in the active region between the second blocking insulating pattern 116b and the isolation pattern 114a. The fourth impurity region 132b may be formed in the substrate 100 along the surface of the second trench 110b in which the second blocking insulating pattern 116b is formed. The third impurity region 136b and the fourth impurity region 132b may be connected to each other.

[0186] Since the height of the bottom of the first blocking insulating pattern 116a and the height of the bottom of the second blocking insulating pattern 116b are different from each other, the second impurity region 132a under the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b under the bottom of the second blocking insulating pattern 116b may not be located on the same plane. The second impurity region 132a under the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b under the bottom of the second blocking insulating pattern 116b may be arranged in an inclined direction. Therefore, the distance P between the second impurity region 132a under the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b under the bottom of the second blocking insulating pattern 116b can be increased. The possibility of generating an unwanted channel path at the portion between the second impurity region 132a under the bottom of the first blocking insulating pattern 116a and the fourth impurity region 132b under the bottom of the second blocking insulating pattern 116b can be reduced. Therefore, the possibility of punch-through can be reduced.

[0187] The first contact plug 142a may contact the first impurity region 136a. The second contact plug 142b may contact the third impurity region 136b.

[0188] Figure 31 to Figure 34 are cross-sectional views illustrating various stages of a method of fabricating a vertical semiconductor device according to an exemplary embodiment of the present disclosure.

[0189] refer to Fig.31 , a gate insulating layer, a first gate layer, and a first mask layer may be formed on the substrate 100 including the memory cell region and the peripheral region.

[0190] The first mask layer may be patterned to form a first mask pattern 106 a .

[0191] The first gate layer, the gate insulating layer and the substrate 100 may be etched using the first mask pattern 106a as an etching mask to form a preliminary trench 109. In addition, the first gate layer and the gate insulating layer may be patterned by an etching process to form preliminary first gate patterns 104a and preliminary gate insulating patterns 102a.

[0192] The preliminary trench 109 may be formed at a region for forming an isolation region and the first and second trenches in the substrate 100 .

[0193] refer to Fig.32 , a mask pattern 113 exposing a portion of the preliminary trench 109 may be formed on the first mask pattern 106 a.

[0194] The mask pattern 113 may expose a portion of the initial trench 109 where the isolation trench and the first trench are subsequently formed. In addition, the mask pattern 113 may cover a portion of the initial trench 109 where the second trench is subsequently formed. For example, the mask pattern 113 may selectively expose a portion where the isolation pattern and the first blocking insulating pattern are subsequently formed.

[0195] Thereafter, the substrate 100 may be etched using the mask pattern 113 as an etching mask. Thus, the exposed initial trenches in the initial trenches 109 of the substrate 100 may be further etched to form the isolation trench 108 and the first trench 110a. In addition, the unetched initial trenches may be used as the second trench 110b. Thereafter, the mask pattern 113 may be removed.

[0196] refer to Fig.33 , the second mask pattern 150 may cover the isolation trench 108 and the memory cell region and expose the first trench 110 a and the second trench 110 b .

[0197] Impurities may be implanted (or doped) along surfaces of the first and second trenches 110a and 110b exposed by the second mask pattern 150 to form initial first impurity regions 112. Thereafter, the second mask pattern 150 may be removed.

[0198] refer to Fig.34 , can be executed with reference Figures 12 to 16 Thus, a first blocking insulating pattern 116a and a second blocking insulating pattern 116b may be formed in the first trench 110a and the second trench 110b, respectively. In addition, first to fourth impurity regions 136a, 132a, 136b, and 132b may be formed in the substrate 100 adjacent to the side of the gate structure 130.

[0199] Reference again Fig.30 , the first contact plug 142 a and the second contact plug 142 b may contact the first impurity region 136 a and the third impurity region 136 b , respectively.

[0200] Fig.35 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure. Fig.36 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0201] exist Fig.35 and Fig.36 In each of the active regions, a plurality of high voltage transistors formed in the active region may be electrically connected to each other. The structure of each high voltage transistor may be similar to that of the reference Fig.30 The structures of the high voltage transistors shown are essentially the same.

[0202] refer to Fig.35 , a plurality of gate structures 130 extending in the second direction may be formed on the substrate 100. The plurality of gate structures 130 may be spaced apart from each other in the first direction.

[0203] The first trench 110a may be formed between the gate structures 130 adjacent in the first direction. Therefore, the first blocking insulating pattern 116a may be formed between the gate structures 130 adjacent in the first direction.

[0204] In an exemplary embodiment of the present disclosure, the first impurity region 136a may be a common impurity region of two high voltage transistors connected to each other in the first direction. In an exemplary embodiment of the present disclosure, the two high voltage transistors may be symmetrical with respect to a straight line passing through the center of the first impurity region 136a in the second direction. In this case, the first impurity region 136a may be disposed between the first blocking insulating patterns 116a in the two high voltage transistors.

[0205] In an exemplary embodiment of the present disclosure, the second trench 110b may be spaced apart from the second sidewall of the gate structure 130. A second blocking insulating pattern 116b may be formed in the second trench 110b.

[0206] In an exemplary embodiment of the present disclosure, the third impurity region 136 b may be formed between the second blocking insulating pattern 116 b and the isolation pattern 114 a .

[0207] In an exemplary embodiment of the present disclosure, a bottom of the second blocking insulating pattern 116 b may be higher than a bottom of the first blocking insulating pattern 116 a .

[0208] In some exemplary embodiments of the present disclosure, Fig.36 As shown, a bottom of the second blocking insulating pattern 116 b may be lower than a bottom of the first blocking insulating pattern 116 a .

[0209] The first contact plug 142a may be formed on an upper surface of the first impurity region 136a. The second contact plug 142b may be formed on an upper surface of the third impurity region 136b.

[0210] Figure 37 to Figure 39They are cross-sectional views respectively showing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0211] Figure 37 to Figure 39 Each high voltage transistor shown can be connected with Figure 3 The high voltage transistor shown is substantially the same except that insulating spacers are further formed on the sidewalls of the gate structure.

[0212] exist Figure 37 to Figure 39 In each transistor shown, the insulating spacer may include, for example, silicon nitride or silicon oxide. The insulating spacer may include one or more layers.

[0213] refer to Fig.37 , the bottom of the insulating spacer 148 formed on the sidewall of the gate structure 130 may not overlap with the upper portion of the first trench 110a and the second trench 110b, respectively. Fig.37 As shown, each of the first trench 110a and the second trench 110b may be spaced apart from the sidewall of the insulating spacer 148. Therefore, the sidewall of the insulating spacer 148 and the first trench 110a on the first sidewall of the gate structure 130 may be spaced apart from each other, and the sidewall of the insulating spacer 148 and the second trench 110b on the second sidewall of the gate structure 130 may be spaced apart from each other.

[0214] refer to Fig.38 , the bottom of the insulating spacer 148 formed on the sidewall of the gate structure 130 may not overlap with the upper portion of the first trench 110a and the upper portion of the second trench 110b, respectively. Fig.38 As shown, the sidewalls of the insulating spacer 148 and the sidewalls of the first trench 110a may be aligned with each other, and the sidewalls of the insulating spacer 148 and the sidewalls of the second trench 110b may be aligned with each other. Therefore, the sidewalls of the insulating spacer 148 formed on the first sidewall of the gate structure 130 and the first trench 110a may not be spaced apart from each other. The sidewalls of the insulating spacer 148 formed on the second sidewall of the gate structure 130 and the second trench 110b may not be spaced apart from each other.

[0215] refer to Fig.39 , the bottom of the insulating spacer 148 formed on the sidewall of the gate structure 130 may overlap with the upper portion of the first trench 110a and the upper portion of the second trench 110b, respectively. Fig.39 As shown, the bottom of the insulating spacer 148 formed on the first sidewall of the gate structure 130 may partially cover the upper portion of the first trench 110a. Also, the bottom of the insulating spacer 148 formed on the second sidewall of the gate structure 130 may partially cover the upper portion of the second trench 110b.

[0216] Manufacturing reference Fig.39The high voltage transistor process described can be compared with Figures 9 to 17 However, when executing reference Fig.15 After the illustrated process, an insulating spacer layer may be further formed on the surface of the substrate 100 and the gate structure, and the insulating spacer layer may be anisotropically etched. Thus, insulating spacers may be formed on the sidewalls of the gate structure.

[0217] In each of the high voltage transistors according to the exemplary embodiments of the present disclosure described above, an insulating spacer may be further formed on a sidewall of the gate structure.

[0218] Fig.40 is a cross-sectional view showing a high voltage transistor according to an exemplary embodiment of the present disclosure.

[0219] Fig.40 The transistor shown can be used with Figure 3 The transistors shown are substantially identical except for the inner widths of the first and second trenches.

[0220] refer to Fig.40 , the inner width of the first trench 110a may be different from the inner width of the second trench 110b. Therefore, the width of the first blocking insulating pattern 116a may be different from the width of the second blocking insulating pattern 116b.

[0221] For example, the second trench 110b may have an inner width greater than the inner width of the first trench 110a. In this case, the second blocking insulating pattern 116b may have a width greater than the width of the first blocking insulating pattern 116a. In each high voltage transistor according to the exemplary embodiment of the present disclosure described above, the first blocking insulating pattern 116a and the second blocking insulating pattern 116b may have different widths.

[0222] The foregoing is an illustration of exemplary embodiments of the present disclosure and should not be construed as limiting thereof. Although some exemplary embodiments of the present disclosure have been described, it will be readily appreciated by those skilled in the art that many modifications in the exemplary embodiments of the present disclosure are possible without substantially departing from the novel teachings and aspects of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention.

[0223] This application claims the benefit of Korean Patent Application No. 10-2019-0089099 filed on July 23, 2019, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: A gate structure disposed on a substrate, the gate structure having a first sidewall and a second sidewall opposite to the first sidewall; a first impurity region disposed within an upper portion of the substrate, the first impurity region being spaced apart from the first sidewall; a third impurity region disposed within the upper portion of the substrate, the third impurity region being spaced apart from the second sidewall; A first trench is disposed in the substrate between the first sidewall and the first impurity region, the first trench being spaced apart from the first sidewall; as well as a first blocking insulating pattern disposed in the first trench, a second impurity region formed in the substrate between the first sidewall and the first impurity region and extending along a surface of the first trench, the second impurity region being connected to the first impurity region and having at least one horizontal section disposed between the first trench and the first sidewall or between the first trench and the first impurity region.

2. The semiconductor device according to claim 1, wherein The second impurity region is formed along a surface of the substrate under the first blocking insulating pattern. 3 . The semiconductor device according to claim 1 , further comprising a fourth impurity region formed in the substrate between the second sidewall and the third impurity region, the fourth impurity region being connected to the third impurity region.

4. The semiconductor device according to claim 3, wherein: The impurity concentrations of the first impurity region and the third impurity region are higher than the impurity concentrations of the second impurity region and the fourth impurity region.

5. The semiconductor device according to claim 3, wherein: The first impurity region, the second impurity region, the third impurity region, and the fourth impurity region are all doped with impurities having the same conductivity type.

6. The semiconductor device according to claim 1, further comprising: a second trench disposed in the substrate between the second sidewall and the third impurity region, the second trench being spaced apart from the second sidewall; as well as A second blocking insulating pattern is disposed in the second trench.

7. The semiconductor device according to claim 6, further comprising a fourth impurity region disposed within the substrate between the second sidewall and the third impurity region, wherein the fourth impurity region is formed along the substrate below a surface of the second blocking insulating pattern and the fourth impurity region is connected to the third impurity region.

8. The semiconductor device according to claim 6, wherein: A distance between the first sidewall and the first trench is the same as a distance between the second sidewall and the second trench.

9. The semiconductor device according to claim 6, wherein: A distance between the first sidewall and the first trench is different from a distance between the second sidewall and the second trench.

10. The semiconductor device according to claim 6, wherein The bottom of the first groove and the bottom of the second groove are located on the same plane.

11. The semiconductor device according to claim 6, wherein: A bottom of the first trench and a bottom of the second trench are located on different planes from each other.

12. The semiconductor device according to claim 6, wherein: An inner width of the first trench is the same as an inner width of the second trench.

13. The semiconductor device according to claim 6, wherein: The inner width of the first trench is different from the inner width of the second trench.

14. The semiconductor device according to claim 1, wherein An upper surface of the substrate between the second side wall and the third impurity region is flat.

15. The semiconductor device according to claim 1, wherein The gate structure includes a gate insulating pattern and a gate pattern stacked on the gate insulating pattern.

16. The semiconductor device according to claim 1, wherein The substrate further includes an isolation pattern, and the first impurity region and / or the third impurity region contacts the isolation pattern. 17 . The semiconductor device according to claim 1 , further comprising a spacer formed on the first sidewall of the gate structure.

18. The semiconductor device according to claim 17, wherein: A bottom of the spacer overlaps with an upper portion of the first trench, or does not overlap with the upper portion of the first trench.

19. A semiconductor device comprising: a gate structure formed on a substrate; forming a first impurity region in the substrate, the first impurity region being spaced apart from a first sidewall of the gate structure; a second impurity region formed in the substrate between the first sidewall and the first impurity region and extending along a surface of a first trench formed in the substrate between the first sidewall and the first impurity region, the second impurity region being connected to the first impurity region and having at least one horizontal section disposed between the first trench and the first sidewall or between the first trench and the first impurity region; a third impurity region formed in the substrate, the third impurity region being spaced apart from a second sidewall of the gate structure opposite to the first sidewall; a fourth impurity region formed in the substrate between the second sidewall and the third impurity region, the fourth impurity region being connected to the third impurity region; as well as a first blocking insulating pattern filling the first trench, The first blocking insulating pattern is spaced apart from the first sidewall of the gate structure, and the second impurity region is formed along a surface of the substrate below the first blocking insulating pattern.

20. The semiconductor device according to claim 19, wherein The fourth impurity region is formed at an upper planar portion of the substrate between the second sidewall of the gate structure and the third impurity region. 21 . The semiconductor device of claim 19 , further comprising a second trench formed in the substrate between the second sidewall and the third impurity region, wherein the second trench is spaced apart from the second sidewall.

22. The semiconductor device according to claim 21, further comprising a second blocking insulating pattern disposed in the second trench, wherein The fourth impurity region is formed along a surface of the substrate under the second blocking insulating pattern.

23. The semiconductor device according to claim 22, wherein: A bottom of the first blocking insulating pattern and a bottom of the second blocking insulating pattern are located on different planes.

24. A semiconductor device comprising: a gate structure formed on a substrate; a first impurity region formed at an upper portion of the substrate, the first impurity region being spaced apart from a first sidewall of the gate structure; a second impurity region formed in the substrate between the first sidewall and the first impurity region, the second impurity region being connected to the first impurity region and having at least one horizontal section disposed between a first trench formed in the substrate between the first sidewall and the first impurity region and the first sidewall or between the first trench and the first impurity region; a third impurity region formed at an upper portion of the substrate, the third impurity region being spaced apart from a second sidewall of the gate structure opposite to the first sidewall; forming a fourth impurity region in the substrate between the second sidewall and the third impurity region, the fourth impurity region being connected to the third impurity region; a first blocking insulating pattern filling the first trench; an insulating intermediate layer, at least partially covering the gate structure on the substrate; as well as a first contact plug and a second contact plug passing through the insulating interlayer, the first contact plug and the second contact plug contacting the first impurity region and the third impurity region respectively; The first blocking insulating pattern is spaced apart from the first sidewall, and the first to fourth impurity regions are all doped with impurities of the same conductive type.

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