High-voltage transistor with source / drain regions of fins and trench gate structures and method for its manufacture

Abstract

Transistor, comprising: a first set of fins (175A, 190A) fixed over a substrate (110); a second set of fins (175B, 190B) fixed above the substrate (110); a gate structure (131) embedded in the substrate (110) between the first set of fins (175A, 190A) and the second set of fins (175B, 190B), wherein the first set of fins (175A, 190A) and the second set of fins (175B, 190B) are doped with a first dopant type and the substrate (110) is doped with a second dopant type that is different from the first dopant type; a first well disposed in the substrate (110) below the first set of fins (175A, 190A); and a second well disposed in the substrate (110) below the second set of fins (175B, 190B), wherein the first well and the second well are doped with the first dopant type.

Description

BackgroundField of the InventionThe present invention relates generally to the fabrication of semiconductor devices, and more particularly to a high voltage transistor having fin source / drain regions and a trench gate structure.Description of the Prior ArtIn US 2014 / 0 167 162 A1, a semiconductor device having an isolation layer, an active semiconductor layer formed on the upper surface of the isolation layer, and a plurality of fins formed on the isolation layer is described.In US 2009 / 0 085 113 A1, a semiconductor device is provided with a semiconductor layer of a first conductivity type and an annular deep trench extending in the depth direction through the semiconductor layer and surrounding a region in which a circuit element is formed.Integrated circuits formed on semiconductor wafers typically include a large number of circuit elements forming an electrical circuit. In addition to active devices such as field effect transistors and / or bipolar transistors, integrated circuits may also comprise passive devices such as resistors, inductors and / or capacitors. In particular, in the manufacture of complex integrated circuits in CMOS technology, millions of transistors, i.e. N-channel transistors and P-channel transistors, are formed on a substrate with a crystalline semiconductor layer.Regardless of whether it is an N-channel transistor or a P-channel transistor, a MOS transistor is formed, for example, from so-called PN junctions formed by an interface between highly doped drain and source regions and an opposite or lightly doped channel region arranged between the drain region and the source region. The conductivity of the channel region, in particular the operating current of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin gate insulating layer. The conductivity of the channel region when forming a conductive channel by applying a corresponding control voltage to the gate electrode depends, inter alia, on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source region and the drain region, which is also referred to as channel length. In combination with the ability to rapidly create a conductive channel beneath the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region therefore substantially determines the performance of the MOS transistors.High voltage transistors are needed for rectification and / or switching applications. Particularly in semiconductor manufacturing, there is an increasing need for integration of high voltage and high power (e.g., low voltage, high speed) devices and high yield conventional bulk transistor devices for system-on-chip applications. Such integrated devices are useful, for example, in analog and mixed signal applications.However, in practice, SOI-FETs (Semiconductor-on-Insulator Field Effect Transistors) have proven problematic in the integration of high-voltage and high-power components (Fully Depleted), which is attributable in part to the differences in the dimensional scaling of the respective components. Complicated structuring methods are required, which significantly increase the overall complexity of the production. Moreover, due to the current limitations caused by the gate insulation layer (e.g., oxide materials) processes used today, there are significant processing challenges when gate insulation layers (e.g., oxide materials) are present on the same chip that support both high-power low-voltage transistor devices and high-voltage transistor devices that can operate at voltages above 5 or 10V. This is partly because a gate insulation layer on a particular chip is typically optimized for either a high-power device or a high-voltage device, but not both at the same time. Moreover, according to the prior art, relatively thicker gate insulating layers of high voltage transistor devices are to be formed in the course of gate patterning of other low voltage FETs, which significantly complicates the overall patterning process.The present invention relates to various methods and apparatus resulting therefrom that can avoid, or at least reduce, the effects of one or more of the problems identified above.SummaryA transistor according to the invention has the features of claim 1.A method according to the invention has the features of claim 9.Embodiments of the invention have the features of the dependent claims.Brief Description of the DrawingsThe invention will be understood with reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate like elements, and in which: FIGS. 1-12 show a method of fabricating a high voltage transistor with source / drain regions of fins and a trench gate structure.Detailed DescriptionVarious illustrative embodiments of the invention are described below. The present subject matter will now be described with reference to the accompanying drawings. Various structures, systems, and devices are schematically illustrated in the drawings for purposes of explanation and in order not to obscure the present invention with details known to those skilled in the art. However, the accompanying drawings are included to describe and explain illustrative examples of the present invention.The present invention relates generally to various methods of fabricating a high voltage transistor having fin and trench gate structure source / drain regions and the resulting devices. As will be readily apparent to those skilled in the art upon a full reading of the present application, the present method is applicable to a variety of devices including, but not limited to, logic devices, memory devices, etc. With reference to the accompanying drawings, various illustrative embodiments of the methods and devices described herein will now be described in more detail.FIGS. 1-10 illustrate various novel methods described herein for forming a high voltage transistor device 100. FIG. 1 shows a cross-sectional view of a plurality of fins 105 defined in a substrate 110. The number of fins 105 and the spacing between fins 105 may vary depending on the particular characteristics of the device(s) to be formed. The substrate 110 may have a variety of configurations, such as the bulk silicon configuration illustrated. The substrate 110 may also have a silicon-on-insulator (SOI) configuration including a bulk silicon layer, a buried isolation layer, and an active layer, wherein semiconductor devices are formed in and over the active layer. The substrate 110 may be formed of silicon or silicon germanium or materials other than silicon, such as germanium. Therefore, the terms "substrate" or "semiconductor substrate" should be understood to include all semiconductor materials and all forms of such materials. The substrate 110 may include various layers. For example, the fins 105 may be formed in a process layer formed over the base layer of the substrate 110.In general, the process flow for forming the resistor device 100 may be integrated with a process flow for forming low voltage FinFET transistor devices (not shown). Similar fins (not shown) may be used, wherein source / drain regions and channel regions may be formed for the FinFET devices.FIG. 2 illustrates the high voltage transistor device 100 after a dielectric layer 115 is formed over the fins 105 and planarized to expose the top surfaces of the fins 105. In some embodiments, the dielectric layer is formed of silicon dioxide, a low-k dielectric material, or another suitable material.FIG. 3 illustrates the high voltage transistor device 100 after a patterned hard mask 120 is formed over the dielectric layer 115. In some embodiments, the patterned hardmask 120 includes multiple layers. For example, a silicon nitride layer may be formed over a silicon dioxide layer. In some embodiments, a photolithography stack is used to pattern the hard mask layer 120. For example, a bottom anti-reflective coating (BARC) may be formed over the hard mask layer, an organic planarization layer (OPL) over the BARC layer, and a photoresist layer over the OPL layer. The photoresist layer is exposed to a light source to define a pattern, and one or more etching processes are performed to transfer the pattern to the hard mask layer 120.FIG. 4 illustrates the high voltage transistor device 100 after an etching process (e.g., an anisotropic etching process) is performed in the presence of the patterned hard mask layer 120 to remove the exposed fins and define the trenches 115A, 115B in the substrate 110 and the hard mask layer 120 is removed. In some embodiments, the trenches 115A define single diffusion break regions (single diffusion break regions) and the trench 115B defines double diffusion break regions (double diffusion break region).FIG. 5 illustrates the high voltage transistor device 100 after a deposition process has been performed to form a dielectric layer 125 in the trenches 115A, 115B. In some embodiments, first portions 125A of the dielectric layer 125 in the trenches 115A are constricted, substantially filling the trenches 115A, and a second portion 125B of the dielectric layer 125 forms a conformal layer in the trench 115B. In some embodiments, air gaps (not shown) are defined in the first portions 125A due to incomplete pinch-off. The first portions 125A define diffusion fractures.FIG. 6 illustrates the high voltage transistor device 100 after a deposition process for forming a gate electrode 130 in the trench 115B and a planarization process are performed. In some embodiments, the planarization process removes portions of the dielectric layer 125 that are disposed over the dielectric layer 115. In some embodiments, the gate electrode 130 is formed of polysilicon. In some embodiments, the polysilicon is doped in situ, while in other embodiments, a masked implantation process is performed to dope the polysilicon. In some embodiments, the polysilicon is later replaced with a metal, e.g., during a replacement metal gate (RMG) process used for other FinFET devices in the product. The gate electrode 130 and the portion 125B of the dielectric layer 125 thinly coating the trench 115B define a gate structure 131.FIG. 7 illustrates the high voltage transistor device 100 after one or more implantation processes have been performed to form wells 132 in the substrate 110, source / drain regions 135 in the fins 105, and a substrate contact 140 in the substrate 110. In an example, the substrate 110 may be doped with a P-type dopant and the high voltage transistor device 100 is an N-type device. The implantation process introduces N-type (N-) dopants into the substrate 105 to define the wells 132 and into the fins 105 (N+) to define the source / drain regions 135. A separate masked implantation process may be performed to introduce P-type dopants (P+) into the substrate 110 to define the substrate contact 140. In some embodiments, substrate contacts 140 are formed on both sides of the diffusion cracks 125A.In another example, the substrate 110 may be doped with a P-type dopant and the high voltage transistor device 100 is a P-type device. The implantation process introduces P-type (P-) dopants into the substrate 105 to define the wells 132 and into the fins 105 (P+) to define the source / drain regions 135. A separate masked implantation process may be performed to introduce N-type dopants (N+) into the substrate 110 to define the substrate contact 140 and to define an N-type triple well 143 (shown in phantom in FIG. 7, but not otherwise shown).FIG. 8 illustrates the high voltage transistor device 100 after an epitaxial growth process is performed to form epitaxial regions 145 (e.g., N-doped) on end portions of the fins 105 in the source / drain regions 135. In some embodiments, the epitaxial regions 145 may be grown until they coalesce above the fins. The epitaxial regions 145 represent a contact location to which a subsequent contact may be formed. In some embodiments, an epitaxial region 147 is also grown on the gate electrode 130.FIG. 9 illustrates the high voltage transistor device 100 after multiple processes have been performed to form, embedded in a dielectric layer 165, a substrate contact 150, source / drain contacts 155, and a gate contact 160. The substrate contact 150 extends through the dielectric layer 115 to contact the substrate contact 140. The source / drain contacts 155 contact the epitaxial regions 145 and a gate contact 160 contacts the gate electrode 130. The dielectric layer 165 was formed over the dielectric layer 115 and the epitaxial regions 145. A masked etching process was performed to define contact openings and one or more deposition processes were performed to form conductive material in the contact openings to form the contacts 150, 155, 160. In some embodiments, the contacts 150, 155, 160 are formed of silicide material. In some embodiments, the contacts 150, 155, 160 are formed of metal. In some embodiments, the contacts 150, 155, 160 include multiple layers, such as a barrier layer, a seed layer, and a conductive fill layer. In some embodiments, the conductive fill layer may be formed of cobalt, copper, tungsten, aluminum, another metal or silicide of any of the listed metals or another metal.FIG. 10 is a simplified top view of the high voltage transistor device 100 showing the orientation of the fins 105 relative to the gate electrode 130. In the embodiment of FIG. 10, the fins 105 and the gate structure 131 extend parallel to each other in an axial longitudinal direction 170. Trench 115B for forming gate electrode 130 was formed by removing selected fins 105 to provide a first set 175A and a second set 175B of parallel fins 105.FIGS. 11 and 12 respectively illustrate a cross-section and simplified top views of an alternative embodiment of a high voltage transistor device 100', wherein the gate structure 131 extends in an axial direction 180 perpendicular to an axial direction 185 in which the fins 105 extend. Trench 115B for forming gate electrode 130 was formed by slicing fins 105 along the axial length of fins 105 to provide a first set 190A and a second set 190B of axially aligned fins 105. The processes illustrated in FIGS. 1-10 may be used to form the high voltage transistor device 100' illustrated in FIGS. 11 and 12. In the embodiment of FIGS. 11 and 12, the substrate contacts 140 are formed on the sides of the gate electrode 130.The processes for forming the high voltage transistor device 100, 100' may be integrated with those of other FinFET devices (e.g., low voltage devices). For example, the etching process of FIG. 4 may be combined with the etching process to form diffusion breaks in the FinFET devices. The formation of the gate electrode 130 may also be integrated into the gate processing of the FinFET device. The channel length of the high voltage transistor device 100, 100' may be controlled based on the width of the trench 115B. The operating voltage of the high voltage transistor device 100, 100' may depend on the thickness of the portion 125B of the dielectric layer 125 thinly coating the trench 115B. For example, a thickness of about 200 angstroms supports an operating voltage of about 10V and a thickness of about 1000 angstroms supports an operating voltage of about 50V.

Claims

A transistor comprising: a first set of fins (175A, 190A) defined over a substrate (110); a second set of fins (175B, 190B) defined over the substrate (110); a gate structure (131) embedded in the substrate (110) between the first set of fins (175A, 190A) and the second set of fins (175B, 190B), wherein the first set of fins (175A, 190A) and the second set of fins (175B, 190B) are doped with a first dopant type and the substrate (110) is doped with a second dopant type different than the first dopant type; a first well disposed in the substrate (110) under the first set of fins (175A, 190A); and a second well disposed in the substrate (110) under the second set of fins (175B, 190B), wherein the first well and the second well are doped with the first dopant type.The transistor of claim 1, further comprising: a substrate contact (140) defined in the substrate (110); and an isolation structure disposed in the substrate (110) between the substrate contact (140) and the first well.The transistor of claim 1, further comprising a third well disposed in the substrate (110) below the gate structure (131), the third well being doped with the second dopant type.The transistor of claim 1, further comprising a substrate contact (140) defined in the substrate (110) either adjacent to the gate structure (131) or adjacent to the first set of fins (175A, 190A).The transistor of claim 1, wherein the gate structure (131) comprises: a dielectric layer (125B) coating a trench (115B) defined in the substrate (110); and a gate electrode (130) disposed over the dielectric layer (125B) in the trench (115B).The transistor of claim 1, further comprising: a first epitaxial region disposed on the first set of fins (175A, 190A); and a second epitaxial region disposed on the second set of fins (175B, 190B).The transistor of claim 1, wherein the first set of fins (175A) and the second set of fins (175B) extend in a first axial direction and the gate structure (131) extends in a second axial direction parallel to the first axial direction.The transistor of claim 1, wherein the first set of fins (190A) and the second set of fins (190B) are axially aligned and extend in a first axial direction and the gate structure (131) extends in a second axial direction perpendicular to the first axial direction.A method comprising: forming a first set of fins (175A, 190A) doped with a first dopant type over a substrate (110); forming a second set of fins (175B, 190B) doped with the first dopant type over the substrate (110); forming a first trench (115B) in the substrate (110) between the first set of fins (175A, 190A) and the second set of fins (175B, 190B); forming a gate structure (131) in the first trench (115B), wherein the substrate (110) is doped with a second dopant type different from the first dopant type; forming a first well doped with the first dopant type in the substrate (110) under the first set of fins (175A, 190A); and forming a second well doped with the first dopant type in the substrate (110) under the second set of fins (175B, 190B).The method of claim 9, further comprising: forming a second trench (115A) in the substrate (110); forming an isolation structure in the second trench (115A); and forming a substrate contact (140) in the substrate (110), wherein the substrate contact (140) is doped with the second dopant type and the isolation structure is disposed between the substrate contact (140) and the first well.The method of claim 9, further comprising forming a third well in the substrate (110) below the gate structure (131), wherein the third well is doped with the second dopant type.The method of claim 9, further comprising forming a substrate contact (140) in the substrate (110) adjacent to the gate structure (131) or the first set of fins (175A, 190A).The method of claim 9, wherein forming the gate structure (131) comprises: forming a dielectric layer (125B) in the first trench (115B); and forming a gate electrode (130) disposed over the dielectric layer (125B) in the first trench (115B).The method of claim 9, further comprising: forming a first epitaxial region on the first set of fins (175A, 190A); and forming a second epitaxial region on the second set of fins (175B, 190B).The method of claim 9, wherein forming the first set of fins (175A) and forming the second set of fins (175B) comprises: forming a plurality of fins (105) comprising the first set of fins (175A) and the second set of fins (175B); and removing a subset of the plurality of fins (105) between the first set of fins (175A) and the second set of fins (175B), wherein the first set of fins (175A) and the second set of fins (175B) extend in a first axial direction and the gate structure (131) extends in a second axial direction parallel to the first axial direction.The method of claim 9, wherein forming the first set of fins (190A) and forming the second set of fins (190B) comprises: forming a plurality of fins (105); and removing a portion of the plurality of fins (105) along an axial length of the plurality of fins (105) to define the first set of fins (190A) that is axially aligned with the second set of fins (190B) that extend in a first axial direction, wherein the gate structure (131) extends in a second axial direction perpendicular to the first axial direction.The method of claim 9, further comprising: forming a plurality of fins (105) over the substrate (110); removing a portion of the plurality of fins (105) and a portion of the substrate (110), thereby defining the first trench (115B) in the substrate (110) and dividing the plurality of fins (105) into the first set of fins (175A, 190A) and the second set of fins (175B, 190B); doping the first (175A, 190A) and second (175B, 190B) sets of fins with the first dopant type; forming a second trench (115A) in the substrate (110); forming a dielectric layer (125A, 125B) in the first trench (115B) and the second trench (115A); forming a gate electrode (130) in the first trench (115B) over the dielectric layer (125B); and forming a substrate contact (140) doped with the second dopant type in the substrate (110) adjacent to the second trench (115A).

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