Display device, method for manufacturing the display device, and multi-display device

Abstract

The present invention relates to a display device, a manufacturing method of the display device and a multi-display device. The display device comprises: a first substrate; a second substrate arranged on the first substrate; an image display layer arranged between the first substrate and the second substrate; a gate driving unit arranged on a first side surface of the first substrate; a data driving unit arranged on a second side surface of the first substrate; and a plurality of first conductive layers arranged in a first recessed portion defined on the first side surface, wherein the gate driving unit is connected to the first conductive layer.

Description

Technical Field

[0001] The present invention relates to a display device, a method for manufacturing the display device, and a multi-display device, and more particularly, to a display device capable of achieving a narrow frame, a method for manufacturing the display device, and a multi-display device. Background Art

[0002] Generally, a display device includes: a display panel including a plurality of pixels for displaying an image; a gate driving unit providing a gate signal to the pixels; and a data driving unit providing a data voltage to the pixels. The gate driving unit and the data driving unit are connected to the display panel.

[0003] The gate driving part generates a gate signal and provides the generated gate signal to the pixel. The data driving part generates a data voltage and provides the generated data voltage to the pixel. The pixel receives the data voltage in response to the gate signal to display an image.

[0004] The region where the gate driving part and the data driving part are arranged is defined as a frame region. Recently, it is required to develop a technology for reducing the frame region. Summary of the invention

[0005] An object of the present invention is to provide a display device capable of achieving a narrow frame, a method for manufacturing the display device, and a multi-display device.

[0006] A display device according to an embodiment of the present invention may include: a first substrate; a second substrate arranged on the first substrate; an image display layer arranged between the first substrate and the second substrate; a gate driving unit arranged on a first side of the first substrate; a data driving unit arranged on a second side of the first substrate; and a plurality of first conductive layers arranged in a first recessed portion defined on the first side, wherein the gate driving unit is connected to the first conductive layer.

[0007] A method for manufacturing a display device according to an embodiment of the present invention may include the following steps: defining a first recessed portion on a first side surface of a first substrate; defining a second recessed portion on a second side surface of the first substrate; providing a plurality of first conductive layers in the first recessed portion; providing a plurality of second conductive layers in the second recessed portion; connecting a gate driving portion to the first conductive layer; and connecting a data driving portion to the second conductive layer.

[0008] A multi-display device according to an embodiment of the present invention may include: a plurality of display panels connected to each other, the display panels respectively including: a first substrate; a second substrate arranged on the first substrate; an image display layer arranged between the first substrate and the second substrate; a gate driving unit arranged on the first side of the first substrate; a data driving unit arranged on the second side of the first substrate; a plurality of first conductive layers arranged in a first recessed portion defined on the first side; and a plurality of second conductive layers arranged in a second recessed portion defined on the first side. The gate driving unit may be connected to the first conductive layer, the data driving unit may be connected to the second conductive layer, and the first side of the kth display panel and the first side of the k+1th display panel in the display panels face each other.

[0009] According to an embodiment of the present invention, the gate driving unit and the data driving unit may be connected to a conductive layer arranged in a recessed portion defined in the first substrate in order to be connected to the side of the display panel. Since the gate driving unit and the data driving unit are connected to the side of the first substrate, when viewed from a plane, the area for arranging the gate driving unit and the data driving unit can be minimized, thereby achieving a narrow frame of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0011] Figure 2 yes Figure 1 A perspective view of the display device shown.

[0012] Figure 3 It is shown Figure 1 A diagram showing the composition of any pixel shown.

[0013] Figure 4 It is a schematic diagram Figure 3 A cross-section of a pixel is shown.

[0014] Figure 5 It is a graphic Figure 2 A diagram showing a portion of a first side surface where a first gate driving unit is arranged.

[0015] Figure 6 yes Figure 5 A cross-sectional view taken along line II' is shown.

[0016] Figure 7 Observation from a third party Figure 5 A diagram showing a connection state between the first pad and the first conductive layer.

[0017] Figure 8 It is a graphic Figure 2A diagram showing a portion of the second side surface where a data driving unit is arranged.

[0018] Fig. 9 yes Figure 8 A cross-sectional view taken along line II-II' is shown.

[0019] Fig.10 Observation from a third party Figure 8 A diagram showing a connection state between the second pad and the second conductive layer.

[0020] Figures 11 to 16 FIG. 1 is a diagram for explaining a method for manufacturing a display device according to an embodiment of the present invention.

[0021] Figures 17 to 23 FIG. 1 is a diagram for explaining a method for manufacturing a display device according to another embodiment of the present invention.

[0022] Fig.24 is a diagram illustrating a multi-display device according to an embodiment of the present invention.

[0023] Fig.25 yes Fig.24 A cross-sectional view along line III-III' is shown.

[0024] Figure symbols:

[0025] DD: Display Device MDD: Multi-Display Device

[0026] DP: Display panel SUB1: First substrate

[0027] SUB2: Second substrate GDR1: First gate drive unit

[0028] GDR2: Second gate driver DDR: Data driver

[0029] FPC1: first flexible circuit board IC1: first driver chip

[0030] FPC2: Second flexible circuit board IC2: Second driver chip

[0031] PD1: First pad PD2: Second pad

[0032] SF1: First side SF2: Second side

[0033] BS1: first base substrate BS2: second base substrate

[0034] RES1: first recessed portion RES2: second recessed portion

[0035] CTL1: first conductive layer CTL2: second conductive layer

[0036] GL: Gate line DL: Data line

[0037] CET: Connecting Electrodes DETAILED DESCRIPTION

[0038] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being "on" another component, "connected to" another component, or "combined with" another component, it means that it can be directly arranged on another component or directly connected / combined with another component, or a third component may be arranged between them.

[0039] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, ratio, and size of the components are exaggerated for the purpose of effectively explaining the technical contents.

[0040] “And / or” includes all combinations of more than one that can be defined for the related constituents.

[0041] The terms first, second, etc. may be used to describe a variety of constituent elements, but the constituent elements should not be limited by the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Singular expressions include plural expressions as long as they do not clearly indicate different meanings in the context.

[0042] Furthermore, terms such as “below”, “lower side”, “above”, and “upper side” are used to describe the relationship between the components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and are explicitly defined herein unless they are interpreted as ideal or excessively formal meanings.

[0044] The terms "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0047] Reference Figure 1 The display device DD may include a display panel DP, gate driving parts GDR1 and GDR2, a data driving part DDR, and a printed circuit board PCB. The display panel DP may have a rectangular shape including a long side extending along a first direction DR1 and a short side extending along a second direction DR2 crossing the first direction DR1. However, the shape of the display panel DP may not be limited thereto.

[0048] Hereinafter, a direction substantially perpendicularly crossing a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in this specification, the meaning of "when viewed from a plane" may refer to a state viewed from the third direction DR3.

[0049] The display panel DP may be a liquid crystal display panel including a liquid crystal layer. However, it is not limited thereto, and the display panel DP may be an electrophoretic display panel including an electrophoretic layer or an electrowetting display panel including an electrowetting layer. The liquid crystal layer, the electrophoretic layer, and the electrowetting layer may be defined as an image display layer.

[0050] The display panel DP may include a plurality of pixels PX, a plurality of gate lines GL1 ˜GLm and a plurality of data lines DL1 ˜DLn. m and n are positive integers. The gate lines GL1 ˜GLm and the data lines DL1 ˜DLn may extend in a manner of being insulated from each other and crossing each other.

[0051] The pixels PX may be connected to the gate lines GL1 to GLm and the data lines DL1 to DLn. Each pixel PX may display one of the primary colors. The primary colors may include red, green, blue, and white. However, it is not limited thereto, and the primary colors may also include various colors such as yellow, cyan, and magenta.

[0052] The gate lines GL1-GLm may extend along the first direction DR1, and the data lines DL1-DLn may extend along the second direction DR2. The gate driving units GDR1 and GDR2 may be connected to the display panel DP and further connected to the gate lines GL1-GLm. The data driving unit DDR may be connected to the display panel DP and further connected to the data lines DL1-DLn.

[0053] In order to illustrate the plan view of the gate driving units GDR1, GDR2 and the data driving unit DDR, for convenience, the gate driving units GDR1, GDR2 and the data driving unit DDR are shown in a state separated from the display panel DP. The structure of connecting the gate driving units GDR1, GDR2 and the data driving unit DDR to the display panel DP will be described in detail below.

[0054] The gate driving part GDR1 and GDR2 may include first and second gate driving parts GDR1 and GDR2 adjacent to opposite sides of the display panel DP in the first direction DR1 , respectively. The first and second gate driving parts GDR1 and GDR2 may be adjacent to short sides of the display panel DP, respectively.

[0055] The first gate driving unit GDR1 may be connected to odd-numbered gate lines among the gate lines GL1 ˜GLm, and the second gate driving unit GDR2 may be connected to even-numbered gate lines among the gate lines GL1 ˜GLm.

[0056] Although two gate driving units GDR1 and GDR2 are exemplarily shown in the figure, the present invention is not limited thereto, and one gate driving unit may be arranged at one side of the display panel DP and connected to the gate lines GL1 ˜GLm.

[0057] The first gate driving unit GDR1 and the second gate driving unit GDR2 may include a plurality of first flexible circuit boards FPC1 and a plurality of first driving chips IC1 respectively mounted on the first flexible circuit boards FPC1. The first driving chips IC1 may be connected to the display panel DP through the first flexible circuit boards FPC1.

[0058] The first driving chip IC1 of the first gate driving unit GDR1 may be connected to the odd-numbered gate lines through the first flexible circuit board FPC1 of the first gate driving unit GDR1. The first driving chip IC1 of the second gate driving unit GDR2 may be connected to the even-numbered gate lines through the first flexible circuit board FPC1 of the second gate driving unit GDR2.

[0059] exist Figure 1 2 exemplarily illustrates four first driving chips IC1 and four first flexible circuit boards FPC1 of each of the first gate driving part GDR1 and the second gate driving part GDR2 . However, the number of the first driving chips IC1 and the first flexible circuit boards FPC1 is not limited thereto according to the size of the display panel DP.

[0060] The data driving part DDR may be adjacent to one of two sides of the display panel DP that are opposite to each other in the second direction DR2. The data driving part DDR may be adjacent to any one of the long sides of the display panel DP.

[0061] The data driving unit DDR may include a plurality of second flexible circuit boards FPC2 and a plurality of second driving chips IC2 respectively mounted on the second flexible circuit boards FPC2. The second driving chips IC2 may be connected to the display panel DP through the second flexible circuit boards FPC2.

[0062] exist Figure 1 FIG. 5 exemplarily illustrates five second driving chips IC2 and five second flexible circuit boards FPC2 . However, according to the size of the display panel DP, the number of the second driving chips IC2 and the second flexible circuit boards FPC2 is not limited thereto.

[0063] The second flexible circuit board FPC2 may be connected to the printed circuit board PCB. The second driving chip IC2 may be connected to the printed circuit board PCB through the second flexible circuit board FPC2.

[0064] A timing controller (not shown) may be arranged on the printed circuit board PCB. The timing controller may be mounted on the printed circuit board PCB in the form of an integrated circuit chip. The timing controller may be connected to the first gate driving unit GDR1, the second gate driving unit GDR2 and the data driving unit DDR. The timing controller may output a gate control signal, a data control signal and image data.

[0065] The first gate driving part GDR1 and the second gate driving part GDR2 may receive a gate control signal from the timing controller and generate a plurality of gate signals in response to the gate control signal. The gate signals may be output sequentially. The gate signals may be provided to the pixels PX through the gate lines GL1 ˜GLm.

[0066] The data driving unit DDR may receive image data and a data control signal from the timing controller. The data driving unit DDR may generate and output a data voltage corresponding to the image data in an analog form in response to the data control signal. The data voltage may be provided to the pixel PX through the data lines DL1 ˜DLn.

[0067] The pixels PX may receive data voltages through the data lines DL1 ˜DLn in response to gate signals received through the gate lines GL1 ˜GLm. The pixels PX may display images by displaying color gradations corresponding to the data voltages.

[0068] Figure 2 yes Figure 1 A perspective view of the display device shown.

[0069] Reference Figure 2, the display panel DP may include a first substrate SUB1, a second substrate SUB2, and an encapsulation layer SL disposed between the first substrate SUB1 and the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may have a rectangular shape including a long side extending in a first direction DR1 and a short side extending in a second direction DR2. The encapsulation layer SL may extend along an edge of each of the first substrate SUB1 and the second substrate SUB2 to bond the first substrate SUB1 and the second substrate SUB2.

[0070] The display device DD may include a backlight unit BLU disposed under the display panel DP. The backlight unit BLU may generate and provide light to the display panel DP. The pixels PX of the display panel DP may display an image using the light received from the backlight unit BLU.

[0071] The first gate driver GDR1 and the second gate driver GDR2 may be arranged on the side of the display panel DP. For example, the first gate driver GDR1 and the second gate driver GDR2 may be arranged on two side surfaces of the first substrate SUB1 that are opposite to each other along the first direction DR1. Although the first gate driver GDR1 arranged on one side of the first substrate SUB1 is shown in the perspective view, the second gate driver GDR2 may also be arranged on the other side of the first substrate SUB1.

[0072] Hereinafter, two side surfaces of the first substrate SUB1 where the first gate driving part GDR1 and the second gate driving part GDR2 are arranged are defined as first side surfaces SF1. The first side surfaces SF1 may be defined as short sides of the first substrate SUB1. The first side surfaces SF1 may extend along the second direction DR2.

[0073] The data driving unit DDR may be arranged on the other side of the display panel DP. For example, the data driving unit DDR may be arranged on one of the two side surfaces of the first substrate SUB1 that are opposite to each other along the second direction DR2. Hereinafter, the side surface of the first substrate SUB1 on which the data driving unit DDR is arranged is defined as the second side surface SF2. The second side surface SF2 may be defined by any one of the long sides of the first substrate SUB1. The second side surface SF2 may extend along the first direction DR1.

[0074] The first gate driving unit GDR1 and the second gate driving unit GDR2 may be connected to the first side surface SF1. The data driving unit DDR may be connected to the second side surface SF2. Such a structure will be described in detail below.

[0075] Figure 3 It is shown Figure 1 A diagram showing the composition of any pixel shown.

[0076] For ease of explanation, Figure 3 The figure shows the structure of the pixel PXij connected to the gate line GLi and the data line DLj, and other pixels PX of the display panel DP. Figure 3 The pixels PXij shown are identical.

[0077] Reference Figure 3 , the first substrate SUB1 may include a gate line GLi, a data line DLj, and a pixel PXij connected to the gate line GLi and the data line DLj. Specifically, the pixel PXij may include a transistor TR connected to the gate line GLi and the data line DLj, a liquid crystal capacitor Clc connected to the transistor TR, and a storage capacitor Cst connected in parallel with the liquid crystal capacitor Clc. The storage capacitor Cst may be omitted. i and j are positive integers.

[0078] The transistor TR may include a gate electrode (not shown) connected to the gate line GLi, a source electrode (not shown) connected to the data line DLj, and a drain electrode (not shown) connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

[0079] The liquid crystal capacitor Clc may include a pixel electrode PE disposed on the first substrate SUB1 and connected to the transistor TR, a common electrode CE disposed on the second substrate SUB2, and a liquid crystal layer LC disposed between the pixel electrode PE and the common electrode CE. The liquid crystal layer LC may function as a dielectric.

[0080] exist Figure 3 In the embodiment, the pixel electrode PE is a non-slit structure, but is not limited thereto, and the pixel electrode PE may have a slit structure including a cross-shaped trunk and a plurality of branches radially extending from the trunk. The common electrode CE may be disposed on the entire second substrate SUB2.

[0081] The storage capacitor Cst may include a pixel electrode PE, a storage electrode (not shown) branched from a storage line (not shown), and an insulating film arranged between the pixel electrode PE and the storage electrode. The storage line may be arranged on the first substrate SUB1 and formed at the same layer as the gate lines GL1 to GLm. The storage electrode may partially overlap the pixel electrode PE.

[0082] The pixel PXij may also include a color filter CF showing one of red, green and blue. The color filter CF will be described below. Figure 4 Medium picture.

[0083] The transistor TR may be turned on in response to a gate signal received through the gate line GLi. The data voltage received through the data line DLj may be provided to the pixel electrode PE of the liquid crystal capacitor Clc through the turned-on transistor TR. The common electrode CE may be applied with a common voltage.

[0084] Due to the difference in voltage levels between the data voltage and the common voltage, an electric field may be formed between the pixel electrode PE and the common electrode CE. Liquid crystal molecules of the liquid crystal layer LC may be driven by the electric field formed between the pixel electrode PE and the common electrode CE. Images may be displayed by adjusting light transmittance through the liquid crystal molecules driven by the electric field.

[0085] The storage line may be applied with a storage voltage having a constant voltage level. However, it is not limited thereto, and the storage line may be applied with a common voltage. The storage capacitor Cst may play a role in supplementing the charge amount of the liquid crystal capacitor Clc.

[0086] Figure 4 It is a schematic diagram Figure 3 A cross-section of a pixel is shown.

[0087] For ease of explanation, Figure 4 The structure of the storage capacitor is omitted.

[0088] Reference Figure 4 , the first substrate SUB1 may include a first base substrate BS1, a transistor TR, a color filter CF, and a pixel electrode PE. The area on the plane of the pixel PXij may include a pixel area PA and a non-pixel area NPA around the pixel area PA. The transistor TR may be arranged in the non-pixel area NPA, and the pixel electrode PE may overlap with the pixel area PA.

[0089] The first base substrate BS1 may be a transparent or opaque insulating substrate. For example, the first base substrate BS1 may include a silicon substrate, a glass substrate, or a plastic substrate.

[0090] A gate electrode GE of the transistor TR may be disposed on the first base substrate BS1. The gate electrode GE may be substantially formed by branching from the gate line GLi. A first insulating film INS1 may be disposed on the first base substrate BS1 in a manner covering the gate electrode GE. The first insulating film INS1 may be defined as a gate insulating film. The first insulating film INS1 may be an inorganic insulating film including an inorganic substance.

[0091] A semiconductor layer SM of the transistor TR may be disposed on the first insulating film INS1 covering the gate electrode GE. Although not shown, the semiconductor layer SM may include an active layer and an ohmic contact layer.

[0092] The source electrode SE and the drain electrode DE of the transistor TR may be disposed on the semiconductor layer SM and the first insulating film INS1 to be spaced apart from each other. The semiconductor layer SM may form a conductive channel between the source electrode SE and the drain electrode DE.

[0093] A color filter CF may be disposed on the first insulating film INS1 to cover the source electrode SE and the drain electrode DE. The source electrode SE may be substantially formed by branching from the data line DLj.

[0094] Although not shown, a passivation layer may be arranged on the first insulating film INS1 in a manner covering the source electrode SE and the drain electrode DE. The passivation layer may be an inorganic insulating film including an inorganic substance. A color filter CF may be arranged on the passivation layer. A contact hole CH exposing a predetermined area of ​​the drain electrode DE may be defined in the color filter CF.

[0095] In the pixel area PA, the pixel electrode PE may be disposed on the color filter CF. The pixel electrode PE may extend toward the non-pixel area NPA and be electrically connected to the drain electrode DE through the contact hole CH.

[0096] A liquid crystal layer LC may be disposed between the first substrate SUB1 and the second substrate SUB2. The second substrate SUB2 may include a second base substrate BS2, a black matrix BM, a second insulating film INS2, and a common electrode CE. The second base substrate BS2 may include the same material as the first base substrate BS1.

[0097] In the non-pixel area NPA, the black matrix BM may be disposed under the second base substrate BS2. A second insulating film INS2 may be disposed under the second base substrate BS2 to cover the black matrix BM. A common electrode CE may be disposed under the second insulating film INS2.

[0098] The liquid crystal capacitor Clc may include a pixel electrode PE, a common electrode CE facing the pixel electrode PE, and a liquid crystal layer LC between the pixel electrode PE and the common electrode CE.

[0099] Figure 5 It is a graphic Figure 2 A diagram showing a portion of a first side surface where a first gate driving unit is arranged.

[0100] Reference Figure 5 The gate line GL may extend along the first direction DR1 to the first side surface SF1 of the first substrate SUB1. Figure 5 The gate lines GL shown may be a part of the gate lines GL1 ˜GLm.

[0101] A plurality of first recesses RES1 may be defined at the first side SF1 of the first substrate SUB1. A plurality of first conductive layers CTL1 may be disposed at the first recess RES1. The first side SF1 of the first substrate SUB1 may be defined as the first side SF1 of the first base substrate BS1. Therefore, the first recess RES1 may be defined at the first side SF1 of the first base substrate BS1.

[0102] The first recessed portion RES1 may be arranged along the second direction DR2. The first recessed portion RES1 may be defined below the gate line GL. The first conductive layer CTL1 disposed in the first recessed portion RES1 may contact the gate line GL. Therefore, one side of the gate line GL may be electrically connected to the first conductive layer CTL1. With the second direction DR2 as a reference, the width of each first conductive layer CTL1 may be greater than the width of each gate line GL.

[0103] The first flexible circuit board FPC1 of the first gate driving part GDR1 may be arranged to face the first side surface SF1. The first gate driving part GDR1 may include a plurality of first pads PD1 arranged on one side OSF1 of the first flexible circuit board FPC1 facing the first side surface SF1. The first pads PD1 may include a conductive substance.

[0104] The first pad PD1 may be arranged along the second direction DR2. When viewed in the first direction DR1, the first pad PD1 may overlap the first conductive layer CTL1 and the gate line GL. The first driving chip IC1 may be disposed on the opposite side of one side OSF1 of the first flexible circuit board FPC1.

[0105] Figure 6 yes Figure 5 A cross-sectional view taken along line II' is shown. Figure 7 Observation from a third party Figure 5 A diagram showing a connection state between the first pad and the first conductive layer.

[0106] For ease of explanation, Figure 7 4 shows the gate line GL and the first conductive layer CTL1 arranged on the first base substrate BS1.

[0107] Reference Figure 6 The encapsulation layer SL may be disposed between the edge of the first substrate SUB1 and the edge of the second substrate SUB2 to bond the first substrate SUB1 and the second substrate SUB2. The liquid crystal layer LC may be accommodated between the first substrate SUB1 and the second substrate SUB2 through the encapsulation layer SL.

[0108] The first recess RES1 may extend in the first direction DR1. The lower portion of the gate line GL may be exposed through the first recess RES1. The first conductive layer CTL1 may be disposed in the first recess RES1 so that the first conductive layer CTL1 contacts the lower portion of the gate line GL. Therefore, the first conductive layer CTL1 may be electrically connected to the gate line GL.

[0109] The first pad PD1 may be connected to the first driving chip IC1. Although not shown, the wiring connected to the first driving chip IC1 may be connected to the first pad PD1 through a through hole defined in the first flexible circuit board FPC1.

[0110] The first pad PD1 may be electrically connected to the first conductive layer CTL1 and the gate line GL. A first anisotropic conductive film ACF1 may be disposed between the first pad PD1 and the first conductive layer CTL1 and between the first pad PD1 and the gate line GL.

[0111] The first pad PD1 and the first conductive layer CTL1 may be electrically connected to each other through the first anisotropic conductive film ACF1, and the first pad PD1 and the gate line GL may be electrically connected to each other. In addition, the first pad PD1 may be electrically connected to the gate line GL through the first conductive layer CTL1.

[0112] Reference Figure 7 , a first anisotropic conductive film ACF1 may be disposed between the first pad PD1 and the first conductive layer CTL1 and between the first pad PD1 and the gate line GL, and the first flexible circuit board FPC1 is pressed toward the first side surface SF1.

[0113] Due to the pressurization operation, the conductive balls BO1 of the first anisotropic conductive film ACF1 disposed between the first pad PD1 and the first conductive layer CTL1 may contact each other to electrically connect the first pad PD1 and the first conductive layer CTL1 to each other. Also, the conductive balls BO1 disposed between the first pad PD1 and the gate line GL may contact each other to electrically connect the first pad PD1 and the gate line GL to each other.

[0114] Reference Figure 6 and Figure 7 The first flexible circuit board FPC1 is connected to the first conductive layer CTL1 through the first pad PD1, so that the first gate driving unit GDR1 can be connected to the first conductive layer CTL1. Although not shown in the figure, in the same way, the second gate driving unit GDR2 can also be connected to the first conductive layer arranged in the first recessed portion of the other first side surface SF1.

[0115] The first flexible circuit board FPC1 may be arranged in parallel with the third direction DR3. That is, the first gate driving part GDR1 is connected to the first side surface SF1, so that the first flexible circuit board FPC1 may extend along the third direction DR3 perpendicular to the plane of the first substrate SUB1. The first flexible circuit board FPC1 may substantially have a plane defined by the second direction DR2 and the third direction DR3.

[0116] If the first flexible circuit board FPC1 is arranged parallel to the plane of the first substrate SUB1 and connected to the upper surface of the first substrate SUB1 adjacent to one side of the first substrate SUB1, the area for arranging the first gate driver GDR1 and the second gate driver GDR2 may be increased. However, in the embodiment of the present invention, the first gate driver GDR1 and the second gate driver GDR2 are connected to the first side surface SF1 of the first substrate SUB1, so when viewed from a plane, the area for arranging the first gate driver GDR1 and the second gate driver GDR2 can be minimized.

[0117] Figure 8 It is a graphic Figure 2 A diagram showing a portion of the second side surface where a data driving unit is arranged.

[0118] Reference Figure 8 The data line DL may extend along the second direction DR2 to the second side surface SF2 of the first substrate SUB1. Figure 8 The data lines DL shown may be a part of the data lines DL1 ˜DLn.

[0119] A plurality of second recesses RES2 may be defined at the second side SF2 of the first substrate SUB1. A plurality of second conductive layers CTL2 may be disposed at the second recess RES2. The second side SF2 of the first substrate SUB1 may be defined as the second side SF2 of the first base substrate BS1. Therefore, the second recess RES2 may be defined at the second side SF2 of the first base substrate BS1.

[0120] The second recessed portions RES2 may be arranged along the first direction DR1. The second recessed portions RES2 may be defined below the data lines DL. With reference to the first direction DR1, the width of each second conductive layer CTL2 may be greater than the width of each data line DL.

[0121] The second conductive layer CTL2 may be electrically connected to the data line DL. For example, a plurality of connection electrodes CET may be arranged between the second conductive layer CTL2 and the data line DL. The connection electrodes CET may be arranged at the same layer as the gate line GL. The second conductive layer CTL2 may be electrically connected to the data line DL through the connection electrodes CET, and such a configuration will be described in detail below.

[0122] Based on the first direction DR1, the width of each connection electrode CET may be greater than the width of each data line DL. Based on the first direction DR1, the width of each connection electrode CET may be equal to the width of each second conductive layer CTL2. However, it is not limited thereto, and the width of each connection electrode CET may be greater than or less than the width of each second conductive layer CTL2.

[0123] The second flexible circuit board FPC2 of the data driving part DDR may be arranged to face the second side surface SF2. The data driving part DDR may include a plurality of second pads PD2 arranged on one side OSF2 of the second flexible circuit board FPC2 facing the second side surface SF2. The second pads PD2 may include a conductive substance.

[0124] The second pad PD2 may be arranged along the first direction DR1. When viewed in the second direction DR2, the second pad PD2 may overlap the second conductive layer CTL2 and the connection electrode CET. The second driving chip IC2 may be disposed on the opposite side of one side OSF2 of the second flexible circuit board FPC2.

[0125] Fig. 9 yes Figure 8 A cross-sectional view taken along line II-II' is shown. Fig.10 Observing in a third direction Figure 8 A diagram showing a connection state between the second pad and the second conductive layer.

[0126] For ease of explanation, Fig.10 FIG. 4 shows the data lines DL and the connection electrodes CET arranged on the first base substrate BS1 .

[0127] Reference Fig. 9 The second recess RES2 may extend along the second direction DR2. The lower portion of the connection electrode CET may be exposed through the second recess RES2. The second conductive layer CTL2 may be disposed in the second recess RES2, and the connection electrode CET may be disposed on the second conductive layer CTL2.

[0128] The second conductive layer CTL2 may contact the lower portion of the connection electrode CET. Therefore, the second conductive layer CTL2 may be electrically connected to the connection electrode CET. When viewed in the third direction DR3, the connection electrode CET may overlap the second conductive layer CTL2.

[0129] A first insulating film INS1 may be disposed on the first base substrate BS1 in a manner of covering the connection electrode CET. A data line DL may be disposed on the first insulating film INS1. A first contact hole CH1 for exposing a predetermined region of the connection electrode CET may be defined on the first insulating film INS1. The data line DL may be electrically connected to the connection electrode CET through the first contact hole CH1. Therefore, the data line DL may be electrically connected to the second conductive layer CTL2 through the connection electrode CET.

[0130] The second pad PD2 may be connected to the second driving chip IC2. Although not shown, the wiring connected to the second driving chip IC2 may be connected to the second pad PD2 through a through hole defined in the second flexible circuit board FPC2.

[0131] The second pad PD2 may be electrically connected to the second conductive layer CTL2 and the connection electrode CET. A second anisotropic conductive film ACF2 may be disposed between the second pad PD2 and the second conductive layer CTL2 and between the second pad PD2 and the connection electrode CET.

[0132] The second pad PD2 and the second conductive layer CTL2 may be electrically connected to each other through the second anisotropic conductive film ACF2, and the second pad PD2 and the connection electrode CET may be electrically connected to each other. Also, the second pad PD2 may be electrically connected to the data line DL through the second conductive layer CTL2 and the connection electrode CET.

[0133] Reference Fig.10 A second anisotropic conductive film ACF2 may be disposed between the second pad PD2 and the second conductive layer CTL2 and between the second pad PD2 and the connection electrode CET, and the second flexible circuit board FPC2 is pressed toward the second side surface SF2.

[0134] Through the pressurizing operation, the second pad PD2 and the second conductive layer CTL2 may be electrically connected to each other through the conductive balls BO2 contacting each other, and the second pad PD2 and the connection electrode CET may be electrically connected to each other.

[0135] Reference Fig. 9 and Fig.10 Similar to the first gate driving part GDR1 and the second gate driving part GDR2, the second flexible circuit board FPC2 is connected to the second conductive layer CTL2 through the second pad PD2, so that the data driving part DDR can be connected to the second conductive layer CTL2.

[0136] The second flexible circuit board FPC2 may be arranged in parallel with the third direction DR3. That is, the data driving part DDR is connected to the second side surface SF2, so that the second flexible circuit board FPC2 may extend along the third direction DR3 perpendicular to the plane of the first substrate SUB1. The second flexible circuit board FPC2 may substantially have a plane defined by the first direction DR1 and the third direction DR3.

[0137] If the second flexible circuit board FPC2 is arranged parallel to the plane of the first substrate SUB1 and connected to the upper surface of the first substrate SUB1 adjacent to one side of the first substrate SUB1, the area for arranging the data driving part DDR may be increased. However, in the embodiment of the present invention, the data driving part DDR is connected to the second side surface SF2 of the first substrate SUB1, so when viewed from a plane, the area for arranging the data driving part DDR can be minimized.

[0138] As a result, the display device DD according to the embodiment of the present invention can minimize the area for arranging the first and second gate driving parts GDR1 and GDR2 and the data driving part DDR, thereby being able to achieve a narrow frame.

[0139] Figures 11 to 16 FIG. 1 is a diagram for explaining a method for manufacturing a display device according to an embodiment of the present invention.

[0140] For ease of explanation, Figures 11 to 16 The diagram shows Figure 5 , Figure 6 , Figure 8 and Fig. 9 Corresponding sides and cross sections.

[0141] Reference Fig.11 and Fig.12 , a first substrate SUB1 and a second substrate SUB2 bonded by a sealing layer SL may be prepared. Here, the first substrate SUB1 refers to the first substrate SUB1 without forming the first recessed portion RES1 and the second recessed portion RES2.

[0142] The laser LAR may be irradiated toward the first side surface SF1. Specifically, the laser LAR may be irradiated toward a portion of the first side surface SF1 below the gate line GL. The laser LAR may form a first recess RES1 at the first side surface SF1 of the first base substrate BS1. The first recess RES1 may expose the lower portion of the gate line GL.

[0143] Reference Fig.13 and Fig.14, the laser LAR may be irradiated toward the second side surface SF2. Specifically, the laser LAR may be irradiated toward the portion below the connection electrode CET in the second side surface SF2. The laser LAR may form a second recessed portion RES2 on the second side surface SF2 of the second base substrate BS2. The lower portion of the connection electrode CET may be exposed by the second recessed portion RES2.

[0144] Reference Fig.15 and Fig.16 A first conductive layer CTL1 may be disposed in the first recess RES1, and a second conductive layer CTL2 may be disposed in the second recess RES2. The first conductive layer CTL1 may be connected to the gate line GL, and the second conductive layer CTL2 may be connected to the data line DL through the connection electrode CET.

[0145] The first conductive layer CTL1 and the second conductive layer CTL2 may include metal. For example, the first conductive layer CTL1 and the second conductive layer CTL2 may include silver, gold or titanium. The first conductive layer CTL1 and the second conductive layer CTL2 may be disposed in the first recessed portion RES1 and the second recessed portion RES2 by inkjet or spraying.

[0146] The first gate driving unit GDR1 may be connected to the first conductive layer CTL1 through the first anisotropic conductive film ACF1. For example, the first pad PD1 may be connected to the first conductive layer CTL1 through the first anisotropic conductive film ACF1. Since the manner in which the first pad PD1 is connected to the first conductive layer CTL1 through the first anisotropic conductive film ACF1 has been described in detail above, the description is omitted. The second gate driving unit GDR2 may also be connected to the first substrate SUB1 in the same manner.

[0147] The data driving unit DDR may be connected to the second conductive layer CTL2 through the second anisotropic conductive film ACF2. For example, the second pad PD2 may be connected to the second conductive layer CTL2 through the second anisotropic conductive film ACF2. Since the manner in which the second pad PD2 is connected to the second conductive layer CTL2 through the second anisotropic conductive film ACF2 has been described in detail above, the description is omitted.

[0148] According to the manufacturing process described above, the first gate driving unit GDR1 and the second gate driving unit GDR2 may be connected to the gate line GL through the first conductive layer CTL1 , and the data driving unit DDR may be connected to the data line DL through the second conductive layer CTL2 .

[0149] Figures 17 to 23 FIG. 1 is a diagram for explaining a method for manufacturing a display device according to another embodiment of the present invention.

[0150] For ease of explanation, Figures 17 to 23The diagram shows Figure 6 and Fig. 9 The corresponding cross section. Figures 11 to 16 The manufacturing method described above is mainly based on a different manufacturing method to illustrate a manufacturing method of a display device according to another embodiment of the present invention.

[0151] Reference Fig.17 and Fig.18 The laser LAR may be irradiated toward the upper surface of the first base substrate BS1 adjacent to the first side surface SF1 of the first base substrate BS1. The laser LAR may form the first recess RES1 at the first side surface SF1.

[0152] The laser LAR may be irradiated toward the upper surface of the first base substrate BS1 adjacent to the second side SF2 of the first base substrate BS1. The second recess RES2 may be formed at the second side SF2 by the laser LAR.

[0153] Reference Fig.19 and Fig. 20 A first conductive layer CTL1 may be disposed in the first recess RES1. A gate line GL may be disposed on the first conductive layer CTL1. The gate line GL may contact the first conductive layer CTL1 and be electrically connected to the first conductive layer CTL1.

[0154] Reference Fig.21 A second conductive layer CTL2 may be disposed in the second recess RES2. A connection electrode CET may be disposed on the second conductive layer CTL2. The connection electrode CET may contact the second conductive layer CTL2 and be electrically connected to the second conductive layer CTL2.

[0155] Reference Fig. 22 and Fig.23 , a first insulating film INS1 may be disposed on the first base substrate BS1 in a manner covering the gate line GL and the connection electrode CET. A data line DL and a color filter CF may be disposed on the first insulating film INS1 to form a first substrate SUB1. Although not shown, the first substrate SUB1 may include a transistor TR and a pixel electrode PE. The data line DL may be electrically connected to the connection electrode CET through a first contact hole CH1 defined in the first insulating film INS1.

[0156] A first substrate SUB1 may be disposed, a second substrate SUB2 may be disposed on the first substrate SUB1, and the first substrate SUB1 and the second substrate SUB2 may be bonded to each other by an encapsulation layer SL.

[0157] The first pad PD1 of the first gate driving unit GDR1 may be connected to the first conductive layer CTL1 through the first anisotropic conductive film ACF1. The second gate driving unit GDR2 may also be connected to the first substrate SUB1 in the same manner as the first gate driving unit GDR1. The second pad PD2 of the data driving unit DDR may be connected to the second conductive layer CTL2 through the second anisotropic conductive film ACF2.

[0158] Fig.24 is a diagram illustrating a multi-display device according to an embodiment of the present invention. Fig.25 yes Fig.24 A cross-sectional view along line III-III' is shown.

[0159] Reference Fig.24 and Fig.25 The multi display device MDD of the present invention may include a plurality of display panels DP. Although four display panels DP arranged in two rows and two columns are exemplarily illustrated, the number of the display panels DP is not limited thereto.

[0160] Each display panel DP may be connected to a first gate driver GDR1, a second gate driver GDR2, and a data driver DDR. The first gate driver GDR1, the second gate driver GDR2, and the data driver DDR are connected to the display panel DP in the same manner as described above. Figures 1 to 10 The structure of the instructions is the same.

[0161] like Fig.25 As shown, the first side surface SF1 of the kth display panel DPk and the first side surface SF1 of the k+1th display panel DPk+1 may be arranged to face each other. Accordingly, the second gate driving unit GDR2 connected to the kth display panel DPk and the first gate driving unit GDR1 connected to the k+1th display panel DPk+1 may be arranged adjacent to and facing each other. k is a positive integer.

[0162] The first gate driving part GDR1 connected to the kth display panel DPk and the second gate driving part GDR2 connected to the k+1th display panel DPk+1 may be arranged opposite to each other. Also, the data driving part DDR connected to the display panel DP may be arranged toward the outer contour of the multi display device MDD.

[0163] An adhesive AD may be arranged between the display panels DP. The adhesive AD may be arranged higher than the first gate driver GDR1 and the second gate driver GDR2. The display panels DP may be connected to each other by the adhesive AD. Since the area for arranging the first gate driver GDR1 and the second gate driver GDR2 and the data driver DDR can be minimized, the frame area of ​​the multi-display device MDD can be reduced.

[0164] Although the above embodiments are described, those skilled in the art will appreciate that the present invention can be modified and altered in various ways without departing from the concept and scope of the present invention as described in the claims. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical concept of the present invention, and all technical concepts within the scope of the claims and the scope equivalent thereto should be interpreted as being included within the scope of the present invention.

Claims

1. A display device, comprising: a first substrate; An image display layer, arranged on the first substrate; A gate driving unit, arranged on a first side surface of the first substrate; A data driving unit, arranged on the second side surface of the first substrate; A plurality of first conductive layers, arranged in a first recessed portion defined on the first side surface and independent of both the gate driving portion and the data driving portion; as well as a plurality of second conductive layers, arranged in a second recessed portion defined on the second side surface and independent of both the gate driving portion and the data driving portion; The gate driving unit is electrically connected to the plurality of first conductive layers at the first side surface of the first substrate. The first substrate comprises: A plurality of gate lines extending along a first direction; a plurality of data lines insulated from the plurality of gate lines and extending along a second direction intersecting the first direction; and A plurality of pixels are respectively connected to the plurality of gate lines and the plurality of data lines, Wherein, the plurality of gate lines are electrically connected to the plurality of first conductive layers respectively, The plurality of data lines are electrically connected to the plurality of second conductive layers respectively, The gate driving unit comprises: a first flexible circuit board; A first driving chip mounted on the first flexible circuit board; and a plurality of first pads arranged on a surface of the first flexible circuit board facing the first side surface and connected to the first driving chip, wherein the plurality of first pads are electrically connected to the plurality of first conductive layers respectively, The data driving unit comprises: a second flexible circuit board; A second driving chip mounted on the second flexible circuit board; and a plurality of second pads, arranged on a surface of the second flexible circuit board facing the second side surface and connected to the second driving chip, wherein the plurality of second pads are electrically connected to the plurality of second conductive layers respectively, The gate line and the first conductive layer are separated and contact each other, The data line and the second conductive layer are separated and contact each other.

2. The display device according to claim 1, wherein: The second side surface extends along a first direction, the first side surface extends along the second direction, the first recessed portions are arranged along the second direction, and each of the first recessed portions extends along the first direction.

3. The display device according to claim 1, wherein: A width of each of the plurality of first conductive layers is greater than a width of each of the plurality of gate lines.

4. The display device according to claim 1, wherein: The first flexible circuit board extends along a third direction intersecting a plane defined by the first direction and the second direction.

5. The display device according to claim 1, wherein: Also includes: The second recessed portions are arranged along the first direction and each of the plurality of second recessed portions extends along the second direction, and the data driving portion is connected to the plurality of second conductive layers at the second side surface of the first substrate.

6. The display device according to claim 5, wherein: Also includes: A plurality of connection electrodes are respectively arranged between the plurality of second conductive layers and the plurality of data lines and respectively electrically connect the plurality of data lines and the plurality of second conductive layers to each other.

7. The display device according to claim 6, wherein: A width of each of the plurality of second conductive layers and a width of each of the plurality of connection electrodes are greater than a width of each of the plurality of data lines.

8. The display device according to claim 6, wherein: The plurality of connection electrodes and the plurality of gate lines are arranged at the same layer.

9. The display device according to claim 1, wherein: The second flexible circuit board extends along a third direction intersecting a plane defined by the first direction and the second direction.

10. A method for manufacturing a display device, comprising the following steps: A first recessed portion is defined on a first side surface of the first substrate; A second recessed portion is defined on a second side surface of the first substrate; Disposing a plurality of first conductive layers in the first recessed portion; Disposing a plurality of second conductive layers in the second recessed portion; electrically connecting a gate driving unit independent of the plurality of first conductive layers to the plurality of first conductive layers at the first side surface of the first substrate; as well as electrically connecting a data driving unit independent of the plurality of second conductive layers to the plurality of second conductive layers at the second side surface of the first substrate, The first substrate comprises: A first base substrate, defining the first recessed portion and the second recessed portion; A plurality of gate lines are arranged on the first base substrate and extend along a first direction; an insulating film, arranged on the first base substrate in a manner of covering the plurality of gate lines; and a plurality of data lines arranged on the insulating film and extending along a second direction intersecting the first direction, The gate driving unit comprises: a first flexible circuit board; A first driving chip mounted on the first flexible circuit board; and a plurality of first pads arranged on a surface of the first flexible circuit board facing the first side surface and connected to the first driving chip, The data driving unit comprises: a second flexible circuit board; A second driving chip mounted on the second flexible circuit board; and a plurality of second pads, arranged on a surface of the second flexible circuit board facing the second side surface and connected to the second driving chip, The first pads are electrically connected to the first conductive layers, and the second pads are electrically connected to the second conductive layers. The gate line and the first conductive layer are separated and contact each other, The data line and the second conductive layer are separated and contact each other.

11. The method for manufacturing a display device according to claim 10, wherein: The step of defining the first recessed portion includes the steps of: irradiating a laser toward the first side surface to form the first recessed portion on the first side surface; The step of defining the second recessed portion includes the step of irradiating a laser toward the second side surface to form the second recessed portion on the second side surface.

12. The method for manufacturing a display device according to claim 10, wherein: in, The second side extends along the first direction, the first side extends along the second direction, each of the first recessed portions extends along the first direction, and each of the second recessed portions extends along the second direction, Furthermore, the plurality of gate lines are respectively connected to the plurality of first conductive layers, and the plurality of data lines are respectively connected to the plurality of second conductive layers.

13. The method for manufacturing a display device according to claim 12, wherein: The step of defining the plurality of first recessed portions comprises the following steps: irradiating a laser beam toward an upper surface of the first base substrate adjacent to the first side surface to form the first recessed portion, The step of defining the plurality of second recessed portions comprises the following steps: The second recessed portion is formed by irradiating a laser beam toward an upper surface of the first base substrate adjacent to the second side surface.

14. The method for manufacturing a display device according to claim 13, wherein: The following steps are also included: Disposing a plurality of gate lines electrically connected to the plurality of first conductive layers respectively and a plurality of connection electrodes electrically connected to the plurality of second conductive layers respectively on the first base substrate; disposing an insulating film on the first base substrate in a manner of covering the plurality of gate lines and the plurality of connection electrodes; as well as A plurality of data lines are arranged on the insulating film, The plurality of data lines are electrically connected to the plurality of connection electrodes respectively through first contact holes defined in the insulating film.

15. A multi-display device, comprising: Multiple display panels connected to each other, Each of the plurality of display panels comprises: a first substrate; An image display layer, arranged on the first substrate; A gate driving unit, arranged on a first side surface of the first substrate; A data driving unit, arranged on the second side surface of the first substrate; a plurality of first conductive layers, arranged in a first recessed portion defined on the first side surface and independent of the gate driving portion; and a plurality of second conductive layers, arranged in a second recessed portion defined on the first side surface and independent of the data driving portion, The gate driving unit is electrically connected to the plurality of first conductive layers at the first side surface of the first substrate, and the data driving unit is electrically connected to the plurality of second conductive layers at the second side surface of the first substrate. The first side surface of the kth display panel and the first side surface of the k+1th display panel among the plurality of display panels face each other, k is a positive integer, The first substrate comprises: A plurality of gate lines extending along a first direction; a plurality of data lines insulated from the plurality of gate lines and extending along a second direction intersecting the first direction; and A plurality of pixels are respectively connected to the plurality of gate lines and the plurality of data lines, Wherein, the plurality of gate lines are electrically connected to the plurality of first conductive layers respectively, The gate driving unit comprises: a first flexible circuit board; A first driving chip mounted on the first flexible circuit board; and a plurality of first pads arranged on a surface of the first flexible circuit board facing the first side surface and connected to the first driving chip, wherein the plurality of first pads are electrically connected to the plurality of first conductive layers respectively, The data driving unit comprises: a second flexible circuit board; A second driving chip mounted on the second flexible circuit board; and a plurality of second pads, arranged on a surface of the second flexible circuit board facing the second side surface and connected to the second driving chip, wherein the plurality of second pads are electrically connected to the plurality of second conductive layers respectively, The gate line and the first conductive layer are separated and contact each other, The data line and the second conductive layer are separated and contact each other.

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