Display device, method for obtaining overdrive data thereof, and method for operating the same

Abstract

The present application relates to a display device, a method for obtaining overdrive data thereof, and a method for operating the same. The method for obtaining overdrive data includes: providing, in a first frame, a first data voltage corresponding to a current line reference gray level to a second pixel during a first data writing time and a second data writing time for a first pixel and the second pixel; measuring a first luminance based on the first data voltage; applying, in a second frame, a second data voltage corresponding to a previous line reference gray level during the first data writing time; providing, in the second frame, a third data voltage obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage during the second data writing time; measuring a second luminance based on the third data voltage; and when the second luminance is the same as the first luminance, determining an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level as the predicted overdrive gray level.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a method of obtaining overdrive data of a display device, a method of operating a display device, and the display device itself. Background Art

[0002] A display device provides a data voltage to a pixel to display an image corresponding to the data voltage. Depending on the distance from a data driver to the pixel, the data voltage may be delayed due to a resistor-capacitor (RC) delay. In other words, the transition time of the data voltage for a pixel relatively far from the data driver may be longer than the transition time of the data voltage for a pixel relatively close to the data driver. Therefore, as the distance of the pixel from the data driver increases, the transition time of the data voltage increases, and thus the charging rate of the pixel decreases, which results in deterioration of image quality. For example, as the resolution of the display device increases, the length of one horizontal time (1H) decreases, and thus the deterioration of image quality may be aggravated. Summary of the Invention

[0003] Some embodiments provide a method of obtaining overdrive data of a display device, which can provide a substantially uniform charging rate.

[0004] Some embodiments provide a method of operating a display device, which can provide a substantially uniform charging rate.

[0005] Some embodiments provide a display device using overdrive data, which can provide a substantially uniform charging rate.

[0006] According to some embodiments, there is provided a method of obtaining overdrive data of a display device, the display device including a first pixel, a second pixel, and a third pixel respectively connected to a first gate line, a second gate line, and a third gate line and connected to the same data line. The method includes: providing, in a first frame, a first data voltage corresponding to a current line reference gray level to the second pixel during a first data write time for the first pixel and a second data write time for the second pixel; measuring a first luminance of an image displayed based on the first data voltage; applying, in a second frame, a second data voltage corresponding to a previous line reference gray level to the data line during the first data write time; providing, in the second frame, a third data voltage to the second pixel during the second data write time, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage; measuring a second luminance of an image displayed based on the third data voltage; and when the second luminance is substantially the same as the first luminance, determining an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level as the predicted overdrive gray level.

[0007] Providing a first data voltage to a second pixel in a first frame may include: shifting a first gate signal in the first frame such that the first gate signal is not applied to a first gate line during a first data writing time in the first frame; applying a second gate signal to a second gate line during the first data writing time and a second data writing time in the first frame; and applying the first data voltage to a data line during the first data writing time and the second data writing time in the first frame.

[0008] The method may further include generating the first gate signal synchronously with a first gate clock signal input to a gate driver, wherein shifting the first gate signal includes shifting the first gate clock signal input to the gate driver.

[0009] The method may further include advancing the first gate clock signal by one horizontal time when a source boost test enable signal has an active level.

[0010] The method may further include providing a second data voltage to a third pixel during a third data writing time for the third pixel in the first frame.

[0011] The method may further include shifting the first gate signal in a second frame such that the first gate signal is not applied to the first gate line during the first data writing time in the second frame.

[0012] The method may further include changing a predicted overdrive gray level when a second luminance is different from a first luminance.

[0013] The method may further include providing the second data voltage to the third pixel during the third data writing time for the third pixel in the second frame.

[0014] The method may further include displaying corresponding different colors through the first pixel, the second pixel, and the third pixel.

[0015] The first pixel may include a blue pixel, the second pixel may include a green pixel, and the third pixel may include a red pixel.

[0016] The method may further include: determining an overdrive value at each of N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels, where N is an integer greater than 0 and M is an integer greater than 0; and storing overdrive data representing the overdrive values determined at the N×M reference gray level pairs in an overdrive data memory of the display device.

[0017] The method may further include: acquiring overdrive data at each of a plurality of sampling positions on a display panel of the display device; and storing the overdrive data acquired at the plurality of sampling positions in the overdrive data memory.

[0018] According to some embodiments, a method of operating a display device is provided. The display device includes a first pixel, a second pixel, and a third pixel respectively connected to a first gate line, a second gate line, and a third gate line and connected to the same data line. The method includes: providing, during a first data writing time for the first pixel and a second data writing time for the second pixel in a first frame, a first data voltage corresponding to a current line reference gray level to the second pixel; measuring a first luminance of an image displayed based on the first data voltage; in a second frame, applying a second data voltage corresponding to a previous line reference gray level to the data line during the first data writing time; in the second frame, providing, during the second data writing time, a third data voltage to the second pixel, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage; measuring a second luminance of an image displayed based on the third data voltage; when the second luminance is substantially the same as the first luminance, determining an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level as the predicted overdrive gray level; storing overdrive data representing the determined overdrive value in an overdrive data memory of the display device; receiving input image data; generating output image data by compensating the input image data based on the overdrive data; and displaying an image based on the output image data.

[0019] The method may further include determining an overdrive value at each of N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels, where N is an integer greater than 0 and M is an integer greater than 0, and the overdrive data stored in the overdrive data memory represents the overdrive values determined at the N×M reference gray level pairs.

[0020] When the input image data represents a first gray level for the first pixel and a second gray level for the second pixel, the method may further include: calculating an overdrive value for the second pixel by performing bilinear interpolation on the overdrive values at the reference gray level pairs of two previous line reference gray levels adjacent to the first gray level among the M previous line reference gray levels and two current line reference gray levels adjacent to the second gray level among the N current line reference gray levels; and generating output image data for the second pixel by adding the overdrive value for the second pixel and the second gray level.

[0021] The method may further include: obtaining overdrive data at each of a plurality of sampling positions on a display panel of the display device; and storing the overdrive data obtained at the plurality of sampling positions in the overdrive data memory.

[0022] The method may further include: calculating an overdrive value for each pixel by performing bilinear interpolation on the overdrive values at four sampling positions adjacent to each pixel among a plurality of sampling positions; and generating output image data for each pixel by adding the calculated overdrive value for each pixel and the gray level represented by the input image data for each pixel.

[0023] According to some embodiments, there is provided a display device, which includes: a display panel including a plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; an overdrive data memory configured to store overdrive data representing overdrive values for at least one pixel among the plurality of pixels; and a controller configured to control the gate driver and the data driver, wherein the data driver is configured to: provide a first data voltage corresponding to a current line reference gray level to at least one pixel in a first frame for at least two horizontal times, and measure a first luminance of an image displayed based on the first data voltage; apply a second data voltage corresponding to a previous line reference gray level to a data line connected to at least one pixel in a second frame, and provide a third data voltage to at least one pixel in the second frame for one horizontal time, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage, and measure a second luminance of an image displayed based on the third data voltage, and wherein, when the second luminance is substantially the same as the first luminance, determine the overdrive value for at least one pixel as the predicted overdrive gray level.

[0024] The controller may include a gate clock shifter configured to shift at least one of a plurality of gate clock signals input to the gate driver in response to a source enhancement test enable signal.

[0025] The controller may include a data compensator configured to receive input image data, generate output image data by compensating the input image data based on the overdrive data stored in the overdrive data memory, and provide the output image data to the data driver.

[0026] As described above, in the method for obtaining overdrive data of a display device, the method for operating a display device, and the display device according to each embodiment, the first luminance may be measured by providing a data voltage corresponding to a current line reference gray level to at least one pixel for at least two horizontal times in a first frame, the second luminance may be measured by providing a voltage obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and a data voltage to at least one pixel for one horizontal time in a second frame, and an overdrive value for at least one pixel may be determined based on the first luminance and the second luminance. Accordingly, optimal overdrive data for the display device may be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary non-limiting embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram showing a display device according to some embodiments of the present disclosure.

[0029] Figure 2 is a diagram showing Figure 1 an example of a display panel included in the display device.

[0030] Figure 3 is a diagram showing Figure 1 an example of a gate driver included in the display device.

[0031] Figure 4 is a diagram for describing Figure 1 an example of overdrive data stored in an overdrive data memory included in the display device.

[0032] Figure 5 is a diagram for describing an example of multiple sampling positions for obtaining overdrive data.

[0033] Figure 6 is a diagram for describing Figure 1 an example of bilinear interpolation performed by a data compensator included in the display device.

[0034] Figure 7 is a flowchart showing a method for obtaining overdrive data of a display device according to some embodiments of the present disclosure.

[0035] Figure 8 is a timing diagram showing examples of a gate clock signal, a gate signal, and a data signal in a first frame of a display device.

[0036] Figure 9 is a block diagram for describing an example of measuring the luminance of an image displayed by a display device.

[0037] Figure 10 It is a timing diagram showing examples of a gate clock signal, a gate signal, and a data signal in a second frame of a display device.

[0038] Figure 11 It is a flowchart showing a method of operating a display device according to some embodiments of the present disclosure.

[0039] Figure 12 It is a block diagram showing an example of an electronic device including a display device according to some embodiments of the present disclosure. Detailed Description

[0040] By referring to the detailed description of the embodiments and the drawings, the features of the inventive concept and its implementation method can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be implemented in many different forms and should not be construed as limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the inventive concept to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described.

[0041] Unless otherwise noted, the same reference numerals in all the drawings and the written description denote the same elements, and thus, their descriptions will not be repeated. Additionally, parts not relevant to the description of the embodiments may not be shown to make the description clear. In the drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated.

[0042] In the detailed description, for purposes of illustration, many specific details are described to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0043] It should be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first part described below may be referred to as the second element, second component, second region, second layer, or second part.

[0044] It will be understood that when an element, layer, region or component is referred to as being "on", "connected to" or "coupled to" another element, layer, region or component, the element, layer, region or component can be directly on the other element, layer, region or component, directly connected to or directly coupled to the other element, layer, region or component, or there can be one or more intermediate elements, layers, regions or components. However, "directly connected / coupled" means that a component is directly connected or coupled to another component without an intermediate component. At the same time, other expressions describing the relationship between components, such as "between", "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intermediate elements or layers.

[0045] For the purposes of the present disclosure, when an expression such as "at least one of..." follows a list of elements, it modifies the entire list of elements, rather than individual elements in the list. For example, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be understood to mean only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as, by way of example, XYZ, XYY, YZ and ZZ. The same reference numerals throughout the specification denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "an" are intended to also include the plural forms. It will also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0047] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent deviations of measured or calculated values recognized by a person of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated value and the average within an acceptable deviation range of the stated value as determined by a person of ordinary skill in the art considering the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" indicates "one or more embodiments of the present disclosure."

[0048] When a particular embodiment can be implemented differently, the specific process order can be performed differently from the order described. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the order described.

[0049] An electronic device or an electrical device and / or any other relevant device or component according to some embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Additionally, various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on one substrate.

[0050] Furthermore, various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device such as, by way of example, random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as, by way of example, CD-ROM, flash drive, etc. Additionally, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be understood as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0052] Figure 1 is a block diagram showing a display device according to some embodiments of the present disclosure, Figure 2 is showing Figure 1 an example of a display panel included in the display device of, Figure 3 is showing Figure 1 an example of a gate driver included in the display device of, Figure 4 is for describing Figure 1 an example of overdrive data stored in an overdrive data memory included in the display device of, Figure 5 is a diagram for describing examples of multiple sampling positions for obtaining overdrive data, and Figure 6 is for describing Figure 1 an example of bilinear interpolation performed by a data compensator included in the display device of.

[0053] Referring to Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a controller 140, and an overdrive data memory 160. The display panel 110 includes a plurality of pixels PX. The gate driver 120 provides gate signals GS to the plurality of pixels PX. The data driver 130 provides data signals DS to the plurality of pixels PX. The controller 140 controls the gate driver 120 and the data driver 130. The overdrive data memory 160 stores overdrive data.

[0054] The display panel 110 may include a plurality of gate lines, a plurality of data lines, and a plurality of pixels PX connected to the plurality of gate lines and the plurality of data lines. In some embodiments, each pixel PX may include a switching transistor and a liquid crystal capacitor connected to the switching transistor, and the display panel 110 may be a liquid crystal display (LCD) panel. In other embodiments, each pixel PX may include at least two transistors, at least one capacitor, and an organic light emitting diode (OLED), and the display panel 110 may be an OLED display panel. However, the display panel 110 is not limited to LCD panels and OLED panels, and may be any display panel in other embodiments.

[0055] In some embodiments, as Figure 2As shown, each data line DL of the display panel 110a can be connected to pixels BPX, GPX, and RPX that display two or more different colors. In Figure 2 the display panel 110a, the first pixel BPX, the second pixel GPX, and the third pixel RPX that are connected to the same data line DL and are respectively connected to the first gate line GL1, the second gate line GL2, and the third gate line GL3 can display different colors, and the fourth pixel BPX, the fifth pixel GPX, and the sixth pixel RPX that are connected to the same data line DL and are respectively connected to the fourth gate line GL4, the fifth gate line GL5, and the sixth gate line GL6 can display different colors. For example, the first pixel BPX connected to the first gate line GL1 in the first row line can be a blue pixel, the second pixel GPX connected to the second gate line GL2 in the second row line can be a green pixel, the third pixel RPX connected to the third gate line GL3 in the third row line can be a red pixel, the fourth pixel BPX connected to the fourth gate line GL4 in the fourth row line can be a blue pixel, the fifth pixel GPX connected to the fifth gate line GL5 in the fifth row line can be a green pixel, and the sixth pixel RPX connected to the sixth gate line GL6 in the sixth row line can be a red pixel.

[0056] In addition, as Figure 2 shown, each data line DL can be alternately (or in a zigzag form) connected to a left pixel PX or a right pixel PX in groups of three pixels PX (for example, each data line DL can be connected to a pixel PX on its left and a pixel PX on its right), but the connection between the data line DL and the pixel PX is not limited to Figure 2 the example shown. In addition, although Figure 2 shows an example in which pixels BPX, GPX, and RPX that display different colors are connected to each data line DL, the arrangement of the pixels BPX, GPX, and RPX is not limited to Figure 2 the example. For example, multiple pixels PX can be arranged such that pixels PX that display the same color can be connected to the same data line DL.

[0057] The gate driver 120 can generate a gate signal GS based on a gate control signal GCTRL provided from the controller 140, and can sequentially apply the gate signal GS to multiple gate lines. In some embodiments, the gate control signal GCTRL can include, but is not limited to, a gate clock signal CKN, an inverted gate clock signal CKBN, a scan start pulse, etc. According to some embodiments, the gate driver 120 can be directly mounted on the display panel 110, can be connected to the display panel 110 in the form of a tape carrier package (TCP) or a chip on film (COF), and can be integrated in the peripheral portion of the display panel 110.

[0058] In some embodiments, the gate clock signal CKN and the inverted gate clock signal CKBN provided from the controller 140 to the gate driver 120 may include a plurality of gate clock signals CKN and a plurality of inverted gate clock signals CKBN having different phases. For example, as Figure 3 shown, the gate driver 120a may include a plurality of stages 121, 122, 123, 124, 125, and 126 that respectively apply a plurality of gate signals GS1, GS2, GS3, GS4, GS5, and GS6 to a plurality of gate lines. The gate driver 120a may receive a first gate clock signal CK1, a second gate clock signal CK2, a third gate clock signal CK3, a fourth gate clock signal CK4, a fifth gate clock signal CK5, and a sixth gate clock signal CK6 having different phases or sequentially delayed by one horizontal time (1H) from the controller 140, and may also receive a first inverted gate clock signal CKB1, a second inverted gate clock signal CKB2, a third inverted gate clock signal CKB3, a fourth inverted gate clock signal CKB4, a fifth inverted gate clock signal CKB5, and a sixth inverted gate clock signal CKB6 from the controller 140, where the first inverted gate clock signal CKB1, the second inverted gate clock signal CKB2, the third inverted gate clock signal CKB3, the fourth inverted gate clock signal CKB4, the fifth inverted gate clock signal CKB5, and the sixth inverted gate clock signal CKB6 are inverted signals of the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6. The gate driver 120a may generate a plurality of gate signals GS1, GS2, GS3, GS4, GS5, and GS6 that are synchronized with the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6 that are sequentially delayed, and the first inverted gate clock signal CKB1, the second inverted gate clock signal CKB2, the third inverted gate clock signal CKB3, the fourth inverted gate clock signal CKB4, the fifth inverted gate clock signal CKB5, and the sixth inverted gate clock signal CKB6.

[0059] For example, the first stage 121 can receive a first gate clock signal CK1 and a first inverted gate clock signal CKB1, and can generate a first gate signal GS1 synchronized with the first gate clock signal CK1. The second stage 122 can receive a second gate clock signal CK2 and a second inverted gate clock signal CKB2, and can generate a second gate signal GS2 synchronized with the second gate clock signal CK2. The third stage 123 can receive a third gate clock signal CK3 and a third inverted gate clock signal CKB3, and can generate a third gate signal GS3 synchronized with the third gate clock signal CK3. The fourth stage 124 can receive a fourth gate clock signal CK4 and a fourth inverted gate clock signal CKB4, and can generate a fourth gate signal GS4 synchronized with the fourth gate clock signal CK4. The fifth stage 125 can receive a fifth gate clock signal CK5 and a fifth inverted gate clock signal CKB5, and can generate a fifth gate signal GS5 synchronized with the fifth gate clock signal CK5. The sixth stage 126 can receive a sixth gate clock signal CK6 and a sixth inverted gate clock signal CKB6, and can generate a sixth gate signal GS6 synchronized with the sixth gate clock signal CK6. In addition, the subsequent seventh to twelfth stages can generate seventh to twelfth gate signals respectively synchronized with the first inverted gate clock signal CKB1, the second inverted gate clock signal CKB2, the third inverted gate clock signal CKB3, the fourth inverted gate clock signal CKB4, the fifth inverted gate clock signal CKB5, and the sixth inverted gate clock signal CKB6, and the subsequent thirteenth to eighteenth stages can generate thirteenth to eighteenth gate signals respectively synchronized with the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6.The first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6, as well as the first inverted gate clock signal CKB1, the second inverted gate clock signal CKB2, the third inverted gate clock signal CKB3, the fourth inverted gate clock signal CKB4, the fifth inverted gate clock signal CKB5, and the sixth inverted gate clock signal CKB6 can be sequentially delayed by one horizontal time, and thus a plurality of gate signals GS1, GS2, GS3, GS4, GS5, and GS6 generated synchronously with the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6, as well as the first inverted gate clock signal CKB1, the second inverted gate clock signal CKB2, the third inverted gate clock signal CKB3, the fourth inverted gate clock signal CKB4, the fifth inverted gate clock signal CKB5, and the sixth inverted gate clock signal CKB6 can be sequentially delayed by one horizontal time.

[0060] The data driver 130 can generate a data signal DS based on the output image data ODAT and the data control signal DCTRL provided by the controller 140, and can apply the data signal DS to a plurality of data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, a horizontal start signal, a load signal, etc. According to some embodiments, the data driver 130 can be directly mounted on the display panel 110, can be connected to the display panel 110 in the form of a TCP connection or a COF connection, and can be integrated in the peripheral portion of the display panel 110.

[0061] A controller (e.g., a timing controller (TCON)) 140 can receive input image data IDAT and a control signal CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In some embodiments, the input image data IDAT can be RGB data including red image data, green image data, and blue image data. In some embodiments, the control signal CTRL can include a source enhancement test enable signal STEST_EN, which notifies that an operation for obtaining overdrive data will be performed. Additionally, in some embodiments, the control signal CTRL can further include, but is not limited to, a data enable signal, a main clock signal, etc. The controller 140 can generate a gate control signal GCTRL, a data control signal DCTRL, and output image data ODAT based on the control signal CTRL and the input image data IDAT. The controller 140 can control the operation of the gate driver 120 by providing the gate control signal GCTRL to the gate driver 120, and can control the operation of the data driver 130 by providing the data control signal DCTRL and the output image data ODAT to the data driver 130.

[0062] A data signal DS output from the data driver 130 may be delayed according to the distance of a plurality of pixels PX from the data driver 130. For example, each data line and the plurality of pixels PX connected to the data line can be represented as an equivalent model including a resistor connected in series and a capacitor connected to the resistor, and according to the respective distances of the plurality of pixels PX (e.g., the respective distances from the data driver 130), the data signal DS may be delayed due to the resistor-capacitor (RC) delay of the resistor and the capacitor. Therefore, pixels PX located far from the data driver 130 may not receive and store the data signal DS having a desired voltage level, and thus the image quality of the display device 100 may deteriorate. Additionally, for a first pixel PX in a previous row line and a second pixel PX in a current row line that are connected to the same data line, in a case where there is a relatively large gray level difference between the input image data IDAT for the first pixel PX and the input image data IDAT for the second pixel PX, the data signal DS having a desired voltage level may not be provided or stored in the second pixel PX.

[0063] However, in the display device 100 according to some embodiments of the present disclosure, overdrive data can be used to provide and store the data signal DS having a desired voltage level in each pixel PX. The overdrive data memory 160 can store overdrive data representing an overdrive value for at least one pixel PX among the plurality of pixels PX of the display panel 110. According to some embodiments, the overdrive data memory 160 can be located inside or outside the controller 140.

[0064] In some embodiments, for at least one pixel PX, the overdrive data stored in the overdrive data memory 160 may represent at least one overdrive value determined at one or more reference gray level pairs. For example, the overdrive value may be determined at each of the N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels, where N is an integer greater than 0 and M is an integer greater than 0. The overdrive data stored in the overdrive data memory 160 may represent the overdrive values determined at the N×M reference gray level pairs.

[0065] For example, as Figure 4 shown, the overdrive value ODV may be determined at the reference gray level pairs of nine current line reference gray levels CLRG (e.g., 0-gray level, 2-gray level, 4-gray level, 8-gray level, 16-gray level, 32-gray level, 64-gray level, 128-gray level, and 255-gray level) and nine previous line reference gray levels PLRG (e.g., 0-gray level, 2-gray level, 4-gray level, 8-gray level, 16-gray level, 32-gray level, 64-gray level, 128-gray level, and 255-gray level). In some embodiments, at the reference gray level pairs where the current line reference gray level CLRG and the previous line reference gray level PLRG are substantially the same, the overdrive value ODV may not be required. In this case, for each pixel PX, the overdrive data may represent seventy-two different overdrive values ODV at seventy-two reference gray level pairs.

[0066] According to some embodiments, in the overdrive data memory 160, all of the overdrive data for the pixels PX of the display panel 110 may be stored, or the overdrive data for a part of the pixels PX may be stored. In some embodiments, the overdrive data may be obtained for the pixels PX located at a plurality of sampling positions of the display panel 110, and the overdrive data for the pixels PX located at the plurality of sampling positions may be stored in the overdrive data memory 160.

[0067] For example, as Figure 5 shown, the overdrive data may be obtained for the pixels PX located at six sampling positions SP1, SP2, SP3, SP4, SP5, and SP6, and the overdrive data for the pixels PX located at the six sampling positions SP1, SP2, SP3, SP4, SP5, and SP6 may be stored in the overdrive data memory 160. In some embodiments, as Figure 5As shown, there may be little RC delay near the data driver 130, and thus, overdrive data may not be obtained near the data driver 130. In the example, the first sampling position SP1 and the fifth sampling position SP5 may be symmetric to each other, and thus, the overdrive data obtained at only one of the first sampling position SP1 and the fifth sampling position SP5 may be stored in the overdrive data memory 160. In addition, the third sampling position SP3 and the sixth sampling position SP6 may be symmetric to each other, and thus, the overdrive data obtained at only one of the third sampling position SP3 and the sixth sampling position SP6 may be stored in the overdrive data memory 160.

[0068] The controller 140 may include a data compensator 170 that receives the input image data IDAT, generates output image data ODAT by compensating the input image data IDAT based on the overdrive data stored in the overdrive data memory 160, and provides the output image data ODAT to the data driver 130. For example, for each pixel PX, the data compensator 170 may generate the output image data ODAT for the pixel PX by adding the overdrive value represented by the overdrive data and the gray level represented by the input image data IDAT for the pixel PX. For example, the overdrive data representing the overdrive values corresponding to multiple reference gray level pairs at multiple sampling positions for each pixel PX may be stored in the overdrive data memory 160, and the data compensator 170 may calculate the overdrive value for each pixel PX by performing interpolation between gray levels and / or interpolation between positions on the overdrive data.

[0069] For example, in the case where the overdrive values determined at N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels are stored in the overdrive data memory 160, the first pixel PX and the second pixel PX are sequentially connected to the same data line, the input image data IDAT for the first pixel PX represents the first gray level, and the input image data IDAT for the second pixel PX represents the second gray level, the data compensator 170 may calculate the overdrive value for the second pixel PX by performing bilinear interpolation on the overdrive values at the reference gray level pairs of two previous line reference gray levels adjacent to the first gray level among the M previous line reference gray levels and two current line reference gray levels adjacent to the second gray level among the N current line reference gray levels. In addition, the data compensator 170 may generate the output image data ODAT for the second pixel PX by adding the overdrive value for the second pixel PX and the second gray level. This interpolation between gray levels may be performed before or after the interpolation between positions described below.

[0070] In addition, the data compensator 170 may calculate the overdrive value for each pixel PX by performing bilinear interpolation on the overdrive values at four sampling positions adjacent to the pixel PX. For example, as Figure 6 shown, the data compensator 170 may calculate the overdrive value at the first intermediate position PA by performing linear interpolation on the overdrive values at the first sampling position SP1 and the second sampling position SP2, may calculate the overdrive value at the second intermediate position PB by performing linear interpolation on the overdrive values at the third sampling position SP3 and the fourth sampling position SP4, and may calculate the overdrive value for the pixel PX by performing linear interpolation on the overdrive values at the first intermediate position PA and the second intermediate position PB. In addition, the data compensator 170 may generate the output image data ODAT for the pixel PX by adding the calculated overdrive value for the pixel PX and the gray level represented by the input image data IDAT for the pixel PX. The interpolation between such positions may be performed before or after the interpolation between the gray levels described above.

[0071] As described above, the output image data ODAT may be generated by compensating the input image data IDAT based on the overdrive data stored in the overdrive data memory 160, and the data driver 130 may drive the display panel 110 based on the output image data ODAT. Thus, in the display device 100 according to some embodiments of the present disclosure, the plurality of pixels PX of the display panel 110 may have substantially uniform charging rates.

[0072] The overdrive data stored in the overdrive data memory 160 of the display device 100 may be accurately obtained such that the plurality of pixels PX may have substantially uniform charging rates. In the display device 100 according to some embodiments of the present disclosure, the optimal overdrive data for the display device 100 may be obtained as described below with reference to Figures 7 to 10 the description, and the optimal overdrive data may be stored in the overdrive data memory 160.

[0073] For example, in the first frame, a first data voltage corresponding to the current line reference gray level may be provided to at least one pixel PX for at least two horizontal times, and the first luminance of the image displayed based on the first data voltage may be measured. The gate signal GS applied to the previous line may be shifted or may be advanced by one horizontal time such that the first data voltage is not provided to the pixel PX located in the previous line for two horizontal times.

[0074] In some embodiments, one of the plurality of gate clock signals CKN input to the gate driver 120 may be shifted such that the gate signal GS applied to the previous row line may be shifted. To perform this operation, the controller 140 may include a gate clock shifter 150 that shifts at least one of the plurality of gate clock signals CKN input to the gate driver 120 in response to a source enhancement test enable signal STEST_EN. In some embodiments, when the source enhancement test enable signal STEST_EN has an active level, the gate clock shifter 150 may advance at least one of the plurality of gate clock signals CKN by one horizontal time. In a second frame, a second data voltage corresponding to a previous line reference gray level may be applied to a data line connected to at least one pixel PX, a third data voltage (which is obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and a first data voltage) may be provided to at least one pixel PX for one horizontal time, and a second luminance of an image displayed based on the third data voltage may be measured.

[0075] When the second luminance is substantially the same as the first luminance, the overdrive value for at least one pixel PX may be determined as the predicted overdrive gray level. The overdrive value corresponding to one or more reference gray level pairs may be obtained at one or more sampling positions, and the overdrive data representing the overdrive value may be stored in the overdrive data memory 160. As described above, the target luminance (or the first luminance) may be measured after a sufficient time (e.g., at least two horizontal times) has elapsed since the first data voltage corresponding to the current line reference gray level is provided to the pixel PX, the overdrive value for the pixel PX may be determined such that the luminance of the pixel PX reaches the target luminance, and thus the optimal drive data for the display device 100 may be obtained.

[0076] Figure 7 is a flowchart illustrating a method of obtaining overdrive data of a display device according to some embodiments of the present disclosure, Figure 8 is a timing diagram illustrating an example of gate clock signals, gate signals, and data signals in a first frame of a display device, Figure 9 is a block diagram for describing an example of measuring the luminance of an image displayed by a display device, and Figure 10 is a timing diagram illustrating an example of gate clock signals, gate signals, and data signals in a second frame of a display device.

[0077] Reference Figure 1 、 Figure 2 and Figure 7, in the method for obtaining overdrive data of the display device 100 according to some embodiments of the present disclosure, the display device 100 may shift at least one of a plurality of gate clock signals CKN input to the gate driver 120 in response to a source boost test enable signal STEST_EN (S210). In some embodiments, the source boost test enable signal STEST_EN may have an active level when the method for obtaining overdrive data is executed, and may have an inactive level after the overdrive data is stored in the overdrive data memory 160. The gate clock shifter 150 may advance at least one of the plurality of gate clock signals CKN when the source boost test enable signal STEST_EN has an active level. For example, as shown in Figure 8 and Figure 10 , the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6 may be input to the gate driver 120, and the gate clock shifter 150 may advance the first gate clock signal CK1 and the fourth gate clock signal CK4 by one horizontal time.

[0078] For a first pixel BPX, a second pixel GPX, and a third pixel RPX that are respectively connected to a first gate line GL1, a second gate line GL2, and a third gate line GL3 and are connected to the same data line DL, the display device 100 may provide a first data voltage corresponding to a current line reference gray level to the second pixel GPX during a first data write time for the first pixel BPX and a second data write time for the second pixel GPX in a first frame (S220). In addition, the display device 100 may provide a second data voltage corresponding to a previous line reference gray level to the third pixel RPX during a third data write time for the third pixel RPX in the first frame. Here, the first data write time for the first pixel BPX may be a time allocated for providing and storing a data signal DS in the first pixel BPX, the second data write time for the second pixel GPX may be a time allocated for providing and storing a data signal DS in the second pixel GPX, and the third data write time for the third pixel RPX may be a time allocated for providing and storing a data signal DS in the third pixel RPX. Each of the first data write time to the third data write time may have a length of one horizontal time. In addition, the second data write time may start at the end of the first data write time, and the third data write time may start at the end of the second data write time.

[0079] In some embodiments, to provide a first data voltage to a second pixel GPX in a first frame, the display device 100 may shift a first gate signal in the first frame such that the first gate signal is not applied to the first gate line GL1 during a first data writing time in the first frame, may apply a second gate signal to the second gate line GL2 during the first data writing time and a second data writing time in the first frame, and may apply the first data voltage to the data line DL during the first data writing time and the second data writing time in the first frame. Further, in some embodiments, the first gate signal (e.g., GS1) may be generated in synchronization with a first gate clock signal (e.g., CK1) input to the gate driver 120, and the first gate clock signal input to the gate driver 120 may be shifted to shift the first gate signal.

[0080] For example, as Figure 8 shown, a first gate clock signal CK1, a second gate clock signal CK2, a third gate clock signal CK3, a fourth gate clock signal CK4, a fifth gate clock signal CK5, and a sixth gate clock signal CK6, each having a high period corresponding to six horizontal times (e.g., Figure 8 6H in ) may be input to the gate driver 120. Further, the first gate clock signal CK1 and the fourth gate clock signal CK4 may be shifted by one horizontal time. Accordingly, the first gate clock signal CK1 may have a phase substantially the same as that of an inverted signal of the sixth gate clock signal CK6, and the fourth gate clock signal CK4 may have a phase substantially the same as that of the third gate clock signal CK3. Accordingly, the first gate signal GS1 and the fourth gate signal GS4 generated in synchronization with the first gate clock signal CK1 and the fourth gate clock signal CK4 may be shifted by one horizontal time.

[0081] Each frame may sequentially have a plurality of data write times DWT1, DWT2, DWT3, DWT4, DWT5, and DWT6 respectively corresponding to a plurality of row lines. Each of the plurality of data write times DWT1, DWT2, DWT3, DWT4, DWT5, and DWT6 may have a length of one horizontal time (1H). When the first gate clock signal CK1, the second gate clock signal CK2, the third gate clock signal CK3, the fourth gate clock signal CK4, the fifth gate clock signal CK5, and the sixth gate clock signal CK6 are not shifted, during each data write time DWT1, DWT2, DWT3, DWT4, DWT5, and DWT6, the corresponding gate signals GS1, GS2, GS3, GS4, GS5, and GS6 may have a high level, and at the end of each data write time DWT1, DWT2, DWT3, DWT4, DWT5, and DWT6, the corresponding gate signals GS1, GS2, GS3, GS4, GS5, and GS6 may transition to a low level. However, since the first gate signal GS1 and the fourth gate signal GS4 are shifted by one horizontal time, during the first data write time DWT1 of the first pixel BPX connected to the first gate line GL1, the first gate signal GS1 may not be applied to the first gate line GL1, and during the fourth data write time DWT4 of the fourth pixel BPX connected to the fourth gate line GL4, the fourth gate signal GS4 may not be applied to the fourth gate line GL4.

[0082] As Figure 8 and Figure 10 shown, the reference numerals "DS@130" and "DS@PX" may respectively represent the data signal at the data driver 130 and the data signal at the pixel PX. During the first data write time DWT1 in the first frame, the data driver 130 may apply a first data voltage DV1 corresponding to the current line reference gray level to the data line DL. Accordingly, the first data voltage DV1 may be provided to the second pixel GPX connected to the second gate line GL2. For example, the current line reference gray level may be the 128 gray level 128G, and the first data voltage DV1 may have a first data voltage level DVL1 corresponding to the 128 gray level 128G. Since the first gate signal GS1 is not applied to the first gate line GL1 during the first data write time DWT1, the first data voltage DV1 may not be provided to the first pixel BPX connected to the first gate line GL1.

[0083] During a second data write time DWT2 in a first frame, the data driver 130 may apply a first data voltage DV1 to the data line DL. Accordingly, the first data voltage DV1 may be provided to a second pixel GPX connected to a second gate line GL2. Even if the second pixel GPX is positioned relatively far from the data driver 130, the first data voltage DV1 may be provided to the second pixel GPX during a first data write time DWT1 and the second data write time DWT2, or the first data voltage DV1 may be provided to the second pixel GPX for two horizontal times, and thus the first data voltage DV1 having a desired voltage level or a first data voltage level DVL1 corresponding to 128 gray levels 128G may be provided to the second pixel GPX.

[0084] During a third data write time DWT3 in a first frame, the data driver 130 may apply a second data voltage DV2 corresponding to a previous line reference gray level to the data line DL. Accordingly, the second data voltage DV2 may be provided to a third pixel RPX connected to a third gate line GL3. For example, the previous line reference gray level may be a 0 gray level 0G, and the second data voltage DV2 may have a second data voltage level DVL2 corresponding to the 0 gray level 0G.

[0085] During a fourth data write time DWT4 and a fifth data write time DWT5 in a first frame, the data driver 130 may apply the first data voltage DV1 to the data line DL. The first data voltage DV1 may not be provided to a fourth pixel BPX connected to a fourth gate line GL4, and the first data voltage DV1 may be provided to a fifth pixel GPX connected to a fifth gate line GL5. In addition, during a sixth data write time DWT6 in the first frame, the data driver 130 may apply the second data voltage DV2 to the data line DL, and accordingly, the second data voltage DV2 may be provided to a sixth pixel RPX connected to a sixth gate line GL6. Even if the fifth pixel GPX is positioned relatively far from the data driver 130, the first data voltage DV1 having a desired voltage level may be provided to the fifth pixel GPX.

[0086] A first luminance of an image displayed based on the first data voltage may be measured (S230). In some embodiments, as Figure 9As shown, the first luminance can be measured by the test device 350. For example, the test device 350 can measure the first luminance by providing test image data (e.g., image data representing the current line reference gray level and the previous line reference gray level) to the display device 100 and capturing the image displayed by the display device 100 based on the test image data using a camera 370 (e.g., a charge-coupled device (CCD) camera). Since the first data voltage DV1 is not provided to the first pixel BPX but to the second pixel GPX during the first data write time DWT1 and the second data write time DWT2, or the first data voltage DV1 is not provided to the first pixel BPX but to the second pixel GPX for two horizontal times, the first luminance of the image displayed based on the first data voltage DV1 can be the target luminance with a desired luminance level.

[0087] The display device 100 may apply a second data voltage corresponding to the previous line reference gray level to the data line DL during the first data write time in the second frame (S240). In some embodiments, the display device 100 may shift the first gate signal in the second frame such that the first gate signal is not applied to the first gate line GL1 during the first data write time in the second frame. In addition, the display device 100 may provide a third data voltage to the second pixel GPX during the second data write time in the second frame, where the third data voltage is obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage (S250). In addition, the display device 100 may provide the second data voltage to the third pixel RPX during the third data write time for the third pixel RPX in the second frame.

[0088] For example, as Figure 10 shown, in the second frame, the first gate clock signal CK1 and the fourth gate clock signal CK4 may be shifted by one horizontal time, and thus, the first gate signal GS1 and the fourth gate signal GS4 generated synchronously with the first gate clock signal CK1 and the fourth gate clock signal CK4 may be shifted by one horizontal time.

[0089] The data driver 130 may apply a second data voltage DV2 corresponding to a previous line reference gray level (e.g., 0 gray level 0G) to the data line DL during a first data write time DWT1 in a second frame, and may apply a third data voltage DV3 (which is obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level PODV and a first data voltage DV1 corresponding to a current line reference gray level (e.g., 128 gray level 128G)) to the data line DL during a second data write time DWT2 in the second frame. For example, the third data voltage DV3 may have a third data voltage level DVL3, which is obtained by adding a voltage level corresponding to the predicted overdrive gray level PODV and a first data voltage level DVL1 of the first data voltage DV1.

[0090] In a case where the predicted overdrive gray level PODV is an optimal overdrive gray level, a data signal DS at a second pixel GPX connected to a second gate line GL2 or the third data voltage DV3 at the second pixel GPX may have a desired voltage level of the first data voltage DV1, or may have a first data voltage level DVL1 corresponding to 128 gray levels at an end point of the second data write time DWT2. During a third data write time DWT3 in the second frame, the data driver 130 may apply the second data voltage DV2 to the data line DL.

[0091] The data driver 130 may apply the second data voltage DV2 to the data line DL during a fourth data write time DWT4 in the second frame, may apply the third data voltage DV3 to the data line DL during a fifth data write time DWT5 in the second frame, and may apply the second data voltage DV2 to the data line DL during a sixth data write time DWT6 in the second frame. In a case where the predicted overdrive gray level PODV is an optimal overdrive gray level, a data signal DS at a fifth pixel GPX connected to a fifth gate line GL5 may have a desired voltage level of the first data voltage DV1, or may have a first data voltage level DVL1 corresponding to 128 gray levels at an end point of the fifth data write time DWT5.

[0092] A second luminance (S260) of an image displayed based on the third data voltage may be measured. When the second luminance is different from the first luminance (S270: No), the predicted overdrive gray level may be changed (S280), the second data voltage and the third data voltage may be applied again, and the second luminance in the second frame may be measured again (S240, S250, and S260).

[0093] When the second luminance is substantially the same as the first luminance (S270: Yes), the predicted overdrive gray level can be determined as the overdrive value corresponding to the reference gray level pair of the current line reference gray level and the previous line reference gray level (S290). As described above, since the first luminance can be measured as the target luminance after a sufficient or appropriate time (e.g., two horizontal times) for supplying the first data voltage corresponding to the current line reference gray level to each green pixel (e.g., the second pixel GPX and the fifth pixel GPX), the overdrive value for the green pixels (e.g., the second pixel GPX and the fifth pixel GPX) can be determined such that the second luminance of the image displayed based on the third data voltage can be substantially the same as the target luminance, and thus the overdrive value can be the optimal overdrive value for the green pixels (e.g., the second pixel GPX and the fifth pixel GPX).

[0094] In some embodiments, the overdrive value can be determined at each of the N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels, where N is an integer greater than 0 and M is an integer greater than 0, and overdrive data representing the overdrive values determined at the N×M reference gray level pairs can be generated.

[0095] In addition, in some embodiments, the overdrive data can be obtained at each of the plurality of sampling positions of the display panel 110, and the overdrive data obtained at the plurality of sampling positions can be stored in the overdrive data memory 160 of the display device 100. As described above, since the overdrive data is generated based on the target luminance measured at the display device 100, the overdrive data can be the optimal overdrive data for the display device 100.

[0096] Figure 11 is a flowchart showing a method of operating a display device according to some embodiments of the present disclosure.

[0097] Referring to Figure 1 and Figure 11 , in the method of operating the display device 100, the overdrive data can be obtained, and the obtained overdrive data can be stored in the overdrive data memory 160 (S310). The obtaining and storing of the overdrive data can be performed by Figure 7 's method.

[0098] For example, for a first pixel, a second pixel, and a third pixel respectively connected to a first gate line, a second gate line, and a third gate line and also connected to the same data line, in a first frame, a first data voltage corresponding to a current line reference gray level can be provided to the second pixel during a first data writing time for the first pixel and a second data writing time for the second pixel, a first luminance of an image displayed based on the first data voltage can be measured, in a second frame, a second data voltage corresponding to a previous line reference gray level can be applied to the data line during the first data writing time, in the second frame, a third data voltage (which is obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage) can be provided to the second pixel during the second data writing time, a second luminance of an image displayed based on the third data voltage can be measured, an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level can be determined as the predicted overdrive gray level when the second luminance is substantially the same as the first luminance, and overdrive data representing the determined overdrive value can be stored in an overdrive data memory 160 of the display device 100.

[0099] The display device 100 can receive input image data IDAT (S330), can generate output image data ODAT by compensating the input image data IDAT based on the overdrive data stored in the overdrive data memory 160 (S350), and can display an image based on the output image data ODAT (S370).

[0100] In some embodiments, an overdrive value can be determined at each of N×M reference gray level pairs of N current line reference gray levels and M previous line reference gray levels, where N is an integer greater than 0 and M is an integer greater than 0, and the overdrive data stored in the overdrive data memory 160 can represent the overdrive values determined at the N×M reference gray level pairs.

[0101] In a case where the input image data IDAT represents a first gray level for a first pixel and a second gray level for a second pixel, an overdrive value for the second pixel can be calculated by performing bilinear interpolation on the overdrive values at the reference gray level pairs of two previous line reference gray levels adjacent to the first gray level among the M previous line reference gray levels and two current line reference gray levels adjacent to the second gray level among the N current line reference gray levels, and output image data ODAT for the second pixel can be generated by adding the overdrive value for the second pixel and the second gray level.

[0102] In addition, in some embodiments, overdrive data may be obtained at each of a plurality of sampling positions on the display panel 110 of the display device 100, and the overdrive data obtained at the plurality of sampling positions may be stored in the overdrive data memory 160. The overdrive value for each pixel PX may be calculated by performing bilinear interpolation on the overdrive values at four sampling positions adjacent to the pixel PX among the plurality of sampling positions, and the output image data ODAT for the pixel PX may be generated by adding the calculated overdrive value for the pixel PX and the gray level represented by the input image data IDAT for the pixel PX.

[0103] As described above, since the output image data ODAT is generated by compensating the input image data IDAT based on the overdrive data stored in the overdrive data memory 160, and since the image is displayed based on the output image data ODAT, in the display device 100 according to some embodiments of the present disclosure, the plurality of pixels PX on the display panel 110 may have substantially uniform charging rates, and thus the display quality of the display device 100 may be improved.

[0104] Figure 12 is a block diagram illustrating an example of an electronic device including a display device according to some embodiments of the present disclosure.

[0105] Referring Figure 12 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0106] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 1110 may also be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0107] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0108] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touch screen, etc. and an output device such as a printer, speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100.

[0109] In the display device 1160, the first luminance may be measured in a first frame by applying a data voltage corresponding to a current line reference gray level to at least one pixel for at least two horizontal times, the second luminance may be measured in a second frame by applying a voltage obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and a data voltage to at least one pixel for one horizontal time, and an overdrive value for at least one pixel may be determined based on the first luminance and the second luminance. Accordingly, optimal overdrive data for the display device 1160 may be obtained.

[0110] According to some embodiments, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital TV, a 3D TV, a personal computer (PC), a household appliance, a laptop computer, a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0111] The foregoing is a description of embodiments and should not be construed as a limitation thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is a description of various embodiments and should not be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims, and their functional equivalents will be included herein.

Claims

1. A method for obtaining overdrive data of a display device, the display device including a first pixel, a second pixel, and a third pixel respectively connected to a first gate line, a second gate line, and a third gate line and connected to the same data line, the method comprising: During a first frame, providing a first data voltage corresponding to a current line reference gray level to the second pixel during a first data writing time for the first pixel and a second data writing time for the second pixel; Measuring a first luminance of an image displayed based on the first data voltage; During a second frame, applying a second data voltage corresponding to a previous line reference gray level to the data line during the first data writing time; During the second frame, providing a third data voltage to the second pixel during the second data writing time, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage; Measuring a second luminance of an image displayed based on the third data voltage; And When the second luminance is the same as the first luminance, determining an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level as the predicted overdrive gray level, and when the second luminance is different from the first luminance, changing the predicted overdrive gray level.

2. The method according to claim 1, wherein Providing the first data voltage to the second pixel during the first frame includes: During the first frame, shifting a first gate signal such that the first gate signal is not applied to the first gate line during the first data writing time in the first frame; During the first frame, applying a second gate signal to the second gate line during the first data writing time and the second data writing time; and During the first frame, applying the first data voltage to the data line during the first data writing time and the second data writing time.

3. The method according to claim 2, further comprising generating the first gate signal synchronously with a first gate clock signal input to a gate driver, Among them, Shifting the first gate signal includes shifting the first gate clock signal input to the gate driver.

4. The method according to claim 3, further comprising advancing the first gate clock signal by one horizontal time when a source boosting test enable signal has an effective level.

5. The method according to claim 1, further comprising providing the second data voltage to the third pixel during a third data writing time for the third pixel during the first frame.

6. The method according to claim 1, further comprising shifting the first gate signal during the second frame such that the first gate signal is not applied to the first gate line during the first data writing time in the second frame.

7. The method according to claim 1, further comprising providing the second data voltage to the third pixel during a third data writing time for the third pixel during the second frame.

8. A method of operating a display device, the display device including a first pixel, a second pixel, and a third pixel respectively connected to a first gate line, a second gate line, and a third gate line and connected to the same data line, the method comprising: Providing, in a first frame, a first data voltage corresponding to a current line reference gray level to the second pixel during a first data writing time for the first pixel and a second data writing time for the second pixel; Measuring a first luminance of an image displayed based on the first data voltage; Applying, in a second frame, a second data voltage corresponding to a previous line reference gray level to the data line during the first data writing time; Providing, in the second frame, a third data voltage to the second pixel during the second data writing time, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage; Measuring a second luminance of an image displayed based on the third data voltage; When the second luminance is the same as the first luminance, determining an overdrive value corresponding to a reference gray level pair of the current line reference gray level and the previous line reference gray level as the predicted overdrive gray level, and when the second luminance is different from the first luminance, changing the predicted overdrive gray level; Storing overdrive data representing the determined overdrive value in an overdrive data memory of the display device; Receiving input image data; Generating output image data by compensating the input image data based on the overdrive data; And Displaying an image based on the output image data.

9. A display device, comprising: A display panel including a plurality of pixels; A gate driver configured to provide gate signals to the plurality of pixels; A data driver configured to provide data signals to the plurality of pixels; An overdrive data memory configured to store overdrive data representing an overdrive value for at least one of the plurality of pixels; And A controller configured to control the gate driver and the data driver, Wherein the data driver is configured to: Provide, in a first frame, a first data voltage corresponding to a current line reference gray level to the at least one pixel for at least two horizontal times, wherein a first luminance of an image displayed based on the first data voltage is measured; and Apply, in a second frame, a second data voltage corresponding to a previous line reference gray level to the data line connected to the at least one pixel, and provide, in the second frame, a third data voltage to the at least one pixel for one horizontal time, the third data voltage being obtained by adding an overdrive voltage corresponding to a predicted overdrive gray level and the first data voltage, wherein a second luminance of an image displayed based on the third data voltage is measured, and Wherein when the second luminance is the same as the first luminance, determining the overdrive value for the at least one pixel as the predicted overdrive gray level, and Wherein when the second luminance is different from the first luminance, changing the predicted overdrive gray level.

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