Display device

Abstract

The present disclosure relates to a display device, the display device comprising: a first pixel region including a first pixel connected to a data line and a first scan line; a second pixel region in contact with the first pixel region at a first boundary, and the second pixel region including a second pixel connected to the data line and a second scan line; and a third pixel region in contact with the second pixel region at a second boundary, and the third pixel region including a third pixel connected to the data line and a third scan line, wherein the display device is configured to: scale an image displayed in the second pixel region one or more times based on the second pixel region remaining in a folded state.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0090995, filed with the Korean Intellectual Property Office on July 26, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some example embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of information technology, display devices that provide a connection medium between a user and information are becoming more important. In response thereto, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly used.

[0005] Recently, by applying a flexible board to a display panel, various products such as foldable display devices, rollable display devices, and stretchable display devices have been developed and introduced.

[0006] For example, a foldable display device may be configured to display an image on the entire pixel unit in an unfolded state and display an image only on a part of the pixel unit in a folded state.

[0007] In this case, the degree or rate of deterioration of pixels may be different between the region of the pixel unit where an image is displayed in both the folded state and the unfolded state and the region of the pixel unit where an image is displayed only in the unfolded state. That is, the degree or rate of deterioration of pixels may be different in different regions, and a user may visually recognize the boundary between different regions.

[0008] In addition, it may be desirable to reduce the power consumption of a region that does not display an image or displays a black image in a folded state.

[0009] The above information disclosed in this background art section is only for enhancing the understanding of the background, and thus, the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0010] Aspects of some example embodiments of the present disclosure may include a display device and a method of driving the display device, which may prevent or reduce the difference in the degree or rate of deterioration of pixels located in different positions or regions and reduce the power consumption in a folded state.

[0011] A display device according to some example embodiments of the present disclosure includes: a first pixel region including first pixels connected to data lines and a first scan line; a second pixel region in contact with the first pixel region at a first boundary, and the second pixel region includes second pixels connected to the data lines and a second scan line; and a third pixel region in contact with the second pixel region at a second boundary, and the third pixel region includes third pixels connected to the data lines and a third scan line. While the second pixel region remains in a folded state, the image displayed in the second pixel region is scaled one or more times.

[0012] According to some example embodiments, while the second pixel region remains in a folded state, the first pixel region may display an unscaled image.

[0013] According to some example embodiments, while the second pixel region remains in the folded state, the images displayed in the first pixel region and the second pixel region may be seamless at the first boundary.

[0014] According to some example embodiments, while the second pixel region remains in the folded state, the third pixel region may not display an image or may display a black image, and the second pixels of the second pixel region in contact with the second boundary may not display the image or may display the black image.

[0015] According to some example embodiments, a first image region of the image in the second pixel region in contact with the first boundary may be enlarged, and a second image region of the image in the second pixel region in contact with the second boundary may be reduced.

[0016] According to some example embodiments, as the first image region and the second image region increase, the display region in the second pixel region may increase, and the non-display region in the second pixel region may decrease.

[0017] According to some example embodiments, a first image region of the image in the second pixel region in contact with the first boundary may be reduced, and a second image region of the image in the second pixel region in contact with the second boundary may be enlarged.

[0018] According to some example embodiments, as the first image region and the second image region increase, the display region in the second pixel region may decrease, and the non-display region in the second pixel region may increase.

[0019] According to some example embodiments, while the second pixel region maintains the folded state, the first pixel and the second pixel in contact with the first boundary may update an image in a first period, and the third pixel and the second pixel in contact with the second boundary may update an image in a second period, and the first period may be shorter than the second period.

[0020] According to some example embodiments, while the second pixel region maintains the folded state, a scan signal having a conductive level may be stopped from being supplied to scan disconnection lines that are part of the second scan line for at least one frame period, and the number of the scan disconnection lines may be changed one or more times.

[0021] According to some example embodiments, the number of times the number of the scan disconnection lines is changed may be less than or equal to the number of times the image displayed in the second pixel region is scaled.

[0022] A display device according to some example embodiments of the present disclosure includes: a first pixel region including first pixels connected to data lines and a first scan line; a second pixel region in contact with the first pixel region at a first boundary, and the second pixel region includes second pixels connected to the data lines and a second scan line; and a third pixel region in contact with the second pixel region at a second boundary, and the third pixel region includes third pixels connected to the data lines and a third scan line. While the second pixel region maintains the folded state, a scan signal having a conductive level is stopped from being supplied to scan disconnection lines that are part of the second scan line for at least one frame period, and the number of the scan disconnection lines is changed one or more times.

[0023] According to some example embodiments, while the second pixel region maintains the folded state, the image displayed in the second pixel region may be scaled one or more times.

[0024] According to some example embodiments, the number of times the number of the scan disconnection lines is changed may be equal to or less than the number of times the image displayed in the second pixel region is scaled.

[0025] According to some example embodiments, in a method of driving a display device, the display device includes: a first pixel region including a first pixel connected to a data line and a first scan line; a second pixel region in contact with the first pixel region at a first boundary, and the second pixel region includes a second pixel connected to the data line and a second scan line; and a third pixel region in contact with the second pixel region at a second boundary, and the third pixel region includes a third pixel connected to the data line and a third scan line. The method includes: when the second pixel region is in an unfolded state, displaying an image in the first pixel region, the second pixel region, and the third pixel region; detecting that the second pixel region is in a folded state; and while the second pixel region remains in the folded state, scaling the image displayed in the second pixel region one or more times.

[0026] According to some example embodiments, while the second pixel region remains in the folded state, the first pixel region may display an unscaled image, and the image displayed in the first pixel region and the image displayed in the second pixel region may be seamless at the first boundary.

[0027] According to some example embodiments, while the second pixel region remains in the folded state, the third pixel region may not display an image or may display a black image, and the second pixel of the second pixel region in contact with the second boundary may not display the image or may display the black image.

[0028] According to some example embodiments, during scaling, when a first image region of the image in the second pixel region in contact with the first boundary can be enlarged, a second image region of the image in the second pixel region in contact with the second boundary can be reduced, and when the first image region is reduced, the second image region can be enlarged.

[0029] According to some example embodiments, the method may further include: while the second pixel region remains in the folded state, stopping supplying a scan signal having a conductive level to a scan disconnection line that is part of the second scan line for at least one frame period, and changing the number of scan disconnection lines one or more times.

[0030] According to some example embodiments, the number of times the number of scan disconnection lines is changed may be less than or equal to the number of times the image displayed in the second pixel region is scaled.

[0031] A display device and a method of driving the display device according to some exemplary embodiments of the present disclosure can prevent or reduce a rapid change in the degree or rate of deterioration of pixels at a specific boundary and can reduce power consumption in a folded state. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a diagram showing a display device according to some exemplary embodiments of the present disclosure.

[0033] Figure 2 is a diagram showing a pixel according to some exemplary embodiments of the present disclosure.

[0034] Figure 3 is a diagram showing an exemplary method of driving Figure 2 the pixels.

[0035] Figure 4 is a diagram showing a case where the second pixel region is in an unfolded state.

[0036] Figure 5 is a diagram showing a case where the second pixel region is in a folded state.

[0037] Figure 6 is a diagram showing an image scaling unit according to some exemplary embodiments of the present disclosure.

[0038] Figures 7 to 10 is a diagram showing a scaling method for shifting an image in the second pixel region in a first direction according to some exemplary embodiments of the present disclosure.

[0039] Figure 11 and Figure 12 is a diagram showing a scaling method for shifting an image in the second pixel region in a direction opposite to the first direction according to some exemplary embodiments of the present disclosure.

[0040] Figure 13 is a diagram showing a scan disconnection unit according to some exemplary embodiments of the present disclosure.

[0041] Figures 14 to 18 is a diagram showing an exemplary operation of the scan disconnection unit.

[0042] Figure 19 is a diagram showing an image scaling unit according to some exemplary embodiments of the present disclosure.

[0043] Figure 20 and Figure 21 is a diagram showing Figure 19 an exemplary operation of the image scaling unit. DETAILED DESCRIPTION

[0044] In the following, aspects of various exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in many different forms and is not limited to the exemplary embodiments described herein. Embodiments according to the present disclosure can be used in combination with each other or can be used independently of each other.

[0045] To clearly describe the present disclosure, parts irrelevant to the understanding of the description may be omitted, and throughout the specification, the same or similar configuration elements are denoted by the same reference numerals. Therefore, the foregoing reference numerals can be used in other drawings.

[0046] In addition, since the dimensions and thicknesses of each configuration shown in the drawings are arbitrarily shown for convenience of description, embodiments according to the present disclosure are not necessarily limited to the shown dimensions and thicknesses. That is, in the drawings, the dimensions and thicknesses of various components may be enlarged to more clearly show various layers and regions.

[0047] Figure 1 is a diagram showing a display device according to some exemplary embodiments of the present disclosure.

[0048] Referring to Figure 1 , a display device 10 according to some exemplary embodiments of the present disclosure may optionally include: a timing control unit 11, a data driving unit 12, a scan driving unit 13, a light emitting driving unit 14, a pixel unit 15, an image scaling unit 16, and a scan off unit 17.

[0049] The timing control unit 11 may receive grayscale values and control signals for each image frame from an external processor. The timing control unit 11 may provide control signals suitable for each specification to the data driving unit 12, the scan driving unit 13, the light emitting driving unit 14, etc. to display an image corresponding to the image frame.

[0050] The timing control unit 11 may render the grayscale values to correspond to the specification of the pixel unit 15. For example, the external processor may provide a red grayscale value, a green grayscale value, and a blue grayscale value for each unit dot. However, for example, when the pixel unit 15 has a Pentile structure, adjacent unit dots may share pixels, so that the pixels may not correspond one-to-one to each grayscale value. In this case, rendering of the grayscale values may be performed. When the pixels correspond one-to-one to each grayscale value, rendering of the grayscale values may not be performed.

[0051] Rendered or unrendered grayscale values can be provided to the data driving unit 12 or the image scaling unit 16. For example, when the second pixel region AR2 is in the unfolded state, the grayscale values can be directly provided to the data driving unit 12. For example, when the second pixel region AR2 is in the folded state, at least some of the grayscale values can be provided to the data driving unit 12 after being converted by the image scaling unit 16.

[0052] The image scaling unit 16 can convert the grayscale values so that the image displayed in the second pixel region AR2 is scaled one or more times while the second pixel region AR2 remains in the folded state. The image scaling unit 16 can provide scan disconnection line information to the scan disconnection unit 17 based on the converted grayscale values.

[0053] The data driving unit 12 can generate data voltages to be provided to the data lines DL1, DL2, DL3, ……, DLj, ……, and DLn by using the grayscale values and control signals. For example, the data driving unit 12 samples the grayscale values by using a clock signal and applies the data voltages corresponding to the grayscale values to the data lines DL1 to DLn in units of pixel rows (e.g., pixels connected to the same scan line). j and n can be integers greater than zero.

[0054] The scan driving unit 13 can receive a clock signal, a scan start signal, etc. from the timing control unit 11, and can generate scan signals to be provided to the scan lines SL1, SL2, SL3, ……, SL(i - 1), SLi, ……, SL(k - 1), SLk, ……, SL(p - 1), SLp, ……, and SLm. i, k, p, and m can be integers greater than zero. k can be an integer greater than i. p can be an integer greater than k. m can be an integer greater than p.

[0055] The scan driving unit 13 can sequentially supply scan signals of pulses having an on - level to the scan lines SL1 to SLm. The scan driving unit 13 can include scan stages configured in the form of a shift register. The scan driving unit 13 can generate scan signals in such a manner that a scan start signal in the form of a pulse having an on - level is sequentially transmitted to the next scan stage under the control of the clock signal.

[0056] The first scan lines SL1 to SLi can be connected to the first pixels PX1 in the first pixel region AR1. The second scan lines SL(k - 1) and SLk can be connected to the second pixels PX2 in the second pixel region AR2. The third scan lines SL(p - 1), SLp, and SLm can be connected to the third pixels PX3 in the third pixel region AR3.

[0057] The scan disconnection unit 17 may stop supplying a scan signal of a conduction level to scan disconnection lines that are part of the second scan lines SL(k-1) and SLk based on scan disconnection line information during one or more frame periods. During a period in which the supply of the scan signal of the conduction level to the scan disconnection lines is stopped, the supply of the scan signal of the conduction level to all of the third scan lines SL(p-1), SLp, and SLm may be stopped.

[0058] The emission driving unit 14 may receive a clock signal, a light emission stop signal, etc. from the timing control unit 11, and may generate a light emission signal to be provided to the light emission lines EL1, EL2, EL3, ……, ELi, ……, ELk, ……, ELp, ……, and ELo. o may be an integer greater than zero. o may be an integer greater than p. For example, the emission driving unit 14 may sequentially provide a light emission signal of a pulse having a cut-off level to the light emission lines EL1 to ELo. For example, each light emission stage of the emission driving unit 14 may be configured in the form of a shift register, and may generate a light emission signal in such a manner that a light emission stop signal in the form of a pulse having a cut-off level is sequentially transmitted to the next light emission stage under the control of the clock signal. According to some example embodiments, the emission driving unit 14 may be omitted according to the circuit configurations of the pixels PX1, PX2, and PX3.

[0059] The pixel unit 15 may include a first pixel region AR1, a second pixel region AR2, and a third pixel region AR3. The first pixel region AR1 may include a first pixel PX1 connected to the j-th data line DLj and the first scan lines SL1 to SLi. The second pixel region AR2 may be in contact with the first pixel region AR1 at a first boundary EDG1, and may include a second pixel PX2 connected to the j-th data line DLj and the second scan lines SL(k-1) and SLk. The third pixel region AR3 may be in contact with the second pixel region AR2 at a second boundary EDG2, and may include a third pixel PX3 connected to the j-th data line DLj and the third scan lines SL(p-1), SLp, and SLm.

[0060] Each of the pixels PX1, PX2, and PX3 may be connected to a corresponding data line, a corresponding scan line, and a corresponding light-emitting line. According to some example embodiments, when the emission driving unit 14 is omitted, the pixels PX1, PX2, and PX3 may not be connected to the light-emitting lines EL1 to ELo. In the first pixel PX1, the scan input terminal may be connected to the i-th scan line SLi, and the data input terminal may be connected to the j-th data line DLj. In the second pixel PX2, the scan input terminal may be connected to the k-th scan line SLk, and the data input terminal may be connected to the j-th data line DLj. In the third pixel PX3, the scan input terminal may be connected to the p-th scan line SLp, and the data input terminal may be connected to the j-th data line DLj.

[0061] The folding axis FAX may be positioned between the first boundary EDG1 and the second boundary EDG2. The folding axis FAX may overlap with the second pixel region AR2. That is, when the display device 10 is folded, the second pixel region AR2 may be folded. At this time, the first pixel region AR1 and the third pixel region AR3 may remain flat. The second pixel region AR2 may be referred to as the folding region.

[0062] According to some example embodiments, the folding axis FAX may be physically defined. For example, the display device 10 may further include a mechanical structure such that the display device 10 is configured to be folded or unfolded only on the folding axis FAX. In such a configuration, the folding axis FAX may be fixed. At this time, the pixel regions AR1, AR2, and AR3 may be fixed regions. According to some example embodiments, the bracket covering the display panel in the display device 10 may also be flexible. In such an embodiment, the position of the folding axis FAX may change, and the positions of the pixel regions AR1, AR2, and AR3 may change. In such an embodiment, the display device 10 may further include a pressure sensor, a bending sensor, a resistance sensor, etc. to detect the position of the folding axis FAX.

[0063] In Figure 1 order to compare positions, the first pixel PX1, the second pixel PX2, and the third pixel PX3 are shown connected to the same j-th data line DLj. However, according to various embodiments, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be connected to different data lines from each other.

[0064] Figure 2 is a diagram showing pixels according to some example embodiments of the present disclosure.

[0065] Refer to Figure 2, the first pixel PX1 includes transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light-emitting diode LD. Since the second pixel PX2 can have the same or a similar configuration as the first pixel PX1 except for the connected scan lines SL(k - 1) and SLk and the light-emitting line ELk, the description of the second pixel PX2 is omitted. Since the third pixel PX3 can also have the same or a similar configuration as the first pixel PX1 except for the scan lines SL(p - 1) and SLp and the light-emitting line ELp, the description of the third pixel PX3 is omitted. In some embodiments, the circuit configurations of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different from each other.

[0066] Hereinafter, as an example, a circuit configured with P-type transistors will be described. However, those skilled in the art will be able to design a circuit configured with N-type transistors by changing the polarity of the voltage applied to their gate terminals. Similarly, those skilled in the art will be able to design a circuit configured with a combination of P-type transistors and N-type transistors. A P-type transistor is a general term for a transistor in which, when the voltage difference between the gate electrode and the source electrode of the transistor increases in the negative direction, the amount of current to be conducted increases. An N-type transistor is a general term for a transistor in which, when the voltage difference between the gate electrode and the source electrode of the transistor increases in the positive direction, the amount of current to be conducted increases. Transistors can be configured in various forms, such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0067] In the first transistor T1, the gate electrode of the first transistor T1 can be connected to the first node NP1, the first electrode of the first transistor T1 can be connected to the second node NP2, and the second electrode of the first transistor T1 can be connected to the third node NP3. The first transistor T1 can be referred to as a driving transistor.

[0068] In the second transistor T2, the gate electrode of the second transistor T2 can be connected to the i-th scan line SLi, the first electrode of the second transistor T2 can be connected to the j-th data line DLj, and the second electrode of the second transistor T2 can be connected to the second node NP2. The second transistor T2 can be referred to as a scan transistor. The first electrode of the second transistor T2 can be the data input terminal DIT of the first pixel PX1. In addition, the gate electrode of the second transistor T2 can be the scan input terminal SIT of the first pixel PX1.

[0069] In the third transistor T3, the gate electrode of the third transistor T3 may be connected to the i-th scan line SLi, the first electrode of the third transistor T3 may be connected to the first node NP1, and the second electrode of the third transistor T3 may be connected to the third node NP3. The third transistor T3 may be referred to as a transistor connected in diode fashion.

[0070] In the fourth transistor T4, the gate electrode of the fourth transistor T4 may be connected to the (i-1)-th scan line SL(i-1), the first electrode of the fourth transistor T4 may be connected to the first node NP1, and the second electrode of the fourth transistor T4 may be connected to the initialization line INTL. In another embodiment, the gate electrode of the fourth transistor T4 may be connected to another scan line. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0071] In the fifth transistor T5, the gate electrode of the fifth transistor T5 may be connected to the i-th emission line ELi, the first electrode of the fifth transistor T5 may be connected to the first power supply line ELVDDL, and the second electrode of the fifth transistor T5 may be connected to the second node NP2. The fifth transistor T5 may be referred to as an emission transistor. According to some example embodiments, the gate electrode of the fifth transistor T5 may be connected to another emission line.

[0072] In the sixth transistor T6, the gate electrode of the sixth transistor T6 may be connected to the i-th emission line ELi, the first electrode of the sixth transistor T6 may be connected to the third node NP3, and the second electrode of the sixth transistor T6 may be connected to the anode of the light emitting diode LD. The sixth transistor T6 may be referred to as an emission transistor. In another embodiment, the gate electrode of the sixth transistor T6 may be connected to another emission line.

[0073] In the seventh transistor T7, the gate electrode of the seventh transistor T7 may be connected to the i-th scan line SLi, the first electrode of the seventh transistor T7 may be connected to the initialization line INTL, and the second electrode of the seventh transistor T7 may be connected to the anode of the light emitting diode LD. The seventh transistor T7 may be referred to as a light emitting diode initialization transistor. According to some example embodiments, the gate electrode of the seventh transistor T7 may be connected to another scan line. For example, the gate electrode of the seventh transistor T7 may be connected to the (i+1)-th scan line (not shown).

[0074] The first electrode of the storage capacitor Cst may be connected to the first power supply line ELVDDL, and the second electrode of the storage capacitor Cst may be connected to the first node NP1.

[0075] The light-emitting diode LD may have an anode connected to the second electrode of the sixth transistor T6 and a cathode connected to the second power supply line ELVSSL. The light-emitting diode LD may be configured by an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, or the like. The degradation of the first pixel PX1 may refer to the degradation of the light-emitting diode LD.

[0076] A first power supply voltage may be applied to the first power supply line ELVDDL, a second power supply voltage may be applied to the second power supply line ELVSSL, and an initialization voltage may be applied to the initialization line INTL. For example, the first power supply voltage may be greater than the second power supply voltage. For example, the initialization voltage may be equal to or greater than the second power supply voltage. For example, the initialization voltage may correspond to the minimum data voltage among the available data voltages. For example, the magnitude of the initialization voltage may be smaller than the magnitude of the available data voltages.

[0077] Figure 3 is a diagram showing an example method of driving Figure 2 the pixels.

[0078] First, the data voltage DATA(i - 1)j for the (i - 1)-th pixel is applied to the j-th data line DLj, and a scan signal at a conductive level (logic low level) is applied to the (i - 1)-th scan line SL(i - 1).

[0079] At this time, since a scan signal at a cut-off level (logic high level) is applied to the i-th scan line SLi, the second transistor T2 is cut off, and the data voltage DATA(i - 1)j for the (i - 1)-th pixel is prevented from being input to the first pixel PX1.

[0080] At this time, since the fourth transistor T4 is conductive, the first node NP1 is connected to the initialization line INTL, and the voltage of the first node NP1 is initialized. Since a light-emitting signal at a cut-off level is applied to the i-th light-emitting line ELi, the transistors T5 and T6 are cut off, and the situation where the light-emitting diode LD emits light unnecessarily during the application of the initialization voltage can be prevented or reduced.

[0081] Next, the data voltage DATAij for the i-th first pixel PX1 is applied to the j-th data line DLj, and a scan signal at a conductive level is applied to the i-th scan line SLi. Accordingly, the transistors T2, T1, and T3 are conductive, and the j-th data line DLj is electrically connected to the first node NP1. Accordingly, a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node NP1) of the storage capacitor Cst, and the storage capacitor Cst holds a voltage corresponding to the difference between the first power supply voltage and the compensation voltage. This period may be referred to as a threshold voltage compensation period.

[0082] At this time, since the seventh transistor T7 is turned on, the anode of the light-emitting diode LD is connected to the initialization line INTL, and the light-emitting diode LD is initialized to a charge amount corresponding to the voltage difference between the initialization voltage and the second power supply voltage.

[0083] Thereafter, when a light-emitting signal of a conduction level is applied to the i-th light-emitting line ELi, the transistors T5 and T6 can be turned on. Accordingly, a drive current path of the first power supply line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light-emitting diode LD, and the second power supply line ELVSSL is formed.

[0084] The amount of drive current flowing through the first electrode and the second electrode of the first transistor T1 is adjusted according to the voltage held in the storage capacitor Cst. The light-emitting diode LD emits light having a luminance corresponding to the amount of drive current. The light-emitting diode LD emits light until a light-emitting signal of a cut-off level is applied to the i-th light-emitting line ELi.

[0085] Figure 4 is a diagram showing a case where the second pixel region is in an unfolded state, and Figure 5 is a diagram showing a case where the second pixel region is in a folded state.

[0086] As described above, the first pixel region AR1 and the second pixel region AR2 may be in contact with the first boundary EDG1, and the second pixel region AR2 and the third pixel region AR3 may be in contact with the second boundary EDG2.

[0087] Referring to Figure 4 , the relative positional relationship among the pixel regions AR1, AR2, and AR3 may be defined based on the unfolded state of the display device 10. The second pixel region AR2 may be positioned in the first direction DR1 from the first pixel region AR1. The third pixel region AR3 may be positioned in the first direction DR1 from the second pixel region AR2. The first pixel region AR1, the second pixel region AR2, and the third pixel region AR3 may have a planar shape defined based on the first direction DR1 and the second direction DR2. At this time, the third direction DR3 may be the image display direction of the first pixel region AR1, the second pixel region AR2, and the third pixel region AR3. The first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other. The first boundary EDG1, the second boundary EDG2, and the folding axis FAX may extend in the second direction DR2.

[0088] The configuration of the display device 10 described above may be changed according to an embodiment. For example, in the case of a circular display, Figure 4Differently, each of the pixel regions AR1, AR2, and AR3 may include a curved surface in the unfolded state.

[0089] In the unfolded state of the display device 10, all the pixel regions AR1, AR2, and AR3 may display images. At this time, the image displayed in the first pixel region AR1 and the image displayed in the second pixel region AR2 may be seamless at the first boundary EDG1. In addition, the image displayed in the second pixel region AR2 and the image displayed in the third pixel region AR3 may be seamless at the second boundary EDG2. The seamlessness of the images at each of the boundaries EDG1 and EDG2 means that continuous letters, graphics, pictures, photos, videos, numbers, hues, colors, patterns, etc. may be presented above each of the boundaries EDG1 and EDG2. For example, if a graphic, shape, or pattern extends across a boundary from one region to another region, then if the graphic, shape, or pattern is not distorted and / or the boundary line has no perceivable visibility, the graphic, shape, or pattern extends across the boundary and is seamlessly displayed between different regions. Therefore, the boundaries EDG1 and EDG2 can be prevented from being recognized by the user.

[0090] In the unfolded state of the display device 10, all the pixel regions AR1, AR2, and AR3 may update images at the same period. That is, the driving frequencies of all the pixel regions AR1, AR2, and AR3 may be equal to each other.

[0091] Referring to Figure 5 , a case where the second pixel region AR2 is folded is shown. The first pixel region AR1 exposed to the user may display an image, and the third pixel region AR3 not exposed to the user may not display an image or may display a black image.

[0092] The second pixel PX2 in the second pixel region AR2 that contacts the first boundary EDG1 may display an image. At this time, the second pixel PX2 that contacts the first boundary EDG1 may refer not only to the second pixel PX2 that directly forms the first boundary EDG1, but also to the first group of second pixels PX2 located within a certain range (for example, a set range or a predetermined range) from the first boundary EDG1. For example, the second pixel PX2 connected to the second scan line other than the scan disconnection line described below may belong to the first group.

[0093] The second pixel PX2 in the second pixel region AR2 that contacts the second boundary EDG2 may not display an image or may display a black image. At this time, the second pixel PX2 that contacts the second boundary EDG2 may refer not only to the second pixel PX2 that directly forms the second boundary EDG2, but also to the second pixel PX2 of the second group positioned within a certain range (e.g., a set range or a predetermined range) from the second boundary EDG2. For example, the second pixel PX2 connected to a scan disconnection line described below may belong to the second group.

[0094] The second pixel PX2 of the first group and the second pixel PX2 of the second group described above do not overlap with each other. However, as will be described below, the number of scan disconnection lines in the second scan line may change, and at this time, the number of the second pixel PX2 of the first group and the number of the second pixel PX2 of the second group may also change.

[0095] According to this embodiment, while the second pixel region AR2 remains in a folded state, the image displayed in the second pixel region AR2 may be scaled one or more times. At this time, the first pixel region AR1 may display an unscaled image. At this time, the image displayed in the first pixel region AR1 and the image displayed in the second pixel region AR2 may be seamless at the first boundary EDG1.

[0096] When the image displayed in the second pixel region AR2 is scaled, the boundary between the second pixel PX2 of the first group and the second pixel PX2 of the second group may shift in the second pixel region AR2. That is, the boundary between the image display region and the image non-display region (or black display region) may shift in the second pixel region AR2 at periodic or non-periodic time intervals. Therefore, the degree of deterioration of the pixels in the second pixel region AR2 can be dispersed, and the user can be prevented from visually recognizing the boundary between the image display region and the image non-display region.

[0097] While the second pixel region AR2 remains in a folded state, the first pixel PX1 and the second pixel PX2 that contacts the first boundary EDG1 may update the image at a first period. At this time, the third pixel PX3 and the second pixel PX2 that contacts the second boundary EDG2 may update the image at a second period. At this time, the first period may be shorter than the second period. That is, the third pixel PX3 and the second pixel PX2 of the second group may be driven at a lower driving frequency than the first pixel PX1 and the second pixel PX2 of the first group. Since the third pixel PX3 and the second pixel PX2 of the second group display a black image (or other still image) or do not display an image, even if the driving frequency is reduced, the image is not visually recognized as defective by the user. Therefore, the power consumption of the display device 10 can be reduced.

[0098] Figure 6 is a diagram showing an image scaling unit according to an embodiment of the present disclosure. Figures 7 to 10 is a diagram showing a scaling method for shifting an image of a second pixel region in a first direction according to another embodiment of the present disclosure. Figure 11 and Figure 12 is a diagram showing a scaling method for shifting an image of a second pixel region in a direction opposite to the first direction according to another embodiment of the present disclosure.

[0099] Referring to Figure 6 , an image scaling unit 16 according to an embodiment of the present disclosure may include a frame counter 161, a shift direction determination unit 162, a first window definition unit 163, a first data configuration unit 164, and a first data operation unit 165.

[0100] The frame counter 161 may check which frame the first image IMG1, which is a display target of the second pixel region AR2, corresponds to. For example, the frame counter 161 may output the frame number FRn of the target frame based on the vertical synchronization signal Vsync. The vertical synchronization signal Vsync may be a control signal indicating the end of data supply for the previous frame and the start of data supply for the current frame. For example, the vertical synchronization signal Vsync may be in the form of a pulse, and the generation period of the pulse of the vertical synchronization signal Vsync may be the same as the period of the frame. Therefore, the frame counter 161 may check the number of the frame corresponding to the first image IMG1 by counting the pulses of the vertical synchronization signal Vsync.

[0101] Referring to Figure 7 , as an example, a display device 10 that displays the first image IMG1 in a folded state is shown. For ease of comparative explanation, it may be assumed that Figure 7 the display device 10 displays an image in the previous frame. For example, an external processor may provide gray level values corresponding to the first image IMG1 during the previous frame period. In addition, the external processor may provide gray level values corresponding to the first image IMG1 again during the current frame period.

[0102] Second pixels PX21 and PX22 in contact with the first boundary EDG1 may display a seamless image and the image displayed in the first pixel region AR1. Second pixels PX23, PX24, and PX25 adjacent to the second boundary EDG2 may display a black image or may not display an image. The third pixel region AR3 may display a black image or may not display an image.

[0103] Hereinafter, the area, width, length, etc. of each pixel are related to the light-emitting region of the pixel and are independent of the pixel circuit. The area, width, length, etc. of the light-emitting region of the pixel can be changed according to the color of the pixel. However, for the sake of description, it is assumed that the widths W1 of the second pixels PX21, PX22, PX23, PX24, and PX25 are all equal to each other. It is assumed that the width direction refers to the first direction DR1, and the length direction refers to the second direction DR2.

[0104] The shift direction determination unit 162 can determine the shift direction and shift amount of the first image IMG1 and output first shift information SHF1 (for example, the first shift information SHF11, SHF12, and SHF13 in the following respective embodiments). The first shift information SHF1 corresponding to the frame number FRn can be stored in a separate look-up table (LUT) or the like.

[0105] The shift direction can be the first direction DR1 or the direction opposite to the first direction DR1. The shift amount can be less than the width W1 of one pixel. For example, the shift amount can correspond to approximately 1 / 32 of the pixel width W1. However, for the sake of description, in Figures 7 to 12 the shift amount may be exaggerated.

[0106] For example, in Figure 8 and Figure 9 of the embodiment, the shift direction of the first shift information SHF11 can be the first direction DR1, and the shift amount can be approximately 1 / 4 of the pixel width W1. For example, in Figure 10 of the embodiment, the shift direction of the first shift information SHF12 can be the first direction DR1, and the shift amount can be approximately 2 / 4 of the pixel width W1. For example, in Figure 11 and Figure 12 of the embodiment, the shift direction of the first shift information SHF13 is the direction opposite to the first direction DR1, and the shift amount can be approximately 1 / 4 of the pixel width W1.

[0107] The first window definition unit 163 can divide the first image IMG1 into a first image region IMA1, a second image region IMA2, and a third image region IMA3 based on the first shift information SHF1. The first image region IMA1 can be the region in the first image IMG1 that is in contact with and displayed along the first boundary EDG1. The second image region IMA2 can be the region in the first image IMG1 that is in contact with and displayed along the second boundary EDG2. The third image region IMA3 can be the region between the first image region IMA1 and the second image region IMA2.

[0108] The first window definition unit 163 may determine whether to designate the first image area IMA1 as an enlarged area or a reduced area according to the shift direction of the first shift information SHF1.

[0109] For example, as shown in the embodiments of Figure 8 and Figure 9 , when the first shift direction SHF11 is the first direction DR1, the first image area IMA1 may be designated as an enlarged area. In this case, the second image area IMA2 may be designated as a reduced area. The third image area IMA3 may be a non-scaled area regardless of the first shift direction SHF1.

[0110] In addition, in the embodiments of Figure 10 , since the shift direction of the first shift information SHF12 is the first direction DR1, the first image area IMA1 may be designated as an enlarged area, the second image area IMA2 may be designated as a reduced area, and the third image area IMA3 may be a non-scaled area.

[0111] Meanwhile, as shown in the embodiments of Figure 11 and Figure 12 , when the shift direction of the first shift information SHF13 is a direction opposite to the first direction DR1, the first image area IMA1 may be designated as a reduced area, the second image area IMA2 may be designated as an enlarged area, and the third image area IMA3 may be a non-scaled area.

[0112] Pixels windows PW1 to PW5 will be described based on the embodiments of Figure 8 and Figure 9 . The non-scaled area (the third image area IMA3) may include pixels windows PW2, PW3, and PW4 having the same width W1 as the width W1 of the second pixels PX21 to PX25. The enlarged area (the first image area IMA1) may include a pixels window PW1 having a width W2 smaller than the width W1 of the second pixels PX21 to PX25. The reduced area (the second image area IMA2) may include a pixels window PW5 having a width W3 larger than the width W1 of the second pixels PX21 to PX25.

[0113] The number of pixels windows PW1 to PW5 and the number of the second pixels PX21 to PX25 may be equal to each other. The sum of the widths of pixels windows PW1 to PW5 and the sum of the widths of the second pixels PX21 to PX25 may be equal to each other. The total area of pixels windows PW1 to PW5 may be equal to the total area of the second pixels PX21 to PX25. For example, pixels windows PW1 to PW5 may completely overlap with the second pixels PX21 to PX25.

[0114] The first window definition unit 163 may determine the sizes of the first image area IMA1 and the second image area IMA2 according to the shift amount of the first shift information SHF1. For example, as the shift amount increases, the first image area IMA1 and the second image area IMA2 may become larger. Accordingly, as the shift amount increases, the third image area IMA3 may become smaller.

[0115] A relatively large first image area IMA1 means that the number of pixel windows included in the first image area IMA1 is relatively large. For example, in an embodiment where the shift amount is relatively small Figure 8 and Figure 9 the first image area IMA1 may include five pixel windows PW1. For example, in an embodiment where the shift amount is relatively large Figure 10 the first image area IMA1 may include ten pixel windows PW1 and PW2.

[0116] A relatively large second image area IMA2 means that the number of pixel windows included in the second image area IMA2 is relatively large. For example, in an embodiment where the shift amount is relatively small Figure 8 and Figure 9 the second image area IMA2 may include five pixel windows PW5. For example, in an embodiment where the shift amount is relatively large Figure 10 the second image area IMA2 may include ten pixel windows PW4 and PW5.

[0117] A relatively small third image area IMA3 means that the number of pixel windows included in the third image area IMA3 is relatively small. For example, in an embodiment where the shift amount is relatively small Figure 8 and Figure 9 the third image area IMA3 may include 15 pixel windows PW2, PW3, and PW4. For example, in an embodiment where the shift amount is relatively large Figure 10 the third image area IMA3 may include five pixel windows PW3.

[0118] In this way, the first window definition unit 163 may provide the first window definition information DW1 to the pixel windows PW1 to PW5 based on the first shift information SHF1. For example, Figure 8 the first window definition information DW11 may indicate that each window row sequentially includes one pixel window PW1 having a width W2, three pixel windows PW2, PW3, and PW4 having a width W1, and one pixel window PW5 having a width W3 along the first direction DR1. For example, Figure 10The first window definition information DW12 can indicate that each window row sequentially includes two pixel windows PW1 and PW2 with a width of W2, one pixel window PW3 with a width of W1, and two pixel windows PW4 and PW5 with a width of W3 along the first direction DR1. For example, Figure 11 The first window definition information DW13 can indicate that each window row sequentially includes one pixel window PW1 with a width of W3, three pixel windows PW2, PW3, and PW4 with a width of W1, and one pixel window PW5 with a width of W2 along the first direction DR1.

[0119] The first data configuration unit 164 can provide the first data configuration information DC1 by determining the source image region corresponding to each of the pixel windows PW1 to PW5 based on the first window definition information DW1. At this time, the first data configuration unit 164 can be in a state where specific gray level values for each source image region are not provided to the first data configuration unit 164.

[0120] Hereinafter, the operation of the first data configuration unit 164 will be described with reference to Figure 8 the embodiments of

[0121] Equation 1

[0122] DC1[PW1] = (GD[PX21] × W2) / W2 = GD[PX21]

[0123] Here, DC1[PW1] can be the first data configuration information DC1 for the pixel window PW1, and GD[PX21] can be the gray level value of the second pixel PX21.

[0124] Similarly, the first data configuration information DC1 for the pixel window PW2 can be provided as in Equation 2 below.

[0125] Equation 2

[0126] DC1[PW2] = (GD[PX21] × W1 × 1 / 4 + GD[PX22] × W1 × 3 / 4) / W1 = GD[PX21] × 1 / 4 + GD[PX22] × 3 / 4

[0127] Here, DC1[PW2] can be the first data configuration information DC1 for the pixel window PW2, GD[PX21] can be the gray level value of the second pixel PX21, and GD[PX22] can be the gray level value of the second pixel PX22.

[0128] Similarly, the first data configuration information DC1 for the pixel window PW3 can be provided as in Equation 3 below.

[0129] Equation 3

[0130] DC1[PW3] = (GD[PX22] × W1 × 1 / 4 + GD[PX23] × W1 × 3 / 4) / W1 = GD[PX22] × 1 / 4 + GD[PX23] × 3 / 4

[0131] Here, DC1[PW3] can be the first data configuration information DC1 for the pixel window PW3, GD[PX22] can be the gray - level value of the second pixel PX22, and GD[PX23] can be the gray - level value of the second pixel PX23.

[0132] Similarly, the first data configuration information DC1 for the pixel window PW4 can be provided as in Equation 4 below.

[0133] Equation 4

[0134] DC1[PW4] = (GD[PX23] × W1 × 1 / 4 + GD[PX24] × W1 × 3 / 4) / W1 = GD[PX23] × 1 / 4 + GD[PX24] × 3 / 4

[0135] Here, DC1[PW4] can be the first data configuration information DC1 for the pixel window PW4, GD[PX23] can be the gray - level value of the second pixel PX23, and GD[PX24] can be the gray - level value of the second pixel PX24.

[0136] Similarly, the first data configuration information DC1 for the pixel window PW5 can be provided as in Equation 5 below.

[0137] Equation 5

[0138] DC1[PW5] = (GD[PX24] × W1 × 1 / 4 + GD[PX25] × W1) / W3 = GD[PX24] × 1 / 5 + GD[PX25] × 4 / 5

[0139] Here, DC1[PW5] can be the first data configuration information DC1 for the pixel window PW5, GD[PX24] can be the gray - level value of the second pixel PX24, and GD[PX25] can be the gray - level value of the second pixel PX25.

[0140] In this way, the information of the second pixels PX21 to PX25 overlapping with their respective pixel windows PW1 to PW5 and the information of the weights corresponding to the overlapping ratios can be provided as the first data configuration information DC1.

[0141] The first data operation unit 165 can generate the gray-level value of the second image IMG2 by inserting the gray-level value of the first image IMG1 into the first data configuration information DC1. Refer to Figure 9 , a situation is shown where the display device 10 displays the converted second image IMG2. DC1[PW1] of Equation 1 can become the converted gray-level value of the second pixel PX21. Similarly, DC1[PW2] of Equation 2 can become the converted gray-level value of the second pixel PX22. Similarly, DC1[PW3] of Equation 3, DC1[PW4] of Equation 4, and DC1[PW5] of Equation 5 can respectively become the converted gray-level value of the second pixel PX23, the converted gray-level value of the second pixel PX24, and the converted gray-level value of the second pixel PX25.

[0142] It can be assumed that in the first image IMG1, the second pixels PX23, PX24, and PX25 display a black gray-level, and the second pixels PX21 and PX22 display a white gray-level.

[0143] Referring to the second image IMG2 converted by the image scaling unit 16 according to the present embodiment, the second pixel PX23 has a gray-level that is brighter than the black gray-level and darker than the white gray-level, and thus, there is an effect that the image displayed in the second pixel region AR2 is shifted in the first direction DR1. For example, as the first image region IMA1 and the second image region IMA2 increase, the display region of the second pixel region AR2 increases, and the non-display region (or black display region) decreases. If the shift amount is large enough, the second pixel PX23 can display a white gray-level.

[0144] Refer to Figure 11 and Figure 12 , there is an effect that the image displayed in the second pixel region AR2 is shifted in the direction opposite to the first direction DR1. For example, as the first image region IMA1 and the second image region IMA2 increase, the display region of the second pixel region AR2 decreases, and the non-display region (or black display region) increases. If the shift amount is large enough, the second pixel PX22 can display a black gray-level.

[0145] Therefore, even if the external processor provides the same first image IMG1 in consecutive frames, the degree of deterioration of the second pixel PX2 can be dispersed in the second pixel region AR2, and the user can be prevented from visually recognizing the boundary between the image display region and the image non-display region.

[0146] In addition, the first data operation unit 165 may provide a scan disconnection line number OFFn based on the gray level value of the second image IMG2. For example, the scan disconnection line number OFFn may be the smallest number among the numbers of consecutive scan lines when the gray level values of the second pixels PX2 connected to the consecutive scan lines are all black gray level values. For example, in Figure 7 and Figure 12 , the number OFF1 of the scan line connected to the second pixel PX23 may be the scan disconnection line number OFFn. For example, in Figure 9 , the number OFF2 of the scan line connected to the second pixel PX24 may be the scan disconnection line number OFFn.

[0147] According to an embodiment, a margin value may be added to the scan disconnection line number OFFn. For example, when the margin value is 1, the number of the scan line connected to the second pixel PX24 may be the scan disconnection line number OFFn in Figure 7 and Figure 12 . For example, in Figure 9 , the number of the scan line connected to the second pixel PX25 may be the scan disconnection line number OFFn. The margin value may be appropriately selected within the range where defects do not appear according to the specifications of the display device 10.

[0148] Figure 13 is a diagram showing a scan disconnection unit according to an embodiment of the present disclosure.

[0149] Referring to Figure 13 , the scan disconnection unit 17 according to an embodiment of the present disclosure may include a clock counter 171 and a multiplexer 172.

[0150] The clock counter 171 may increase a count value by counting pulses of a clock signal CLK2, and may turn on a first switch SW1 and turn off a second switch SW2 in response to a control signal SWC at a time point when the count value corresponds to the scan disconnection line number OFFn.

[0151] The multiplexer 172 may include a first switch SW1 and a second switch SW2. When the first switch SW1 is turned on, the multiplexer 172 may output the clock signal CLK2 as a second clock signal CLK2'. When the second switch SW2 is turned on, the multiplexer 172 may output a second high voltage VDD2 as the second clock signal CLK2'.

[0152] In Figure 13In the embodiments described below, it is described that the scan disconnect unit 17 adjusts the second clock signal CLK2’, but in another embodiment, the scan disconnect unit 17 may be configured to adjust the first clock signal. In still another embodiment, the scan disconnect unit 17 may be configured to adjust both the first clock signal and the second clock signal CLK2’.

[0153] Figures 14 to 18 is a diagram showing an example operation of the scan disconnect unit.

[0154] Referring to Figure 14 , the scan driving unit 13 according to an embodiment of the present disclosure may include a plurality of scan stages SST1 to SST4. Each of the scan stages SST1 to SST4 is connected to one of the scan lines SL1 to SL4 and is driven in response to the clock signals CLK1 and CLK2’. The scan stages SST1 to SST4 may be implemented by the same circuit.

[0155] Each of the scan stages SST1 to SST4 includes a first input terminal 1001, a second input terminal 1002, a third input terminal 1003, and an output terminal 1004.

[0156] The first input terminal 1001 of each of the scan stages SST1 to SST4 receives the output signal (i.e., the scan signal) of the previous scan stage or the scan start signal SSP. For example, the first input terminal 1001 of the first scan stage SST1 receives the scan start signal SSP, and the first input terminals 1001 of the remaining scan stages SST2 to SST4 receive the output signal of the previous stage.

[0157] The second input terminal 1002 of the jth (j is odd or even) scan stage SSTj (not shown) receives the first clock signal CLK1, and the third input terminal 1003 receives the second clock signal CLK2’. The second input terminal 1002 of the (j + 1)th scan stage SSTj+1 receives the second clock signal CLK2’, and the third input terminal 1003 of the (j + 1)th scan stage SSTj+1 receives the first clock signal CLK1.

[0158] The first clock signal CLK1 and the second clock signal CLK2’ have the same period, and the phases of the first clock signal CLK1 and the second clock signal CLK2’ do not overlap with each other. For example, when the period during which the scan signal is supplied to one scan line is referred to as one horizontal period 1H, each of the clock signals CLK1 and CLK2 has a period of 2H, and each of the clock signals CLK1 and CLK2 is supplied in different horizontal periods.

[0159] In addition, each of the scan levels SST1 to SST4 receives a first high voltage VDD1 and a low voltage VSS. Here, the first high voltage VDD1 may be set to a gate cutoff voltage, for example, a logic high voltage. Additionally, the low voltage VSS may be set to a gate conduction voltage, for example, a logic low voltage.

[0160] Figure 15 shows an Figure 14 example of the scan level shown in. In Figure 15 order to facilitate description, the first scan level SST1 and the second scan level SST2 are shown.

[0161] Referring to Figure 15 , the first scan level SST1 according to an embodiment of the present disclosure includes a first driving unit 1210, a second driving unit 1220, an output unit 1230 (or buffer), and a first transistor M1.

[0162] The output unit 1230 controls the voltage supplied to the output terminal 1004 in response to the voltages of the first node N1 and the second node N2. To this end, the output unit 1230 includes a fifth transistor M5 and a sixth transistor M6.

[0163] The fifth transistor M5 is positioned between the first high voltage VDD1 and the output terminal 1004, and the gate electrode of the fifth transistor M5 is connected to the first node N1. The fifth transistor M5 controls the connection between the first high voltage VDD1 and the output terminal 1004 in response to the voltage applied to the first node N1.

[0164] The sixth transistor M6 is positioned between the output terminal 1004 and the third input terminal 1003, and the gate electrode of the sixth transistor M6 is connected to the second node N2. The sixth transistor M6 controls the connection between the output terminal 1004 and the third input terminal 1003 in response to the voltage applied to the second node N2. The output unit 1230 operates as a buffer. Additionally, the fifth transistor M5 and / or the sixth transistor M6 may be configured by a plurality of transistors connected in parallel.

[0165] The first driving unit 1210 controls the voltage of the third node N3 in response to the signals supplied to the first input terminal 1001 to the third input terminal 1003. To this end, the first driving unit 1210 includes second transistors M2 to M4.

[0166] The second transistor M2 is positioned between the first input terminal 1001 and the third node N3, and the gate electrode of the second transistor M2 is connected to the second input terminal 1002. The second transistor M2 controls the connection between the first input terminal 1001 and the third node N3 in response to the signal supplied to the second input terminal 1002.

[0167] The third transistor M3 and the fourth transistor M4 are connected in series between the third node N3 and the first high voltage VDD1. In fact, the third transistor M3 is positioned between the fourth transistor M4 and the third node N3, and the gate electrode of the third transistor M3 is connected to the third input terminal 1003. The third transistor M3 controls the connection between the fourth transistor M4 and the third node N3 in response to the signal supplied to the third input terminal 1003.

[0168] The fourth transistor M4 is positioned between the third transistor M3 and the first high voltage VDD1, and the gate electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 controls the connection between the third transistor M3 and the first high voltage VDD1 in response to the voltage of the first node N1.

[0169] The second driving unit 1220 controls the voltage of the first node N1 in response to the voltages of the second input terminal 1002 and the third node N3. For this purpose, the second driving unit 1220 includes a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

[0170] The first capacitor C1 is connected between the second node N2 and the output terminal 1004. The first capacitor C1 is charged with a voltage corresponding to the conduction and cutoff of the sixth transistor M6.

[0171] The second capacitor C2 is connected between the first node N1 and the first high voltage VDD1. The second capacitor C2 is charged with the voltage applied to the first node N1.

[0172] The seventh transistor M7 is positioned between the first node N1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 is connected to the third node N3. The seventh transistor M7 controls the connection between the first node N1 and the second input terminal 1002 in response to the voltage of the third node N3.

[0173] The eighth transistor M8 is positioned between the first node N1 and the low voltage VSS, and the gate electrode of the eighth transistor M8 is connected to the second input terminal 1002. The eighth transistor M8 controls the connection between the first node N1 and the low voltage VSS in response to the signal of the second input terminal 1002.

[0174] The first transistor M1 is positioned between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 is connected to the low voltage VSS. While the first transistor M1 remains in the on state, the electrical connection between the third node N3 and the second node N2 is maintained. Additionally, the first transistor M1 limits the voltage drop width of the third node N3 in response to the voltage of the second node N2. In other words, even if the voltage of the second node N2 drops to a voltage lower than the low voltage VSS, the voltage of the third node N3 does not drop to a voltage lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the low voltage VSS. A detailed description thereof will be given below.

[0175] Figure 16 is a waveform diagram showing an embodiment of a method for driving Figure 15 the scan stage shown therein. In Figure 16 order to facilitate the description, the operation process will be described by using the first scan stage SST1.

[0176] Referring to Figure 16 , the first clock signal CLK1 and the second clock signal CLK2' have a period of two horizontal periods 2H, and the first clock signal CLK1 and the second clock signal CLK2' are supplied in different horizontal periods. In other words, the second clock signal CLK2' is set to a signal shifted by half a period (i.e., one horizontal period) from the first clock signal CLK1. Additionally, the scan start signal SSP supplied to the first input terminal 1001 is supplied synchronously with the clock signal (i.e., the first clock signal CLK1) supplied to the second input terminal 1002.

[0177] Furthermore, when the scan start signal SSP is supplied, the first input terminal 1001 can be set to the low voltage VSS, and when the scan start signal SSP is not supplied, the first input terminal 1001 can be set to the high voltage VDD1. Additionally, when the clock signal CLK is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to the low voltage VSS, and when the clock signal CLK is not supplied, the second input terminal 1002 and the third input terminal 1003 can be set to the first high voltage VDD1.

[0178] Specifically, the scan start signal SSP is supplied synchronously with the first clock signal CLK1.

[0179] When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. When the second transistor M2 is turned on, the first input terminal 1001 is electrically connected to the third node N3. Here, since the first transistor M1 is always set to the on state, the electrical connection between the second node N2 and the third node N3 is maintained.

[0180] When the first input terminal 1001 is electrically connected to the third node N3, the third node N3 and the second node N2 are set to a low voltage by the scan start signal SSP supplied to the first input terminal 1001. If the third node N3 and the second node N2 are set to the low voltage VSS, the sixth transistor M6 and the seventh transistor M7 are turned on.

[0181] When the sixth transistor M6 is turned on, the third input terminal 1003 is electrically connected to the output terminal 1004. Here, the third input terminal 1003 is set to a high voltage (i.e., the second clock signal CLK2' is not supplied), and thus, the high voltage is also output to the output terminal 1004. When the seventh transistor M7 is turned on, the second input terminal 1002 is electrically connected to the first node N1. Then, the voltage of the first clock signal CLK1 supplied to the second input terminal 1002 (i.e., the low voltage) is supplied to the first node N1.

[0182] In addition, when the first clock signal CLK1 is supplied, the eighth transistor M8 is turned on. When the eighth transistor M8 is turned on, the low voltage VSS is supplied to the first node N1. Here, the low voltage VSS is set to the same (or similar) voltage as the first clock signal CLK1, and thus, the first node N1 stably holds the low voltage.

[0183] When the first node N1 is set to the low voltage VSS, the fourth transistor M4 and the fifth transistor M5 are turned on. If the fourth transistor M4 is turned on, the first high voltage VDD1 is electrically connected to the third transistor M3. Here, since the third transistor M3 is set to the cut-off state, even if the fourth transistor M4 is turned on, the third node N3 stably holds the low voltage VSS. If the fifth transistor M5 is turned on, the first high voltage VDD1 is supplied to the output terminal 1004. Here, the first high voltage VDD1 is set to the same voltage as the high voltage supplied to the third input terminal 1003, and thus, the output terminal 1004 stably holds the high voltage.

[0184] Thereafter, the supply of the scan start signal SSP and the first clock signal CLK1 stops. If the supply of the first clock signal CLK1 stops, the second transistor M2 and the eighth transistor M8 are turned off. At this time, the sixth transistor M6 and the seventh transistor M7 remain in the on state in response to the voltage stored in the first capacitor C1. That is, due to the voltage stored in the first capacitor C1, the second node N2 and the third node N3 hold the low voltage VSS.

[0185] When the sixth transistor M6 remains in the conductive state, the electrical connection between the output terminal 1004 and the third input terminal 1003 is maintained. When the seventh transistor M7 remains in the conductive state, the electrical connection between the first node N1 and the second input terminal 1002 is maintained. Here, in response to the supply stop of the first clock signal CLK1, the voltage of the second input terminal 1002 is set to a high voltage, and thus, the first node N1 is also set to a high voltage. If a high voltage is supplied to the first node N1, the fourth transistor M4 and the fifth transistor M5 are turned off.

[0186] Thereafter, the second clock signal CLK2' is supplied to the third input terminal 1003. At this time, since the sixth transistor M6 is set to the conductive state, the second clock signal CLK2' supplied to the third input terminal 1003 is supplied to the output terminal 1004. In this case, the output terminal 1004 outputs the second clock signal CLK2' as a scan signal to the first scan line SL1.

[0187] Meanwhile, when the second clock signal CLK2' is supplied to the output terminal 1004, due to the coupling of the first capacitor C1, the voltage of the second node N2 drops to a voltage lower than the low voltage VSS, and thus, the sixth transistor M6 stably remains in the conductive state.

[0188] On the other hand, even if the voltage of the second node N2 drops, the voltage of the third node N3 is maintained at approximately the low voltage VSS (e.g., the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the low voltage VSS) through the first transistor M1.

[0189] After the scan signal is output to the first scan line SL1, the supply of the second clock signal CLK2' stops. If the supply of the second clock signal CLK2' stops, the output terminal 1004 outputs a high voltage. In addition, the voltage of the second node N2 rises to approximately the low voltage VSS in response to the high voltage of the output terminal 1004.

[0190] Thereafter, the first clock signal CLK1 is supplied. If the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. If the second transistor M2 is turned on, the first input terminal 1001 is electrically connected to the third node N3. At this time, the first input terminal 1001 is not supplied with the scan start signal SSP, and thus, the first input terminal 1001 is set to a high voltage. Therefore, if the first transistor M1 is turned on, a high voltage is supplied to the third node N3 and the second node N2, and thus, the sixth transistor M6 and the seventh transistor M7 are turned off.

[0191] If the eighth transistor M8 is turned on, a low voltage VSS is supplied to the first node N1, and thereby, the fourth transistor M4 and the fifth transistor M5 are turned on. If the fifth transistor M5 is turned on, a high voltage VDD1 is supplied to the output terminal 1004. Thereafter, the fourth transistor M4 and the fifth transistor M5 remain turned on in response to the voltage charged in the second capacitor C2, and thereby, the output terminal 1004 is stably supplied with the first high voltage VDD1.

[0192] In addition, when the second clock signal CLK2’ is supplied, the third transistor M3 is turned on. At this time, since the fourth transistor M4 is set to the turned-on state, the first high voltage VDD1 is supplied to the third node N3 and the second node N2. In this case, the sixth transistor M6 and the seventh transistor M7 are stably kept in the off state.

[0193] The second scan stage SST2 receives the output signal (i.e., the scan signal) of the first scan stage SST1 to be synchronized with the second clock signal CLK2’. In this case, the second scan stage SST2 outputs the scan signal to the second scan line SL2 to be synchronized with the first clock signal CLK1. While repeating the above process, the scan stages SST1 to SST4 sequentially output the scan signal to the scan lines.

[0194] Referring to Figure 17 , assume a case where the scan line corresponding to the scan disconnection line number OFFn is the q-th scan line SLq. The clock counter 171 can detect, within the horizontal period HP(q - 2), a count value corresponding to the scan disconnection line number OFFn. Therefore, the clock counter 171 can turn off the first switch SW1 and turn on the second switch SW2 in response to the control signal SWC. Therefore, starting from the horizontal period HP(q - 1), the second high voltage VDD2 can be output as the second clock signal CLK2’. For example, the first high voltage VDD1 and the second high voltage VDD2 can have the same voltage level. Therefore, in the horizontal period HPq, the q-th scan stage may not output a scan signal of a conductive level to the q-th scan line SLq. In addition, in the corresponding period, scan stages having numbers greater than q may not output a scan signal of a conductive level to the scan lines. In the present embodiment, the scan lines from the q-th scan line SLq to the last scan line in the second scan line can be defined as scan disconnection lines. That is, while the second pixel region AR2 remains in the folded state, the supply of a scan signal of a conductive level to the scan disconnection lines, which are part of the second scan line, can be stopped for at least one frame period.

[0195] However, while the second pixel region AR2 remains in the folded state, the number of scan disconnect lines can be changed one or more times. This is because, while the second pixel region AR2 remains in the folded state, the scan disconnect line number OFFn can be changed one or more times according to the operation of the image scaling unit 16. However, in order to change the scan disconnect line number OFFn, the amount of image shift in the second pixel region AR2 may need to be large enough. Therefore, the number of times the scan disconnect lines are changed can be equal to or less than the number of times the image displayed in the second pixel region AR2 is scaled.

[0196] Referring Figure 18 , four exemplary consecutive frame periods FPN, FP(N + 1), FP(N + 2), and FP(N + 3) are shown.

[0197] Scan lines SL1 to SL(q - 1) can supply a scan signal of a conductive level during four consecutive frame periods FPN, FP(N + 1), FP(N + 2), and FP(N + 3). At the same time, scan lines SLq to SLm can supply a scan signal of a conductive level only during two frame periods FP(N + 1) and FP(N + 3) out of the four consecutive frame periods FPN, FP(N + 1), FP(N + 2), and FP(N + 3) according to the operation of the scan disconnect unit 17.

[0198] In this case, a first period, which is an image update period of pixels connected to scan lines SL1 to SL(q - 1), can be shorter than a second period, which is a pixel update period of pixels connected to scan lines SLq to SLm. That is, a first driving frequency of pixels connected to scan lines SL1 to SL(q - 1) can be greater than a second driving frequency of pixels connected to scan lines SLq to SLm.

[0199] Since pixels connected to scan lines SLq to SLm display a black image (or other static image) or do not display an image, even if the driving frequency is relatively low, the image is not visually recognized as a defect by the user. Therefore, the power consumption of the display device 10 can be reduced.

[0200] In addition, as described above, while the second pixel region AR2 remains in the folded state, the optimal scan disconnect line number OFFn can be updated by the image scaling unit 16, and the power consumption of the display device 10 can be more effectively reduced. For example, in Figure 18 the embodiment, it is assumed that the scan disconnect line number OFFn corresponds to the q-th scan line SLq, but the scan disconnect line number OFFn can be updated according to image scaling after a certain time (e.g., a set or predetermined time) has elapsed to correspond to the (q - 1)-th scan line SL(q - 1) or the (q + 1)-th scan line SL(q + 1).

[0201] Figure 19 FIG. is a diagram showing an image scaling unit according to another embodiment of the present disclosure. Figure 20 And Figure 21 is a diagram showing Figure 19 an example operation of the image scaling unit.

[0202] Compared with Figure 6 the image scaling unit 16 of Figure 19 the image scaling unit 16' may further include a second window definition unit 163', a second data configuration unit 164' and a second data operation unit 165'.

[0203] The shift direction determination unit 162 is different from Figure 6 the embodiment of

[0204] in that the shift direction determination unit 162 can not only output the first shift information SHF1 of the first image IMG1', but also output the second shift information SHF2. The shift direction of the second shift information SHF2 may be the second direction DR2 or the direction opposite to the second direction DR2.

[0205] Except that the operation direction is the second direction DR2, the second window definition unit 163', the second data configuration unit 164' and the second data operation unit 165' perform substantially the same functions as the first window definition unit 163, the first data configuration unit 164 and the first data operation unit 165, and therefore, redundant descriptions thereof will be omitted and the differences between them will be mainly described. Figure 6 As described above with reference to

[0206] the first data operation unit 165 can convert the first image IMG1' into the second image IMG2'. The second data operation unit 165' can generate the third image IMG3 by converting the second image IMG2' relative to the second direction DR2 based on the second data configuration information DC2.

[0207] In this embodiment, the scan disconnection line number OFFn may be output by the second data operation unit 165' instead of the first data operation unit 165. Figure 7 In this embodiment, compared with

[0208] Therefore, the shift of the third image IMG3 along the second direction DR2 according to the second shift information SHF21 may be important. In addition, the second data operation unit 165' may output the updated scan disconnection line number OFF3 (see Figure 21 ).

[0209] An electronic or electrical device and / or any other related device or component according to an embodiment of the present disclosure described herein may be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or may be formed on a substrate. In addition, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices that execute computer program instructions and interact with other system components for performing the various functions described herein. The computer program instructions are stored in a memory, which may be implemented in a computing device using a standard storage device (such as, by way of example, a random access memory (RAM)). The computer program instructions may also be stored in other non-transitory computer-readable media (such as, by way of example, a CD-ROM or a flash drive, etc.). Additionally, those skilled in the art should recognize that, without departing from the spirit and scope of the exemplary embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed over one or more other computing devices.

[0210] The detailed description of the present disclosure described with reference to the previously mentioned drawings is only an example of the present disclosure, and is only for the purpose of illustrating the present disclosure, and is not used to limit the meaning or scope of the present disclosure described in the present disclosure and its equivalents. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present disclosure will have to be defined by the technical idea of the present disclosure and its equivalents.

Claims

1. A display device, wherein, The display device includes: A first pixel region including first pixels connected to data lines and a first scan line; A second pixel region contacting the first pixel region at a first boundary, and the second pixel region includes second pixels connected to the data lines and a second scan line; and A third pixel region contacting the second pixel region at a second boundary, and the third pixel region includes third pixels connected to the data lines and a third scan line, wherein the display device is configured to: based on the second pixel region remaining in a folded state, scale an image displayed in the second pixel region one or more times, and when the image displayed in the second pixel region is scaled, a boundary between an image display region and an image non-display region shifts in the second pixel region at periodic or non-periodic time intervals.

2. The display device according to claim 1, wherein, The display device is configured to: based on the second pixel region remaining in the folded state, display an unscaled image at the first pixel region.

3. The display device according to claim 2, wherein, The display device is configured to: based on the second pixel region remaining in the folded state, seamlessly display a first image in the first pixel region and a second image in the second pixel region across the first boundary.

4. The display device according to claim 3, wherein, The display device is configured to: based on the second pixel region remaining in the folded state, control the third pixel region not to display an image or to display a black image, and control second pixels in the second pixel region contacting the second boundary not to display the image or to display the black image.

5. The display device according to claim 1, Among them, The display device is configured to magnify an image displayed at a first image region contacting the first boundary, and wherein the display device is configured to reduce an image displayed at a second image region contacting the second boundary.

6. The display device according to claim 5, wherein, When the first image region and the second image region increase, a display region in the second pixel region increases, and a non-display region in the second pixel region decreases.

7. The display device according to claim 1, Among them, The display device is configured to reduce an image displayed at a first image region contacting the first boundary, and wherein the display device is configured to magnify an image displayed at a second image region contacting the second boundary.

8. The display device according to claim 7, wherein, As the first image region and the second image region increase, the display region in the second pixel region decreases, and the non-display region in the second pixel region increases.

9. The display device according to claim 1, Among them, While the second pixel region remains in the folded state, the first pixels and the second pixels contacting the first boundary update images at a first period, and the third pixels and the second pixels contacting the second boundary update images at a second period, and wherein the first period is shorter than the second period.

10. The display device according to claim 1, wherein, While maintaining the folded state in the second pixel region, a scanning signal having a conductive level is stopped from being supplied to a scanning disconnection line that is part of the second scanning line for at least one frame period, and the number of the scanning disconnection lines is changed one or more times, and wherein the number of times the number of the scanning disconnection lines is changed is less than or equal to the number of times the image displayed in the second pixel region is scaled.

Images