Display panel, control method thereof, and display device

Abstract

Embodiments of the present application provide a display panel and a control method thereof, and a display device, which relate to the technical field of display, and can solve the problem of display panel brightness unevenness caused by simultaneous opening of multiple gate lines; the display panel comprises a plurality of pixel driving circuits; the pixel driving circuit comprises a switching transistor, a driving transistor, a detection transistor and a storage capacitor; the gate of the detection transistor is connected with a second scanning end, and the first electrode of the detection transistor is connected with a first control node in the pixel driving circuit; in the display panel, at least two detection signal lines are provided corresponding to the pixel driving circuits in the same column; in the pixel driving circuits in the same column, the pixel driving circuits in adjacent rows are connected with different detection signal lines through the second electrodes of the detection transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a control method thereof and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) display has the advantages of self-illumination, thinness, low power consumption, high contrast, high color gamut, and flexible display. AMOLED (Active-matrix OLED) has been widely used in various electronic devices including computers, mobile phones and other electronic products due to its fast response time, high luminous efficiency, high brightness, wide viewing angle and other advantages.

[0003] For the OLED display panel, in the related technology, the pixel driving circuit with 3T1C structure is adopted, in the process of display, there is a period of simultaneous opening of the gate lines connected with the pixel driving circuits of adjacent rows, that is, there is an overlapping part of the waveforms of the scanning signals received by the gate lines connected with the pixel driving circuits of the rows, which is easy to cause the voltage of the related control nodes in the pixel driving circuit to be unstable, and further causes the poor brightness uniformity of the display panel. SUMMARY

[0004] Embodiments of the present application provide a display panel, a control method thereof and a display device, which can solve the problem of uneven brightness of the display panel caused by the simultaneous opening of multiple gate lines.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] The embodiment of the present application provides a display panel, comprising a plurality of pixel driving circuits; the pixel driving circuit comprises a switching transistor, a driving transistor, a detection transistor and a storage capacitor; the gate of the detection transistor is connected with a second scanning end, and the first electrode of the detection transistor is connected with a first control node in the pixel driving circuit; in the display panel, at least two detection signal lines are provided corresponding to the pixel driving circuits in the same column; in the pixel driving circuits in the same column, the pixel driving circuits in adjacent rows are connected with different detection signal lines through the second electrode of the detection transistor.

[0007] In some embodiments, in the display panel, N detection signal lines are provided corresponding to each column of pixel driving circuits; N is a positive integer greater than or equal to 2.

[0008] In some embodiments, for the pixel driving circuits in the same column and the N detection signal lines corresponding thereto: the N detection signal lines are connected with the second electrode of the detection transistor in the pixel driving circuit in the column in turn periodically.

[0009] In some embodiments, N=2.

[0010] In some embodiments, in the same column pixel driving circuit: the time period when the second scan end connected with the i-th row pixel driving circuit receives the scan signal and the time period when the second scan end connected with the i+N-1-th row pixel driving circuit receives the scan signal have an overlapping area; the time period when the second scan end connected with the i-th row pixel driving circuit receives the scan signal and the time period when the second scan end connected with the i+N-th row pixel driving circuit receives the scan signal have no overlapping area.

[0011] In some embodiments, for the at least two detection signal lines arranged corresponding to the same column pixel driving circuit: each of the detection signal lines is connected with a control unit; the control unit comprises a first switch, a second switch, a sample-and-hold circuit and an analog-to-digital converter; the detection signal line is connected with the sample-and-hold circuit through the first switch, and the sample-and-hold circuit is connected with the analog-to-digital converter; the detection signal line is also connected with a reference voltage end through the second switch.

[0012] In some embodiments, the gate of the switch transistor is connected with the first scan end, the first pole is connected with the data signal end, and the second pole is connected with the gate of the driving transistor; the first pole of the storage capacitor is connected with the gate of the driving transistor, and the second pole is connected with the first control node; the first pole of the driving transistor is connected with the first power voltage end, the second pole is connected with the first control node, and the first control node is connected with the second power voltage end through the light-emitting unit.

[0013] The display device provided by the embodiments of the present application comprises the display panel as described above.

[0014] The control method of the display panel as described above provided by the embodiments of the present application comprises: in the pixel data writing stage in the display period of the display panel: when a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of the row through the detection signal line connected with the row of pixel driving circuits; in the data writing stage and the data writing back stage in the compensation detection period of the display panel: when a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of the row through the detection signal line connected with the row of pixel driving circuits; in the sampling stage in the compensation detection period of the display panel: when a row of pixel driving circuits is turned on, the voltage of the first control node in each pixel driving circuit of the row is collected through the detection signal line connected with the row of pixel driving circuits.

[0015] In some embodiments, when the detection signal line is connected to the sample-and-hold circuit through the first switch, and the sample-and-hold circuit is connected to the analog-to-digital converter; and when the detection signal line is also connected to the reference voltage terminal through the second switch: the inputting of the reference voltage to the first control node in each pixel driving circuit in the row through the detection signal line connected to the row of pixel driving circuits comprises: controlling the second switch connected to the detection signal line to be turned on, while controlling the second switch connected to the remaining detection signal lines and all the first switches to be turned off, so as to input the reference voltage of the reference voltage terminal to the first control node in each pixel driving circuit in the row; and the sampling of the voltage of the first control node in each pixel driving circuit in the row through the detection signal line connected to the row of pixel driving circuits comprises: controlling the first switch connected to the detection signal line to be turned on, while controlling the first switch connected to the remaining detection signal lines and all the second switches to be turned off, so as to sample the voltage of the first control node in each pixel driving circuit in the row.

[0016] The display panel provided by the embodiment of the present application, the control method thereof, and the display device have the following advantages.

[0017] In summary, by connecting the pixel driving circuits in adjacent rows in the same column to different detection signal lines through the detection transistors, when the detection transistors connected to a row of pixel driving circuits are turned on, even if the detection transistors in the pixel driving circuits in the adjacent row of the row are turned on, the current and IR Drop on the detection signal line connected to the row of pixel driving circuits will not increase; and the influence of the turned-on detection transistors in multiple rows of pixel driving circuits on the potential of the first control node is avoided, that is, the accuracy (i.e., the deviation is reduced) of the potential of the first control node in the pixel driving circuit is improved, and thus the display brightness uniformity of the display panel is improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0019] Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in the figure.

[0020] Figure 2 A connection relationship schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in the figure.

[0021] Figure 3 A connection relationship schematic diagram of a column of pixel driving circuits provided by an embodiment of the present application is shown in the figure.

[0022] Figure 4 A connection relationship schematic diagram of a column of pixel driving circuits provided by an embodiment of the present application is shown in the figure.

[0023] Figure 5 A timing diagram of scanning signals of a plurality of rows of pixel driving circuits provided by an embodiment of the present application is shown in the figure.

[0024] Figure 6 A connection relationship schematic diagram of a column of pixel driving circuits provided by an embodiment of the present application is shown in the figure.

[0025] Figure 7 A timing control schematic diagram of a display panel in a display period provided by an embodiment of the present application is shown in the figure.

[0026] Figure 8 A timing control schematic diagram of a display panel in a compensation detection period provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0028] Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0029] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0030] This invention provides a display device, which can be a television, mobile phone, computer, laptop, tablet computer, personal digital assistant (PDA), in-vehicle computer, etc. The display device includes a frame, a display panel disposed within the frame, a circuit board, a display driver IC, and other electronic components.

[0031] The aforementioned display panel can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, etc., and the present invention does not specifically limit it.

[0032] OLED display panels have attracted widespread attention due to their advantages such as self-illumination, thinness, low power consumption, high contrast, wide color gamut, and flexibility, and are hailed as a next-generation display technology. The following embodiments of this invention use the aforementioned OLED display panel as an example to illustrate the invention.

[0033] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. (See reference) Figure 1The display panel 001 includes: a display area 1 (active area, AA; also known as the effective display area) and a peripheral area 2 surrounding the display area 1.

[0034] In addition, such as Figure 1 As shown, the display panel 001 has a plurality of sub-pixels P in the display area 1. These sub-pixels P include at least: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, second color, and third color are three primary colors (e.g., red, green, and blue).

[0035] For ease of explanation, this application uses a matrix arrangement of the aforementioned sub-pixels P as an example. In this case, sub-pixels P arranged in a row along the horizontal direction X are referred to as sub-pixels in the same row; sub-pixels P arranged in a row along the vertical direction Y are referred to as sub-pixels in the same column.

[0036] like Figure 1 As shown, each sub-pixel P in the display area 1 of the display panel 001 is provided with a pixel driving circuit 10; at the same time, the display panel 001 is also provided with multiple gate lines G and multiple data lines D in the display area 1.

[0037] In some embodiments, the same gate line G is connected to the pixel driving circuit 10 located in the same row sub-pixel P, and the same data line D is connected to the pixel driving circuit 10 located in the same column sub-pixel P.

[0038] In addition, such as Figure 1 As shown, the display panel 001 also includes a gate driving circuit 01 connected to the gate line G and a data driving circuit 02 connected to the data line D in the peripheral area 2. The gate driving circuit 01 sequentially activates the pixel driving circuits 10, and when a row of pixel driving circuits 10 is activated, the data driving circuit 02 writes the pixel data voltage to each pixel driving circuit 10 in that row for image display.

[0039] In some embodiments, such as Figure 1 As shown, the gate driving circuit 01 can be disposed in the peripheral region 2 along the extension direction of the gate line G, and the data driving circuit 02 can be disposed in the peripheral region 2 along the extension direction of the data line D.

[0040] In some embodiments, the gate driving circuit 01 can be a GOA (Gate Driver on Array) circuit, that is, the gate driving circuit 01 is directly integrated into the array substrate of the display panel 001. Compared with setting the gate driving circuit 01 as a gate driving IC, setting the gate driving circuit 01 as a GOA circuit can reduce manufacturing costs on the one hand, and narrow the bezel width of the display device on the other hand.

[0041] Regarding the pixel driving circuit 10 described above, in some embodiments, such as Figure 2 As shown, the pixel driving circuit 10 may include a switching transistor T1, a detection transistor T2, a driving transistor T3, and a storage capacitor Cst.

[0042] The gate of switching transistor T1 is connected to the first scan terminal Scan1, and the first terminal of switching transistor T1 is connected to the data signal terminal Data. The second terminal of switching transistor T1 is connected to the gate of driving transistor T3 through the second control node g. The first terminal of storage capacitor Cst is connected to the gate of driving transistor T3 through the second control node g, and the second terminal of storage capacitor Cst is connected to the second terminal of driving transistor T3 through the first control node s. The first terminal of driving transistor T3 is connected to the first power supply voltage terminal ELVDD, and the second terminal of driving transistor T3 is connected to the first control node s. The first control node s is connected to one terminal of organic light-emitting diode (OLED), and the other terminal of OLED is connected to the second power supply voltage terminal ELVSS.

[0043] Based on this, refer to Figure 2 For the detection transistor T2 in the pixel driving circuit 10, the gate of the detection transistor T2 is connected to the second scanning terminal Scan2, the first terminal a of the detection transistor T2 is connected to the first control node s, and the second terminal b of the detection transistor T2 is connected to the detection signal line SL (Sense Line).

[0044] It should be noted that the pixel driving circuit 10 in this invention is not limited to... Figure 2 The circuit structure shown in the figure may include other transistors in some embodiments of the pixel driving circuit 10. For example, a transistor may be placed between the first terminal of the driving transistor T3 and the first power supply voltage terminal ELVDD, or between the second terminal of the driving transistor T3 and the organic light-emitting diode OLED; however, the present invention does not limit this to any of these.

[0045] In some embodiments of the pixel driving circuit 10 described above, in sub-pixels P located in the same row, the first scanning terminal Scan1 of each pixel driving circuit 10 is connected to the same first gate line G1, and the second scanning terminal Scan2 of each pixel driving circuit 10 is connected to the same second gate line G2; that is, the pixel driving circuit 10 in the sub-pixel P in the same row is connected to two gate lines (first gate line G1 and second gate line G2). In addition, in sub-pixels P located in the same column, the data signal terminal Data of each pixel driving circuit 10 is connected to the same data line D.

[0046] In related technologies, the second terminal of each transistor T2 in the pixel driving circuit 10 located in the same column is connected to the same detection signal line SL. When the scan signals received by the gates of the detection transistors T2 in adjacent multi-row pixel driving circuits 10 overlap (i.e., the detection transistors T2 in adjacent multi-row pixel driving circuits 10 have periods of simultaneous conduction), the simultaneous activation of multiple detection transistors T2 causes an increase in current on the detection signal line SL, thereby increasing the IR drop (current resistance voltage drop) generated on the detection signal line SL. As a result, when the display panel 001 is displaying, the voltage input to the first control node s via the detection signal line SL and detection transistors T2 will have a large deviation, leading to poor uniformity of display brightness on the display panel 001.

[0047] Based on this, such as Figure 3 As shown, in the display panel 001 provided in this embodiment of the invention, at least two detection signal lines SL are correspondingly provided for the pixel driving circuits 10 in the same column (not limited to...). Figure 3 (2 of them). Furthermore, in the same column pixel driving circuit 10, the pixel driving circuits 10 located in adjacent rows are connected to different detection signal lines SL through the second pole b of the detection transistor T2.

[0048] In summary, by configuring the pixel driving circuits 10 in the same column, adjacent rows of pixel driving circuits 10 are connected to different detection signal lines SL via detection transistors T2. In this way, when the detection transistors T2 connected to a row of pixel driving circuits 10 are turned on, even if the detection transistors T2 in the adjacent rows of pixel driving circuits 10 are turned on, it will not cause an increase in the current and IR drop on the detection signal lines SL connected to that row of pixel driving circuits 10. This avoids the impact of the detection transistors T2 in multiple rows of pixel driving circuits 10 on the potential of the first control node s, thereby improving the accuracy of the potential of the first control node s in the pixel driving circuit 10 (i.e., reducing deviation), and thus improving the uniformity of the display brightness of the display panel.

[0049] For the pixel driving circuit 10 in the same column mentioned above, at least two detection signal lines SL are provided:

[0050] In some embodiments, in the display panel 001, the number of detection signal lines SL corresponding to each column of pixel driving circuit 10 is the same; that is, each column of pixel driving circuit 10 is provided with N detection signal lines SL, where N is a positive integer greater than or equal to 2.

[0051] In other embodiments, the number of detection signal lines SL corresponding to each column of pixel driving circuits 10 in the display panel 001 may not be exactly the same.

[0052] The following embodiments of the present invention are all illustrated by the example that the number of detection signal lines SL corresponding to each column of pixel driving circuit 10 is the same.

[0053] In some embodiments, for the N detection signal lines SL corresponding to the same column pixel driving circuit 10, the N detection signal lines are periodically connected to the second terminal b of the detection transistor T2 in the same column pixel driving circuit 10.

[0054] For example, such as Figure 3 As shown, in some embodiments, the pixel driving circuits 10 in the same column are respectively provided with two (i.e., N=2) detection signal lines SL (11, 12). In this case, the pixel driving circuits 10 located in the odd-numbered rows are connected to one detection signal line SL (11) through the second terminal of the detection transistor T2; the pixel driving circuits 10 located in the even-numbered rows are connected to another detection signal line SL (12) through the second terminal of the detection transistor T2. Figure 3 And in the following figures: G1(i) represents the first gate line connected to the pixel driving circuit 10 of the i-th row, and G2(i) represents the second gate line connected to the pixel driving circuit 10 of the i-th row.

[0055] For example, such as Figure 4 As shown, in some embodiments, the pixel driving circuits 10 in the same column are provided with two or more detection signal lines SL. For example, Figure 4 In the case where N=4, four detection signal lines SL (11, 12, 13, 14) are periodically connected to the second terminal b of the detection transistor T2 in the pixel drive circuit 10 of that column.

[0056] That is, when N=4, the pixel driving circuit 10 of the 4k+1 row is connected to the detection signal line SL(11) through the second terminal b of the detection transistor T2, the pixel driving circuit 10 of the 4k+2 row is connected to the detection signal line SL(12) through the second terminal b of the detection transistor T2, the pixel driving circuit 10 of the 4k+3 row is connected to the detection signal line SL(13) through the second terminal b of the detection transistor T2, and the pixel driving circuit 10 of the 4k+4 row is connected to the detection signal line SL(14) through the second terminal b of the detection transistor T2; wherein, 4k+4 is less than or equal to the total number of rows of pixel driving circuit 10 (or sub-pixel P) in the display panel 001.

[0057] Based on this, in order to minimize the potential of the first control node s in the row pixel driving circuit 10, which is affected by the detection transistor T2 in other row pixel driving circuits 10, in some embodiments, such as Figure 5 As shown, in the same column pixel driving circuit 10, when the scanning signals received by the second scanning terminal Scan2 connected to the pixel driving circuit 10 of the most adjacent rows have overlapping areas, N can be selected to be equal to the number of rows of the most adjacent rows.

[0058] In other words, the time period of the scan signal received by the second scanning terminal Scan2 connected to the pixel driving circuit 10 in the i-th row overlaps with the time period of the scan signal received by the second scanning terminal Scan2 connected to the pixel driving circuit 10 in the (i+N-1)-th row; and the time period of the scan signal received by the second scanning terminal Scan2 connected to the pixel driving circuit 10 in the i-th row overlaps with the time period of the scan signal received by the second scanning terminal Scan2 connected to the pixel driving circuit 10 in the (i+N)-th row.

[0059] For example, such as Figure 5 As shown, the time period of the scan signal received by the second scanning terminal Scan2 (corresponding to G2(1)) connected to the pixel driving circuit 10 in the first row has an overlapping area with the time period of the scan signal received by the second scanning terminal Scan2 (corresponding to G2(4)) connected to the pixel driving circuit 10 in the fourth row, but there is no overlapping area with the time period of the scan signal received by the second scanning terminal Scan2 (corresponding to G2(5)) connected to the pixel driving circuit 10 in the fifth row; in this case, N=4 can be set.

[0060] Based on this, in some embodiments, it is necessary to input a reference voltage to the first control node s through the detection signal line SL, and to collect the voltage of the first control node s; based on this, the relevant settings of the detection signal line SL will be further explained below.

[0061] In some embodiments, such as Figure 6 As shown ( Figure 6The middle section contains four detection signal lines (SL). Figure 6 The resistor R connected to each detection signal line SL represents the equivalent resistance of that detection signal line SL. For at least two detection signal lines SL that are configured corresponding to the pixel driving circuit 10 in the same column:

[0062] Each detection signal line SL is connected to a control unit U (that is, different control units U are set for each individual detection signal line SL in the display panel 001). The control unit U includes a first switch K1, a second switch K2, a sample-and-hold circuit (S / H), and an analog-to-digital converter (ADC). The detection signal line SL is connected to the sample-and-hold circuit (S / H) through the first switch K1, and the sample-and-hold circuit (S / H) is connected to the analog-to-digital converter (ADC). The detection signal line SL is also connected to the reference voltage terminal VREF through the second switch K2.

[0063] Based on this, in the actual control process, by controlling the first switch K1 to be turned on and the second switch K2 to be turned off, the voltage of the first control node s is sampled through the sample-and-hold circuit (S / H) and the analog-to-digital converter (ADC). By controlling the first switch K1 to be turned off and the second switch K2 to be turned on, the voltage of the reference voltage terminal VREF is input to the first control node s.

[0064] In some embodiments, the control unit U connected to the detection signal line SL corresponding to the multi-column pixel driving circuit 10 can be integrated into the same IC chip, and the IC chip is disposed in the peripheral area 2 of the display panel 001 along the extension direction of the detection signal line SL.

[0065] The following provides a further explanation of the driving process of the pixel driving circuit 10 provided in the embodiments of the present invention.

[0066] In the actual driving process of the display panel 001, the driving of the pixel driving circuit 10 includes the display period and the compensation detection period.

[0067] The following is for reference Figure 2 , Figure 6 as well as Figure 7 The driving process of the pixel driving circuit 10 during the display period of the display panel 001 will be explained.

[0068] The aforementioned display periods include: pixel data writing phase S1 and emission phase S2.

[0069] In the pixel data writing stage S1:

[0070] The first scan signal is input to the first scan terminal Scan1 through the first gate line G1, and the second scan signal is input to the second scan terminal Scan2 through the second gate line G2. The switching transistor T1 and the detection transistor T2 are turned on, that is, the row pixel driving circuit 10 is turned on.

[0071] The pixel data voltage is input to the data signal terminal Data via data line D, and this pixel data voltage is stored in the storage capacitor Cst via the turned-on switching transistor T1. The reference voltage Vref at the reference voltage terminal VREF is input to the first control node s via the turned-on detection transistor T2 through the detection signal line SL connected to the detection transistor T2.

[0072] It is understandable that the pixel data voltage writing period (pixel data voltage writing pulse width) corresponds to the last period of the first scan signal input by the first gate line G1, and the first gate line located in the row before the first gate line does not output a scan signal during this period.

[0073] Based on this, the voltage of the second control node g gradually increases, driving transistor T3 to conduct, and the voltage of the first control node s gradually increases accordingly. Through the bootstrap effect of the storage capacitor Cst, the voltage of the second control node g is further boosted, and the pixel driving circuit 10 enters the light emission stage S2, and the organic light-emitting diode OLED begins to emit light.

[0074] for Figure 7 The detection signal line SL shown is connected to the sample-and-hold circuit (S / H) via the first switch K1, and the sample-and-hold circuit (S / H) is connected to the analog-to-digital converter (ADC). When the detection signal line SL is also connected to the reference voltage terminal VREF via the second switch K2, in the aforementioned pixel data writing stage S1, the aforementioned input of the reference voltage Vref of the reference voltage terminal VREF to the first control node s via the activated detection transistor T2 through the detection signal line SL connected to the detection transistor T2 may include:

[0075] The second switch K2 connected to the detection signal line SL of each pixel driving circuit 10 in the currently opened row is turned on, while the second switch K2 connected to the remaining detection signal lines SL and all the first switches K1 are turned off, so that the reference voltage Vref of the reference voltage terminal VREF is input to the first control node s in each pixel driving circuit 10 in that row through the turned-on detection transistor T2.

[0076] The following is for reference Figure 2 , Figure 6 as well as Figure 8 The driving process of the pixel driving circuit 10 during the compensation detection period of the display panel 001 will be explained.

[0077] The aforementioned compensation detection periods include: data writing phase t1, charging phase t2, sampling phase t3, and data write-back phase t4.

[0078] Throughout the entire compensation detection period (t1, t2, t3, t4), a scan signal is input to the second scan terminal Scan2 through the second gate line G2, and the detection transistor T2 remains on; and throughout the entire compensation detection period, a data signal is continuously input to the data signal terminal Data through the data line D. That is, the row pixel driving circuit 10 is turned on.

[0079] During data writing phase t1:

[0080] A scan signal is input to the first scan terminal Scan1 through the first gate line G1. The switching transistor T1 is turned on, and the data signal on the data line D is input to the second control node g and stored in the storage capacitor Cst.

[0081] The reference voltage is input to the first control node s via the detection signal line SL and the conducting detection transistor T2.

[0082] During charging phase t2:

[0083] When the detection signal line SL stops inputting the reference voltage to the first control node s, the first control node s is in a floating state. At this time, under the action of the voltage of the second control node g, the driving transistor T3 is turned on, and the first control node s begins to charge (that is, to charge the detection signal line SL).

[0084] During sampling phase t3:

[0085] After a period of charging in the charging phase t2, the voltage on the detection signal line SL remains relatively stable. At this time, the voltage on the detection signal line SL is collected (that is, the voltage of the first control node s connected to the detection signal line SL is collected).

[0086] During the data write-back phase t4:

[0087] The scanning signal is input to the first scanning terminal Scan1 again through the first gate line G1, the switching transistor T1 is turned on, and the data signal on the data line D is input to the second control node g; the reference voltage is input to the first control node s through the detection signal line SL via the turned-on detection transistor T2.

[0088] for Figure 7The detection signal line SL shown is connected to the sample-and-hold circuit (S / H) via the first switch K1, and the sample-and-hold circuit (S / H) is connected to the analog-to-digital converter (ADC); the detection signal line SL is also connected to the reference voltage terminal VREF via the second switch K2:

[0089] In the aforementioned data write phase t1 and data write-back phase t4, inputting a reference voltage to the first control node s via the detection signal line SL and the turned-on detection transistor T2 may include:

[0090] The second switch K2 connected to the detection signal line SL of each pixel driving circuit 10 in the currently opened row is turned on, while the second switch K2 connected to the remaining detection signal lines SL and all the first switches K1 are turned off, so that the reference voltage Vref of the reference voltage terminal VREF is input to the first control node s in each pixel driving circuit 10 in that row through the turned-on detection transistor T2.

[0091] During the sampling phase t3 described above, data acquisition by detecting the voltage on the signal line SL may include:

[0092] The first switch K1 connected to the detection signal line SL of the pixel driving circuit 10 of the currently opened row is turned on, while the first switch K1 connected to the remaining detection signal lines SL and all the second switches K2 are turned off, so that the voltage of the first control node s in each pixel driving circuit 10 of the row is converted into the corresponding digital signal by the analog-to-digital converter (ADC) after passing through the sample-and-hold circuit (S / H).

[0093] For the digital signal obtained above that corresponds to the voltage of the first control node s, the threshold voltage of the driving transistor can be obtained through subsequent data processing and calculation, and the pixel data voltage can be compensated according to the threshold voltage during the subsequent display time for display; this part is not specifically limited in this invention.

[0094] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0095] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display panel comprising a plurality of pixel driving circuits; said pixel driving circuit comprising a switching transistor, a driving transistor, a detection transistor, and a storage capacitor; characterized in that, The gate of the detection transistor is connected to the second scanning terminal, and the first terminal of the detection transistor is connected to the first control node in the pixel driving circuit. In the display panel, each column of pixel driving circuits is provided with N detection signal lines; N is a positive integer greater than or equal to 2; In the same column of pixel driving circuits, pixel driving circuits located in adjacent rows are connected to different detection signal lines; and the N detection signal lines are periodically connected to the second terminal of the detection transistor in the same column of pixel driving circuits in sequence. In the same column pixel driving circuit: No. The time period of the scan signal received by the second scan terminal connected to the row pixel driving circuit is related to the first... The time period of the scan signal received by the second scan terminal connected to the row pixel driving circuit has an overlapping area; The first The time period of the scan signal received by the second scan terminal connected to the row pixel driving circuit is related to the first... The time period of the scan signal received by the second scan end connected to the row pixel driving circuit has no overlapping area; Pixel data writing phase during the display period of the display panel: When a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of that row through the detection signal line connected to that row of pixel driving circuits; The data writing phase and data write-back phase during the compensation detection period of the display panel: When a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of that row through the detection signal line connected to that row of pixel driving circuits; During the sampling phase of the compensation detection period on the display panel: When a row of pixel driving circuits is turned on, the voltage of the first control node in each pixel driving circuit of that row is collected through the detection signal line connected to that row of pixel driving circuits.

2. The display panel according to claim 1, characterized in that, For at least two detection signal lines corresponding to the pixel driving circuit in the same column: each detection signal line is connected to a control unit; the control unit includes a first switch, a second switch, a sample-and-hold circuit, and an analog-to-digital converter; The detection signal line is connected to the sample-and-hold circuit via the first switch, and the sample-and-hold circuit is connected to the analog-to-digital converter. The detection signal line is also connected to the reference voltage terminal via the second switch.

3. The display panel according to claim 1 or 2, characterized in that, The gate of the switching transistor is connected to the first scan terminal, the first terminal is connected to the data signal terminal, and the second terminal is connected to the gate of the driving transistor. The first terminal of the storage capacitor is connected to the gate of the driving transistor, and the second terminal is connected to the first control node; The first terminal of the driving transistor is connected to the first power supply voltage terminal, the second terminal is connected to the first control node, and the first control node is connected to the second power supply voltage terminal through the light-emitting unit.

4. A display device, characterized in that, Includes the display panel as described in any one of claims 1-3.

5. A control method for a display panel as described in any one of claims 1-3, characterized in that, include: Pixel data writing phase during the display period of the display panel: When a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of that row through the detection signal line connected to that row of pixel driving circuits; During the data writing and data write-back phases of the compensation detection period on the display panel: When a row of pixel driving circuits is turned on, a reference voltage is input to the first control node in each pixel driving circuit of that row through the detection signal line connected to that row of pixel driving circuits; Sampling phase during the compensation detection period of the display panel: When a row of pixel driving circuits is turned on, the voltage of the first control node in each pixel driving circuit of that row is collected through the detection signal line connected to that row of pixel driving circuits.

6. The control method for the display panel according to claim 5, characterized in that, When the detection signal line is connected to a sample-and-hold circuit via a first switch, and the sample-and-hold circuit is connected to an analog-to-digital converter; and the detection signal line is also connected to a reference voltage terminal via a second switch: The step of inputting a reference voltage to the first control node in each pixel driving circuit of the row via a detection signal line connected to the row's pixel driving circuit includes: The second switch connected to the pixel driving circuit of that row via the detection signal line is turned on, while the second switches connected to the remaining detection signal lines and all the first switches are turned off, so as to input the reference voltage of the reference voltage terminal to the first control node in each pixel driving circuit of that row. The step of acquiring the voltage of the first control node in each pixel driving circuit of the row through the detection signal line connected to the row pixel driving circuit includes: The system controls the first switch connected to the pixel driving circuit of that row via the detection signal line to turn on, and simultaneously controls the first switch connected to the remaining detection signal lines and all the second switches to turn off, so as to collect the voltage of the first control node in each pixel driving circuit of that row.

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