Decoupling capacitor packaging structure and manufacturing method thereof

Abstract

The present disclosure is directed to a method for forming a metal-insulator-metal decoupling capacitor with scalable capacitance. The method may include forming a first redistribution layer having a metal line on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form a first interlayer via opening and a second interlayer via opening spaced apart in the photoresist layer, wherein the first interlayer via opening is wider than the second interlayer via opening. The method may further include depositing metal in the first interlayer via opening and the second interlayer via opening to form a first interlayer via structure and a second interlayer via structure, respectively, contacting the metal line, removing the photoresist layer, forming a high-k dielectric on top surfaces of the first interlayer via structure and the second interlayer via structure, and depositing a metal layer on the high-k dielectric layer to form a first capacitor and a second capacitor, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Decoupling capacitors can be built into the chip to prevent voltage spikes in the power supply (for example, when power is initially supplied to the chip or when activating various components of the chip). During chip manufacturing, decoupling capacitors can be integrated into the back end of the line during or after chip packaging. Summary of the invention

[0003] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: depositing a polymer layer on a carrier substrate; forming a first capacitor structure and a second capacitor structure on the polymer layer, wherein forming the first capacitor structure and the second capacitor structure comprises: forming a first redistribution layer on a portion of the polymer layer, the first redistribution layer comprising a plurality of metal lines; depositing a photoresist layer on the first redistribution layer; etching the photoresist layer to form spaced-apart first interposer through-hole openings and second interposer through-hole openings in the photoresist layer to expose respective portions of the metal lines of the redistribution layer, wherein the first interposer through-hole opening is wider than the second interposer through-hole opening; depositing metal in the first interposer through-hole opening and the second interposer through-hole opening to respectively form a first interposer through-hole structure and a second interposer through-hole structure contacting the metal lines; removing the photoresist layer; forming a high-k dielectric on the top surfaces of the first interposer through-hole structure and the second interposer through-hole structure; and depositing a metal layer on the high-k dielectric layer to respectively form a first capacitor and a second capacitor; and forming a second redistribution layer on the first capacitor and the second capacitor.

[0004] According to some embodiments of the present disclosure, an interposer structure is provided, comprising: a polymer layer, a first redistribution layer, a chip, a molding compound, and a second redistribution layer. The first redistribution layer is located on the polymer layer. A plurality of spaced apart capacitor structures have different surface areas on the first redistribution layer, wherein each spaced apart capacitor structure comprises: an interposer through hole, a dielectric material, and a top metal layer. The interposer through hole contacts the first redistribution layer, wherein the surface area of ​​the capacitor structure is based on the length and width of the interposer through hole. The dielectric material covers the top surface of the interposer through hole, wherein the dielectric material is spaced apart from the interposer through hole and a plurality of sidewalls of the first redistribution layer. The top metal layer is located on the dielectric material. The chip is attached to the polymer layer and adjacent to the spaced apart capacitor structures. The molding compound is disposed between the chip and each spaced apart capacitor structure. The second redistribution layer is disposed on the chip and the spaced apart capacitor structures.

[0005] According to some embodiments of the present disclosure, a semiconductor structure is provided, comprising: a first redistribution layer, an interposer structure and a molding compound. The first redistribution layer comprises a plurality of solder bumps. The interposer structure is used to electrically connect to the first redistribution layer, and comprises: a plurality of capacitor structures and one or more chips. Each capacitor structure comprises: an interposer through hole, a high dielectric constant dielectric and a metal layer. The interposer through hole is used to electrically couple to the first redistribution layer. The high dielectric constant dielectric is located on the interposer through hole. The metal layer is located on the high dielectric constant dielectric. The molding compound surrounds the chip and the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with the practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity, the size of the various features can be arbitrarily increased or reduced.

[0007] Figure 1A and Figure 1B is a flow chart of a method for forming a metal insulator metal (MIM) capacitor with scalable capacitance in an integrated fan-out (InFO) packaging structure according to some embodiments;

[0008] Figures 2 to 15 are cross-sectional and plan views of an integrated fan-out (InFO) package structure during various manufacturing operations to form a metal-insulator-metal (MIM) capacitor with scalable capacitance according to some embodiments;

[0009] FIG. 16A to FIG. 16F and FIG. 17A to FIG. 17F is a plan view of exemplary shapes of metal-insulator-metal (MIM) capacitors having scalable capacitance according to some embodiments.

[0010]

Explanation of symbols

[0011] 100: Method

[0012] 110: Operation

[0013] 120: Operation

[0014] 130: Operation

[0015] 140: Operation

[0016] 150: Operation

[0017] 160: Operation

[0018] 180: Operation

[0019] 190: Operation

[0020] 200: Carrier substrate

[0021] 210: Protective layer / polymer layer

[0022] 220: Light to heat conversion layer

[0023] 300:Metal wire

[0024] 310:Metal wire

[0025] 400: Photoresist layer

[0026] 410: Intermediate layer through hole opening

[0027] 420: Intermediate layer through hole opening

[0028] 430: Intermediate layer through hole opening

[0029] 500: Seed layer stacking

[0030] 600: Copper layer

[0031] 610: Intermediary layer through hole

[0032] 620:Intermediary layer through hole

[0033] 630:Interposer through hole

[0034] 800: Chip

[0035] 810: Chip lamination

[0036] 900: Molding compound

[0037] 1010: High dielectric constant dielectric

[0038] 1020:Metal layer

[0039] 1030: Photoresist pattern

[0040] 1100: Dielectric layer

[0041] 1110:Metal layer

[0042] 1200: polymer layer

[0043] 1210: First redistribution layer

[0044] 1220:Metal Wire

[0045] 1300: Second redistribution layer

[0046] 1400: polymer layer

[0047] 1410: Under Bump Metal Contact

[0048] 1420:Solder bump

[0049] 1430:Solder Bump

[0050] 1440:Solder Bump

[0051] A: Metal-insulator-metal capacitor

[0052] B: Metal-insulator-metal capacitor

[0053] C: Metal-insulator-metal capacitor

[0054] L: Length

[0055] S: Spacing

[0056] W: Width

[0057] W1: Width

[0058] W2: Width

[0059] W3: Width

[0060] x: axis

[0061] y:axis

[0062] z: axis DETAILED DESCRIPTION

[0063] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may repeat reference numerals and / or text in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0064] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "above," etc. may be used in the present disclosure to describe one element or feature relative to another element or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0065] As used in this disclosure, the term "nominal" refers to the expected or target value of a characteristic or parameter for a component or process operation set during the design phase of a product or process, as well as values ​​above and / or below the expected value. The range of values ​​may be due to minor variations in the manufacturing process or tolerances.

[0066] In some embodiments, the terms "about" and "substantially" may represent that the value of a given quantity varies within 5% of a target value (eg, ±1%, ±2%, ±3%, ±4%, and ±5% of the target value).

[0067] As used in this disclosure, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0068] Decoupling capacitors (DeCAP) can be built into the chip to prevent voltage spikes when the power is supplied (for example, when power is initially supplied to the chip or when activating various components of the chip). Since the power supply cannot respond immediately to such changes in power demand, the chip's supply voltage may change briefly until the power supply can respond and stabilize the voltage. Voltage spikes may occur during this transient time. Decoupling capacitors can suppress these voltage spikes. Decoupling capacitors with higher capacitance can further suppress voltage spikes.

[0069] During the chip manufacturing process, decoupling capacitors can be integrated into the end of the back-end process during or after chip packaging. For example, the decoupling capacitors can be surface mounted on the packaging substrate using surface-mount technology (SMT). However, surface-mount technology requires external interconnection between the packaging substrate and the decoupling capacitors mounted externally. External interconnection or connection will increase time delay (for example, the delay between spike generation and spike suppression). The present disclosure describes an embodiment of a method for forming a decoupling capacitor, which can be integrated into a three-dimensional (3D) integrated circuit (IC) package (for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package). Integrating decoupling capacitors into a three-dimensional integrated circuit package has the advantage of internal interconnection, which can be shorter than the external interconnection. Chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) chip packages can integrate multiple functional chips onto an interposer with space allocated between each chip so that input / output (I / O) connection points can be formed. In some embodiments, the decoupling capacitor formed as an interposer as part of the chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) chip packages is a metal insulator metal (MIM) structure, which can include a high dielectric constant (high-k) material (e.g., having a dielectric constant greater than about 3.9). Compared to decoupling capacitors mounted on a substrate using surface mount technology, embodiments of the integrated metal insulator metal (MIM) capacitors described in the present disclosure can (i) reduce time delay due to shorter interconnect length; (ii) have higher capacitance and a wider range of capacitance values; (iii) reduce power consumption; (iv) increase operating speed; and (v) reduce package size.

[0070] Figure 1A and Figure 1BA flow chart is depicted of a method 100 according to some embodiments for forming a metal insulator metal (MIM) decoupling capacitor with "scalable" capacitance embedded in an integrated fan-out (InFO) three-dimensional integrated circuit package. The metal insulator metal (MIM) decoupling capacitor manufactured using the method 100 can have different surface areas to provide various capacitances for power management and radio frequency (RF) components. For example, the capacitance of the metal insulator metal (MIM) decoupling capacitor manufactured using the method 100 can range from the femto Farad (fF) range to the nano Farad (nF) range. Other process operations can be performed between the various operations of the method 100 and may be omitted for clarity. For exemplary purposes, the method 100 will be described using an integrated fan-out (InFO) three-dimensional integrated circuit package. However, the method 100 can also be applied to other types of packages (e.g., a chip on wafer on substrate (CoWoS) three-dimensional integrated circuit package). These other types of packages are within the spirit and scope of the present disclosure.

[0071] Reference Figures 2 to 17F Method 100 is described. Figures 2 to 17F For illustration purposes only and are not drawn to scale. Figures 2 to 17F The actual geometry of the actual structure, features or layers may not be reflected. For the purpose of illustration and clarity, some structures, layers or geometries may have been intentionally added or omitted.

[0072] Reference Figure 1A The exemplary manufacturing method 100 begins with operation 110, wherein a protective layer 210 is disposed on a glass carrier substrate 200, such as Figure 2As shown. In some embodiments, the glass carrier substrate 200 provides mechanical support for structural elements attached or manufactured in subsequent operations of the method 100. By way of example and not limitation, the protective layer 210 may include polyimide (PI), polybenzoxazole (PBO), or another suitable polymer material. In some embodiments, the protective layer 210 (also referred to as "polymer layer 210" in the present disclosure) is a stress relief coating that serves as a protective layer or "buffer coating" before forming a redistribution layer (RDL). In some embodiments, a light to heat conversion layer (LTHC) 220 is sandwiched between the glass carrier substrate 200 and the polymer layer 210. The light to heat conversion layer 220 is an adhesive layer that can be cured with ultraviolet light (UVlight) to form a temporary bond between the protective layer 210 and the glass carrier substrate 200. Once the integrated fan-out (InFO) package is completed, this temporary bond can be broken to release the polymer layer 210 from the glass carrier substrate 200. By way of example and not limitation, irradiating the light-to-heat conversion layer 220 through the back side of the glass carrier substrate 200 with a focused laser beam may generate sufficient heat to decompose the light-to-heat conversion layer 220 and release the glass carrier substrate 200 from the polymer layer 210. In order to successfully release the glass carrier substrate 200, the glass carrier substrate 200 needs to be transparent to the light source (e.g., laser) that irradiates and decomposes the light-to-heat conversion layer 220.

[0073] Reference Figure 1A The method 100 continues with operation 120 and a process of forming a bottom redistribution layer on the polymer layer 210. Figure 3As shown, the bottom redistribution layer may include metal lines 300 and 310. As an example and not limited thereto, metal lines 300 and 310 are formed by a patterned metal stack including an electroplated copper top layer, a copper seed middle layer, and a titanium bottom layer. The titanium bottom layer and the copper seed middle layer may be deposited to a thickness of about 100 nm to about 500 nm, respectively, by a physical vapor deposition (PVD) process. The electroplated copper top layer may be formed to a thickness of about 7 microns (μm). In some embodiments, the metal stack may be blanket deposited (e.g., deposited to cover the entire top surface of the polymer layer 210), and then patterned by photolithography and etching operations to form metal lines 300 and 310. For example, a photoresist may be coated on the metal stack and patterned to form an opening in the photoresist layer to expose an area of ​​the metal stack. The exposed area of ​​the metal stack may then be removed by a wet etching process. The metal stack area covered by the photoresist may be protected and not removed by the chemical substances of the wet etching. In other words, the photoresist acts as a mask for the wet etching. The wet etching chemistry may remove the exposed areas of the metal stack until the underlying polymer layer 210 is exposed. After the wet etching operation, the photoresist is removed, leaving the patterned areas of the metal stack (e.g., metal lines 300 and 310). In some embodiments, additional metal lines similar to metal lines 300 and 310 may be formed throughout the polymer layer 210. Therefore, the bottom redistribution layer may not be limited to metal lines 300 and 310.

[0074] Reference Figure 1A , method 100 continues with operation 130 and a process of forming through interposer vias (TIVs) in contact with the bottom redistribution layer (e.g., metal lines 300 and 310). In some embodiments, one or more interposer vias formed during operation 130 can be used to define the surface area of ​​a corresponding metal insulator metal (MIM) capacitor, and one or more interposer vias formed during operation 130 can serve as conductive structures for electrically connecting various components of the package structure. By way of example and not limitation, photolithography and etching operations can be used to form the interposer vias in operation 130. For example, referring to Figure 4A , a photoresist layer 400 having a thickness between about 180 μm and about 250 μm may be spin-coated on the metal lines 300, 310 and the polymer layer 210. The photoresist layer 400 may then be patterned to form interposer via openings 410, 420, and 430 to expose corresponding portions of the metal lines 300 and 310, such as Figure 4A shown.

[0075] In some embodiments, the interposer via opening 410 is used to define the surface area of ​​the formed metal-insulator-metal (MIM) decoupling capacitor, while the interposer via openings 420 and 430 are used to form an interposer via structure that electrically connects various components of the package structure. The interposer via opening 410 can be designed to have different dimensions from the interposer via openings 420 and 430. For example, the plurality of interposer via openings 410 can each have different widths, such as having widths W1, W2, and W3, and a length L that is different from the respective widths and lengths of the interposer via openings 420 and 430, such as Figure 4B As shown ( Figure 4B yes Figure 4A ). In some embodiments, interposer via openings 410 having the same length L but different widths W1, W2, and W3 may be formed to allow the metal insulator metal (MIM) capacitors to have different surface areas (width times length). In this case, different widths, such as widths W1, W2, and W3) may be used to effectively adjust the surface area of ​​each metal insulator metal (MIM) capacitor. However, this is not limiting, and each interposer via opening 410 may independently define both the width and length to modify the surface area of ​​each metal insulator metal (MIM) capacitor. Independently varying the width and length may provide additional design flexibility, however, independently varying the width and length may increase manufacturing complexity due to potential lithography and etching limitations.

[0076] By way of example and not limitation, Figure 4A and Figure 4B As shown, W1 can be greater than W2, and W2 can be greater than W3. Furthermore, W2 can be greater than W3, and W3 can be greater than W1. The aforementioned width relationship is not limiting, and other width relationships are possible depending on the desired number of metal insulator metal (MIM) capacitors and the resulting capacitance. In addition, any number of interposer via openings 410 having widths different or similar to W1, W2, and W3 can be formed. By way of example and not limitation, W1 can be approximately 1000 μm, W2 can be approximately 100 μm, and W3 can be approximately 10 μm, while interposer via openings 420 and 430 can have a width of approximately 120 μm. In addition, the shape of interposer via openings 410 can be rectangular, oval, circular, or have any other suitable geometric shape.

[0077] refer to Figure 5 , a titanium and copper seed layer stack 500 is deposited (e.g., by a physical vapor deposition process) on the patterned photoresist layer 400 to cover the sidewalls and bottom surfaces of the interposer via openings 410, 420, and 430. In some embodiments, the seed layer stack 500 is deposited above the photoresist layer 400, such as Figure 5In some embodiments, the titanium layer may be approximately 1000 angstroms. The copper seed layer can be approximately exist Figure 6 In some embodiments, the deposited copper layer 600 may be grown on the seed layer stack 500 above the photoresist layer 400. The copper layer 600 may then be planarized and polished by a chemical mechanical planarization process to remove the portion of the copper layer 600 above the top surface of the photoresist layer 400. In some embodiments, during the chemical mechanical planarization process of copper, the seed layer stack 500 is also removed from the top surface of the photoresist layer 400, as shown in FIG. Figure 6 In some embodiments, the thickness of the photoresist layer 400 may be in the range of about 180 μm to about 250 μm, and the thickness of the photoresist layer 400 defines the height of the interposer vias 610 , 620 , and 630 at this stage of the manufacturing process.

[0078] After forming the interposer through holes 610, 620 and 630, the photoresist layer 400 may be removed by a wet etching process, such as Figure 7 According to some embodiments, reference Figure 4A and Figure 4B The interposer via openings 410, 420, and 430 shown in FIG. 4 have different widths when compared to interposer vias 620 and 630. For example, interposer via 610 may have a width of about 10 μm to 1000 μm, while interposer vias 620 and 630 may have a width of about 120 μm. In some embodiments, Figure 4A and Figure 4B The widths W1, W2, and W3 of the interposer via opening 410 are shown to define the width of each interposer via 610. In some embodiments, interposer via 610 is an integral part of a metal-insulator-metal (MIM) capacitor structure, while interposer vias 620 and 630 provide electrical connections between layers in an integrated fan-out (InFO) package.

[0079] Reference Figure 1A The method 100 continues with operation 140 and the process of attaching the wafer 800 to the polymer layer 210, such as Figure 8As shown. In some embodiments, the chip 800 may have a function such as radio frequency communication (e.g., an RF chip), or may have other or additional functions. The chip 800 may have been prefabricated using a chip process and may include multiple transistors and multiple interconnect layers to achieve its functionality (e.g., radio frequency communication). In some embodiments, a die attach film (DAF) 810 serves as a glue layer and is between the chip 800 and the polymer layer 210. By way of example and not limitation, the thickness of the die attach film 810 may be between about 10 μm and about 20 μm. In some embodiments, the die attach film 810 is a dielectric. By way of example and not limitation, the height of the chip 800 may be comparable to the height of the interposer through holes 610, 620, and 630. If the chip 800 is taller than the interposer through holes 610, 620, and 630, it may be recessed to the height of the interposer through holes 610, 620, and 630. According to some embodiments, multiple wafers may be attached to polymer layer 210 during operation 140. To avoid parasitic capacitance between interposer vias 610, 620, and 630 and wafer 800, a suitable minimum spacing S may be between about 20 μm and 30 μm. If a material with a sufficiently low dielectric constant (e.g., less than about 2.8) is used to isolate interposer vias and wafer 800, spacing S may be adjusted to be less than about 20 μm.

[0080] Reference Figure 1A and Fig. 9 , the method 100 continues with operation 150 and a process of disposing a molding compound (MC) 900 on the polymer layer 210 to surround the wafer 800 and the interposer vias 610, 620, and 630. By way of example and not limitation, the molding compound 900 may be spin-coated on the polymer layer 210. According to some embodiments, the molding compound 900 is an epoxy-based material that is solid at room temperature and liquid when heated at a temperature greater than 250°C. In some embodiments, the molding compound 900 is melted before being spin-coated on the polymer layer 210. According to some embodiments, the wafer 800 and the interposer vias 610, 620, and 630 may be embedded in the molding compound 900. By way of example and not limitation, the thickness of the spin-coated molding compound 900 may be between about 230 μm and about 300 μm. This means that the applied molding compound 900 has an excess coverage thickness of about 50 μm (eg, it may extend about 50 μm over the top surface of the wafer 800 and the interposer vias 610 , 620 , and 630 ).

[0081] After the molding compound 900 is coated on the glass carrier substrate 200, the molding compound 900 can be cooled and hardened. After the molding compound 900 is hardened, it can be partially ground to remove about 98% of the excess overlay thickness of 50 μm. The grinding process will roughen the top surface of the molding compound 900. According to some embodiments, a chemical mechanical planarization process can then be used to planarize, polish, and remove the remaining portion of the molding compound 900 (for example, about 1 μm, where this 1 μm is about 2% of the excess overlay thickness of 50 μm) until the top surface of the wafer 800 and the interposer through-holes 610, 620, and 630 are exposed. In some embodiments, the molding compound 900 provides structural support and electrical isolation for the wafer 800 and the interposer through-holes 610, 620, and 630. Since the molding compound 900 melts at a temperature greater than about 250°C, the thermal budget of any subsequent manufacturing operations should be limited to about 250°C. If a molding compound with a higher temperature tolerance is used, the thermal budget for subsequent manufacturing operations may be increased if no other thermal budget constraints exist.

[0082] refer to Figure 1A The method 100 continues with operation 160 to form a high-k dielectric on the molding compound 900, the interposer vias 610, 620, and 630, and the wafer 800. Fig.10 , a high-k dielectric 1010 is blanket deposited on the molding compound 900, the interposer vias (e.g., 610, 620, and 630), and the wafer 800. In some embodiments, when the high-k dielectric 1010 is patterned, it can form the dielectric of each metal-insulator-metal (MIM) capacitor. In some embodiments, the high-k dielectric 1010 is deposited at a temperature below about 250° C. (e.g., at about 180° C. or about 210° C.), depending on the type of dielectric layer and the deposition method used. In addition, the thickness of the high-k dielectric 1010 can be greater than about 1 nm to avoid charge leakage and capacitance loss.

[0083] In some embodiments, the dielectric constant of high dielectric constant dielectric 1010 is greater than about 3.9, depending on the type of material. By way of example and not limitation, high dielectric constant dielectric 1010 may be silicon nitride (SiN) with a dielectric constant of about 7. x) film, which is deposited by plasma-enhanced chemical vapor deposition (PECVD) process at a temperature of about 180° C., wherein the deposited thickness is greater than about 30 nm. Furthermore, the high dielectric constant dielectric 1010 can be silicon oxynitride (SiON) deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), metal organic chemical vapor deposition (MOCVD), etc. x In some embodiments, the high-k dielectric 1010 may be a dielectric stack that may include a bottom layer of zirconium oxide (ZrO2) having a dielectric constant value greater than about 13 (e.g., 13.6) deposited at a temperature of about 210° C., an intermediate layer of aluminum oxide (Al2O3), and a top layer of zirconium oxide (ZrO2). In some embodiments, the high-k dielectric 1010 may be a dielectric that includes a hafnium-based dielectric (e.g., hafnium oxide (HfO x ) and hafnium silicate (HfSiO x )), titanium oxide (TiO2) or tantalum oxide (TaO x ). The high dielectric constant dielectric 1010 may also be a liquid phase high dielectric constant polymer (e.g., polybenzoxazole or polyimide that is cured and hardened at a temperature below about 250°C). The high dielectric constant dielectric 1010 may also be spin on glass (SOG) or liquid phase silicon dioxide (SiO2), which has a low curing temperature (e.g., below about 250°C) and a dielectric constant value between about 4 and about 4.2. In addition, the high dielectric constant dielectric 1010 may be strontium titanate (SrTiO3) having a dielectric constant value between 100 and 200, barium titanate (BaTiO3) having a dielectric constant value of about 500, barium strontium titanate (BaSrTiO3) having a dielectric constant value between about 250 and about 300, or lead zirconate titanate (PbZrTiO3) having a dielectric constant value between about 1000 and about 1500.

[0084] In some embodiments, the high-k dielectric 1010 may be deposited by physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, or other suitable chemical vapor deposition-based deposition processes, which may deposit the dielectric material at a deposition temperature below about 250° C. (e.g., at about 180° C. or about 210° C.). Alternatively, in some embodiments, the high-k dielectric 1010 may be spin-coated at a temperature below about 250° C. (e.g., at about 180° C. or about 210° C.).

[0085] According to some embodiments, a thicker dielectric with a higher dielectric constant value can provide a capacitance comparable to a thinner dielectric with a lower dielectric constant value. This can be advantageous when considering leakage current through the dielectric. In addition, according to the parallel plate capacitance formula, a material with a higher dielectric constant value increases the capacitance value of a metal insulator metal (MIM) capacitor. The parallel plate capacitance formula is Where C is the capacitance of the metal insulator metal (MIM) capacitor, k is the dielectric constant of the high-k dielectric in the metal insulator metal (MIM) capacitor (eg, the dielectric constant of the high-k dielectric 1010), ε o is the dielectric constant of a vacuum, A is the effective surface area of ​​the capacitor, and d is the thickness of the high dielectric constant dielectric material (eg, the thickness of high dielectric constant dielectric 1010).

[0086] refer to Figure 1B , method 100 continues with operation 170 and a process of depositing a metal layer on high-k dielectric 1010. For example, referring to Fig.10 , a metal layer 1020 is deposited as a capping film on the high-k dielectric 1010. In some embodiments, the metal layer 1020, when patterned, forms a top metal plate of a metal-insulator-metal (MIM) capacitor. The metal layer 1020 (similar to metal lines 300 and 310) is a metal stack made of an electroplated copper top layer, a copper seed middle layer, and a titanium bottom layer. The titanium bottom layer and the copper seed middle layer can be deposited by a physical vapor deposition process with a thickness between about 100 nm and about 500 nm, respectively. The electroplated copper top layer can have a thickness of about 7 μm.

[0087] In reference Figure 1BAccording to some embodiments, method 100 continues with operation 180 and the process of patterning metal layer 1020 and high-k dielectric 1010 to form a metal-insulator-metal (MIM) capacitor structure. In some embodiments, metal layer 1020 and high-k dielectric are patterned successively. In some embodiments, patterning of metal layer 1020 and high-k dielectric 1010 can be accomplished by photolithography and etching operations. For example, Fig.10 As shown, a photoresist may be spin-coated on the metal stack and then patterned to form a photoresist pattern 1030 on each interposer through hole 610. Each photoresist pattern 1030 is substantially aligned with a top surface of each interposer through hole 610. A wet etching process may remove a portion of the metal layer 1020 not covered by the photoresist pattern 1030, and a subsequent dry etching process may remove a portion of the high-k dielectric 1010 not covered by the photoresist pattern 1030. Fig.11 The resulting patterned dielectric layer 1100 and metal layer 1110 are shown after removing the photoresist pattern 1030. According to some embodiments, the patterned dielectric layer 1100, the patterned metal layer 1110, and the interposer via 610 form metal insulator metal (MIM) capacitors A, B, and C. In some embodiments, the metal insulator metal (MIM) capacitors A, B, and C are decoupling capacitors that can suppress voltage spikes of the respective power supplies to which they are connected.

[0088] By way of example and not limitation, the capacitance of metal insulator metal (MIM) capacitor A may be in the nanofarad (nF) range (e.g., approximately 100 nF), the capacitance of metal insulator metal (MIM) capacitor B may be in the picofarad (pF) range (e.g., 100 pF), and the capacitance of metal insulator metal (MIM) capacitor C may be in the femtofarad (fF) range (e.g., 100 fF). The capacitance value of each metal insulator metal (MIM) capacitor A, B, and C is defined by its respective surface area, since the high dielectric constant dielectric material and high dielectric constant dielectric thickness may be shared between metal insulator metal (MIM) capacitors A, B, and C. Furthermore, according to the parallel plate capacitance formula, assuming that the length of each metal insulator metal (MIM) capacitor A, B, and C along the y-axis is substantially similar, the width of each metal insulator metal (MIM) capacitor along the x-axis defines the capacitance value. As described above, the width of each metal insulator metal (MIM) capacitor may be defined by its respective surface area. Figure 4A and Figure 4B The illustrated opening widths W1, W2, and W3 of the interposer via opening 410 are defined. Therefore, the opening widths W1, W2, and W3 of the interposer via opening 410 may correspond to the respective widths of the formed metal-insulator-metal (MIM) capacitors A, B, and C.

[0089] By varying (i) the width of each capacitor (and thus the area of ​​each MIM capacitor); (ii) the type of material of the high-k dielectric; and (iii) the thickness of the high-k dielectric, a wide range of capacitance values ​​can be achieved. For example, capacitors with capacitance values ​​ranging from femtofarads (fF) (e.g., 10 -15 Farad) to nanofarad (nF) range (e.g. 10 -9 A metal insulator metal (MIM) capacitor having a capacitance of 10 ...

[0090] According to some embodiments, FIG. 16A to FIG. 16F Various shapes of metal insulator metal (MIM) capacitors A, B, and C formed using method 100 are shown. FIG. 16A to FIG. 16F In the example of FIG. 1 , metal insulator metal (MIM) capacitors with different combinations of width W and length L are shown. These variations are exemplary and not limiting. FIG. 17A to FIG. 17F As shown, other shapes of metal-insulator-metal (MIM) capacitors A, B and C are also possible. FIG. 16A to FIG. 16F and FIG. 17A to FIG. 17F The metal insulator metal (MIM) capacitors shown are exemplary and non-limiting. Thus, the metal insulator metal (MIM) capacitors A, B, and C can be formed in a variety of ways to achieve the desired capacitor area and capacitance value. In some embodiments, depending on the capacitance requirements, multiple metal insulator metal (MIM) capacitors with different capacitance values ​​can be formed simultaneously in a packaging structure (e.g., an integrated fan-out (InFO) package). By way of example and not limitation, FIG. 16A to FIG. 16F and FIG. 17A to FIG. 17F Any combination of the metal insulator metal (MIM) capacitors shown in FIG. 1 may be formed in the package structure.

[0091] Reference Figure 1B , method 100 continues with operation 190 and a process of forming one or more redistribution layers to provide electrical connections to metal insulator metal (MIM) capacitors A, B, and C. During operation 190, electrical connections to other components and interposer vias may be formed. For example, electrical connections to wafer 800 and interposer vias 620 and 630 may also be made during operation 190.

[0092] By way of example and not limitation, each additional redistribution layer may include a new polymer layer. Fig.12, a polymer layer 1200 (similar to polymer layer 210) is disposed on molding compound 900. In some embodiments, polymer layer 1200 is a low-k dielectric material having a dielectric constant value of about 2.8 and a thickness of about 4.5 μm. The polymer layer 1200 may then be patterned to form a plurality of openings therein, and redistribution layer metal lines are to be formed in these openings. For example, in Fig.12 In the embodiment of the present invention, a first redistribution layer 1210 may be formed on the interposer vias 620 and 630, the wafer 800, and the metal insulator metal (MIM) capacitors A, B, and C. The alignment of the first redistribution layer 1210 with the interposer vias 620 and 630, the wafer 800, and the metal insulator metal (MIM) capacitors A, B, and C may be achieved through one or more photolithography and etching operations. As an example and not limitation, a photoresist layer may be spin-coated on the polymer layer 1200. The photoresist layer may be patterned to form openings in the photoresist layer that are aligned with the interposer vias 620 and 630, the wafer 800, and the metal insulator metal (MIM) capacitors A, B, and C. A subsequent etching process may remove portions of the polymer layer 1200 that are not covered by the photoresist to form openings that are substantially aligned with the interposer vias 620 and 630, the wafer 800, and the metal insulator metal (MIM) capacitors A, B, and C. Once the openings are formed in the polymer layer 1200 , the photoresist layer may be removed, and a blanket metal stack may be deposited and patterned to form the metal lines 1220 of the first redistribution layer 1210 .

[0093] Similar to metal line 300, metal line 1220 may include a metal stack of an electroplated copper top layer, a copper seed middle layer, and a titanium bottom layer. By way of example and not limitation, the titanium bottom layer and the copper seed middle layer may be deposited by a physical vapor deposition process to a thickness of approximately 100 nm and 500 nm, respectively. The electroplated copper top layer may have a thickness of approximately 7 μm or more. In some embodiments, the metal stack may partially fill the opening in polymer layer 1200, such as Fig.12 shown.

[0094] like Fig.13 As shown, the above operations may be continuously repeated to form a second redistribution layer 1300. The number of redistribution levels provided in the present disclosure is exemplary and should not be considered limiting. Therefore, fewer or more redistribution levels may be formed according to an integrated fan-out (InFO) package design. As an example and not a limitation, four or more redistribution layers may be formed on metal insulator metal (MIM) capacitors A, B, and C. Fig.14 Once all redistribution layers have been formed, a top polymer layer 1400 is disposed on the topmost redistribution layer (eg, Fig.141400) and then patterned. According to some embodiments, a patterning operation is performed after the metal deposition to form an under bump metallurgy (UBM) contact 1410. The under bump metal contact 1410 forms an interface between the second redistribution layer 1300 and the solder bumps 1420, 1430 and 1440. In some embodiments, the under bump metal contact 1410 may include a metal stack of an electroplated copper top layer, a copper seed middle layer and a titanium bottom layer. Furthermore, the under bump metal contact 1410 may include an alloy such as titanium (Ti) and copper (Cu), titanium (Ti)-tungsten (W) and copper (Cu), aluminum (Al)-nickel (Ni)-vanadium (V) and copper (Cu), or chromium (Cr) and copper (Cu). The solder bumps 1420 , 1430 , and 1440 may be part of a ball grid array (BGA) and may be made of a metal alloy that may include tin (Sn), silver (Ag), and copper (Cu), or may be made of a metal alloy that may include lead (Pb) and tin (Sn).

[0095] In some embodiments, the glass carrier substrate 200 can be separated (released) from the polymer layer 210. For example, irradiating the light-to-heat conversion layer 220 with a focused laser beam through the back side of the glass carrier substrate 200 can generate sufficient heat to decompose the light-to-heat conversion layer 220 and release the glass carrier substrate 200 from the polymer layer 210. In some embodiments, the polymer layer 210 serves as a backside protection layer for an integrated fan-out (InFO) package.

[0096] In some embodiments, solder bump 1420 (which is electrically connected to metal line 300 through interposer via 620) can be connected to an external ground, and solder bump 1430 (which is electrically connected to metal insulator metal (MIM) capacitor A) can be electrically coupled to an external power supply through metal layer 1110 of metal insulator metal (MIM) capacitor A. In some embodiments, metal insulator metal (MIM) capacitor A is a decoupling capacitor that suppresses voltage spikes from an external power supply connected thereto. Therefore, capacitors B and C can be electrically coupled to an external power supply through metal layer 1110 of metal insulator metal (MIM) capacitor A. Fig.15 The solder bumps not shown in the figure are coupled to the same or different external power supplies. For example, the direction along the y-axis (e.g., into the page; in Fig.15 A metal layer 1110 is formed at a location (not visible in FIG. 1 ) that is electrically connected to metal insulator metal (MIM) decoupling capacitors B and C. In some embodiments, such as Fig.15Additional solder bumps of solder bump 1430, not shown, are electrically coupled to metal insulator metal (MIM) decoupling capacitors B and C. In some embodiments, solder bumps 1440 (which are electrically connected to chip 800) can be electrically connected to an external integrated circuit that provides input and power signals to chip 800. In addition, Fig.15 The number of solder bumps shown is not limited. Therefore, additional solder bumps are within the spirit and scope of the present disclosure.

[0097] According to some embodiments, solder bumps such as solder bumps 1420, 1430, and 1440 can electrically connect the integrated fan-out (InFO) package to one or more external power supplies or ground connections. The external power supply is, for example, a power supply that is not integrated into the integrated fan-out (InFO) package. For example, an integrated fan-out (InFO) package having metal insulator metal (MIM) capacitors A, B, and C can be connected to a wafer or printed circuit board (PCB) having solder bump receivers through solder bumps 1420, 1430, and 1440. Metal insulator metal (MIM) capacitors A, B, and C can be used for internal or external components of the integrated fan-out (InFO) package.

[0098] The present disclosure is directed to a method for forming a metal insulator metal (MIM) decoupling capacitor with scalable capacitance. The metal insulator metal (MIM) decoupling capacitor described in the present disclosure can be integrated (or embedded) into a three-dimensional integrated circuit package (e.g., a chip on wafer on substrate (CoWoS) or an integrated fan-out (InFO) package). In some embodiments, the metal insulator metal (MIM) capacitors described in the present disclosure are characterized by high dielectric constant dielectric materials and have different shapes and sizes. For example, a larger range of capacitance values ​​can be achieved by adjusting (i) the area of ​​each metal insulator metal (MIM) capacitor; (ii) the material type of the high dielectric constant dielectric; and (iii) the thickness of the high dielectric constant dielectric. In some embodiments, a MIM capacitor with a capacitance ranging from femtofarads (fF) (e.g., 10 -15 Farad) to nanofarad (nF) range (e.g. 10 -9 Farads). Therefore, metal insulator metal (MIM) capacitors suitable for electrical components requiring different capacitances can be integrated into a packaging structure (eg, a single three-dimensional integrated circuit).

[0099] In some embodiments disclosed herein, a method for manufacturing a semiconductor structure includes depositing a polymer layer on a carrier substrate, and forming a first capacitor structure and a second capacitor structure on the polymer layer. Forming the first capacitor structure and the second capacitor structure includes: forming a first redistribution layer having a metal line on a portion of the polymer layer; depositing a photoresist layer on the first redistribution layer; and etching the photoresist layer to form a first interposer through hole opening and a second interposer through hole opening spaced apart in the photoresist layer, wherein the first interposer through hole opening and the second interposer through hole opening respectively expose a portion of the metal line of the corresponding redistribution layer, and the first interposer through hole opening is wider than the second interposer through hole opening. Forming the first capacitor structure and the second capacitor structure also includes: depositing metal in the first interposer through hole opening and the second interposer through hole opening to form a first interposer through hole structure and a second interposer through hole structure respectively contacting the metal line; removing the photoresist layer; forming a high dielectric constant dielectric on the top surface of the first interposer through hole structure and the second interposer through hole structure; and depositing a metal layer on the high dielectric constant dielectric layer to form a first capacitor and a second capacitor respectively. In addition, the method includes forming a second redistribution layer on the first capacitor and the second capacitor. In some embodiments, before forming the second redistribution layer, attaching one or more wafers to the polymer layer adjacent to the first interposer through-hole structure and the second interposer through-hole structure. In some embodiments, the method further comprises forming a third redistribution layer on the second redistribution layer; attaching a plurality of solder bumps to the third redistribution layer; attaching a printed circuit board to the solder bumps; and removing the carrier substrate. In some embodiments, the high-k dielectric comprises silicon nitride (SiN x ), silicon oxide (SiO2), silicon oxynitride (SiON x ), hafnium oxide (HfO x ), Hafnium Silicate (HfSiO x ), titanium oxide (TiO2), tantalum oxide (TaO x), polybenzoxazole, polyimide, spin on glass, liquid silicon oxide (SiO2), strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lead zirconate titanate (PbZrTiO3), or a combination thereof. In some embodiments, etching the photoresist layer to form a first interposer via opening and a second interposer via opening spaced apart includes forming a first interposer via opening and a second interposer via opening having substantially equal lengths. In some embodiments, forming a high-k dielectric includes forming a stack having a bottom layer of zirconium oxide (ZrO2), a middle layer of aluminum oxide (Al2O3), and a top layer of zirconium oxide (ZrO2). In some embodiments, forming the first capacitor structure and the second capacitor structure includes forming a first capacitor having a larger surface area than the second capacitor based on a length and a width of the first interposer via structure and the second interposer via structure. In some embodiments, forming a high-k dielectric includes setting an epoxy-based material to surround a plurality of sidewalls of a first interposer via structure and a second interposer via structure; depositing the high-k dielectric material on the epoxy-based material and the first interposer via structure and the second interposer via structure; and etching the high-k dielectric material in the epoxy-based material.

[0100] In some embodiments of the present disclosure, an interposer structure includes: a polymer layer; a first redistribution layer on the polymer layer; and spaced-apart capacitor structures having different surface areas on the first redistribution layer. Each spaced-apart capacitor structure includes: an interposer via in contact with the first redistribution layer (wherein the surface area of ​​the capacitor structure is based on the length and width of the interposer via); a dielectric material covering the top surface of the interposer via (wherein the dielectric material is separated from the sidewalls of the interposer via and the first redistribution layer); and a top metal layer on the dielectric material. The interposer structure also includes: a chip attached to the polymer layer and adjacent to the spaced-apart capacitor structures; a molding compound disposed between the chip and each spaced-apart capacitor structure; and a second redistribution layer disposed on the chip and the spaced-apart capacitor structures. In some embodiments, the second redistribution layer includes a plurality of electrical contacts for electrically connecting to the chip. In some embodiments, the interposer structure also includes a third redistribution layer for electrically connecting to the second redistribution layer, and a plurality of solder bumps for electrically connecting to the third redistribution layer and the spaced-apart capacitor structures. In some embodiments, the width of each interposer via is between about 10 micrometers (μm) and about 1000 micrometers. In some embodiments, the dielectric material has a dielectric constant between about 3.9 and about 1000. In some embodiments, the dielectric material comprises silicon nitride (SiN x ), silicon oxide (SiO2), silicon oxynitride (SiONx ), hafnium oxide (HfO x ), Hafnium Silicate (HfSiO x ), titanium oxide (TiO2), tantalum oxide (TaO x ), polybenzoxazole, polyimide, spin on glass, liquid silicon oxide (SiO2), strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lead zirconate titanate (PbZrTiO3), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof. In some embodiments, the separated capacitor structure includes a first capacitor structure having a first interposer via and a second capacitor structure having a second interposer via, wherein the first interposer via has a different width or length than the second interposer via.

[0101] In some embodiments, a semiconductor structure includes a first redistribution layer having solder bumps and an interposer structure for electrically connecting to the first redistribution layer. The interposer structure includes capacitor structures, wherein each capacitor structure includes: an interposer via for electrically coupling to the first redistribution layer; a high dielectric constant dielectric on the interposer via; and a metal layer on the high dielectric constant dielectric. The structure also includes one or more chips and a molding compound surrounding the one or more chips and the capacitor structures. In some embodiments, the high dielectric constant dielectric and the metal layer of each capacitor structure are spaced apart from the sidewalls of the interposer via. In some embodiments, the surface area of ​​each capacitor structure is defined by the length and width of the interposer via. In some embodiments, the capacitor structure has a rectangular, circular, elliptical shape or a combination thereof. In some embodiments, the high dielectric constant dielectric comprises silicon nitride (SiN x ), silicon oxide (SiO2), silicon oxynitride (SiON x ), hafnium oxide (HfO x ), Hafnium Silicate (HfSiO x ), titanium oxide (TiO2), tantalum oxide (TaO x ), polybenzoxazole, polyimide, spin on glass, liquid silicon oxide (SiO2), strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lead zirconate titanate (PbZrTiO3), zirconium oxide (ZrO2), aluminum oxide (Al2O3) or a combination thereof.

[0102] It should be understood that the "Detailed Description" section, rather than the "Abstract" section, is intended to be used to interpret the claims. The Abstract of the present disclosure may set forth one or more but not all possible embodiments of the present disclosure and, therefore, is not intended to limit the dependent claims in any way.

[0103] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same benefits as the embodiments introduced in the present disclosure. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: Include: depositing a polymer layer on a carrier substrate; Forming a first capacitor structure and a second capacitor structure separated from each other on the polymer layer, wherein forming the first capacitor structure and the second capacitor structure separated from each other comprises: forming a first redistribution layer on a portion of the polymer layer, the first redistribution layer comprising a plurality of metal lines; depositing a photoresist layer on the first redistribution layer; Etching the photoresist layer to form a first interposer via opening and a second interposer via opening spaced apart from each other in the photoresist layer to expose a first portion and a second portion of a metal line among the metal lines of the first redistribution layer, wherein the first interposer via opening is wider than the second interposer via opening; Depositing a metal in the first interposer via opening and the second interposer via opening to form a first interposer via structure and a second interposer via structure contacting the first portion and the second portion of the metal line, respectively; removing the photoresist layer; Forming a high dielectric constant dielectric on a top surface of the first interposer through-hole structure and a top surface of the second interposer through-hole structure respectively; as well as Depositing a metal layer on the high-k dielectrics to form the first capacitor structure and the second capacitor structure respectively; as well as A second redistribution layer is formed on the first capacitor structure and the second capacitor structure that are spaced apart from each other.

2. The method according to claim 1, characterized in that Prior to forming the second redistribution layer, one or more wafers are attached to the polymer layer adjacent to the first interposer via structure and the second interposer via structure.

3. The method according to claim 1, characterized in that Also includes: forming a third redistribution layer on the second redistribution layer; attaching a plurality of solder bumps to the third redistribution layer; attaching a printed circuit board to the solder bumps; and The carrier substrate is removed.

4. The method according to claim 1, characterized in that: The high-k dielectric includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, hafnium silicate, titanium oxide, tantalum oxide, polybenzoxazole, polyimide, spin-on-glass, strontium titanate, barium titanate, barium strontium titanate, lead zirconate titanate, or a combination thereof.

5. The method according to claim 1, characterized in that Etching the photoresist layer to form the first interposer via opening and the second interposer via opening that are spaced apart includes forming the first interposer via opening and the second interposer via opening to have substantially equal lengths.

6. The method according to claim 1, characterized in that Forming the high-k dielectric separately includes forming a stack having a bottom layer of zirconium oxide, a middle layer of aluminum oxide, and a top layer of zirconium oxide.

7. The method according to claim 1, characterized in that Separately forming the spaced-apart first and second capacitor structures includes forming the first capacitor structure to have a larger surface area than the second capacitor structure based on a length and a width of the first and second interposer via structures.

8. The method according to claim 1, characterized in that Forming the high-k dielectric on the top surface of the first interposer through-hole structure and the top surface of the second interposer through-hole structure respectively comprises: Disposing an epoxy-based material around a plurality of sidewalls of the first interposer via structure and the second interposer via structure; depositing a high-k dielectric material over the epoxy-based material and the first interposer via structure and the second interposer via structure; and The high-k dielectric material is etched into the epoxy-based material.

9. An intermediate layer structure, characterized in that: Include: a polymer layer; a first redistribution layer disposed on the polymer layer; a plurality of spaced-apart capacitor structures having different surface areas on the first redistribution layer, wherein each of the spaced-apart capacitor structures comprises: an interposer via contacting the first redistribution layer, wherein a surface area of ​​the capacitor structure is based on a length and a width of the interposer via; a dielectric material covering a top surface of the interposer via, wherein the dielectric material is spaced apart from sidewalls of the interposer via and the first redistribution layer; and a top metal layer located on the dielectric material; a wafer attached to the polymer layer and adjacent to the spaced-apart capacitor structures, wherein the dielectric materials in the spaced-apart capacitor structures are separated from each other; a molding compound disposed between the wafer and each of the spaced-apart capacitor structures; and A second redistribution layer is disposed on the wafer and the spaced-apart capacitor structures.

10. The interposer structure according to claim 9, characterized in that: The second redistribution layer includes a plurality of electrical contacts for electrically connecting to the wafer.

11. The interposer structure according to claim 9, characterized in that: Also includes: a third redistribution layer electrically connected to the second redistribution layer; and A plurality of solder bumps are used to electrically connect to the third redistribution layer and the spaced apart capacitor structures.

12. The interposer structure according to claim 9, characterized in that: The width of the interposer vias is between 10 microns and 1000 microns.

13. The interposer structure according to claim 9, characterized in that: The dielectric constant of the dielectric material is between 3.9 and 1000.

14. The interposer structure according to claim 9, characterized in that: The dielectric material includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, hafnium silicate, titanium oxide, tantalum oxide, polybenzoxazole, polyimide, spin-on-glass, strontium titanate, barium titanate, barium strontium titanate, lead zirconate titanate, or a combination thereof.

15. The interposer structure according to claim 9, characterized in that: The spaced-apart capacitor structures include a first capacitor structure having a first interposer via and a second capacitor structure having a second interposer via, wherein the first interposer via has a different width or a different length than the second interposer via.

16. A semiconductor structure, characterized in that: Include: a first redistribution layer comprising a plurality of solder bumps; An interposer structure, electrically connected to the first redistribution layer, and comprising: A plurality of spaced-apart capacitor structures, wherein each of the spaced-apart capacitor structures comprises: an interposer via for electrically coupling to the first redistribution layer; A high-k dielectric material located on the interposer through hole; a metal layer disposed on the high-k dielectric, wherein the high-k dielectric in the spaced-apart capacitor structures is separated from each other; as well as one or more wafers; as well as A molding compound surrounds the one or more wafers and the spaced-apart capacitor structures, wherein the interposer vias in the spaced-apart capacitor structures have at least two widths.

17. The semiconductor structure according to claim 16, characterized in that: The high-k dielectric and the metal layer of each of the spaced-apart capacitor structures are spaced apart from sidewalls of the interposer via.

18. The semiconductor structure according to claim 16, characterized in that The surface area of ​​each of the spaced-apart capacitor structures is defined by the length and width of the interposer via.

19. The semiconductor structure according to claim 16, characterized in that The spaced-apart capacitor structures have a rectangular, circular, oval shape or a combination thereof.

20. The semiconductor structure according to claim 16, wherein: The high-k dielectric includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, hafnium silicate, titanium oxide, tantalum oxide, polybenzoxazole, polyimide, spin-on-glass, strontium titanate, barium titanate, barium strontium titanate, lead zirconate titanate, zirconium oxide, aluminum oxide or a combination thereof.

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