Methods of manufacturing capacitors and semiconductor devices, and semiconductor devices and apparatuses

Abstract

Provided are a method of manufacturing a capacitor and a semiconductor device (i.e., a capacitor forming method and a semiconductor device forming method), a semiconductor device, and an apparatus including the semiconductor device. The capacitor forming method can include sequentially forming a first molding layer, a first support material layer, and a second molding layer on a substrate; forming a mask pattern on the second molding layer; forming a recess in the second molding layer, the first support material layer, and the first molding layer using the mask pattern as a mask; forming a lower electrode in the recess; removing the mask pattern through a dry cleaning process; reducing a width of an upper portion of the lower electrode; removing the first molding layer; forming a dielectric layer on a surface of the lower electrode; and forming an upper electrode on the dielectric layer.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0092650, filed July 30, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a method of forming a capacitor, a method of forming a semiconductor device, a semiconductor device, and a semiconductor memory device including the semiconductor device, and more particularly, to a capacitor, a semiconductor device, and a semiconductor memory device having superior electrical properties and a method of easily manufacturing the same. BACKGROUND

[0003] In order to obtain a memory device having superior properties, it can be necessary to improve the properties of a data storage device. In particular, for a DRAM in which data is stored in a capacitor, the properties of the capacitor can affect the properties of the memory device. SUMMARY

[0004] The inventive concept provides a method of easily forming a capacitor having superior properties.

[0005] The inventive concept provides a method of easily manufacturing a semiconductor device having superior properties.

[0006] The inventive concept provides a semiconductor device having superior properties and capable of being easily manufactured.

[0007] The inventive concept provides a semiconductor memory device having superior properties and capable of being easily manufactured.

[0008] According to some embodiments of the inventive concept, there is provided a capacitor forming method including: sequentially forming a first molding layer, a first support material layer, and a second molding layer on a substrate; forming a mask pattern on the second molding layer; forming a recess in the second molding layer, the first support material layer, and the first molding layer using the mask pattern as a mask; forming a lower electrode in the recess; removing the mask pattern through a dry cleaning process; reducing a width of an upper portion of the lower electrode; removing the first molding layer; forming a dielectric layer on a surface of the lower electrode; and forming an upper electrode on the dielectric layer.

[0009] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device is provided. The method can include sequentially forming a first molding layer, a first support material layer, and a second molding layer on a substrate; forming a mask pattern on the second molding layer; patterning the first molding layer, the first support material layer, and the second molding layer by using the mask pattern as a mask to form a recess in the first molding layer, the first support material layer, and the second molding layer; forming a lower electrode in the recess; removing the mask pattern by a dry cleaning process to expose an upper portion of the lower electrode; reducing a width of the upper portion of the lower electrode; removing the first molding layer; forming a dielectric layer on a surface of the lower electrode; and forming an upper electrode on the dielectric layer.

[0010] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device is provided. The method can include forming a transistor including a gate structure and an impurity region on a substrate; forming an interlayer insulating layer covering the transistor and including a contact plug electrically connected to the impurity region on the substrate; sequentially forming a first molding layer, a first support material layer, and a second molding layer on the interlayer insulating layer; forming a mask pattern on the second molding layer; forming a recess in the first molding layer, the first support material layer, and the second molding layer using the mask pattern as a mask; forming a lower electrode material layer on an upper surface of the mask pattern and in the recess; forming a lower electrode by removing a portion of the lower electrode material layer until the upper surface of the mask pattern is exposed; removing the mask pattern by a dry cleaning process; reducing a width of an upper portion of the lower electrode; removing the first molding layer; forming a dielectric layer on a surface of the lower electrode; and forming an upper electrode on the dielectric layer.

[0011] According to some embodiments of the inventive concept, a semiconductor device is provided. The semiconductor device can include a transistor on a substrate, the transistor including a gate structure and an impurity region; a first interlayer insulating layer on the transistor and including a contact plug electrically connected to the impurity region; and a capacitor on the first interlayer insulating layer. The capacitor can include a lower electrode electrically connected to the contact plug, a dielectric layer covering a surface of the lower electrode, and an upper electrode on the dielectric layer. The lower electrode can include a main portion extending in a vertical direction perpendicular to an upper surface of the substrate and having a first horizontal width, and an upper portion on the main portion and having a second horizontal width narrower than the first horizontal width.

[0012] According to some embodiments of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device can include a plurality of semiconductor memory devices on a cell region of a substrate. The substrate can further include a peripheral region. The semiconductor memory device can further include a peripheral circuit on the peripheral region. Each of the semiconductor memory devices can include the aforementioned semiconductor device. The cell region can include a center region and an edge portion between the center region and the peripheral region, and within the center region, the lower electrode has substantially the same vertical dimension. BRIEF DESCRIPTION OF DRAWINGS

[0013] Example embodiments of the inventive concept will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a schematic plan view of an integrated circuit device according to some embodiments of the inventive concept;

[0015] Figure 2 is a block diagram of a structure of an integrated circuit device including a dynamic random access memory (DRAM) device according to some embodiments of the inventive concept;

[0016] Figure 3 is a plan view of a schematic configuration of an integrated circuit device according to some embodiments of the inventive concept;

[0017] Figure 4 is a plan view of a layout of a semiconductor device according to some embodiments of the inventive concept;

[0018] Figure 5 is a side sectional view taken along line A-A' of Figure 4 ;

[0019] Figures 6A-6C is a side sectional view of a lower electrode and a second support layer according to some embodiments of the inventive concept;

[0020] Figure 7 is a side sectional view taken along line A-A' of Figure 4 ;

[0021] Figure 8 is a side sectional view taken along line A-A' of Figure 4 ;

[0022] Figure 9 is a side sectional view taken along line A-A' of Figure 4 ;

[0023] Figures 10A-10P is a side sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept; and

[0024] Figures 11A-11I is a side sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0025] Some embodiments will now be described more fully with reference to the accompanying drawings. In the drawings, like reference numerals can indicate similar components, and the replicative description of like components can be omitted.

[0026] Figure 1 is a plan view of a schematic structure of an integrated circuit device 10 according to some embodiments of the inventive concepts.

[0027] The integrated circuit device 10 can include a substrate 12 including a first region 22, a second region 24 surrounding the first region 22, and an interface region 26 between the first region 22 and the second region 24.

[0028] The substrate 12 can include a semiconductor element such as Si or Ge or at least one compound semiconductor selected from SiGe, SiC, GaAs, InAs, and InP. The substrate 12 can include a conductive region such as an impurity-doped well or an impurity-doped structure, for example.

[0029] In some embodiments, the first region 22 can be a memory cell region of the integrated circuit device 10. In some embodiments, the first region 22 can be a memory cell region of a dynamic random access memory (DRAM). The first region 22 can include a unit memory cell including a transistor and a capacitor or a unit memory cell including a switching device and a variable resistor.

[0030] The second region 24 can include a core region or a peripheral circuit region (hereinafter, referred to as a "peripheral circuit region"). A peripheral circuit for driving a memory cell in the first region 22 can be provided in the second region 24.

[0031] A plurality of conductive lines provided to achieve electrical connection between the first region 22 and the second region 24 and an insulating structure for insulation between the first region 22 and the second region 24 can be provided in the interface region 26.

[0032] Figure 2 is a block diagram of a structure of an integrated circuit device including a DRAM device according to some embodiments of the inventive concepts.

[0033] Referring to Figure 2 In the integrated circuit device 10, the first region 22 can include a memory cell region of a DRAM device, and the second region 24 can include a peripheral circuit region of the DRAM device. The first region 22 can include a memory cell array 22A. In the memory cell array 22A, a plurality of memory cells for storing data can be arranged in a row direction and a column direction. Each of the plurality of memory cells can include a cell capacitor and an access transistor. A gate of the access transistor can be connected to a corresponding one of a plurality of word lines arranged in the row direction, one of a source and a drain of the access transistor can be connected to a bit line or a complementary bit line arranged in the column direction, and the other can be connected to the cell capacitor.

[0034] The second region 24 can include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, a mode register set / extended mode register set (MRS / EMRS) circuit 62, an address buffer 64, and a data input / output circuit 66.

[0035] The sense amplifier 54 can sense and amplify data of a memory cell of the memory cell array 22A, and can store the data in the memory cell. The sense amplifier 54 can be implemented by a cross-coupled amplifier connected between a bit line and a complementary bit line included in the memory cell array 22A.

[0036] Data DQ input via the data input / output circuit 66 can be written in the memory cell array 22A based on the address signal ADD, and data DQ read from the memory cell array 22A based on the address signal ADD can be output to the outside via the data input / output circuit 66. In order to designate a memory cell to which data is to be written or from which data is to be read, the address signal ADD can be input to the address buffer 64. The address buffer 64 can temporarily store the address signal ADD input from the external source.

[0037] The row decoder 52 can decode a row address from the address signal ADD output from the address buffer 64 to designate a word line connected to a memory cell to which data is input or from which data is output. In other words, the row decoder 52 can enable the word line by decoding the row address output from the address buffer 64 in a data write or read mode. The row decoder 52 can enable the word line by decoding a row address generated from an address counter in a self-refresh mode.

[0038] The column decoder 56 can decode a column address from the address signal ADD output from the address buffer 64 to designate a bit line connected to a memory cell to which data is input or from which data is output. The memory cell array 22A can output data from or write data in the memory cell designated by the row address and the column address.

[0039] The command decoder 60 can receive a command signal CMD received from an external source, and decode the received command signal CMD to internally generate a decoded command signal, for example, a self-refresh entry command or a self-refresh exit command.

[0040] The MRS / EMRS circuit 62 can set an internal mode register in response to the address signal ADD and the MRS / EMRS command for designating an operation mode of the integrated circuit device 10.

[0041] Although Figure 2Although not shown in FIG. 1, the integrated circuit device 10 can further include a clock circuit for generating a clock signal and a power circuit for receiving a power voltage from an external source and generating or distributing internal voltages, for example.

[0042] The self-refresh control circuit 58 can control a self-refresh operation of the integrated circuit device 10 in response to a command output by the command decoder 60. The command decoder 60 can include an address counter, a timer, and a core voltage generator. The address counter can generate a row address for designating a row address on which a self-refresh is to be performed in response to a self-refresh entry command output by the command decoder 60, and can apply the row address to the row decoder 52. The address counter can stop a counting operation in response to a self-refresh exit command output by the command decoder 60.

[0043] Figure 3 is a plan view of a schematic configuration of an integrated circuit device 70 according to some embodiments of the inventive concepts.

[0044] Referring to Figure 3 , the integrated circuit device 70 can include a plurality of first regions 22. Each of the plurality of first regions 22 can be surrounded by a second region 24 with an interface region 26 therebetween. In the integrated circuit device 70, each of the plurality of first regions 22 can be a memory cell array region MCA of a DRAM device, and the second region 24 can be a peripheral circuit region of the DRAM device.

[0045] In the plurality of first regions 22, the memory cell array region MCA can include the memory cell array 22A described with reference to Figure 2 Each of the plurality of first regions 22 can be surrounded by the interface region 26.

[0046] The second region 24 can include a sub word line driver block SWD, a sense amplifier block S / A, and a junction block CJT. In the second region 24, a plurality of sub word line driver blocks SWD can be arranged along a word line direction of the memory cell array region MCA, and a plurality of sense amplifier blocks S / A can be arranged along a bit line direction. A plurality of bit line sense amplifiers can be arranged in the sense amplifier block S / A. The junction block CJT can be located at an intersection of the sub word line driver block SWD and the sense amplifier block S / A. Ground drivers and power drivers for driving the bit line sense amplifiers can be alternately arranged in the junction block CJT.

[0047] Although Figure 3 not shown in FIG. 1, peripheral circuits such as an inverter chain or an input / output circuit can also be provided in the second region 24.

[0048] Figure 4 is a plan view of a layout of a semiconductor device 1 according to some embodiments of the inventive concepts.Figure 5 is a side cross-sectional view taken along Figure 4 line A-A' of FIG. 1.

[0049] Referring to Figure 4 and Figure 5 , the semiconductor substrate 100 can include a first region R1 and a second region R2. For example, the first region R1 can include a peripheral circuit region, and the second region R2 can include a cell region.

[0050] In some embodiments, a peripheral circuit including a row decoder and a column decoder, a page buffer, and an input / output circuit can be disposed on the first region R1 of the semiconductor substrate 100. In some embodiments, the peripheral circuit can include CMOS transistors, resistors, and / or capacitors electrically connected to a memory cell array. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] In some embodiments, a memory cell array including a plurality of memory cells can be disposed on the second region R2 of the semiconductor substrate 100. The memory cell array can include a plurality of memory cells and a plurality of word lines WL and bit lines BL electrically connected to the memory cells. In some embodiments, each memory cell can include a capacitor 150 including a lower electrode 151, an upper electrode 155, and a dielectric layer 153 located between the lower electrode 151 and the upper electrode 155. Further, since a first support layer 157a and a second support layer 157b horizontally connect the lower electrodes 151 of the memory cells, the lower electrodes 151 do not collapse.

[0052] In detail, a device isolation layer 101 defining active regions ACT can be formed on the second region R2 of the semiconductor substrate 100. Each active region ACT can have a bar shape, and a long axis of each active region ACT can be disposed in a direction oblique to the word lines WL and the bit lines BL. In some embodiments, each active region ACT can extend longitudinally in a direction crossing the word lines WL and the bit lines BL as shown in Figure 4 .

[0053] The word lines WL can be disposed to cross the active regions ACT. In some embodiments, the word lines WL can be formed by disposing a gate insulating layer GL in a recessed region recessed by a certain depth from a surface of the active regions ACT. Further, an upper surface of the word lines WL can be located at a lower level than an upper surface of the active regions ACT, and the recessed region forming the word lines WL can be filled with an insulating material.

[0054] A plurality of impurity regions 103 such as source regions and drain regions can be formed in the active regions ACT at both sides of the word lines WL. The impurity regions 103 can form a plurality of MOS transistors together with the word lines WL.

[0055] Bit lines BL can be disposed across the word lines WL on the second region R2 of the semiconductor base 100. A first interlayer insulating layer 110 can be located between the bit lines BL and the semiconductor base 100. Bit line contact plugs DC electrically connecting the impurity regions 103 to the bit lines BL can be formed in the first interlayer insulating layer 110.

[0056] The first interlayer insulating layer 110 can include, for example, a high-density plasma (HDP) oxide film, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), tonen silazene (TOSZ), or a combination thereof. In some embodiments, the first interlayer insulating layer 110 can include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The low-k material can have a dielectric constant lower than that of silicon dioxide.

[0057] Further, the device isolation layer 101 can define a peripheral active region in the first region Rl of the semiconductor base 100. A peripheral gate electrode PG can be disposed to cross the peripheral active region, and peripheral source and drain regions 105 can be formed in the peripheral active region at both sides of the peripheral gate electrode PG.

[0058] The second interlayer insulating layer 120 can cover the bit lines BL of the first region Rl and the peripheral gate electrode PG of the second region R2. The second interlayer insulating layer 120 can include an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or a combination thereof. Optionally, the second interlayer insulating layer 120 can include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. As used herein, "element A covers element B" (or similar language) means that element A is on or superposed with element B, but does not necessarily mean that element A completely covers element B.

[0059] A plurality of contact plugs BC electrically connecting the data storage elements (i.e., the capacitors 150) to the impurity regions 103 can be formed in the second interlayer insulating layer 120 of the second region R2. In some embodiments, the contact plugs BC can be disposed in the active regions ACT at both sides of each bit line BL. Further, the contact plugs BC can be arranged in a continuous equilateral triangle, honeycomb, or zigzag form in a plan view.

[0060] Further, the contact plug BC can be formed by forming a contact hole exposing the impurity region 103 in the second interlayer insulating layer 120, depositing a conductive layer for burying the contact hole, and planarizing and node separating the conductive layer. The contact plug BC can include, for example, a polysilicon layer doped with an impurity, a metal layer, a conductive metal nitride layer, and a metal silicide layer, or a combination thereof.

[0061] In some embodiments, a plurality of contact pads CP can be respectively formed on the contact plugs BC. The contact pads CP can be arranged two-dimensionally on the second interlayer insulating layer 120 of the second region R2. The contact pads CP can increase a contact area between the lower electrode 151 of the capacitor 150 formed thereon and each contact plug BC. The contact pads CP can have a shape in which two contact pads CP adjacent with respect to each bit line BL located therebetween extend in opposite directions.

[0062] A third interlayer insulating layer 130 can be formed between the contact pads CP. The third interlayer insulating layer 130 can include, for example, an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or a combination thereof. In some embodiments, the third interlayer insulating layer 130 can include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0063] The lower electrodes 151 of the capacitors 150 can be respectively formed on the contact pads CP. In some embodiments, the lower electrodes 151 can be arranged in the form of a continuous equilateral triangle, a honeycomb shape, or a zigzag shape in a plan view.

[0064] The lower electrode 151 as a certain conductor can include, for example, cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium silicon nitride (TiSiN), tungsten nitride (WN), platinum oxide (PtO), ruthenium oxide (RuO x ), iridium oxide (IrO x ), SRO (SrRuO3), BSRO ((Ba, Sr) RuO3), CRO (CaRuO3), LSCO ((La, Sr) CoO3), or a combination thereof. However, the material of the lower electrode 151 is not limited to the above materials.

[0065] The lower electrode 151 can be supported by the first support layer 157a and the second support layer 157b. The lower electrode 151 can have a high aspect ratio of about 10 to about 40, and when the first support layer 157a and the second support layer 157b are omitted, the lower electrode 151 can fall over to the side and collapse, or can come into contact with an adjacent lower electrode 151. Accordingly, the first support layer 157a and the second support layer 157b are provided to support the lower electrode 151, which does not fall over to the side or collapse.

[0066] The dielectric layer 153 can be conformally formed on a surface of the lower electrode 151, and the upper electrode 155 can be formed on the dielectric layer 153. After the capacitor 150 is formed in the second region R2, a buried insulating layer 160 covering the first region R1 and the second region R2 can be formed.

[0067] Figures 6A-6C is a side sectional view of the lower electrode 151 and the second support layer 157b according to some embodiments of the inventive concept, and corresponds to Figure 5 Region VI of

[0068] Referring to Figure 6A , the lower electrode 151 can include a body portion 151b and an upper portion 151u. The lower electrode 151 can have a shoulder portion 151s between the body portion 151b and the upper portion 151u. In other words, the size of the lower electrode 151 in the horizontal direction can discontinuously change between the body portion 151b and the upper portion 151u. In some embodiments, the size of the lower electrode 151 in the horizontal direction can sharply change between the body portion 151b and the upper portion 151u. The level of the shoulder portion 151s can be between the upper end of the lower electrode 151 and the upper surface of the first support layer 157a. The body portion 151b and the upper portion 151u can extend in a direction perpendicular to the upper surface of the semiconductor substrate 100.

[0069] The upper portion 151u can be supported by the second support layer 157b in the axial direction. In some embodiments, the upper surface of the second support layer 157b can be at substantially the same level as the upper end of the lower electrode 151. The upper surface of the second support layer 157b can be located on substantially the same plane as the upper end of the lower electrode 151. In some embodiments, the upper surface of the second support layer 157b and the upper end of the lower electrode 151 can be coplanar with each other as shown in Figure 6A

[0070] ​The body portion 151b can have a first horizontal dimension W1, and the upper portion 151u can have a second horizontal dimension W2. The first horizontal dimension W1 can be greater than the second horizontal dimension W2. In some embodiments, the second horizontal dimension W2 can be about 60% to about 90% of the first horizontal dimension W1. The first horizontal dimension W1 can refer to a width of the body portion 151b in a horizontal direction, and the second horizontal dimension W2 can refer to a width of the upper portion 151u in the horizontal direction. The horizontal direction can be parallel to the upper surface of the semiconductor substrate 100.

[0071] In some embodiments, the lower electrode 151 can be columnar. In this case, the first horizontal dimension W1 can be a diameter of the body portion 151b, and the second horizontal dimension W2 can be a diameter of the upper portion 151u. In some embodiments, the lower electrode 151 can have a (circular) cylindrical shape as shown in Figure 6A 、 Figure 6B and Figure 6C . An element having a columnar shape can refer to an element including a bottom portion and a vertical portion protruding from the bottom portion in a vertical direction. The vertical portion of the element can or can not have a side surface perpendicular to the upper surface of the substrate. In addition, the vertical portion of the element can have a width varying in a height direction thereof.

[0072] Referring to Figure 6B , the lateral surface of the upper portion 151u can form a slope with the upper surface of the semiconductor substrate 100. In contrast, the body portion 151b can include a lateral surface extending perpendicular to the upper surface of the semiconductor substrate 100. The term "lateral surface" can refer to "side surface".

[0073] The body portion 151b can have a first horizontal dimension W1, and an upper end of the upper portion 151u can have a second horizontal dimension W2. In some embodiments, as shown in Figure 6B , the upper end of the upper portion 151u can contact the dielectric layer 153. The first horizontal dimension W1 can be greater than the second horizontal dimension W2. The horizontal dimension of the upper portion 151u can decrease in a direction away from the body portion 151b. In some embodiments, the second horizontal dimension W2 can be about 60% to about 90% of the first horizontal dimension W1.

[0074] Referring to Figure 6C , the lateral surface of the upper portion 151u can form a slope with the upper surface of the semiconductor substrate 100. Figure 6C The upper portion 151u of the shoulder portion 151s can have a curved surface having a slope decreasing as it gets closer to the upper end thereof. In contrast, the body portion 151b can include a lateral surface extending perpendicular to the upper surface of the semiconductor substrate 100. The shoulder portion 151s can also have a curved surface having a tangent slope varying depending on a position.

[0075] The upper end of the upper portion 151u can not be planar. In this case, the upper surface of the second support layer 157b can have substantially the same level as the upper end of the lower electrode 151.

[0076] Although Figures 6A-6C is not shown in the drawings, in some embodiments, the shoulder portion 151s can be located at substantially the same level as the upper surface of the first support layer 157a. This will be described in detail later.

[0077] Figure 7 is a side cross-sectional view taken along line A-A' of Figure 4 according to some embodiments of the inventive concept. Figure 7 The structure shown in Figure 5 differs from the structure shown in Figures 6A-6C in that the level of the shoulder portion 151s of the lower electrode 151 is substantially the same as the level of the upper surface of the first support layer 157a. This difference will now be described primarily.

[0078] Referring to Figure 7 , the level of the shoulder portion 151s can be substantially the same as the level of the upper surface of the first support layer 157a. In some embodiments, the shoulder portion 151s can not be completely level. In this case, the level of the shoulder portion 151s can be represented by the level of the outermost circumference of the shoulder portion 151s, i.e., the level of the circumference formed at the intersection of the side surface of the main body portion 151b and the shoulder portion 151s.

[0079] In some embodiments, the upper portion 151u can have a tapered shape in a direction away from the main body portion 151b. In other words, the upper portion 151u can have a horizontal dimension that gradually decreases in a direction toward its top. In some embodiments, the upper portion 151u can have a shape similar to that of the upper portion 151u in Figure 6B . In other embodiments, the upper portion 151u can have a constant horizontal dimension. In some embodiments, the upper portion 151u can have a shape similar to that of the upper portion 151u in Figure 6A .

[0080] Figure 8 is a side cross-sectional view taken along line A-A' of Figure 4 according to some embodiments of the inventive concept. Figure 8 The structure shown in Figure 7 differs from the structure shown in in the position and shape of the second support layer 157c. This difference will now be described primarily.

[0081] Figure 8The second support layer 157c can cover a portion of the upper surface of the lower electrode 151 and the lateral surface of the upper portion 151u of the lower electrode 151. Specifically, the second support layer 157c can directly contact the upper surface of the lower electrode 151. Furthermore, the second support layer 157c can extend vertically to contact a portion of the lateral surface of the lower electrode 151, which is connected to the upper surface of the lower electrode 151.

[0082] because Figure 8 The second support layer 157c, while contacting the upper surface of the lower electrode 151, also supports the lateral surface of the lower electrode 151, thus... Figure 7 Compared to the previous embodiment, the area of ​​the second support layer 157c that contacts the lateral surface of the lower electrode 151 can at least ensure sufficient lateral strength. In other words, because the second support layer 157c has a reduced area in contact with the lateral surface of the lower electrode 151, and the area saved by the reduced area can be used to increase capacitance, the electrical performance of the memory device can be improved.

[0083] Figure 9 It is based on some embodiments of the inventive concept. Figure 4 The side section view taken by line A-A'. Figure 9 The structure shown in the figure is similar to Figure 7 The difference in the structure shown lies in the location and shape of the second support layer 157d. This difference will now be described in detail.

[0084] Reference Figure 9 The second support layer 157d can be arranged such that the upper end of the lower electrode 151 penetrates the second support layer 157d and protrudes from the upper surface of the second support layer 157d. Specifically, the upper surface of the second support layer 157d and the upper surface of the lower electrode 151 are not on the same plane, and the upper surface of the lower electrode 151 is horizontally higher in the vertical direction than the upper surface of the second support layer 157d. This structure can provide greater process margin during manufacturing and can be easily manufactured.

[0085] Figures 10A-10P This is a side sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0086] Reference Figure 10A A semiconductor substrate 100, including a first region R1 and a second region R2, can be configured. (Referring to the above...) Figure 5 The semiconductor substrate 100 is described in detail, therefore its description is omitted.

[0087] An active region ACT can be defined by forming a device isolation layer 101 in the semiconductor substrate 100. A gate insulating layer GL and a word line WL can be formed after forming a recess extending across the active region ACT. A cap layer including an insulating material can be formed over the word line WL. Further, an impurity region 103 can be formed by implanting an impurity into the active region ACT at both sides of each word line WL. The impurity region 103 can function as a source region or a drain region. The word line WL and the source and drain regions can constitute a transistor.

[0088] Referring to Figure 10B A first interlayer insulating layer 110 can be formed to cover the active region ACT. The first interlayer insulating layer 110 can be provided with a bit line contact plug DC, which can be later electrically connected to a bit line BL. The first interlayer insulating layer 110 can include, for example, silicon oxide.

[0089] Further, a peripheral gate electrode PG can be formed in the first region R1, and transistors for the peripheral circuit region can be provided by forming impurity regions (i.e., peripheral source and drain regions) 105 at both sides of the peripheral gate electrode PG.

[0090] After forming the bit line BL to be electrically connected to the bit line contact plug DC, a second interlayer insulating layer 120 can be formed to cover the bit line BL. A contact plug BC can be provided in the second interlayer insulating layer 120. The contact plug BC can penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be electrically connected to the impurity region 103.

[0091] Each of the contact plug BC and the bit line contact plug DC can independently include, for example, doped polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof.

[0092] In Figure 10B , although the bit line contact plug DC connected to the bit line BL is not seen, when a person of ordinary skill in the art takes another appropriate cross-section different from that of Figure 10B , the bit line contact plug DC connected to the bit line BL can be seen.

[0093] Next, a third interlayer insulating layer 130 covering the second interlayer insulating layer 120 can be formed. A contact pad CP can be provided in the third interlayer insulating layer 130. The contact pad CP can be in contact with the contact plug BC. In Figure 10B , the contact pad CP not in contact with the contact plug BC can be a contact pad CP electrically connected to the contact plug BC positioned further away from the cross-section in a line-of-sight direction.

[0094] Referring to Figure 10CThe first molding layer 140m1, the first support material layer 157am, and the second molding layer 140m2 can be sequentially formed on the third interlayer insulation layer 130.

[0095] Each of the first molding layer 140m1 and the second molding layer 140m2 can include, for example, silicon oxide, and can be formed, for example, by chemical vapor deposition (CVD). For example, each of the first molding layer 140m1 and the second molding layer 140m2 can independently include a high-density plasma (HDP) oxide film, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), tonen silazene (TOSZ), or a combination thereof.

[0096] A thickness of each of the first molding layer 140m1 and the second molding layer 140m2 can be defined by a distance from a lower surface to an upper surface thereof, and can be determined by considering a height of a capacitor lower electrode to be formed. For example, the thickness of each of the first molding layer 140m1 and the second molding layer 140m2 can be about 200 nm to about 4000 nm.

[0097] The first support material layer 157am can include a material having sufficient etching selectivity with respect to the first molding layer 140m1 and the second molding layer 140m2. In addition, when an etching atmosphere for removing the first molding layer 140m1 and the second molding layer 140m2 in a subsequent process (for example, a lift-off process using an etchant including ammonium fluoride (NH4F), hydrofluoric acid (HF), and water) can be used, the first support material layer 157am can include a material having a relatively low etching rate with respect to the etchant.

[0098] For example, the first support material layer 157am can include at least one of SiN, SiCN, SiGe, TaO, and TiO2. In some embodiments, the first support material layer 157am can be formed by performing a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the first support material layer 157am can have a multi-layer structure. For example, the first support material layer 157am can have a multi-layer structure in which at least two layers of an SiN layer, an SiCN layer, an SiGe layer, a TaO layer, and a TiO2 layer are sequentially stacked.

[0099] The first support material layer 157am can have a thickness of, for example, about 100 nm to about 1000 nm.

[0100] Referring to Figure 10D A mask pattern 190m can be formed on the second mold layer 140m2. In some embodiments, the mask pattern 190m can be a hard mask pattern. In some embodiments, the mask pattern 190m can include, for example, polysilicon, silicon nitride, silicon oxide, silicon oxynitride, a spin-on hard mask (SOH), an amorphous carbon layer (ACL), or a combination thereof.

[0101] The mask pattern 190m can be obtained by forming a layer of a mask pattern material film and then applying photolithography thereto. In detail, a layer of a mask pattern material film is formed, and a photoresist pattern is formed thereon by photolithography. Then, the layer of the mask pattern material film is patterned using the photoresist pattern as an etching mask, thereby forming the mask pattern 190m. After the mask pattern 190m is obtained, the photoresist pattern can be removed by a method such as ashing.

[0102] The mask pattern 190m can have a higher pattern density in the second region R2 than in the first region R1. In Figure 10D In the embodiment, a plurality of recess patterns RM of the mask pattern 190m are formed in the mask pattern 190m of the second region R2. In addition, in the embodiment, the recess pattern RM of the mask pattern 190m formed in the second region R2 close to the first region R1 but not seen in the cross section is indicated by a dotted line. Figure 10D In the embodiment, a plurality of recess patterns RM of the mask pattern 190m are formed in the mask pattern 190m of the second region R2. In addition, in the embodiment, the recess pattern RM of the mask pattern 190m formed in the second region R2 close to the first region R1 but not seen in the cross section is indicated by a dotted line.

[0103] Referring to Figure 10E By patterning the first mold layer 140m1, the first support material layer 157a, and the second mold layer 140m2 using the mask pattern 190m as an etching mask, recess patterns RS can be formed at positions where the lower electrode is to be formed. The recess patterns RS can respectively expose the contact pads CP. When the contact pads CP are not formed, the recess patterns RS can expose the contact plugs BC at positions corresponding to the lower electrode.

[0104] The recess patterns RS can be formed by, for example, anisotropic etching. The anisotropic etching can be performed by a method such as HDP etching, reactive ion etching, sputter etching, or reactive ion beam etching. However, the inventive concept is not limited to these methods.

[0105] The width of each recess pattern RS can be constant along its height direction, or can increase in a direction away from the semiconductor substrate 100. In some embodiments, the width of each recess pattern RS can decrease in a direction away from the semiconductor substrate 100. In some embodiments, the width of each recess pattern RS in the horizontal direction can be uniform along its height direction, or can increase or decrease along its height direction, as shown in FIG. 10B. Figure 10E

[0106] A mask pattern 190 having a shape as shown in FIG. 10B can be obtained by partially removing the upper portion of the mask pattern 190m due to anisotropic etching used to form the recess pattern RS. Figure 10E Figure 10E As shown in FIG. 10B, it can be seen that the height or amount of the mask pattern 190 removed in the second region R2 is greater than the height or amount of the mask pattern 190 removed in the first region Rl.

[0107] Although the inventive concept is not intended to be limited to a particular theory, the mask pattern 190 can be based on a loading effect according to the height difference of the regions. In detail, the mask pattern 190m in the first region Rl in which the pattern density is relatively low exhibits a removal having a relatively two-dimensional shape, while the mask pattern 190m in the second region R2 in which the pattern density is relatively high exhibits a removal having a relatively three-dimensional shape. Thus, the removal rate of the mask pattern 190m in the second region R2 can be faster than the removal rate of the mask pattern 190m in the first region Rl. As a result, the thickness of the mask pattern 190 in the first region Rl can be greater than the thickness of the mask pattern 190 in the second region R2. Figure 10D Figure 10D As shown in FIG. 10B, the mask pattern 190 can have an upper surface whose height relatively sharply changes around the boundary between the first region Rl and the second region R2. However, when the loading effect occurs more gently between the first region Rl and the second region R2, the upper surface of the mask pattern 190 can change with a more gentle slope in the horizontal direction over a longer distance.

[0108] As shown in FIG. 10B, the mask pattern 190 can have an upper surface whose height relatively sharply changes around the boundary between the first region Rl and the second region R2. However, when the loading effect occurs more gently between the first region Rl and the second region R2, the upper surface of the mask pattern 190 can change with a more gentle slope in the horizontal direction over a longer distance. Figure 10E Referring to FIG. 11, a lower electrode material layer 151m can be formed in the recess pattern RS. The lower electrode material layer 151m can be formed by CVD or atomic layer deposition (ALD). The lower electrode material layer 151m can fill the inside of the recess pattern RS, and can also cover the upper surface of the mask pattern 190. As used herein, "element A fills element B" (or similar language) means that element A is in element B, but does not necessarily mean that element A completely fills element B.

[0109] Figure 10F Referring to FIG. 11, a lower electrode material layer 151m can be formed in the recess pattern RS. The lower electrode material layer 151m can be formed by CVD or atomic layer deposition (ALD). The lower electrode material layer 151m can fill the inside of the recess pattern RS, and can also cover the upper surface of the mask pattern 190. As used herein, "element A fills element B" (or similar language) means that element A is in element B, but does not necessarily mean that element A completely fills element B.

[0110] ​​​​The lower electrode material layer 151m can include, for example, cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium silicon nitride (TiSiN), tungsten nitride (WN), platinum oxide (PtO), ruthenium oxide (RuO x ), iridium oxide (IrO x ), SRO (SrRuO3), BSRO ((Ba, Sr) RuO3), CRO (CaRuO3), LSCO ((La, Sr) CoO3), or a combination thereof.

[0111] Referring Figure 10G , the lower electrode 151 can be formed by partially removing the lower electrode material layer 151m. The lower electrode 151 can be formed by etch back (EB), chemical mechanical polishing (CMP), or a combination thereof.

[0112] In some embodiments, CMP can be first performed to reduce the difference between the height of the mask pattern 190 in the first region R1 and the height of the mask pattern 190 in the second region R2. At this time, the lower electrode material layer 151m is partially removed, and thus the lower electrodes 151 separated from each other can be formed. Due to the CMP, the mask pattern 190p can be obtained to have a substantially flat upper surface. When planarization is achieved via the CMP, the upper surface of the mask pattern 190p can have a lower level in the first region R1 than in the second region R2, in which the first region R1 has a lower density of pattern than the dense pattern of the second region R2. This can be due to a loading effect. Such a level variation of the upper surface of the mask pattern 190p according to the location can occur gradually. In particular, such a level variation can occur in and near a boundary region between the first region R1 and the second region R2.

[0113] In some embodiments, when the mask pattern 190 is planarized by etch back rather than CMP, a level variation opposite to that shown in Figure 10G may occur. In other words, when the mask pattern 190 is planarized by etch back, the upper surface of the mask pattern 190p can have a higher level in the first region R1 than in the second region R2.

[0114] The second region R2 includes a central region R2C and an edge region R2E. The edge region R2E can be located between the central region R2C and the first region R1. The central region R2C can be defined as a region in which the vertical dimension of the lower electrode 151 is substantially constant. In the edge region R2E, the height of the lower electrode (indicated by the dotted line of FIG. 2A) can not be uniform. Figure 10G ​

[0115] Referring to Figure 10H The lower electrode 151 protruding from the upper surface of the second mold layer 140m2 can be obtained by selectively removing the remaining mask pattern 190p. At this time, the remaining mask pattern 190p can be selectively removed by a dry cleaning process.

[0116] When the remaining mask pattern 190p is removed by dry etching, the second mold layer 140m2 can be damaged, and thus the exposed surface of the lower electrode 151 can be irregular. According to some embodiments of the inventive concept, the remaining mask pattern 190p is removed by a dry cleaning process rather than dry etching. When the dry cleaning process is used, the remaining mask pattern 190p can be removed with high selectivity with respect to the second mold layer 140m2.

[0117] The dry cleaning process can be performed by using a plasma gas including radical species such as fluorine without applying a bias voltage. Thus, in the dry cleaning process, the mask pattern 190p can be removed isotropically. In some embodiments, in the dry cleaning process, the plasma gas can not contain ionic species. In some embodiments, the dry cleaning process can be performed using the plasma gas without an electric bias voltage. For example, during the dry cleaning process, an electric bias voltage can not be applied to the semiconductor substrate 100. In some embodiments, the plasma gas can include fluorine radicals.

[0118] The plasma gas including radical species can be supplied to the mask pattern 190p after being generated by a remote method, but the inventive concept is not limited thereto. In some embodiments, fluorine radicals in the plasma gas can remove the mask pattern 190p by a dry cleaning process in which the fluorine radicals react with silicon of polysilicon forming the mask pattern 190 as follows.

[0119] Si + 4F → SiF4

[0120] For example, C3F8, C2F6, or CF4 can be used as a supply source of fluorine, but the inventive concept is not limited thereto.

[0121] In some embodiments, when the dry cleaning process is used, the etching selectivity between the remaining mask pattern 190p and the second mold layer 140m2 can be about 500:1 to about 1000:1 or about 700:1 to about 900:1. In other words, the ratio of the amount of the remaining mask pattern 190p removed by the dry cleaning process and the amount of the second mold layer 140m2 with respect to the same period of time can be about 500:1 to about 1000:1 or about 700:1 to about 900:1.

[0122] In some embodiments, the lower electrodes 151e1m and 151e2m of the edge region R2E of the second region R2 can include an upper portion having a height thereof slightly smaller than a height of an upper portion of the lower electrode 151 in the center region R2C of the second region R2. In other words, a level of the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E can be lower than a level of the upper surface of the lower electrode 151 of the center region R2C. The lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have an upper surface lower than an upper surface of the other lower electrode. In some embodiments, the lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have a vertical dimension smaller than a vertical dimension of the other lower electrode. In some embodiments, the upper surface of the lower electrode 151 of the center region R2C can be closer to the semiconductor substrate 100 than the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E. Figure 10H In some embodiments, the lower electrodes 151e1m and 151e2m of the edge region R2E of the second region R2 can include an upper portion having a height thereof slightly smaller than a height of an upper portion of the lower electrode 151 in the center region R2C of the second region R2. In other words, a level of the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E can be lower than a level of the upper surface of the lower electrode 151 of the center region R2C. The lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have an upper surface lower than an upper surface of the other lower electrode. In some embodiments, the lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have a vertical dimension smaller than a vertical dimension of the other lower electrode. In some embodiments, the upper surface of the lower electrode 151 of the center region R2C can be closer to the semiconductor substrate 100 than the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E.

[0123] In some embodiments, the lower electrodes 151e1m and 151e2m of the edge region R2E of the second region R2 can include an upper portion having a height thereof slightly smaller than a height of an upper portion of the lower electrode 151 in the center region R2C of the second region R2. In other words, a level of the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E can be lower than a level of the upper surface of the lower electrode 151 of the center region R2C. The lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have an upper surface lower than an upper surface of the other lower electrode. In some embodiments, the lower electrode closer to the first region R1 among the lower electrodes 151e1m and 151e2m of the edge region R2E can have a vertical dimension smaller than a vertical dimension of the other lower electrode. In some embodiments, the upper surface of the lower electrode 151 of the center region R2C can be closer to the semiconductor substrate 100 than the upper surface of the lower electrodes 151e1m and 151e2m of the edge region R2E.

[0124] Referring to Figure 10I A portion of the lower electrode 151 can be removed to reduce a horizontal dimension of an upper portion of the lower electrode 151. The horizontal dimension of the element A can refer to a width of the element A in a horizontal direction.

[0125] A portion of the lower electrode 151 can be removed by isotropic dry or wet etching. For example, when a portion of the lower electrode 151 is removed by isotropic wet etching, an etchant including phosphoric acid, nitric acid, acetic acid, or a combination thereof can be used. In this case, the exposed portion of the lower electrode 151 can be isotropically etched away.

[0126] In some embodiments, portions of the lower electrodes 151 can be removed so that the horizontal dimension of each lower electrode 151 after etching can be about 60% to about 90% of the horizontal dimension of each lower electrode 151 before etching.

[0127] In some embodiments, the upper portions 151u of the lower electrodes 151 can each extend in a direction perpendicular to the upper surface of the semiconductor substrate 100, as shown in FIG. 1B. Figure 10I In some embodiments, the upper portions 151u of the lower electrodes 151 can have a slightly convexly curved lateral surface, as shown in FIG. 1C. Figure 6B In some embodiments, the upper portions 151u of the lower electrodes 151 can have a slightly convexly curved lateral surface, as shown in FIG. 1C. Figure 6C In some embodiments, the upper portions 151u of the lower electrodes 151 can have a slightly convexly curved lateral surface, as shown in FIG. 1C.

[0128] In some embodiments, the lower electrodes 151e1 and 151e2 of the edge region R2E of the second region R2 can have upper portions whose height is slightly smaller than the height of the upper portions of the lower electrodes 151 of the center region R2C of the second region R2. In other words, the level of the upper surfaces of the lower electrodes 151e1 and 151e2 of the edge region R2E can be lower than the level of the upper surfaces of the lower electrodes 151 of the center region R2C. The lower electrode among the lower electrodes 151e1 and 151e2 of the edge region R2E that is closer to the first region R1 can have an upper surface that is lower than the upper surface of the other lower electrode. In some embodiments, the lower electrode among the lower electrodes 151e1 and 151e2 of the edge region R2E that is closer to the first region R1 can have a vertical dimension that is smaller than the vertical dimension of the other lower electrode.

[0129] In some embodiments, the lower electrodes 151e1 and 151e2 of the edge region R2E of the second region R2 can have upper portions whose height is slightly larger than the height of the upper portions of the lower electrodes 151 of the center region R2C of the second region R2. In other words, the level of the upper surfaces of the lower electrodes 151e1 and 151e2 of the edge region R2E can be higher than the level of the upper surfaces of the lower electrodes 151 of the center region R2C. The lower electrode among the lower electrodes 151e1 and 151e2 of the edge region R2E that is closer to the first region R1 can have an upper surface that is higher than the upper surface of the other lower electrode. In some embodiments, the lower electrode among the lower electrodes 151e1 and 151e2 of the edge region R2E that is closer to the first region R1 can have a vertical dimension that is larger than the vertical dimension of the other lower electrode.

[0130] Referring to FIG. 1A, Figure 10J A third mold layer 140m3 can be formed on the second mold layer 140m2. The third mold layer 140m3 can cover the upper portions of the lower electrodes 151, 151e1, and 151e2.

[0131] The third mold layer 140m3 can include, for example, silicon oxide, and can be formed, for example, by CVD. The third mold layer 140m3 can be formed by low pressure (LP) CVD or plasma enhanced CVD that exhibits good step coverage. For example, the third mold layer 140m3 can include an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or a combination thereof.

[0132] Referring to Figure 10K The third mold layer 140m3 can be partially removed to expose upper ends of the lower electrodes 151, 151e1, and 151e2. The third mold layer 140m3 can be partially removed by EB.

[0133] Referring to Figure 10L A second support material layer 157bm can be formed on the third mold layer 140m3. The second support material layer 157bm can cover the exposed upper ends of the lower electrodes 151, 151e1, and 151e2.

[0134] The second support material layer 157bm can include, for example, at least one of SiN, SiCN, SiGe, TaO, and TiO2, and can be formed by, for example, CVD or PVD.

[0135] Referring to Figure 10M The second support material layer 157bm can be partially removed so that upper surfaces or upper ends of the lower electrodes 151, 151e1, and 151e2 are exposed, thereby forming a second support layer 157b. In the case where the upper surfaces of the lower electrodes 151e1 and 151e2 in the edge region R2E are lower than the upper surface of the lower electrode 151 in the center region R2C, as described above, the upper surfaces of the lower electrodes 151e1 and 151e2 in the edge region R2E can not be exposed.

[0136] The operation of partially removing the second support material layer 157bm can be omitted, and thus a semiconductor device including a second support layer 157c in contact with the upper surface and lateral surfaces of the lower electrode 151 as shown in FIG. 1B can be obtained. Figure 8

[0137] During the partial removal of the second support material layer 157bm, when the second support material layer 157bm is sufficiently removed so that the upper ends of the lower electrode 151 are exposed to protrude, a structure as shown in FIG. 1C can be obtained. Figure 9

[0138] Referring to Figure 10N ​​The second support layer 157b, the third mold layer 140m3, the second mold layer 140m2, the first support layer 157a, and the first mold layer 140m1 in the first region R1 can be removed. Thereafter, the third mold layer 140m3, the second mold layer 140m2, and the first mold layer 140m1 in the second region R2 can be removed to expose the lower electrodes 151, 151e1, and 151e2. The third mold layer 140m3, the second mold layer 140m2, and the first mold layer 140m1 can be removed using, for example, a lift-off process using an etchant such as hydrofluoric acid. The lower electrodes 151, 151e1, and 151e2 can be supported by the first support layer 157a and the second support layer 157b even after the third mold layer 140m3, the second mold layer 140m2, and the first mold layer 140m1 are removed.

[0139] Referring to Figure 10O A dielectric layer 153 can be formed conformally on exposed surfaces of the lower electrodes 151, 151e1, and 151e2. At this time, the dielectric layer 153 can also be formed on exposed surfaces of the first support layer 157a and the second support layer 157b. The dielectric layer 153 can not be formed on portions of the surfaces of the lower electrodes 151, 151e1, and 151e2 that are in contact with the first support layer 157a and the second support layer 157b.

[0140] The dielectric layer 153 can include, for example, a nitride, an oxide, a metal oxide, or a combination thereof. For example, the dielectric layer 153 can have a single layer or a multi-layer structure including silicon nitride, silicon oxide, a metal oxide such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, or TiO2, a dielectric material having a perovskite structure such as STO (SrTiO3), BST ((Ba, Sr)TiO3), BaTiO3, PZT, or PLZT, or a combination thereof. A detailed example of the multi-layer structure can include a structure of a zirconium oxide film / aluminum oxide film / zirconium oxide film (ZAZ) or a zirconium oxide film / aluminum oxide film / tantalum oxide film (ZAT).

[0141] In some embodiments, the dielectric layer 153 can have a thickness of about 5 nm to about 15 nm, but the inventive concept is not limited thereto. The dielectric layer 153 can be formed by, for example, CVD, PVD, or ALD.

[0142] Referring to Figure 10P An upper electrode 155 can be formed. The upper electrode 155 can be formed on the dielectric layer 153. The upper electrode 155 can include Co, Ti, Ni, W, Mo, Pt, Ru, Ir, TiN, TaN, TiAlN, TaAlN, TiSiN, WN, PtO, RuO x , IrO xSrRuO3, (Ba, Sr) RuO3, CaRuO3, (La, Sr) CoO3, or a combination thereof. However, the material used to form the upper electrode 155 is not limited to the above-described materials.

[0143] The upper electrode 155 can be formed by, for example, CVD, MOCVD, PVD, or ALD.

[0144] The lower electrode 151, the dielectric layer 153, and the upper electrode 155 can constitute the capacitor 150.

[0145] As needed, a fourth interlayer insulating layer 160 identical to the buried insulating layer 160 in the semiconductor device 100 can be further formed on the upper electrode 155. Figure 5 The fourth interlayer insulating layer 160 can include, for example, an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or a combination thereof. In some embodiments, the fourth interlayer insulating layer 160 can include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0146] According to embodiments of the inventive concept, the size of the capacitor is increased by the thickness of the mask pattern 190, and thus the manufactured capacitor can have an increased capacitance. In addition, the spacing between the upper ends of the lower electrodes of the capacitor is increased, thereby reducing or possibly preventing the occurrence of device defects.

[0147] Figures 11A-11I is a side sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 11A The operations illustrated in Figure 10H are subsequent operations, and can be performed before the operations illustrated in Figure 11A are performed. Figures 10A-10H The operations illustrated in

[0148] Referring to Figure 11A , the second molding layer 140m2 can be removed to expose the upper surface of the first support layer 157a. For example, the second molding layer 140m2 can be removed by wet etching. In detail, the second molding layer 140m2 can be removed by an LAL solution, which is an etchant in which ammonium fluoride and hydrofluoric acid are mixed. In some embodiments, the second molding layer 140m2 can be removed by isotropic dry etching.

[0149] As described above with reference to Figure 10H , the lower electrodes 151e1m and 151e2m of the edge region R2E of the second region R2 can have upper surfaces located at a level different from that of the upper surface of the lower electrode 151 of the center region R2C.

[0150] Referring to Figure 11B A portion of the lower electrode 151, 151e1, and 151e2 can be removed to reduce the horizontal size of the upper portion of the lower electrode 151, 151e1, and 151e2. This has been described above with reference to Figure 10I A description thereof will be omitted, and thus a redundant description thereof will be omitted.

[0151] However, as shown in Figure 11B the shoulder portion of the lower electrode 151, 151e1, and 151e2 having a reduced horizontal size can be substantially the same as the level of the upper surface of the first support layer 157a.

[0152] Referring to Figure 11C A third molding layer 140m3 can be formed on the first support layer 157a. The third molding layer 140m3 can cover the upper portion of the lower electrode 151, 151e1, and 151e2. This has been described above with reference to Figure 10J A description of the third molding layer 140m3 will be omitted, and thus a detailed description thereof will be omitted.

[0153] Referring to Figure 11D The third molding layer 140m3 can be partially removed to expose the upper end of the lower electrode 151, 151e1, and 151e2. The third molding layer 140m3 can be partially removed by EB.

[0154] Referring to Figure 11E A second support material layer 157bm can be formed on the third molding layer 140m3. The second support material layer 157bm can cover the exposed upper end of the lower electrode 151, 151e1, and 151e2.

[0155] The second support material layer 157bm can include, for example, at least one of SiN, SiCN, SiGe, TaO, and TiO2, and can be formed by, for example, CVD or PVD.

[0156] Referring to Figure 11F The second support material layer 157bm can be partially removed so that the upper surface or the upper end of the lower electrode 151, 151e1, and 151e2 is exposed, thereby forming a second support layer 157b. This has been described above with reference to Figure 10M A description thereof will be omitted, and thus a detailed description thereof will be omitted.

[0157] Referring to Figure 11G The second support layer 157b, the third molding layer 140m3, the first support layer 157a, and the first molding layer 140m1 in the first region R1 can be removed. Thereafter, the third molding layer 140m3 and the first molding layer 140m1 in the second region R2 can be removed to expose the lower electrode 151, 151e1, and 151e2. This has been described above with reference toFigure 10N This is described above, so a redundant description thereof will be omitted.

[0158] Referring to Figure 11H The dielectric layer 153 can be formed conformally on the exposed surfaces of the lower electrodes 151, 151el and 151e2. At this time, the dielectric layer 153 can also be formed on the exposed surfaces of the first and second support layers 157a and 157b. The dielectric layer 153 can not be formed on the portions of the surfaces of the lower electrodes 151, 151el and 151e2 that are in contact with the first and second support layers 157a and 157b. This has been described above with reference to Figure 10O This is described above, so a redundant description thereof will be omitted.

[0159] Referring to Figure 11I The upper electrode 155 can be formed on the dielectric layer 153. This has been described above with reference to Figure 10P This is described above, so a redundant description thereof will be omitted.

[0160] A fourth interlayer insulating layer 160 can also be formed on the upper electrode 155, as needed.

[0161] While some example embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.

[0162] Accordingly, the subject matter disclosed above is to be considered illustrative, and not restrictive, and the claims are intended to cover all such modifications, enhancements, and other embodiments which fall within the spirit and scope of the inventive concept. Thus, the scope will be determined by the following claims and their legal equivalents, and the foregoing description is intended to be illustrative only and is not intended to limit the scope of the claims.

Claims

1. A method for forming a capacitor, the method comprising: A first molding layer, a first support material layer, and a second molding layer are sequentially formed on a substrate; A mask pattern is formed on the second molding layer; A recess is formed in the second molding layer, the first support material layer, and the first molding layer using a mask pattern as a mask; A lower electrode is formed in the recess; The mask pattern is removed using a dry cleaning process to expose the upper part of the lower electrode; Reduce the width of the upper part of the lower electrode; Remove the first molding layer; A dielectric layer is formed on the surface of the lower electrode; as well as An upper electrode is formed on the dielectric layer.

2. The capacitor forming method according to claim 1, further comprising: A second support material layer is formed before the first molding layer is removed.

3. The capacitor forming method according to claim 2, further comprising: Before reducing the width of the upper part of the lower electrode and after removing the mask pattern, a portion of the second molding layer is removed.

4. The capacitor forming method according to claim 3, further comprising: After reducing the width of the upper part of the lower electrode and before forming the second support material layer, a third molding layer is formed on the first support material layer.

5. The capacitor forming method according to claim 4, wherein, The second support material layer is formed on the third molding layer.

6. The capacitor forming method according to claim 5, further comprising: Before forming the second support material layer, a portion of the third molding layer is removed to expose the upper part of the lower electrode.

7. The capacitor forming method according to claim 6, wherein, The second support material layer is formed to cover part of the upper surface of the lower electrode and the upper side surface of the lower electrode.

8. The capacitor forming method according to claim 6, wherein, The second support material layer is formed to expose the upper surface of the lower electrode and cover a portion of the upper side surface of the lower electrode.

9. The capacitor forming method according to claim 1, wherein, Dry cleaning is a plasma cleaning process that does not apply an electrical bias voltage.

10. The capacitor forming method according to claim 9, wherein, The mask pattern includes silicon, and a plasma cleaning process is performed using a plasma gas containing fluorine radicals.

11. The capacitor forming method according to claim 1, wherein, In the dry cleaning process, the etch selectivity of the mask pattern relative to the second molding layer is at least 500:

1.

12. The capacitor forming method according to claim 1, wherein, After reducing the width of the upper part of the lower electrode, the upper end of the lower electrode has a width in the range of 60% to 90% of the width of the lower part of the lower electrode.

13. A method for manufacturing a semiconductor device, the method comprising: A first molding layer, a first support material layer, and a second molding layer are sequentially formed on a substrate; A mask pattern is formed on the second molding layer; By using a mask pattern as a mask, the first molding layer, the first support material layer, and the second molding layer are patterned to form recesses in the first molding layer, the first support material layer, and the second molding layer. A lower electrode is formed in the recess; The mask pattern is removed using a dry cleaning process to expose the upper part of the lower electrode; Reduce the width of the upper part of the lower electrode; Remove the first molding layer; A dielectric layer is formed on the surface of the lower electrode; as well as An upper electrode is formed on the dielectric layer.

14. The method of manufacturing a semiconductor device according to claim 13, wherein, The lower electrode has a cylindrical shape.

15. The method of manufacturing a semiconductor device according to claim 13, the method further comprising: After removing the mask pattern and before reducing the width of the upper part of the lower electrode, a portion of the second molding layer is removed.

16. The method of manufacturing a semiconductor device according to claim 15, wherein, The step of reducing the width of the upper part of the lower electrode includes: reducing the width of the portion of the lower electrode disposed above the first support material layer.

17. A semiconductor device, the semiconductor device comprising: A transistor is located on a substrate and includes a gate structure and an impurity region. The first interlayer insulating layer is located on the transistor and includes a contact plug electrically connected to the impurity region; as well as A capacitor, located on a first interlayer insulating layer, includes a lower electrode electrically connected to a contact plug, a dielectric layer covering the surface of the lower electrode, and an upper electrode located on the dielectric layer. The lower electrode includes: a main body extending vertically along the upper surface of the substrate and having a first horizontal width; and an upper part located on the main body and having a second horizontal width narrower than the first horizontal width. The semiconductor device further includes a support layer, and the upper part of the lower electrode is supported by the support layer. The support layer covers a portion of the upper surface of the lower electrode and the transverse surface of the upper part of the lower electrode, or the support layer is arranged such that the upper end of the lower electrode penetrates the support layer and protrudes from the upper surface of the support layer.

18. The semiconductor device of claim 17, further comprising a first support layer supporting the side surface of the main body portion of the lower electrode.

19. The semiconductor device according to claim 18, wherein, The upper surface of the first support layer is coplanar with the boundary between the upper part of the lower electrode and the main body.

20. A semiconductor memory device, the semiconductor memory device comprising: Multiple semiconductor memory devices are arranged on a cell region of a substrate, wherein the substrate also includes a peripheral region; and Peripheral circuits are located in the peripheral area. Each of the plurality of semiconductor memory devices includes the semiconductor device according to claim 17. The unit region includes a central region and an edge region located between the central region and the outer region, and The lower electrodes located in the central region of the unit area have substantially equal vertical dimensions.

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