Chip package and method of manufacturing the same

Abstract

A chip package and a manufacturing method thereof, the chip package comprising a first chip, a second chip, a packaging material and a redistribution layer. The first chip has a first conductive pad. The second chip is arranged on the first chip and has a second conductive pad. The packaging material covers the first and second chips and has an upper portion, a lower portion and an inclined portion adjacent to the upper portion and the lower portion. The upper portion is located on the second chip, and the lower portion is located on the first chip. The redistribution layer is arranged along the upper portion, the inclined portion and the lower portion, and electrically connects the first conductive pad and the second conductive pad. Since the first and second chips of the chip package are stacked in the vertical direction, not only the area of ​​the chip package can be reduced, but also the chip package can have diversified functions. In addition, since the packaging material has an inclined portion and a lower portion and an upper portion respectively located on the first and second chips, the aspect ratio of the through hole of the packaging material can be effectively reduced, so that the redistribution layer thereon is not easy to be disconnected, thereby improving reliability.

Description

Technical Field

[0001] The invention relates to a chip package and a method for manufacturing the chip package. Background Art

[0002] Traditional chip packages place multiple chips next to each other and electrically connect them to the same side of a printed circuit board (PCB) through wire bonding, while the other side of the PCB is connected to external components through conductive structures (such as solder balls). However, when multiple chips are integrated into the same package, the area of ​​the chip package will increase significantly, which is not conducive to miniaturization design. In addition, the wire bonding packaging method has low reliability and also occupies the volume of the package, such as the height of the top of the wire. Summary of the invention

[0003] A technical aspect of the present invention is a chip package.

[0004] According to one embodiment of the present invention, a chip package includes a first chip, a second chip, a packaging material, and a redistribution layer. The first chip has a first conductive pad. The second chip is disposed on the first chip and has a second conductive pad. The packaging material covers the first chip and the second chip, and has an upper portion, a lower portion, and an inclined portion adjacent to the upper portion and the lower portion. The upper portion is located on the second chip, and the lower portion is located on the first chip. The redistribution layer is disposed along the upper portion, the inclined portion, and the lower portion, and electrically connects the first conductive pad and the second conductive pad.

[0005] In one embodiment of the present invention, the lower portion and the upper portion of the packaging material respectively have a first through hole and a second through hole, and the first conducting pad and the second conducting pad are respectively located in the first through hole and the second through hole.

[0006] In one embodiment of the present invention, an upper surface of the lower portion of the packaging material is lower than an upper surface of the upper portion.

[0007] In one embodiment of the present invention, an obtuse angle is formed between the inclined portion and the lower portion of the packaging material.

[0008] In one embodiment of the present invention, the chip package further includes a bonding adhesive disposed between the first chip and the second chip.

[0009] In one embodiment of the present invention, the chip package further includes a passivation layer covering the redistribution layer and the packaging material.

[0010] In one embodiment of the present invention, the passivation layer and the packaging material are made of different materials.

[0011] In one embodiment of the present invention, the passivation layer includes an opening, and the chip package further includes a conductive structure, and the conductive structure is located on the redistribution layer in the opening.

[0012] Another technical aspect of the present invention is a method for manufacturing a chip package.

[0013] According to one embodiment of the present invention, a method for manufacturing a chip package includes joining a first chip and a second chip, wherein the first chip and the second chip have a first conductive pad and a second conductive pad, respectively; forming a packaging material to cover the first chip and the second chip; removing a portion of the packaging material surrounding the second chip so that the packaging material has an upper portion, a lower portion, and an inclined portion adjacent to the upper portion and the lower portion, wherein the upper portion is located on the second chip and the lower portion is located on the first chip; forming a first through hole and a second through hole in the lower portion and the upper portion of the packaging material, respectively, so that the first conductive pad and the second conductive pad are exposed from the first through hole and the second through hole, respectively; and forming a redistribution layer arranged along the upper portion, the inclined portion, and the lower portion of the packaging material, wherein the redistribution layer extends to the first conductive pad in the first through hole and the second conductive pad in the second through hole.

[0014] In one embodiment of the present invention, removing the portion of the packaging material surrounding the second chip is performed by a tool cutting method.

[0015] In one embodiment of the present invention, the first through hole and the second through hole are formed in the lower part and the upper part of the packaging material respectively by laser drilling.

[0016] In one embodiment of the present invention, the method for manufacturing a chip package further includes forming a passivation layer to cover the redistribution layer and the packaging material.

[0017] In one embodiment of the present invention, the method for manufacturing a chip package further includes forming an opening in the passivation layer to expose the redistribution layer.

[0018] In one embodiment of the present invention, a conductive structure is formed on the redistribution layer in the opening to electrically connect the redistribution layer.

[0019] In the above-mentioned embodiment of the present invention, since the first chip and the second chip of the chip package are stacked in the vertical direction, not only the area of ​​the chip package can be reduced, but also the chip package can have diversified functions. In addition, since the packaging material has an inclined portion and a lower portion and an upper portion respectively located on the first chip and the second chip, the aspect ratio of the through hole of the packaging material can be effectively reduced, so that the redistribution layer thereon is not easy to be disconnected, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A cross-sectional view of a chip package according to an embodiment of the present invention is shown.

[0021] Figures 2 to 6 Draw Figure 1 sectional views of various stages in a method for manufacturing a chip package.

[0022] Figure 7 A cross-sectional view of a second wafer according to an embodiment of the present invention is shown.

[0023] Figure 8 FIG. 4 is a cross-sectional view of a chip package according to another embodiment of the present invention.

[0024] Among them, the simple description of the symbols in the accompanying drawings is as follows:

[0025] 100, 200: chip package; 110: first chip; 112: first conductive pad; 120, 120a: second chip; 122: second conductive pad; 124: body; 126: cover; 128: detector; 130, 132: adhesive; 140: packaging material; 142: upper part; 144: lower part; 146: inclined part; 142T, 144T, 146T: upper surface; 150: first through hole; 160: second through hole; 170: redistribution layer; 180: passivation layer; 182: opening; 190: conductive structure; θ: obtuse angle; 210: first chip; 212: first conductive pad; 220: second chip; 222: second conductive pad; 230: third chip; 232: third conductive pad; 240A, 240B: packaging material; 250A: first through hole; 260A: second through hole; 250B: third through hole; 260B: fourth through hole; 270A, 270B: redistribution layer; 280A, 280B: passivation layer; 282: opening; 290: conductive structure. DETAILED DESCRIPTION

[0026] Several embodiments of the present invention are described below with reference to the drawings. To simplify the drawings, some known conventional structures and elements are depicted in a simple schematic manner.

[0027] Figure 1 A cross-sectional view of a chip package 100 according to an embodiment of the present invention is shown. The chip package 100 comprises a first chip 110, a second chip 120, a packaging material 140 and a redistribution layer 170. The first chip 110 comprises a first conductive pad 112, and the second chip 120 comprises a second conductive pad 122. The packaging material 140 covers the first chip 110 and the second chip 120. The packaging material 140 comprises an upper portion 142, a lower portion 144 and an inclined portion 146 adjacent to the upper portion 142 and the lower portion 144. The upper portion 142 is located on the second chip 120, and the lower portion 144 is located on the first chip 110. In this embodiment, the packaging material 140 may be a molding compound. The redistribution layer 170 is disposed along the upper portion 142, the inclined portion 146 and the lower portion 144, and electrically connects the first conductive pad 112 and the second conductive pad 122.

[0028] In addition, the chip package 100 further has a bonding adhesive 130 disposed between the first chip 110 and the second chip 120 for bonding the first chip 110 and the second chip 120. The chip package 100 of the present invention may be a system in package (SIP) structure. The first chip 110 and the second chip 120 may have different functions, so that the chip package 100 may have diversified functions. For example, the first chip 110 may be an active component, such as an application specific integrated circuit (ASIC). The second chip 120 may be a passive component, such as a micro-electro-mechanical system (MEMS). In some embodiments, the first chip 110 is a computing unit and the second chip 120 is an accelerator. In this embodiment, since the first chip 110 and the second chip 120 of the chip package 100 are stacked in a vertical direction, the area of ​​the chip package 100 may be reduced.

[0029] like Figure 1 As shown, the width of the second chip 120 is smaller than the width of the first chip 110. The first conductive pad 112 does not overlap with the second chip 120, and the first conductive pad 112 does not overlap with the bonding adhesive 130. In other words, a portion of the first chip 110 is not covered by the second chip 120 and the bonding adhesive 130. The first chip 110 is closer to the outside of the chip package 100 than the second chip 120. The lower portion 144 of the packaging material 140 is located on the portion of the first chip 110 that is not covered by the second chip 120, that is, the lower portion 144 of the packaging material 140 covers the first conductive pad 112 of the first chip 110.

[0030] The lower portion 144 of the packaging material 140 has an upper surface 144T, and the upper portion 142 of the packaging material 140 has an upper surface 142T, and the upper surface 144T of the lower portion 144 is lower than the upper surface 142T of the upper portion 142. An obtuse angle θ is formed between the inclined portion 146 of the packaging material 140 and the lower portion 144. The obtuse angle θ is also conducive to the formation of the redistribution layer 170 on the packaging material 140, which can prevent the redistribution layer 170 from being disconnected. In other words, the inclined portion 146 has an upper surface 146T that connects the upper surface 142T of the upper portion 142 and the upper surface 144T of the lower portion 144. Figure 1 As shown in FIG. 1 , the upper surface 142T of the upper portion 142 , the upper surface 146T of the inclined portion 146 , and the upper surface 144T of the lower portion 144 together constitute a stepped surface.

[0031] The lower portion 144 and the upper portion 142 of the packaging material 140 further have a first through hole 150 and a second through hole 160, respectively. The first conductive pad 112 and the second conductive pad 122 are respectively located in the first through hole 150 and the second through hole 160. Since the upper surface 144T of the lower portion 144 of the packaging material 140 is lower than the upper surface 142T of the upper portion 142, the aspect ratio of the first through hole 150 can be effectively reduced. The depth of the first through hole 150 is substantially the same as the thickness of the lower portion 144. In other words, the depth of the first through hole 150 is determined by the thickness of the lower portion 144 of the packaging material 140 and is not limited by the thickness of the second chip 120, so the selection of the second chip 120 is more flexible. In addition, since the second chip 120 is stacked on the first chip 110, the depth of the second through hole 160 is determined by the thickness of the upper portion 142 of the packaging material 140, so the aspect ratio of the second through hole 160 can also be reduced.

[0032] The redistribution layer 170 conforms to the upper portion 142, the inclined portion 146, and the lower portion 144 of the packaging material 140, and extends into the first through hole 150 and the second through hole 160. In this embodiment, since the first through hole 150 and the second through hole 160 have a low depth-to-width ratio, and the redistribution layer 170 is disposed along the stepped surface of the packaging material 140 (i.e., the surface formed by the upper portion 142, the inclined portion 146, and the lower portion 144), it is not easy to break, which can effectively improve reliability. In addition, it can also make it easier to clean the first through hole 150 and the second through hole 160. In this way, the pitch between the first conductive pad 112 and the second conductive pad 122 can also be reduced, thereby improving the competitiveness of the chip package 100.

[0033] The chip package 100 further has a passivation layer 180 and a conductive structure 190. The passivation layer 180 covers the redistribution layer 170 and the packaging material 140, and the passivation layer 180 and the packaging material 140 can be made of different materials. The passivation layer 180 also has an opening 182. The conductive structure 190 is located on the redistribution layer 170 in the opening 182. In some embodiments, the conductive structure 190 can be a ball grid array package (BGA), a conductive bump, or a conductive column.

[0034] In this embodiment, since the chip package 100 electrically connects the first chip 110 and the second chip 120 to the conductive structure 190 through the redistribution layer 170, it is more stable than the traditional wire bonding packaging method and can effectively reduce the volume of the chip package 100. In addition, the distance for the signal to be transmitted from the redistribution layer 170 to the conductive structure 190 is shortened, which can improve the performance of the chip package 100.

[0035] It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, but will be described first. In the following description, a method for manufacturing the chip package 100 will be described.

[0036] Figures 2 to 6 Draw Figure 1 The cross-sectional view of each stage in the manufacturing method of the chip package 100 is shown in FIG. Figure 2 First, the first chip 110 and the second chip 120 are bonded by the bonding adhesive 130. The first conducting pad 112 of the first chip 110 is not covered by the second chip 120 and the bonding adhesive 130 and is exposed.

[0037] See also Figure 3 , a packaging material 140 is formed to cover the first chip 110 and the second chip 120 . Specifically, the packaging material 140 surrounds the second chip 120 and contacts the sidewall of the second chip 120 , and the packaging material 140 covers the first conducting pad 112 and the second conducting pad 122 .

[0038] See also Figure 4 , a portion of the packaging material 140 surrounding the second chip 120 is removed, so that the packaging material 140 has an upper portion 142, a lower portion 144 and an inclined portion 146 adjacent to the upper portion 142 and the lower portion 144. In addition, the upper surface 144T of the lower portion 144 is also made lower than the upper surface 142T of the upper portion 142. Removal of the portion of the packaging material 140 surrounding the second chip 120 is performed by a tool cutting method. For example, the tool may have a specific width, and the opposite sides of the tool have inclined surfaces similar to the upper surface 146T of the inclined portion 146. In this way, the upper surface 146T of the smooth inclined portion 146 and the upper surface 144T of the lower portion 144 can be quickly formed by the tool, and an obtuse angle θ between the inclined portion 146 and the lower portion 144 is formed. In some embodiments, the width of the tool is in the range of about 1um to about 3mm.

[0039] See also Figure 5 A first through hole 150 and a second through hole 160 are formed in the lower portion 144 and the upper portion 142 of the packaging material 140, respectively, so that the first conductive pad 112 and the second conductive pad 122 are exposed from the first through hole 150 and the second through hole 160, respectively. The first through hole 150 and the second through hole 160 are performed by laser drilling. In this way, the first through hole 150 and the second through hole 160 can be accurately exposed to the first conductive pad 112 and the second conductive pad 122, respectively.

[0040] See also Figure 6A redistribution layer 170 is formed along the upper portion 142, the inclined portion 146, and the lower portion 144 of the packaging material 140, wherein the redistribution layer 170 extends to the first conductive pad 112 in the first through hole 150 and the second conductive pad 122 in the second through hole 160. In this embodiment, since the upper surface 146T of the inclined portion 146 is a smooth inclined surface, it is beneficial for the redistribution layer 170 to be attached to the inclined portion 146, thereby preventing the redistribution layer 170 from being disconnected. In addition, since the first through hole 150 and the second through hole 160 have a low depth-to-width ratio, the redistribution layer 170 extending into the first through hole 150 and the second through hole 160 can also be prevented from being disconnected due to gaps.

[0041] Back to Figure 1 After forming the redistribution layer 170, a passivation layer 180 may be formed to cover the redistribution layer 170 and the packaging material 140. Next, an opening 182 is formed in the passivation layer 180 to expose the redistribution layer 170. Thereafter, a conductive structure 190 may be formed on the redistribution layer 170 in the opening 182 to electrically connect the redistribution layer 170.

[0042] In the following description, other types of second chips and chip packages will be described.

[0043] Figure 7 A cross-sectional view of a second chip 120a according to an embodiment of the present invention is shown. The second chip 120a has a body portion 124, a cover portion 126, and a detector 128. The body portion 124 has a second conductive pad 122. The second chip 120a also has a bonding adhesive 132, which is configured to bond the cover portion 126 and the detector 128 to the body portion 124. In some embodiments, the body portion 124 may be a micro-electromechanical system (MEMS). The detector 128 may be, for example, a cantilever valve. In some embodiments, the second conductive pad 122 of the second chip 120a may also be disposed on the cover portion 126.

[0044] Figure 8 A cross-sectional view of a chip package 200 according to another embodiment of the present invention is shown. The chip package 200 comprises a first chip 210, a second chip 220, a packaging material 240A, a redistribution layer 270A, and a passivation layer 280A. The first chip 210 and the second chip 220 respectively comprise a first conducting pad 212 and a second conducting pad 222. The above structure is similar to the structure and manufacturing method of the aforementioned chip package 100, and will not be described in detail herein.

[0045] and Figure 1The difference between the chip package 100 and the chip package 200 is that the chip package 200 further has a third chip 230, a packaging material 240B, a redistribution layer 270B and a passivation layer 280B. The third chip 230 is located on the redistribution layer 270A and the passivation layer 280A, and has a third conductive pad 232. The packaging material 240B covers the third chip 230, the redistribution layer 270A and the passivation layer 280A. The packaging material 240B has a third through hole 250B and a fourth through hole 260B, and the third conductive pad 232 is located in the fourth through hole 260B. The redistribution layer 270B electrically connects the third conductive pad 232 and the second conductive pad 222. Specifically, the second through hole 260A is electrically connected to the third through hole 250B, and the redistribution layer 270B is electrically connected to the second conductive pad 222 through the second through hole 260A and the third through hole 250B. The third through hole 250B and the fourth through hole 260B have structures similar to the first through hole 250A and the second through hole 260A. The packaging material 240B, the redistribution layer 270B and the passivation layer 280B also have structures similar to the packaging material 240A, the redistribution layer 270A and the passivation layer 280A, respectively. In other words, the third chip 230 is stacked on the second chip 220 in the same way as the second chip 220 is stacked on the first chip 210. The chip package 200 also has an opening 282 and a conductive structure 290. The opening 282 is located on the portion where the passivation layer 280B overlaps with the redistribution layer 270B. The conductive structure 290 is located on the redistribution layer 270B in the opening 282.

[0046] In this embodiment, the first chip 210, the second chip 220 and the third chip 230 may have different functions. The chip package 200 can reduce the area of ​​the chip package 200 by stacking the first chip 210, the second chip 220 and the third chip 230 in a vertical direction, and combine multiple different functions into the chip package 200. In addition, the packaging material 240A and the packaging material 240B have the same Figure 1 The stepped surface similar to the packaging material 140 can effectively prevent the redistribution layer 270A and the redistribution layer 270B from being disconnected.

[0047] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of this application.

Claims

1. A chip package, characterized in that: include: A first chip having a first conductive pad; A second chip is disposed on the first chip and has a second conducting pad; A first packaging material covers the first chip and the second chip and has an upper portion, a lower portion, and an inclined portion adjacent to the upper portion and the lower portion, wherein the upper portion is located on the second chip, and the lower portion is located on the first chip, the first packaging material has a first through hole and a second through hole, and the first conducting pad and the second conducting pad are respectively located in the first through hole and the second through hole; A first redistribution layer is disposed along the upper portion, the inclined portion, and the lower portion, and electrically connects the first conducting pad and the second conducting pad; A first passivation layer, covering the first redistribution layer and the first packaging material; A third chip is disposed on the second chip, and the third chip has a third conducting pad; A second packaging material covers the third chip, the first redistribution layer and the first passivation layer, the second packaging material has a third through hole and a fourth through hole, and the third conducting pad is located in the fourth through hole; as well as The second redistribution layer is disposed on the third chip and the second packaging material. The second redistribution layer is located in the third through hole and is electrically connected to the third conducting pad and the second conducting pad.

2. The chip package according to claim 1, wherein: The lower portion and the upper portion of the first packaging material respectively have the first through hole and the second through hole.

3. The chip package according to claim 1, wherein: An obtuse angle is formed between the inclined portion and the lower portion of the first packaging material.

4. The chip package according to claim 1, wherein: The upper surface of the lower portion of the first packaging material is lower than the upper surface of the upper portion.

5. The chip package according to claim 1, wherein: The invention also comprises a bonding adhesive which is arranged between the first chip and the second chip.

6. The chip package according to claim 1, wherein: The invention also comprises a second passivation layer covering the second redistribution layer and the second packaging material.

7. The chip package according to claim 6, wherein: The second passivation layer and the first packaging material are made of different materials.

8. The chip package according to claim 6, wherein: The second passivation layer includes an opening, and the chip package further includes a conductive structure, which is located on the second redistribution layer in the opening.

9. A method for manufacturing a chip package, characterized in that: include: Bonding a first chip and a second chip, wherein the first chip and the second chip have a first conducting pad and a second conducting pad respectively; forming a first packaging material to cover the first chip and the second chip; removing a portion of the first packaging material surrounding the second wafer so that the first packaging material has an upper portion, a lower portion, and an inclined portion adjacent to the upper portion and the lower portion, wherein the upper portion is located on the second wafer and the lower portion is located on the first wafer; Forming a first through hole and a second through hole in the lower portion and the upper portion of the first packaging material respectively, so that the first conducting pad and the second conducting pad are exposed from the first through hole and the second through hole respectively; forming a first redistribution layer disposed along the upper portion, the inclined portion, and the lower portion of the first packaging material, wherein the first redistribution layer extends to the first conductive pad in the first through hole and the second conductive pad in the second through hole; forming a first passivation layer to cover the first redistribution layer and the first packaging material; Bonding a third chip to the second chip, wherein the third chip has a third conducting pad; forming a second packaging material to cover the third chip, the first redistribution layer and the first passivation layer; Forming a third through hole and a fourth through hole in the second packaging material, so that the third conducting pad is exposed from the fourth through hole, and the first redistribution layer is exposed from the third through hole; as well as A second redistribution layer is formed along the second packaging material, wherein the second redistribution layer extends to the third conducting pad in the fourth through hole and the first redistribution layer in the third through hole.

10. The manufacturing method according to claim 9, characterized in that: The removal of the portion of the first packaging material surrounding the second chip is performed by a tool cutting method.

11. The manufacturing method according to claim 9, characterized in that: The first through hole and the second through hole are respectively formed on the lower part and the upper part of the first packaging material by laser drilling.

12. The manufacturing method according to claim 9, characterized in that: Also includes: A second passivation layer is formed to cover the second redistribution layer and the second packaging material.

13. The manufacturing method according to claim 12, characterized in that: Also includes: An opening is formed in the second passivation layer to expose the second redistribution layer.

14. The manufacturing method according to claim 13, characterized in that: Also includes: A conductive structure is formed on the second redistribution layer in the opening to electrically connect the second redistribution layer.

Images