Semiconductor discharge protection device with diode and silicon controlled rectifier arrangement

Abstract

The invention is entitled "Semiconductor Discharge Protection Device with Diode and Silicon Controlled Rectifier Arrangement." Various aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device having one or more fingers divided into two sections having alternating p-diffusion and n-diffusion regions, where each region is associated with at least one of a portion of a diode and / or a silicon controlled rectifier (SCR).

Description

Technical Field

[0001] The implementation plan relates to the field of semiconductor devices, and more specifically to electrostatic discharge protection devices. Background Technology

[0002] Power surges, such as electrical overvoltage or electrostatic discharge (ESD) transient pulses, are a common cause of damage to electronic equipment. To prevent such transient surges, electronic devices are typically protected by surge protection devices or ESD protection devices. These devices provide protection against electrical overvoltage or electrostatic discharge and are commonly used in portable / consumer electronic devices, such as personal computers, audio and video equipment, or mobile phones. Such devices are also used in data transmission lines or data interfaces used in such portable / consumer electronic devices. According to the International Electrotechnical Commission standard IEC 61000-4-2 (also known as the "gun test"), such devices should be protected against system-level ESD stresses up to 8 kV.

[0003] However, original equipment manufacturers (OEMs) of portable / consumer electronic devices have begun to require protection against discharges up to 15kV. To achieve this enhanced level of protection, ESD devices can simply become larger. However, larger devices result in increased device capacitance. Portable / consumer electronic devices must be adequately protected against ESD events according to IEC standards without impairing normal operation. In applications with high-speed interfaces such as Universal Serial Bus (USB) or High Definition Multimedia Interface (HDMI), ESD devices must have low device capacitance to maintain signal integrity along data transmission lines or at data interfaces.

[0004] In view of the above, embodiments of the present invention are provided. Summary of the Invention

[0005] At least one embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least two fingers, wherein each finger includes at least two segments along a surface of a semiconductor surface, wherein each of the at least two segments and each of the at least two fingers is in an alternating diode-rectifier arrangement relative to each other.

[0006] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least two fingers, wherein each finger includes at least two segments along a surface of a semiconductor surface, wherein each of the at least two segments and each of the at least two fingers is in an alternating diode-rectifier arrangement relative to each other, wherein each of the at least two segments is separated by a portion of a diffusion region.

[0007] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least two fingers, wherein each finger includes at least two segments along a surface of a semiconductor surface, wherein each of the at least two segments and each of the at least two fingers are in an alternating diode-rectifier arrangement relative to each other, wherein each of the at least two segments is separated by a portion of a diffusion region, and wherein at least one of the plurality of diodes is a pn diode.

[0008] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least two fingers, wherein each finger includes at least two segments along a surface of a semiconductor surface, wherein each of the at least two segments and each of the at least two fingers is in an alternating diode-rectifier arrangement relative to each other, wherein at least one of the two fingers includes a p-type well having a first p-type diffusion region and a first n-type diffusion region, and wherein the first p-type region is staggered and divides at least one of the segments into two portions associated with at least one of the two fingers.

[0009] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least two fingers, wherein each finger includes at least two segments along a surface of a semiconductor surface, wherein each of the at least two segments and each of the at least two fingers is in an alternating diode-rectifier arrangement relative to each other, wherein at least one of the two fingers includes a p-type well having a first p-type diffusion region and a first n-type diffusion region, and wherein the first p-type region is staggered and divides at least one of the two segments into two portions associated with at least one of the two fingers, wherein the other of the at least two fingers includes an n-type well having a second n-type diffusion region and a second p-type diffusion region, and wherein the second n-type region is staggered and divides at least one of the two segments into two portions associated with at least one of the two fingers.

[0010] Another embodiment includes a semiconductor electrostatic discharge protection device. The semiconductor electrostatic discharge protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least three fingers, wherein each finger includes at least three segments along a surface of a semiconductor surface, wherein each of the at least three segments and each of the at least three fingers is in an alternating diode-rectifier arrangement relative to each other.

[0011] Another embodiment includes a semiconductor electrostatic discharge protection device. The semiconductor electrostatic discharge protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least three fingers, wherein each finger includes at least three segments along a surface of a semiconductor surface, wherein each of the at least three segments and each of the at least three fingers is in an alternating diode-rectifier arrangement relative to each other, and wherein at least one of the plurality of diodes is a pn diode.

[0012] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The semiconductor ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least three fingers, wherein each finger includes at least three segments along a surface of a semiconductor surface, wherein each of the at least three segments and each of the at least three fingers is in an alternating diode-rectifier arrangement relative to each other, and wherein at least one of the three fingers includes a p-type well having a first p-type diffusion region, a second p-type diffusion region, a third p-type diffusion region, a first n-type diffusion region, a second n-type diffusion region, and a third n-type diffusion region.

[0013] Another embodiment includes a semiconductor electrostatic discharge (ESD) protection device. The semiconductor ESD protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least three fingers, wherein each finger includes at least three segments along a surface of a semiconductor surface, wherein each of the at least three segments and each of the at least three fingers is in an alternating diode-rectifier arrangement relative to each other, wherein at least one of the three fingers includes a p-type well having a first p-type diffusion region, a second p-type diffusion region, a third p-type diffusion region, a first n-type diffusion region, a second n-type diffusion region, and a third n-type diffusion region, wherein another finger of the at least one of the three fingers includes an n-type well having a fourth p-type diffusion region, a fifth p-type diffusion region, a sixth p-type diffusion region, a fourth n-type diffusion region, a fourth n-type diffusion region, and a sixth n-type diffusion region.

[0014] Another implementation includes a semiconductor electrostatic discharge protection device. A semiconductor electrostatic discharge protection device may include: a plurality of semiconductor controlled rectifiers and a plurality of diodes, wherein the plurality of semiconductor rectifiers and the plurality of diodes are integrally arranged in at least three fingers, wherein each finger includes at least three segments along the surface of a semiconductor surface, wherein each of the at least three segments and each of the at least three fingers is in an alternating diode-rectifier arrangement relative to each other, wherein at least one of the three fingers includes a p-type well having a first p-type diffusion region, a second p-type diffusion region, a third p-type diffusion region, a first n-type diffusion region, a second n-type diffusion region, and a third n-type diffusion region, wherein another finger of the at least one of the three fingers includes an n-type well having a fourth p-type diffusion region, a fifth p-type diffusion region, a sixth p-type diffusion region, a fourth n-type diffusion region, a fourth n-type diffusion region, and a sixth n-type diffusion region, wherein each p-type diffusion region is alternating with each n-type diffusion region of the n-type diffusion region of the at least three fingers.

[0015] Another embodiment of this disclosure includes a method for fabricating or arranging a semiconductor device. The method includes: providing a semiconductor substrate; and laterally arranging a plurality of semiconductor fingers along the semiconductor substrate such that at least four of the plurality of semiconductor fingers form a silicon controlled rectifier, and at least two of the at least four of the plurality of semiconductor fingers form a diode, wherein each of the at least four of the plurality of semiconductor fingers has an alternating n-diffusion and p-diffusion arrangement. Attached Figure Description

[0016] Figure 1 A top view of a semiconductor device according to at least one embodiment of the present disclosure is shown; and

[0017] Figure 2 A top view of a semiconductor device according to at least one embodiment of the present disclosure is shown.

[0018] Figure 3 A top view of a semiconductor device according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0019] Embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are illustrated. These embodiments should not be construed as limited to those described herein. Rather, they are provided so that this disclosure will be thorough and complete, and will fully convey their scope to those skilled in the art. Throughout the drawings, similar figures refer to similar elements.

[0020] In the following detailed description and / or claims, the terms “on,” “overlapping,” “set on,” and “above” are used. “On,” “overlapping,” “set on,” and “above” can be used to indicate that two or more elements are in direct physical contact with each other. Additionally, the terms “on,” “overlapping,” “set on,” and “above” can indicate that two or more elements are not in direct contact with each other. For example, “above” can mean that one element is on top of another element without contacting each other, and there may be another element or elements between these two elements. Furthermore, the term “and / or” can mean “and,” it can mean “or,” it can mean “exclusive or,” it can mean “one,” it can mean “some, but not all,” it can mean “neither,” and / or it can mean “both,” although the scope of the subject matter protected by the claims is not limited in this respect.

[0021] One or more embodiments of this disclosure relate to at least one silicon controlled rectifier (SCR) having at least one integrated diode associated therewith. In various embodiments, at least one SCR and diode are arranged laterally along a semiconductor substrate. In various embodiments, the diode may be a pn diode. In various embodiments, the SCR and diode arrangement may be used for ESD protection and may be arranged laterally outward in a finger configuration to optimize current distribution; and in various embodiments, alternating and / or staggered SCR and diode segments may be associated with each finger. In various embodiments, this allows for AC current paths for the SCR and diode in the event of an ESD or surge, and in various embodiments, this can increase device density by providing more than one diode and / or SCR relative to two or more fingers. In various embodiments, by appropriately setting the length of each device segment, the trigger current of the SCR can also be increased by providing alternative current paths relative to the p-well region, n-well region, p-diffusion region, and / or n-diffusion region associated with the SCR, which may be advantageous for certain applications requiring high trigger current.

[0022] Figure 1 A top view of an ESD protection device 100 according to at least one embodiment of the present disclosure is shown. In various embodiments, the ESD protection device 100 may include a signal terminal 104 and a ground terminal 111. In various embodiments, the ESD protection device may include one or more fingers 105, 106. The one or more fingers 105 may include a p-well region (pw) 102 having one or more p-diffusion regions 135 and one or more n-diffusion regions 140. In various embodiments, the ESD device 100 may also include at least one p-diffusion segment 135' dividing a single finger 105 into two or more segments, wherein in various embodiments, the division is such that alternating and / or staggered arrangements exist between the n-diffusion regions 140 and p-diffusion regions 135 of the one or more fingers 105. In various embodiments, the ESD device 100 includes one or more fingers 106, which may include an n-well region (nw) 103 having one or more n-diffusion regions 140 and one or more p-diffusion regions 135. One or more fingers 106 may include n-diffusion segments 140' that divide each individual finger 106 into two or more segments, wherein the division causes the p-diffusion regions 135 and n-diffusion regions 140 of one or more fingers 106 to be arranged in an alternating and / or interleaved manner.

[0023] In various embodiments, one or more fingers 105 and one or more fingers 106 are laterally arranged on any suitable semiconductor substrate 101, and in various embodiments, segments divided into individual fingers result in alternating and / or staggered arrangements of the p-diffusion region 135 of one finger 105 relative to the n-diffusion region 140 of another finger 106. The substrate may be n-doped and / or p-doped at various portions along the configuration of the substrate 101 as needed and according to the specific fingers 105, 106, wherein the substrate 101 may be doped with different types of dopants and / or doped with different concentrations of dopants at various portions along the substrate.

[0024] In various embodiments, ESD device 100 can be considered as an arrangement of one or more PNP transistors connected to one or more NPN transistors, forming one or more SCRs and one or more PN diodes. In various embodiments, two or more fingers 105, 106 are divided such that at least PNP and NPN transistors are formed by an arrangement on substrate 101. In various embodiments, the collector of at least one PNP transistor can be connected to the base of at least one NPN transistor, and the base of at least one PNP transistor can be connected to the collector of at least one NPN transistor. Thus, and according to various embodiments, ESD protection device 100 can be considered as comprising one or more SCRs and one or more diodes. In various embodiments, one or more emitters of at least one NPN transistor can form a ground terminal 111 of ESD protection device 100, and one or more emitters of at least one PNP transistor can form a signal terminal 104 of ESD protection device 100. In various embodiments, one or more PN diodes (also referred to as reverse diodes in various embodiments) can be connected across signal terminal 104 and / or ground terminal 111.

[0025] According to Figure 1In various embodiments, the ESD device 100 can be considered as comprising four fingers 105, 106, 105, and 106 of four laterally arranged alternating n-type and p-type semiconductor material layers to form a pnpn structure. In various embodiments, each finger 105, 106, 105, and 106 provides at least two SCR segments, resulting in at least two SCRs laterally formed on the device 100. In various embodiments, the emitter of at least one pnp transistor may be formed by a p+ type diffusion region 135 of the finger, the base of at least one of the pnp transistors may be formed by an nw 103 of at least one finger, and the collector of at least one pnp transistor may be formed by a pw 102 of at least one finger and a p+ type diffusion region 135. In various embodiments, the base of at least one pnp transistor is contacted via an n+ diffusion region 140 of at least one finger. In various embodiments, the emitter of at least one npn transistor may be formed from an n+ diffusion region 140 of at least one finger, and the base of at least one npn transistor may be partially formed from a pw region 102 of at least one finger. The collector of the npn transistor may be formed from an nw 103 of at least one finger and an n+ diffusion region 140.

[0026] In various embodiments, the pn diode of the ESD device 100 can be formed by a p+ type diffusion region 135 formed in at least one finger pw 102, which can form the anode of the pn diode, and by an n+ type diffusion region 140 formed in an n-type well region (nw) 103 of at least one finger, which can form the cathode of the pn diode. Thus, and according to various embodiments, the pn diode can be integrally formed with the SCR 101 in the substrate 110. In various embodiments, the p+ diffusion region 135 of the at least one finger can serve as both the base contact of an npn transistor and the anode of the pn diode. In various embodiments, the p+ diffusion region 135 formed in at least one region of pw 102 can be connected to the n+ diffusion region 140 to form the ground terminal 111 of the ESD device 100. In various embodiments, the n+ diffusion region 140 of the at least one finger can serve as both the base contact of a pnp transistor and the cathode of the pn diode. In various embodiments, an n+ diffusion region 140 formed in an n-type well region 103 of at least one finger can be connected to a p+ diffusion region 135 of at least one finger to form a signal terminal 104 of the ESD device 100.

[0027] In various implementations, the SCR of ESD100 can be activated by a positive pressure voltage caused by an ESD event at signal terminal 104 relative to ground terminal 111. Current can flow from the p+ diffusion region 135 of at least one finger 106 to the n+ diffusion region 140 of at least one finger 105. In this way, excess current on terminal 104 can be drained to ground, and the voltage on signal terminal 104 can be limited in this manner, thereby protecting any external device connected to terminal 104 from overvoltage and overcurrent caused by a positive ESD event. In this case, the voltage is limited to the clamping voltage of the ESD protection device 100. The clamping voltage can be considered as the sum of the SCR's snap-back voltage and the voltage drop caused by the current flowing through the device and the device's on-resistance; the snap-back voltage is the opposite of the breakdown voltage. The clamping voltage can be selected such that it is below the critical voltage that would damage the system to be protected.

[0028] In various embodiments, for negative pressure voltages, which can be caused by an ESD event at signal terminal 104 relative to ground terminal 111, ESD device 100 operates as a pn diode between a p+ diffusion region 135 of at least one finger formed in pw 102 and an n+ diffusion region 140 formed in the nw region of at least one finger. Current can flow from the p+ diffusion region 135 of at least one finger to the n+ diffusion region 140 of at least one finger. In this way, and according to various embodiments, excess current from an ESD event at terminal 104 can be discharged to ground terminal 111 and the voltage at terminal 104 can be limited, thereby protecting any external device connected to terminal 104 from overvoltage and overcurrent caused by a negative ESD event.

[0029] Figure 2An embodiment of an ESD device 200 according to at least one embodiment of the present disclosure is shown. The operation of the ESD device 200 is substantially similar to that of device 100, except that each of its fingers 105, 106 is divided into at least three segments, and in various embodiments, segments 135' and 140' are omitted to achieve this division. In various embodiments, the ESD protection device 200 may include a signal terminal 104 and a ground terminal 111. In various embodiments, the ESD protection device may include one or more fingers 205, 206. The one or more fingers 205 may include a p-well region (pw) 102 having one or more p-diffusion regions 135 and one or more n-diffusion regions 140. In various embodiments, the division of the one or more fingers 205 is such that alternating p-diffusion regions 135 and n-diffusion regions 140 divide the one or more fingers 105 into three or more segments. In various embodiments, this division is such that alternating arrangements exist between the n-diffusion regions 140 and p-diffusion regions 135 of the one or more fingers 205. In various embodiments, the ESD device 200 includes one or more fingers 206, which may include an n-well region (nw) 103 having one or more n-diffusion regions 140 and one or more p-diffusion regions 135. In various embodiments, the division of the one or more fingers 206 is such that alternating p-diffusion regions 135 and n-diffusion regions 140 divide the one or more fingers 106 into three segments.

[0030] In various embodiments, this division results in an alternating arrangement between the n-diffusion region 140 and the p-diffusion region 135. In various embodiments, one or more fingers 205 and one or more fingers 206 are laterally arranged on any suitable semiconductor substrate 101, and in various embodiments, the segmentation into the respective fingers results in an alternating and / or staggered arrangement of the p-diffusion region 135 of one finger 205 relative to the n-diffusion region 140 of another finger 206. The substrate may be n-doped and / or p-doped at various portions along the configuration of the substrate 101 as needed and according to the specific fingers 205, 206, wherein the substrate 101 may be doped with different types of dopants and / or doped with different concentrations of dopants at various portions along the substrate.

[0031] Like ESD 100, ESD 200 utilizes one or more fingers 205, 206 to form one or more SCRs and diodes. The difference is that, as shown in the figure, each finger is divided into three segments, wherein each segment forms at least a portion of at least one SCR and / or diode.

[0032] Figure 3A method 300 for fabricating and / or arranging a semiconductor electrostatic discharge protection device according to at least one embodiment of the present disclosure is illustrated. The method includes providing a suitable semiconductor substrate 302. The semiconductor substrate 302 may be doped with any suitable dopant and with different dopant concentrations suitable for its intended use. The method may also include forming or arranging a plurality of fingers, including four or more fingers, on the semiconductor substrate to form a device 310 as disclosed herein. The four or more fingers may be formed by any suitable series of semiconductor processing steps, including performing one or more etching steps (e.g., wet etching, reactive ion etching, etc.), doping (using any suitable dopant technique to have p-doped and / or n-doped on the substrate and / or other suitable layers), and / or depositing one or more semiconductor material layers (chemical vapor deposition, physical vapor deposition, etc.) on the substrate to form one or more devices as disclosed herein. In various embodiments, the four or more fingers will form at least one SCR device, and two of the four or more fingers may form at least one diode. In various embodiments, four or more fingers are divided into at least two segments having alternating n-diffusion layers and p-diffusion layers, such that two or more SCRs and two or more diodes can be formed, wherein each finger includes two segments and each segment is associated with a portion of the SCR and / or diode.

[0033] While embodiments of the invention have been disclosed with reference to certain embodiments, numerous modifications, alterations, and variations of said embodiments are possible without departing from the spirit and scope of this disclosure as defined in the appended claims. Therefore, embodiments of the invention are not limited to the described embodiments and may have the full scope defined by the language of the following claims and their equivalents.

Claims

1. A semiconductor electrostatic discharge protection device, comprising: Multiple silicon controlled rectifiers; and A plurality of diodes, wherein the plurality of silicon controlled rectifiers and the plurality of diodes are integrally arranged in at least two fingers, the at least two fingers including a first finger and a second finger, the first finger and the second finger being laterally arranged along the surface of a semiconductor substrate, wherein each of the first finger and the second finger includes at least two segments. Wherein, the first finger is arranged in a first configuration, the first configuration including: p-type wells include: The first segment includes the first n-type diffusion region and the first p-type diffusion region. The second segment includes the second n-type diffusion region and the second p-type diffusion region, and The third p-type diffusion region separates the first and second segments and forms an npn transistor. Wherein, the second finger is arranged in a second configuration, the second configuration including: n-type wells include: The first segment includes the first n-type diffusion region and the first p-type diffusion region. The second segment includes the second n-type diffusion region and the second p-type diffusion region, and The third n-type diffusion region separates the first and second segments and forms a pnp transistor. The first diode among the plurality of diodes is formed by a first p-type diffusion region of a first finger and a first n-type diffusion region of a second finger, and each finger provides at least two SCR segments. Wherein, the first p-type diffusion region of the first finger is arranged laterally between the first n-type diffusion region of the first finger and the first n-type diffusion region of the second finger, and the second n-type diffusion region of the first finger is arranged laterally between the second p-type diffusion region of the first finger and the second p-type diffusion region of the second finger.

2. The semiconductor electrostatic discharge protection device according to claim 1 further includes: A third finger, arranged laterally adjacent to the second finger, includes the first arrangement. A fourth finger is arranged laterally adjacent to the third finger, the fourth finger including the second configuration.

3. The semiconductor electrostatic discharge protection device according to claim 1, wherein at least one of the plurality of diodes is a pn diode.

4. The semiconductor electrostatic discharge protection device of claim 2, wherein, The second diode among the plurality of diodes is formed by the second n-type diffusion region of the second finger and the second p-type diffusion region of the third finger.

5. A semiconductor electrostatic discharge protection device, comprising: Multiple silicon controlled rectifiers; and A plurality of diodes, wherein the plurality of silicon controlled rectifiers and the plurality of diodes are integrally arranged in at least two fingers, the at least two fingers including a first finger and a second finger, the first finger and the second finger being laterally arranged along the surface of a semiconductor substrate. Each of the first and second fingers includes a first configuration, the first configuration comprising at least three segments, the first configuration including: The first segment includes the first n-type diffusion region and the first p-type diffusion region; The second segment includes the second n-type diffusion region and the second p-type diffusion region; and The third segment includes the third n-type diffusion region and the third p-type diffusion region. Each segment forms at least a portion of at least one SCR and / or diode. Wherein, the first p-type diffusion region of the first finger is arranged laterally between the first n-type diffusion region of the first finger and the first n-type diffusion region of the second finger, and the second n-type diffusion region of the first finger is arranged laterally between the second p-type diffusion region of the first finger and the second p-type diffusion region of the second finger, and the third p-type diffusion region of the first finger is arranged laterally between the third n-type diffusion region of the first finger and the third n-type diffusion region of the second finger.

6. The semiconductor electrostatic discharge protection device of claim 5, further comprising a third finger, the third finger comprising a first configuration and being laterally disposed with respect to the second finger, wherein, At least one of the first finger, the second finger, and the third finger includes a p-type trap.

7. The semiconductor electrostatic discharge protection device of claim 6, wherein, Another of the first, second, and third fingers includes an n-type trap.

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