Semiconductor Devices

Abstract

A semiconductor device is provided, comprising: a substrate; a first lower pattern and a second lower pattern, which are located on the substrate and arranged in a row in a first direction; a first active pattern stack, which is arranged on the first lower pattern and spaced apart from the first lower pattern; a second active pattern stack, which is arranged on the second lower pattern and spaced apart from the second lower pattern; a fin-shaped cut gate structure, which is arranged on the first lower pattern, a portion of which overlaps with the first lower pattern; a first gate structure, which surrounds the first active pattern stack and extends in a second direction intersecting the first direction; a second gate structure, which surrounds the second active pattern stack and extends in the second direction; and a device isolation layer, which is located between the first gate structure and the second gate structure and separates the first lower pattern from the second lower pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2019-0091487, entitled “Semiconductor Device”, filed on July 29, 2019 in the Korean Intellectual Property Office are incorporated herein by reference. Technical Field

[0003] Embodiments relate to semiconductor devices. Background Art

[0004] As semiconductor devices become more highly integrated, it becomes more difficult to achieve the transistor performance required by users. For this reason, various field effect transistors have been proposed. For example, it has been proposed to replace the ordinary field effect transistor including the gate insulating layer and the gate electrode formed using silicon oxide and polysilicon respectively with a high dielectric layer-metal gate structure.

[0005] As the feature size of field effect transistors decreases, the length of the gate and the length of the channel thereunder become smaller. Therefore, various studies have been conducted on the manufacturing process and structure of integrated circuit devices to improve the operational stability and reliability of transistors, which are factors determining the performance of integrated circuits. Summary of the invention

[0006] An embodiment relates to a semiconductor device, which includes: a substrate; a first lower pattern and a second lower pattern, which are located on the substrate and are arranged in a row in a first direction; a first active pattern stack, which is arranged on the first lower pattern and spaced apart from the first lower pattern; a second active pattern stack, which is arranged on the second lower pattern and spaced apart from the second lower pattern; a fin-cut gate structure is arranged on the first lower pattern, and a portion of the fin-cut gate structure overlaps with the first lower pattern; a first gate structure, which surrounds the first active pattern stack and extends in a second direction intersecting the first direction; a second gate structure, which surrounds the second active pattern stack and extends in the second direction; and a device isolation layer, which is located between the first gate structure and the second gate structure and separates the first lower pattern from the second lower pattern.

[0007] The embodiment also relates to a semiconductor device, comprising: a substrate; a lower pattern disposed on the substrate and extending in a first direction parallel to an upper surface of the substrate; a plurality of sheet patterns disposed on the lower pattern and arranged in a second direction perpendicular to the upper surface of the substrate; a gate electrode surrounding the plurality of sheet patterns; and an insulating pattern contacting the plurality of sheet patterns and comprising a linear insulating pattern and a plurality of protruding insulating patterns. The linear insulating pattern may extend in the second direction, and each of the plurality of protruding insulating patterns may protrude from a sidewall of the linear insulating pattern along the first direction.

[0008] The embodiment also relates to a semiconductor device, the semiconductor device comprising: a substrate, comprising a first region and a second region; a first lower pattern, located in the first region and extending in a first direction; a second lower pattern, located in the second region and extending in a second direction; a first active pattern stack, located on the first lower pattern, the first active pattern stack comprising a plurality of first sheet patterns; a second active pattern stack, located on the second lower pattern, the second active pattern stack comprising a plurality of second sheet patterns; a first gate structure, surrounding the plurality of first sheet patterns; a second gate structure, surrounding the plurality of second sheet patterns; a first device isolation layer, extending along a sidewall of the first gate structure and contacting the first lower pattern; and a second device isolation layer, extending along a sidewall of the second gate structure and contacting the second lower pattern. The first device isolation layer may include a first portion located between an upper surface of the first lower pattern and an uppermost surface of the first active pattern stack, the second device isolation layer may include a second portion located between an upper surface of the second lower pattern and an uppermost surface of the second active pattern stack, the first portion of the first device isolation layer may have a first width in the first direction, and the second portion of the second device isolation layer may have a second width greater than the first width in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A top view of a semiconductor device according to example embodiments is shown.

[0011] Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA.

[0012] Figure 3 Shown along Figure 1 A cross-sectional view taken along line BB.

[0013] Figure 4 Shows Figure 2 An enlarged view of portion X.

[0014] Figure 5 Shows Figure 2 An enlarged view of part Y of FIG.

[0015] Figure 6 Views illustrating a semiconductor device according to example embodiments are shown.

[0016] Figure 7 Views illustrating a semiconductor device according to example embodiments are shown.

[0017] Figure 8 Views illustrating a semiconductor device according to example embodiments are shown.

[0018] Fig. 9 Views illustrating a semiconductor device according to example embodiments are shown.

[0019] Fig.10 Views illustrating a semiconductor device according to example embodiments are shown.

[0020] Fig.11 Views illustrating a semiconductor device according to example embodiments are shown.

[0021] Fig.12 Views illustrating a semiconductor device according to example embodiments are shown.

[0022] Fig.13 Views illustrating a semiconductor device according to example embodiments are shown.

[0023] Fig.14 Views illustrating a semiconductor device according to example embodiments are shown.

[0024] Fig.15 A top view of a semiconductor device according to example embodiments is shown.

[0025] Fig.16 Shown along Fig.15 Cross-sectional view taken along line CC.

[0026] Fig.17 Shown along Fig.15 A cross-sectional view taken along line DD.

[0027] Fig.18 Views illustrating a semiconductor device according to example embodiments are shown.

[0028] Fig.19 Views illustrating a semiconductor device according to example embodiments are shown.

[0029] Fig. 20 Views illustrating a semiconductor device according to example embodiments are shown. DETAILED DESCRIPTION

[0030] Figure 1 is a top plan view illustrating a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB. Figure 4 yes Figure 2 An enlarged view of portion X. Figure 5 yes Figure 2 An enlarged view of part Y of FIG.

[0031] Reference Figures 1 to 5 , a semiconductor device according to example embodiments may include a substrate 100, a first lower pattern 110, a second lower pattern 210, a first active pattern stack 115 and 115_1, a first fin cut pattern stack 116, contacts 175 and 275, a wiring structure 180, interlayer insulating layers 191, 192, and 193, a second active pattern stack 215 and 215_1, a second fin cut pattern stack 216, a first gate structure 120 and 120_1, a second gate structure 220 and 220_1, a first fin cut gate structure 120_2, a second fin cut gate structure 220_2, and a first device isolation layer 160. (For ease of explanation, the first device isolation layer 160 is shown in FIG. 1 ). Figure 1 , the interlayer insulating layers 191, 192 and 193, the contacts 175 and 275, and the wiring structure 180 are omitted. )

[0032] The substrate 100 may be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In example embodiments, the substrate 100 may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or the like.

[0033] The first lower pattern 110 and the second lower pattern 210 may protrude from the substrate 100. The first lower pattern 110 and the second lower pattern 210 may respectively extend longitudinally along a first direction X1 parallel to the upper surface of the substrate 100. The first lower pattern 110 and the second lower pattern 210 may be aligned in a row in the first direction X1 and may be spaced apart from each other in the first direction X1.

[0034] The long sidewalls of the first lower pattern 110 and the long sidewalls of the second lower pattern 210 extending in the first direction X1 may be defined by the fin-shaped groove 105t. In addition, one short sidewall of the short sidewalls of the first lower pattern 110 and one short sidewall of the short sidewalls of the second lower pattern 210 extending in the second direction Y1 intersecting the first direction X1 may be defined by the fin-shaped groove 105t. Another short sidewall of the first lower pattern 110 and another short sidewall of the second lower pattern 210 may be defined by the first device isolation groove 160t. The first lower pattern 110 and the second lower pattern 210 may both have, for example, a fin-shaped shape. In an embodiment, the first lower pattern 110 and the second lower pattern 210 may be completely separated by the first device isolation groove 160t. The semiconductor pattern for connecting the lower portion of the first lower pattern 110 and the lower portion of the second lower pattern 210 may be disposed between the first device isolation layer 160 and the substrate 100.

[0035] The first lower pattern 110 and the second lower pattern 210 may each be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100. The first lower pattern 110 and the second lower pattern 210 may each include a semiconductor material, for example, silicon (Si) or germanium (Ge). In example embodiments, the first lower pattern 110 and the second lower pattern 210 may each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0036] IV-IV compound semiconductors may include binary compounds or ternary compounds including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with IV group elements. III-V compound semiconductors may include binary compounds, ternary compounds, or quaternary compounds, each of which is formed by a combination of a III group element (e.g., at least one of aluminum (Al), gallium (Ga), and indium (In)) and a V group element (e.g., one of phosphorus (P), arsenic (As), and antimony (Sb)).

[0037] The first lower pattern 110 and the second lower pattern 210 may include the same material.

[0038] The field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may fill at least a portion of the fin-shaped trench 105t. The field insulating layer 105 may be disposed on the sidewalls of the first lower pattern 110 and the second lower pattern 210. The field insulating layer 105 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0039] The first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116 may be disposed on the first lower pattern 110 and may be spaced apart from the first lower pattern 110 in the thickness direction Z of the substrate 100 .

[0040] The first active pattern stack 115 may include one or more sheet patterns 115NS arranged in the thickness direction Z of the substrate 100, the first active pattern stack 115_1 may include one or more sheet patterns 115NS_1 arranged in the thickness direction Z of the substrate 100, and the first fin cut pattern stack 116 may include one or more sheet patterns 116NS arranged in the thickness direction Z of the substrate 100. The first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116 may include a plurality of sheet patterns 115NS, a plurality of sheet patterns 115NS_1, and a plurality of sheet patterns 116NS, respectively. For example, the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116 may each include three sheet patterns.

[0041] The first active pattern stacks 115 and 115_1 may include a first normal pattern stack 115 and a first dummy pattern stack 115_1. The first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116 may be arranged in the first direction X1 along the upper surface of the first lower pattern 110. The first epitaxial pattern 150 may be disposed between corresponding pattern stacks in the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116.

[0042] The first normal pattern stack 115 may be connected to two first epitaxial patterns 150 at opposite sides of the first normal pattern stack 115. The first dummy pattern stack 115_1 and the first fin cut pattern stack 116 may each be connected to one first epitaxial pattern 150. The first fin cut pattern stack 116 may be disposed on one end of the first lower pattern 110 defined by the fin trench 105t. The first dummy pattern stack 115_1 may be disposed on the other end of the first lower pattern 110 defined by the first device isolation trench 160t.

[0043] The second active pattern stacks 215 and 215_1 and the second fin cut pattern stack 216 may be disposed on the second lower pattern 210 and may be spaced apart from the second lower pattern 210 in the thickness direction Z of the substrate 100 .

[0044] The second active pattern stacks 215 and 215_1 and the second fin cut pattern stack 216 may include one or more sheet patterns 215NS, 215NS_1, and 216NS, respectively, arranged in the thickness direction Z of the substrate 100 .

[0045] The second active pattern stacks 215 and 215_1 may include a second normal pattern stack 215 and a second dummy pattern stack 215_1. The second active pattern stacks 215 and 215_1 and the second fin cut pattern stack 216 may be arranged in the first direction X1 along the upper surface of the second lower pattern 210. The second epitaxial pattern 250 may be disposed between corresponding ones of the second active pattern stacks 215 and 215_1 and the second fin cut pattern stack 216.

[0046] The second normal pattern stack 215 may be connected to two second epitaxial patterns 250 at opposite sides of the second normal pattern stack 215. The second dummy pattern stack 215_1 and the second fin cut pattern stack 216 may each be connected to one second epitaxial pattern 250. The second fin cut pattern stack 216 may be disposed on one end of the second lower pattern 210 defined by the fin trench 105t. The second dummy pattern stack 215_1 may be disposed on the other end of the second lower pattern 210 defined by the first device isolation trench 160t.

[0047] The first active pattern stacks 115 and 115_1, the first fin cut pattern stack 116, the second active pattern stacks 215 and 215_1, and the second fin cut pattern stack 216 may each include silicon, germanium, or a compound semiconductor (e.g., a group IV-IV compound semiconductor or a group III-V compound semiconductor). The first active pattern stacks 115 and 115_1, the first fin cut pattern stack 116, the second active pattern stacks 215 and 215_1, and the second fin cut pattern stack 216 located at the same level may include the same material.

[0048] The first normal pattern stack 115 and the second normal pattern stack 215 may function as channel regions of transistors having the same conductivity type.

[0049] The first gate structures 120 and 120_1 and the first fin-cut gate structure 120_2 may extend in the second direction Y1 and may cross the first lower pattern 110 . The first gate structures 120 and 120_1 and the first fin-cut gate structure 120_2 may be disposed on the first lower pattern 110 .

[0050] From a top view (e.g. Figure 11 ), a portion of the first fin-shaped cut gate structure 120_2 may overlap with the first lower pattern 110. The first gate structures 120 and 120_1 may overlap with the first lower pattern 110. For example, the overlapping width between the first fin-shaped cut gate structure 120_2 and the first lower pattern 110 in the first direction X1 may be smaller than the width of the first fin-shaped cut gate structure 120_2 in the first direction X1. The overlapping width between each of the first gate structures 120 and 120_1 and the first lower pattern 110 in the first direction X1 may be the same as the width of each of the first gate structures 120 and 120_1 in the first direction X1.

[0051] The first gate structures 120 and 120_1 may surround the first active pattern stacks 115 and 115_1, respectively. The first gate structures 120 and 120_1 may include a first normal gate structure 120 surrounding the first normal pattern stack 115 and a first dummy gate structure 120_1 surrounding the first dummy pattern stack 115_1. The first fin cut gate structure 120_2 may cover the first fin cut pattern stack 116.

[0052] The second gate structures 220 and 220_1 and the second fin-cut gate structure 220_2 may extend in the second direction Y1 and may cross the second lower pattern 210. The second gate structures 220 and 220_1 and the second fin-cut gate structure 220_2 may be disposed on the second lower pattern 210. A portion of the second fin-cut gate structure 220_2 may overlap the second lower pattern 210. The second gate structures 220 and 220_1 may overlap the second lower pattern 210.

[0053] The second gate structures 220 and 220_1 may surround the second active pattern stacks 215 and 215_1, respectively. The second gate structures 220 and 220_1 may include a second normal gate structure 220 surrounding the second normal pattern stack 215 and a second dummy gate structure 220_1 surrounding the second dummy pattern stack 215_1. The second fin cut gate structure 220_2 may cover the second fin cut pattern stack 216.

[0054] The first gate structures 120 and 120_1 and the first fin-cut gate structure 120_2 may each include a first gate electrode 130, a first gate insulating layer 135, a first gate spacer 140, and a first capping pattern 145. The second gate structures 220 and 220_1 and the second fin-cut gate structure 220_2 may each include a second gate electrode 230, a second gate insulating layer 235, a second gate spacer 240, and a second capping pattern 245. Hereinafter, the first gate structures 120 and 120_1 and the first fin-cut gate structure 120_2 will be further described. Through the description of the first gate structures 120 and 120_1 and the first fin-cut gate structure 120_2, the description of the second gate structures 220 and 220_1 and the second fin-cut gate structure 220_2 may be easily understood.

[0055] The first gate spacer 140 may extend along the second direction Y1. The first gate spacer 140 may intersect the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116. The first gate spacer 140 may be disposed on opposite ends of each of the first active pattern stacks 115 and 115_1 extending along the first direction X1. The first normal sheet pattern 115NS and the first dummy sheet pattern 115NS_1 may penetrate the first gate spacers 140 opposite to each other. The first fin cut sheet pattern 116NS may penetrate one of the first gate spacers 140 opposite to each other.

[0056] Each of the first gate spacers 140 may include a first inner spacer 142 and a first outer spacer 141. The first inner spacer 142 may be disposed between the first lower pattern 110 and each of the first active pattern stacks 115 and 115_1, between the first lower pattern 110 and the first fin cut pattern stack 116, and between the sheet patterns 115NS adjacent to each other in the thickness direction Z of the substrate 100, between the sheet patterns 115NS_1 adjacent to each other in the thickness direction Z of the substrate 100, and between the sheet patterns 116NS adjacent to each other in the thickness direction Z of the substrate 100. The first outer spacer 141 may be disposed on each of the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116.

[0057] The first outer spacer 141 and the first inner spacer 142 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. In example embodiments, the first inner spacer 142 may be a single layer.

[0058] The first gate insulating layer 135 may extend along a surface of each of the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116. The first gate insulating layer 135 may be disposed on an upper surface of the field insulating layer 105 and on the first lower pattern 110. The first gate insulating layer 135 may extend along an inner sidewall of the first gate spacer 140. An interface layer (not shown) may be disposed between the first gate insulating layer 135 and each of the first active pattern stacks 115 and 115_1, between the first gate insulating layer 135 and the first fin cut pattern stack 116, and between the first gate insulating layer 135 and the first lower pattern 110.

[0059] The first gate insulating layer 135 may include silicon oxide, silicon oxynitride, silicon nitride, and / or a high-k dielectric material having a higher dielectric constant than silicon oxide. The first gate insulating layer 135 may include a high-k dielectric material, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0060] like Figure 4 As shown, for example, a boundary between the first inner spacer 142 and the first gate insulating layer 135 may be curved.

[0061] The first gate electrode 130 may surround a surface of each of the first active pattern stacks 115 and 115_1 and the first fin cut pattern stack 116. The first gate electrode 130 may be disposed on the first gate insulating layer 135 between the first gate spacers 140.

[0062] The first gate electrode 130 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN ), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. The first gate electrode 130 may include a conductive metal oxide or a conductive metal oxynitride. The first gate electrode 130 may include an oxidized form of the above materials.

[0063] The first capping pattern 145 may be disposed on the first gate electrode 130. In an implementation, the first gate insulating layer 135 may not be disposed between the first gate spacer 140 and the first capping pattern 145.

[0064] like Figure 2 As shown, the first capping pattern 145 may be disposed between the inner sidewalls of the first gate spacer 140, but the inventive concept is not limited thereto. In example embodiments, like the first gate electrode 130, the upper surface of the first gate spacer 140 may be recessed to be lower than the upper surface of the first interlayer insulating layer 191 to be formed in a subsequent process. In this case, the first capping pattern 145 may be disposed on the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode 130.

[0065] The upper surface of the first capping pattern 145 may be coplanar with the upper surface of the first interlayer insulating layer 191. The first capping pattern 145 may include a material having an etching selectivity with respect to the first interlayer insulating layer 191. The first capping pattern 145 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0066] The first epitaxial pattern 150 may be disposed between the first gate structures 120 and 120_1 and the corresponding gate structures in the first fin-cut gate structure 120_2. The first epitaxial pattern 150 may be disposed on the first lower pattern 110. The second epitaxial pattern 250 may be disposed between the second gate structures 220 and 220_1 and the corresponding gate structures in the second fin-cut gate structure 220_2. The second epitaxial pattern 250 may be disposed on the second lower pattern 210. The first epitaxial pattern 150 and the second epitaxial pattern 250 may be formed by an epitaxial growth process.

[0067] The first epitaxial pattern 150 may be included in a source / drain of a transistor using the first general pattern stack 115 as a channel region. The second epitaxial pattern 250 may be included in a source / drain of a transistor using the second general pattern stack 215 as a channel region.

[0068] The first etch stop layer 170 may be disposed on the upper surface of the first epitaxial pattern 150, the upper surface of the second epitaxial pattern 250, the outer sidewalls of the first gate spacer 140, the outer sidewalls of the second gate spacer 240, and the upper surface of the field insulating layer 105. The first etch stop layer 170 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), or a combination thereof. The first etch stop layer 170 may include a material having an etch selectivity with respect to a material of the first interlayer insulating layer 191 .

[0069] The first interlayer insulating layer 191 may be disposed on the first etch stop layer 170. The first interlayer insulating layer 191 may cover outer sidewalls of the first gate spacer 140 and the second gate spacer 240. The first interlayer insulating layer 191 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0070] The second interlayer insulating layer 192 may be disposed on the first interlayer insulating layer 191. The second interlayer insulating layer 192 may cover the first gate structures 120 and 120_1, the first fin-cut gate structure 120_2, the second gate structures 220 and 220_1, and the second fin-cut gate structure 220_2. The second interlayer insulating layer 192 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0071] The first device isolation layer 160 may be disposed between the first lower pattern 110 and the second lower pattern 210. The first device isolation layer 160 may separate the first lower pattern 110 and the second lower pattern 210. The first device isolation layer 160 may be disposed between the first gate structure (i.e., the first dummy gate structure) 120_1 and the second gate structure (i.e., the second dummy gate structure) 220_1. The first device isolation layer 160 may extend along the sidewalls of the first dummy gate structure 120_1 and the sidewalls of the second dummy gate structure 220_1.

[0072] The first device isolation layer 160 may fill the first device isolation trench 160t. A portion of the first device isolation trench 160t may be defined by the first lower pattern 110 and the second lower pattern 210. The first device isolation layer 160 may extend between the first dummy gate structure 120_1 and the second dummy gate structure 220_1, between the first dummy pattern stack 115_1 and the second dummy pattern stack 215_1, and between the first lower pattern 110 and the second lower pattern 210. The first device isolation layer 160 may extend longitudinally in the thickness direction Z of the substrate 100.

[0073] In example embodiments, the first device isolation layer 160 may contact the first dummy pattern stack 115_1 and the second dummy pattern stack 215_1. The first device isolation layer 160 may contact the first inner spacer 142 and the second inner spacer 242. Figure 2 and Figure 4 As shown, the first inner spacer 142 and the second inner spacer 242 may protrude from the sidewall 160 s of the first device isolation layer 160 in the first direction X1 .

[0074] As an example, a height from an upper surface of the first lower pattern 110 to an upper surface of the first device isolation layer 160 may be greater than a height from an upper surface of the first lower pattern 110 to an upper surface of the first dummy gate structure 120_1. In example embodiments, a height from an upper surface of the first lower pattern 110 to an upper surface of the first device isolation layer 160 may be equal to a height from an upper surface of the first lower pattern 110 to an upper surface of the first dummy gate structure 120_1.

[0075] The first device isolation layer 160 may have a first width W11 in the first direction X1 at the uppermost surface of the first dummy pattern stack 115_1. The first device isolation layer 160 may have a second width W12 in the first direction X1 at the upper surface of the first lower pattern 110. In example embodiments, the first width W11 of the first device isolation layer 160 may be equal to the second width W12 of the first device isolation layer 160.

[0076] Here, the uppermost surface of the first dummy pattern stack 115_1 may be an upper surface of the uppermost first dummy sheet pattern among the first dummy sheet patterns 115NS_1 included in the first dummy pattern stack 115_1. For example, the first width W11 of the first device isolation layer 160 may be a distance between an outer sidewall of the first outer spacer 141 and an outer sidewall of the second outer spacer 241 at the uppermost surface of the first dummy pattern stack 115_1.

[0077] The first device isolation layer 160 may include a first portion contacting the first lower pattern 110 and the second lower pattern 210, a second portion located between a level of an upper surface of the first lower pattern 110 and a level of an uppermost surface of the first dummy pattern stack 115_1, and a third portion located between a level of an uppermost surface of the first dummy pattern stack 115_1 and a level of an upper surface of the first dummy gate structure 120_1. In example embodiments, the first device isolation layer 160 may further include a fourth portion located on the third portion of the first device isolation layer 160, and a width of the fourth portion in the first direction X1 may be smaller than a width of the third portion in the first direction X1.

[0078] The first portion of the first device isolation layer 160 may have a third width W13 in the first direction X1. The third width W13 of the first portion of the first device isolation layer 160 may be less than the second width W12 of the first device isolation layer 160. The third width W13 of the first device isolation layer 160 may increase as the distance from the substrate 100 increases. Therefore, the third width W13 of the first portion of the first device isolation layer 160 may decrease in a direction from the upper surface of the first lower pattern 110 to the substrate 100.

[0079] The second portion of the first device isolation layer 160 may have a fourth width W14 in the first direction X1. In example embodiments, the fourth width W14 of the second portion of the first device isolation layer 160 may be constant. The fourth width W14 of the second portion of the first device isolation layer 160 may be constant between the upper surface of the first lower pattern 110 and the uppermost surface of the first dummy pattern stack 115_1. For example, since the material of the first dummy pattern stack 115_1 is different from the material of the first inner spacer 142, the sidewall 160s of the first device isolation layer 160 may include a slight unevenness. As used herein, “the width is constant” means that the distance between the opposite sidewalls 160s of the first device isolation layer 160 is completely equal, but may include a slight change in width due to the slight unevenness of the sidewall 160s of the first device isolation layer 160.

[0080] In example embodiments, a portion of the first etch stop layer 170 may be disposed between the third portion of the first device isolation layer 160 and the first dummy gate structure 120_1 . Thus, a portion of the first etch stop layer 170 may be disposed along a portion of an outer sidewall of the first outer spacer 141 .

[0081] Therefore, if Figure 2 and Figure 5 As shown, the third portion of the first device isolation layer 160 may include a second subregion 160b and a first subregion 160a located on the second subregion 160b. In the third portion of the first device isolation layer 160, the width of the first subregion 160a in the first direction X1 may be smaller than the width of the second subregion 160b in the first direction X1.

[0082] like Figure 1 As shown, the first device isolation layer 160 may span between the two first lower patterns 110 and the two second lower patterns 210 , but the inventive concept is not limited thereto.

[0083] The first device isolation layer 160, the first inner spacer 142, and the second inner spacer 242 may constitute an insulating pattern. The insulating pattern may include a linear insulating pattern longitudinally extending in the thickness direction Z of the substrate 100 and a protruding insulating pattern protruding from and contacting the linear insulating pattern in the first direction X1.

[0084] For example, the linear insulating pattern may be the first device isolation layer 160, and each protruding insulating pattern may be the first inner spacer 142 or the second inner spacer 242. The protruding insulating pattern may contact the plurality of first dummy sheet patterns 115NS_1 and the plurality of second dummy sheet patterns 215NS_1.

[0085] The linear insulating pattern may contact the first lower pattern 110 and the second lower pattern 210. The protruding insulating pattern may be disposed on the upper surface of the first lower pattern 110 and the upper surface of the second lower pattern 210. In example embodiments, when each of the protruding insulating patterns is the first inner spacer 142, the second inner spacer 242, the first outer spacer 141, or the second outer spacer 241, a portion of the first dummy sheet pattern 115NS_1 and a portion of the second dummy sheet pattern 215NS_1 may be disposed between the protruding insulating patterns adjacent to each other in the thickness direction Z of the substrate 100.

[0086] The first contact 175 and the second contact 275 may be disposed in the second interlayer insulating layer 192 and the first interlayer insulating layer 191. The first contact 175 may be connected to the first epitaxial pattern 150 located on the first lower pattern 110. The second contact 275 may be connected to the second epitaxial pattern 250 located on the second lower pattern 210. The silicide layer (not in Figure 2 ) may be disposed between the first contact 175 and the first epitaxial pattern 150 and between the second contact 275 and the second epitaxial pattern 250. The first contact 175 may be connected to one of the first epitaxial patterns 150, and the second contact 275 may be connected to one of the second epitaxial patterns 250.

[0087] In example embodiments, upper surfaces of the first contacts 175, the second contacts 275, the first device isolation layer 160, and the second interlayer insulating layer 192 may be coplanar with each other. For example, the height from the upper surface of the first lower pattern 110 to the upper surface of the first contact 175 may be equal to the height from the upper surface of the first lower pattern 110 to the upper surface of the first device isolation layer 160. As used herein, "equal in height" means that the heights of two locations are completely equal, but may include a slight difference in height due to a process margin.

[0088] The third interlayer insulating layer 193 may be disposed on the second interlayer insulating layer 192. The third interlayer insulating layer 193 may be disposed on the first contact 175, the second contact 275, and the first device isolation layer 160. The third interlayer insulating layer 193 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0089] The wiring structure 180 may be disposed in the third interlayer insulating layer 193. The wiring structure 180 may be formed in a back-end-of-line (BEOL) process.

[0090] The wiring structure 180 may be connected to the first contacts 175 and the second contacts 275. The wiring structure 180 may include a via pattern 181 and a wiring pattern 182.

[0091] Although the first contacts 175 , the second contacts 275 , and the wiring structure 180 are each illustrated as a single layer, this is merely an example.

[0092] Figure 6 is a view illustrating a semiconductor device according to example embodiments. Figure 7 is a view illustrating a semiconductor device according to example embodiments. Figure 6 and Figure 7 yes Figure 2 will not be described or will be briefly mentioned with reference to Figures 1 to 5 The same elements as those described.

[0093] Reference Figure 6 and Figure 7 , in the semiconductor device according to example embodiments, the first inner spacer 142 may have a double-layered structure.

[0094] The first inner spacer 142 may include a double layer including different materials.

[0095] like Figure 6 As shown, the first inner spacer 142 may include an outer protruding insulating layer 142 a and an inner protruding insulating layer 142 b. The outer protruding insulating layer 142 a and the inner protruding insulating layer 142 b may contact the first device isolation layer 160.

[0096] The outer protruding insulating layer 142a may contact the first gate insulating layer 135. The inner protruding insulating layer 142b may be disposed between the first device isolation layer 160 and the outer protruding insulating layer 142a. For example, the outer protruding insulating layer 142a may include silicon nitride, and the inner protruding insulating layer 142b may include silicon oxide.

[0097] like Figure 7 As shown, the first inner spacer 142 may include an outer protruding insulating layer 142 a and an inner air-gap insulating layer 142 c. The outer protruding insulating layer 142 a and the inner air-gap insulating layer 142 c may contact the first device isolation layer 160 .

[0098] The inner air-gap insulating layer 142 c may include an air gap. The air gap may be provided between the outer protruding insulating layer 142 a and the first device isolation layer 160 .

[0099] In example embodiments, the second inner spacer 242 may have the same double-layered structure as the first inner spacer 142. In example embodiments, the second inner spacer 242 may have a double-layered structure different from the first inner spacer 142. In example embodiments, the second inner spacer 242 may have a single-layered structure.

[0100] The first inner spacer 142 may include two layers having different materials. In another example embodiment, the first inner spacer 142 may include three or more layers.

[0101] Figure 8 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0102] Reference Figure 8, in the semiconductor device according to example embodiments, a first width W11 of the first device isolation layer 160 at the uppermost surface of the first dummy pattern stack 115_1 may be smaller than a second width W12 of the first device isolation layer 160 at the upper surface of the first lower pattern 110 .

[0103] A fourth width W14 of the first device isolation layer 160 between the upper surface of the first lower pattern 110 and the uppermost surface of the first dummy pattern stack 115_1 may be greater than a first width W11 of the first device isolation layer 160 at the uppermost surface of the first dummy pattern stack 115_1 .

[0104] Fig. 9 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0105] Reference Fig. 9 In the semiconductor device according to example embodiments, the first device isolation layer 160 may include a first device isolation liner 161 and a first device isolation filling layer 162 .

[0106] The first device isolation liner 161 may extend along the sidewall and bottom surface of the first device isolation trench 160t. The first device isolation filling layer 162 may be disposed on the first device isolation liner 161 and may fill the first device isolation trench 160t. The first device isolation liner 161 and the first device isolation filling layer 162 may include different materials.

[0107] Fig.10 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0108] Reference Fig.10 , the first contact 175 may include a first lower contact 175a and a first upper contact 175b. The second contact 275 may include a second lower contact 275a and a second upper contact 275b.

[0109] The second interlayer insulating layer 192 may include a second lower interlayer insulating layer 192 a on the first interlayer insulating layer 191 and a second upper interlayer insulating layer 192 b on the second lower interlayer insulating layer 192 a .

[0110] The first lower contact 175a and the second lower contact 275a may be disposed in the second lower interlayer insulating layer 192a and the first interlayer insulating layer 191. The first upper contact 175b and the second upper contact 275b may be disposed in the second lower interlayer insulating layer 192b. The first device isolation layer 160 may be disposed in the second lower interlayer insulating layer 192a, but may not be disposed in the second upper interlayer insulating layer 192b. The second upper interlayer insulating layer 192b may cover the upper surface of the first device isolation layer 160.

[0111] In example embodiments, upper surfaces of the first lower contacts 175 a , upper surfaces of the second lower contacts 275 a , upper surfaces of the first device isolation layer 160 , and upper surfaces of the second lower interlayer insulating layer 192 a may be coplanar with each other.

[0112] The height from the upper surface of the first lower pattern 110 to the upper surface of the first lower contact 175 a may be equal to the height from the upper surface of the first lower pattern 110 to the upper surface of the first device isolation layer 160. The height from the upper surface of the first lower pattern 110 to the upper surface of the first device isolation layer 160 may be less than the height from the upper surface of the first lower pattern 110 to the upper surface of the first contact 175.

[0113] Fig.11 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0114] Reference Fig.11 , in the semiconductor device according to example embodiments, the first etch stop layer 170 may not be disposed between the first device isolation layer 160 and the first dummy gate structure 120_1 and between the first device isolation layer 160 and the second dummy gate structure 220_1 .

[0115] Between the uppermost surface of the first dummy pattern stack 115_1 and the upper surface of the first dummy gate structure 120_1 , the width of the first device isolation layer 160 in the first direction X1 may be equal to the distance between the first dummy gate structure 120_1 and the second dummy gate structure 220_1 .

[0116] Fig.12 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0117] Reference Fig.12In the semiconductor device according to example embodiments, the first gate structures 120 and 120_1 , the first fin-cut gate structure 120_2 , the second gate structures 220 and 220_1 , and the second fin-cut gate structure 220_2 may not include an inner spacer.

[0118] The first gate insulating layer 135 and the second gate insulating layer 235 may contact the first device isolation layer 160. The first gate insulating layer 135 may contact the first epitaxial pattern 150. The second gate insulating layer 235 may contact the second epitaxial pattern 250. A first width W11 of the first device isolation layer 160 at the uppermost surface of the first dummy pattern stack 115_1 may be equal to a second width W12 of the first device isolation layer 160 at the upper surface of the first lower pattern 110.

[0119] In example embodiments, the fourth width W14 of the first device isolation layer 160 between the upper surface of the first lower pattern 110 and the uppermost surface of the first dummy pattern stack 115_1 may not be constant. For example, the fourth width W14 of the first device isolation layer 160 between the upper surface of the first lower pattern 110 and the uppermost surface of the first dummy pattern stack 115_1 may increase and then decrease. Therefore, as the distance from the upper surface of the first lower pattern 110 increases, the fourth width W14 of the first device isolation layer 160 between the upper surface of the first lower pattern 110 and the uppermost surface of the first dummy pattern stack 115_1 may increase and then decrease.

[0120] Therefore, the fourth width W14 of the first device isolation layer 160 may increase and then decrease in a direction from the upper surface of the first lower pattern 110 to the uppermost surface of the first dummy pattern stack 115_1 .

[0121] Fig.13 is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0122] Reference Fig.13 , in the semiconductor device according to example embodiments, a first width W11 of the first device isolation layer 160 at the uppermost surface of the first dummy pattern stack 115_1 may be greater than a second width W12 of the first device isolation layer 160 at the upper surface of the first lower pattern 110 .

[0123] The width of the first device isolation layer 160 may increase and then decrease in a direction from the upper surface of the first lower pattern 110 to the uppermost surface of the first dummy pattern stack 115_1 .

[0124] Fig.14is a view showing a semiconductor device according to an example embodiment. Figures 1 to 5 The same elements as those described.

[0125] Reference Fig.14 In the semiconductor device according to example embodiments, a portion of the first contact 175 may extend into the first epitaxial pattern 150 . A portion of the second contact 275 may extend into the second epitaxial pattern 250 .

[0126] The first silicide layer 176 may be disposed between the first epitaxial pattern 150 and a portion of the first contact 175 inserted into the first epitaxial pattern 150. The second silicide layer 276 may be disposed between the second epitaxial pattern 250 and a portion of the second contact 275 inserted into the second epitaxial pattern 250. The first silicide layer 176 and the second silicide layer 276 may each include a metal silicide.

[0127] The lower surface of the first contact 175 may be disposed between the upper surface of the lowest sheet pattern among the plurality of sheet patterns 115NS, 115NS_1, and 116NS and the lower surface of the highest sheet pattern among the plurality of sheet patterns 115NS, 115NS_1, and 116NS. The lower surface of the second contact 275 may be disposed between the upper surface of the lowest sheet pattern among the plurality of sheet patterns 215NS, 215NS_1, and 216NS and the lower surface of the highest sheet pattern among the plurality of sheet patterns 215NS, 215NS_1, and 216NS.

[0128] Fig.15 is a top plan view illustrating a semiconductor device according to example embodiments. Fig.16 It is along Fig.15 Cross-sectional view taken along line CC. Fig.17 It is along Fig.15 A cross-sectional view taken along line DD.

[0129] For ease of explanation, Fig.15 , the interlayer insulating layers 191 and 192 and the contacts 375, 475, 575 and 675 are omitted. Figure 2 Different, in Fig.16 and Fig.17 , the wiring structure 180 and the third interlayer insulating layer 193 are omitted.

[0130] exist Figures 15 to 17, the third to sixth lower patterns 310, 410, 510, and 610, the third to sixth active pattern stacks 315, 315_1, 415, 415_1, 515, 515_1, 615, and 615_1, the third to sixth fin cut pattern stacks 316, 416, 516, and 616, the third to sixth gate structures 320, 320_1, 420, 420_1, 520, 520_1, 620, and 620_1, the third to sixth fin cut gate structures 320_2, 420_2, 520_2, and 620_2 may be similar to the reference numerals. Figures 1 to 14 Descriptions repeated with the previous embodiment will be briefly given.

[0131] Reference Figures 15 to 17 , a semiconductor device according to example embodiments may include third to sixth lower patterns 310, 410, 510, and 610, third to sixth active pattern stacks 315, 315_1, 415, 415_1, 515, 515_1, 615, 615_1, third to sixth fin cut pattern stacks 316, 416, 516, and 616, third to sixth gate structures 320, 320_1, 420, 420_1, 520, 520_1, 620, and 620_1, third to sixth fin cut gate structures 320_2, 420_2, 520_2, and 620_2, a second device isolation layer 360, and a third device isolation layer 560.

[0132] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may include transistors having different conductivity types. For example, the first region I of the substrate 100 may be a region where an NMOS transistor is formed, and the second region II of the substrate 100 may be a region where a PMOS transistor is formed.

[0133] In the first region I of the substrate 100, third and fourth lower patterns 310 and 410, third and fourth active pattern stacks 315, 315_1, 415 and 415_1, third and fourth fin-shaped cut pattern stacks 316 and 416, third and fourth gate structures 320, 320_1, 420 and 420_1, third and fourth fin-shaped cut gate structures 320_2 and 420_2 and a second device isolation layer 360 may be formed.

[0134] In the second region II of the substrate 100, the fifth and sixth lower patterns 510 and 610, the fifth and sixth active pattern stacks 515, 515_1, 615 and 615_1, the fifth and sixth fin-shaped cut pattern stacks 516 and 616, the fifth and sixth gate structures 520, 520_1, 620 and 620_1, the fifth and sixth fin-shaped cut gate structures 520_2 and 620_2 and the third device isolation layer 560 can be formed.

[0135] The third lower pattern 310 and the fourth lower pattern 410 may extend longitudinally along a third direction X2 parallel to the upper surface of the substrate 100. The third lower pattern 310 and the fourth lower pattern 410 may be aligned in a row in the third direction X2 as the length direction thereof. The third lower pattern 310 and the fourth lower pattern 410 may be spaced apart from each other in the third direction X2.

[0136] The fifth lower pattern 510 and the sixth lower pattern 610 may extend longitudinally along a fifth direction X3 parallel to the upper surface of the substrate 100. The fifth lower pattern 510 and the sixth lower pattern 610 may be arranged in a row in the fifth direction X3 as the length direction thereof. The fifth lower pattern 510 and the sixth lower pattern 610 may be spaced apart from each other in the fifth direction X3.

[0137] A field insulation layer 105 may be disposed on sidewalls of the third to sixth lower patterns 310 , 410 , 510 , and 610 .

[0138] The third active pattern stacks 315 and 315_1 and the third fin cut pattern stack 316 may be disposed on the third lower pattern 310 and may be spaced apart from the third lower pattern 310 in the thickness direction Z of the substrate 100. The third active pattern stack 315 may include one or more sheet patterns 315NS arranged in the thickness direction Z of the substrate 100, the third active pattern stack 315_1 may include one or more sheet patterns 315NS_1 arranged in the thickness direction Z of the substrate 100, and the third fin cut pattern stack 316 may include one or more sheet patterns 316NS arranged in the thickness direction Z of the substrate 100. The third active pattern stacks 315 and 315_1 may include a third normal pattern stack 315 and a third dummy pattern stack 315_1.

[0139] The fourth active pattern stacks 415 and 415_1 and the fourth fin cut pattern stack 416 may be disposed on the fourth lower pattern 410 and may be spaced apart from the fourth lower pattern 410 in the thickness direction Z of the substrate 100. The fourth active pattern stack 415 may include one or more sheet patterns 415NS arranged in the thickness direction Z of the substrate 100, the fourth active pattern stack 415_1 may include one or more sheet patterns 415NS_1 arranged in the thickness direction Z of the substrate 100, and the fourth fin cut pattern stack 416 may include one or more sheet patterns 416NS arranged in the thickness direction Z of the substrate 100. The fourth active pattern stacks 415 and 415_1 may include a fourth normal pattern stack 415 and a fourth dummy pattern stack 415_1.

[0140] The fifth active pattern stack 515 and 515_1 and the fifth fin cut pattern stack 516 may be disposed on the fifth lower pattern 510 and may be spaced apart from the fifth lower pattern 510 in the thickness direction Z of the substrate 100. The fifth active pattern stack 515 may include one or more sheet patterns 515NS arranged in the thickness direction Z of the substrate 100, the fifth active pattern stack 515_1 may include one or more sheet patterns 515NS_1 arranged in the thickness direction Z of the substrate 100, and the fifth fin cut pattern stack 516 may include one or more sheet patterns 516NS arranged in the thickness direction Z of the substrate 100. The fifth active pattern stack 515 and 515_1 may include a fifth normal pattern stack 515 and a fifth dummy pattern stack 515_1.

[0141] The sixth active pattern stack 615 and 615_1 and the sixth fin cut pattern stack 616 may be disposed on the sixth lower pattern 610 and may be spaced apart from the sixth lower pattern 610 in the thickness direction Z of the substrate 100. The sixth active pattern stack 615 may include one or more sheet patterns 615NS arranged in the thickness direction Z of the substrate 100, the sixth active pattern stack 615_1 may include one or more sheet patterns 615NS_1 arranged in the thickness direction Z of the substrate 100, and the sixth fin cut pattern stack 616 may include one or more sheet patterns 616NS arranged in the thickness direction Z of the substrate 100. The sixth active pattern stack 615 and 615_1 may include a sixth normal pattern stack 615 and a sixth dummy pattern stack 615_1.

[0142] The third gate structures 320 and 320_1 and the third fin-cut gate structure 320_2 may extend in a fourth direction Y2 intersecting the third direction X2 and may intersect the third lower pattern 310. A portion of the third fin-cut gate structure 320_2 may overlap the third lower pattern 310. The third gate structures 320 and 320_1 may overlap the third lower pattern 310.

[0143] The third gate structures 320 and 320_1 may cover the third active pattern stacks 315 and 315_1, respectively. The third gate structures 320 and 320_1 may include a third normal gate structure 320 surrounding the third normal pattern stack 315 and a third dummy gate structure 320_1 surrounding the third dummy pattern stack 315_1. The third fin cut gate structure 320_2 may surround the third fin cut pattern stack 316.

[0144] The fourth gate structures 420 and 420_1 and the fourth fin cut gate structure 420_2 may extend in the fourth direction Y2 and may intersect the fourth lower pattern 410. A portion of the fourth fin cut gate structure 420_2 may overlap the fourth lower pattern 410. The fourth gate structures 420 and 420_1 may overlap the fourth lower pattern 410.

[0145] The fourth gate structures 420 and 420_1 may cover the fourth active pattern stacks 415 and 415_1, respectively. The fourth gate structures 420 and 420_1 may include a fourth normal gate structure 420 surrounding the fourth normal pattern stack 415 and a fourth dummy gate structure 420_1 surrounding the fourth dummy pattern stack 415_1. The fourth fin cut gate structure 420_2 may surround the fourth fin cut pattern stack 416.

[0146] The fifth gate structures 520 and 520_1 and the fifth fin-cut gate structure 520_2 may extend in a sixth direction Y3 intersecting the fifth direction X3 and may intersect the fifth lower pattern 510. A portion of the fifth fin-cut gate structure 520_2 may overlap the fifth lower structure 510. The fifth gate structures 520 and 520_1 may overlap the fifth lower pattern 510.

[0147] The fifth gate structures 520 and 520_1 may cover the fifth active pattern stacks 515 and 515_1, respectively. The fifth gate structures 520 and 520_1 may include a fifth normal gate structure 520 surrounding the fifth normal pattern stack 515 and a fifth dummy gate structure 520_1 surrounding the fifth dummy pattern stack 515_1. The fifth fin cut gate structure 520_2 may surround the fifth fin cut pattern stack 516.

[0148] The sixth gate structures 620 and 620_1 and the sixth fin-cut gate structure 620_2 may extend in the sixth direction Y3 and may intersect the sixth lower pattern 610. A portion of the sixth fin-cut gate structure 620_2 may overlap the sixth lower pattern 610. The sixth gate structures 620 and 620_1 may overlap the sixth lower pattern 610.

[0149] The sixth gate structures 620 and 620_1 may cover the sixth active pattern stacks 615 and 615_1, respectively. The sixth gate structures 620 and 620_1 may include a sixth normal gate structure 620 surrounding the sixth normal pattern stack 615 and a sixth dummy gate structure 620_1 surrounding the sixth dummy pattern stack 615_1. The sixth fin cut gate structure 620_2 may surround the sixth fin cut pattern stack 616.

[0150] The third and fourth gate structures 320, 320_1, 420 and 420_1 and the third and fourth fin-cut gate structures 320_2 and 420_2 may each include an inner spacer (refer to Figure 2 142). However, the fifth and sixth gate structures 520, 520_1, 620, and 620_1 and the fifth and sixth fin-cut gate structures 520_2 and 620_2 may not include an inner spacer.

[0151] The third epitaxial pattern 350 may be disposed between respective gate structures adjacent to each other among the third gate structures 320 and 320_1 and the third fin-cut gate structure 320_2 . The third epitaxial pattern 350 may be disposed on the third lower pattern 310 .

[0152] The fourth epitaxial pattern 450 may be disposed between respective gate structures adjacent to each other among the fourth gate structures 420 and 420_1 and the fourth fin-cut gate structure 420_2 . The fourth epitaxial pattern 450 may be disposed on the fourth lower pattern 410 .

[0153] The fifth epitaxial pattern 550 may be disposed between respective gate structures adjacent to each other among the fifth gate structures 520 and 520_1 and the fifth fin-cut gate structure 520_2 . The fifth epitaxial pattern 550 may be disposed on the fifth lower pattern 510 .

[0154] The sixth epitaxial pattern 650 may be disposed between corresponding gate structures adjacent to each other among the sixth gate structures 620 and 620_1 and the sixth fin-cut gate structure 620_2 . The sixth epitaxial pattern 650 may be disposed on the sixth lower pattern 610 .

[0155] The second etch stop layer 370 may be disposed on the upper surface of the third epitaxial pattern 350 , the upper surface of the fourth epitaxial pattern 450 , the outer sidewalls of the third gate structures 320 and 320_1 , the outer sidewalls of the third fin-cut gate structure 320_2 , the outer sidewalls of the fourth gate structures 420 and 420_1 , the outer sidewalls of the fourth fin-cut gate structure 420_2 , and the upper surface of the field insulation layer 105 .

[0156] The third etch stop layer 570 can be set on the upper surface of the fifth epitaxial pattern 550, the upper surface of the sixth epitaxial pattern 650, the outer side walls of the fifth gate structure 520 and 520_1, the outer side walls of the fifth fin-shaped cut gate structure 520_2, the outer side walls of the sixth gate structures 620 and 620_1, the outer side walls of the sixth fin-shaped cut gate structure 620_2 and the upper surface of the field insulation layer 105.

[0157] The second device isolation layer 360 may separate the third lower pattern 310 from the fourth lower pattern 410. The second device isolation layer 360 may contact the third lower pattern 310 and the fourth lower pattern 410. The second device isolation layer 360 may be disposed between the third dummy gate structure 320_1 and the fourth dummy gate structure 420_1. The second device isolation layer 360 may extend along the sidewalls of the third dummy gate structure 320_1 and the sidewalls of the fourth dummy gate structure 420_1. The second device isolation layer 360 may fill the second device isolation trench 360t. The second device isolation layer 360 may not contact the gate insulation layer included in each of the third dummy gate structure 320_1 and the fourth dummy gate structure 420_1. The second device isolation layer 360 may contact the internal spacer included in each of the third dummy gate structure 320_1 and the fourth dummy gate structure 420_1.

[0158] At the uppermost surface of the third dummy pattern stack 315_1 , the second device isolation layer 360 may have a fifth width W21 in the third direction X2. At the upper surface of the third lower pattern 310 , the second device isolation layer 360 may have a sixth width W22 in the third direction X2.

[0159] The second device isolation layer 360 may include a first portion contacting the third lower pattern 310 and the fourth lower pattern 410, a second portion between the upper surface of the third lower pattern 310 and the uppermost surface of the third dummy pattern stack 315_1, and a third portion between the uppermost surface of the third dummy pattern stack 315_1 and the upper surface of the third dummy gate structure 320_1. The second portion of the second device isolation layer 360 may have a seventh width W23 in the third direction X2. Therefore, between the upper surface of the third lower pattern 310 and the uppermost surface of the third dummy pattern stack 315_1, the second device isolation layer 360 may have a seventh width W23.

[0160] In example embodiments, the fifth width W21 of the second device isolation layer 360 may be equal to the sixth width W22 of the second device isolation layer 360. A seventh width W23 of the second portion of the second device isolation layer 360 may remain constant between the upper surface of the third lower pattern 310 and the uppermost surface of the third dummy pattern stack 315_1.

[0161] The third device isolation layer 560 may have an eighth width W31 in the fifth direction X3 at the uppermost surface of the fifth dummy pattern stack 515_1 . The third device isolation layer 560 may have a ninth width W32 in the fifth direction X3 at the upper surface of the fifth lower pattern 510 .

[0162] The third device isolation layer 560 may include a first portion contacting the fifth lower pattern 510 and the sixth lower pattern 610, a second portion between the upper surface of the fifth lower pattern 510 and the uppermost surface of the fifth dummy pattern stack 515_1, and a third portion between the uppermost surface of the fifth dummy pattern stack 515_1 and the upper surface of the fifth dummy gate structure 520_1. The second portion of the third device isolation layer 560 may have a tenth width W33 in the fifth direction X3. Therefore, between the upper surface of the fifth lower pattern 510 and the uppermost surface of the fifth dummy pattern stack 515_1, the third device isolation layer 560 may have a tenth width W33.

[0163] In example embodiments, the eighth width W31 of the third device isolation layer 560 may be equal to the ninth width W32 of the third device isolation layer 560. The tenth width W33 of the second portion of the third device isolation layer 560 may increase in a direction away from the upper surface of the fifth lower pattern 510 and then decrease.

[0164] In example embodiments, a ninth width W32 of the third device isolation layer 560 at the upper surface of the fifth lower pattern 510 may be equal to a sixth width W22 of the second device isolation layer 360 at the upper surface of the third lower pattern 510. An eighth width W31 of the third device isolation layer 560 at the uppermost surface of the fifth dummy pattern stack 515_1 may be equal to a fifth width W21 of the second device isolation layer 360 at the uppermost surface of the third dummy pattern stack 315_1.

[0165] Since the tenth width W33 of the second portion of the third device isolation layer 560 increases in a direction away from the upper surface of the fifth lower pattern 510 , the tenth width W33 of the second portion of the third device isolation layer 560 may be greater than the seventh width W23 of the second portion of the second device isolation layer 360 .

[0166] In example embodiments, a depth d1 of a first portion of the second device isolation layer 360 contacting the third lower pattern 310 may be equal to a depth d2 of a first portion of the third device isolation layer 560 contacting the fifth lower pattern 510 .

[0167] The third contact 375 and the fourth contact 475 may be disposed in the second interlayer insulating layer 192 and the first interlayer insulating layer 191. The third contact 375 may be connected to the third epitaxial pattern 350 located on the third lower pattern 310. The fourth contact 475 may be connected to the fourth epitaxial pattern 450 located on the fourth lower pattern 410.

[0168] The fifth contact 575 and the sixth contact 675 may be disposed in the second interlayer insulating layer 192 and the first interlayer insulating layer 191. The fifth contact 575 may be connected to the fifth epitaxial pattern 550 on the fifth lower pattern 510. The sixth contact 675 may be connected to the sixth epitaxial pattern 650 on the sixth lower pattern 610.

[0169] Fig.18 is a view showing a semiconductor device according to an example embodiment. Figures 15 to 17 The same elements as those described.

[0170] Reference Fig.18 In the semiconductor device according to example embodiments, the ninth width W32 of the third device isolation layer 560 at the upper surface of the fifth lower pattern 510 may be smaller than Fig.16 The second device isolation layer 360 is shown to have a sixth width W22 at the upper surface of the third lower pattern 310 .

[0171] In addition, an eighth width W31 of the third device isolation layer 560 at the uppermost surface of the fifth dummy pattern stack 515_1 may be greater than a ninth width W32 of the third device isolation layer 560 at the upper surface of the fifth lower pattern 510 .

[0172] Fig.19 is a view showing a semiconductor device according to an example embodiment. Figures 15 to 17 The same elements as those described.

[0173] Reference Fig.19 , in a semiconductor device according to example embodiments, as Fig.16 The illustrated depth d1 of the first portion of the second device isolation layer 360 contacting the third lower pattern 310 may be greater than the depth d2 of the first portion of the third device isolation layer 560 contacting the fifth lower pattern 510 .

[0174] Fig. 20 is a view showing a semiconductor device according to an example embodiment. Figures 15 to 17 The same elements as those described.

[0175] like Fig.16 As shown, in the semiconductor device according to the example embodiment, relative to the upper surface of the third lower pattern 310 and the upper surface of the fourth lower pattern 410, the upper surface of the third epitaxial pattern 350 and the upper surface of the fourth epitaxial pattern 450 can be higher than the upper surface of the uppermost sheet pattern among the corresponding sheet patterns among the multiple sheet patterns 315NS, 315NS_1, 316NS, 415NS, 415NS_1 and 416NS.

[0176] Reference Fig. 20 In the semiconductor device according to the example embodiment, relative to the upper surface of the fifth lower pattern 510 and the upper surface of the sixth lower pattern 610, the upper surface of the fifth epitaxial pattern 550 and the upper surface of the sixth epitaxial pattern 650 may be located at the same horizontal height as the upper surface of the topmost sheet pattern among the corresponding sheet patterns among the plurality of sheet patterns 515NS, 515NS_1, 516NS, 615NS, 615NS_1 and 616NS.

[0177] As described above, the embodiment relates to a semiconductor device including an MBCFET (Multi-Bridge Channel Effect Transistor).

[0178] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: substrate; A first lower pattern and a second lower pattern are located on the substrate and arranged in a row in a first direction; a first active pattern stack disposed on and spaced apart from the first lower pattern; a second active pattern stack disposed on and spaced apart from the second lower pattern; a field insulating layer, disposed on a sidewall of the first lower pattern and a sidewall of the second lower pattern; a fin-shaped cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern; a first gate structure stacked around the first active pattern and extending in a second direction intersecting the first direction; a second gate structure, stacked around the second active pattern and extending in the second direction; as well as a device isolation layer, located between the first gate structure and the second gate structure and separating the first lower pattern from the second lower pattern, and directly contacting the first lower pattern and the second lower pattern, Wherein, the first gate structure comprises a gate electrode and a gate insulating layer, wherein a height from an upper surface of the first lower pattern to an upper surface of the device isolation layer is greater than a height from the upper surface of the first lower pattern to an upper surface of the gate electrode, and At least a portion of the device isolation layer overlaps with the field insulation layer in the first direction.

2. The semiconductor device according to claim 1, wherein The device isolation layer has a first width in the first direction at the uppermost surface of the first active pattern stack, The device isolation layer has a second width in the first direction at an upper surface of the first lower pattern, and The first width is equal to the second width.

3. The semiconductor device according to claim 1, wherein A width of a first portion of the device isolation layer in the first direction increases as a distance from the substrate increases, and the first portion of the device isolation layer contacts the first lower pattern and the second lower pattern.

4. The semiconductor device according to claim 1, wherein: The width of the second portion of the device isolation layer in the first direction is constant, and the second portion of the device isolation layer is located between a level of the upper surface of the first lower pattern and a level of an uppermost surface of the first active pattern stack.

5. The semiconductor device according to claim 1, wherein A width of a second portion of the device isolation layer increases and then decreases in a direction away from the upper surface of the first lower pattern, and the second portion of the device isolation layer is located between the upper surface of the first lower pattern and an uppermost surface of the first active pattern stack.

6. The semiconductor device according to claim 1, wherein The device isolation layer has a first width in the first direction at the uppermost surface of the first active pattern stack, The device isolation layer has a second width in the first direction at the upper surface of the first lower pattern, and The first width is greater than the second width.

7. The semiconductor device according to claim 1, wherein The device isolation layer comprises: a third portion located between the uppermost surface of the first active pattern stack and the upper surface of the first gate structure, the third portion having a third width in the first direction; and A fourth portion is located on the third portion of the device isolation layer, and the fourth portion has a fourth width in the first direction, and the fourth width is smaller than the third width.

8. The semiconductor device according to claim 1, wherein The gate insulating layer contacts the device isolation layer.

9. The semiconductor device according to claim 1, further comprising: an epitaxial pattern, located on the first lower pattern; A first interlayer insulating layer, located on an upper surface of the first gate structure and an upper surface of the second gate structure; a contact located in the first interlayer insulating layer and connected to the epitaxial pattern; a second interlayer insulating layer located on the first interlayer insulating layer and the contact; and a wiring structure located in the second interlayer insulating layer and connected to the contact, Wherein, a height from the upper surface of the first lower pattern to the upper surface of the device isolation layer is equal to or less than a height from the upper surface of the first lower pattern to the upper surface of the contact.

10. The semiconductor device according to claim 1, wherein The first active pattern stack includes a plurality of sheets stacked on the first lower pattern and / or the second lower pattern.

11. A semiconductor device comprising: substrate; a first lower pattern disposed on the substrate and extending in a first direction parallel to an upper surface of the substrate; a second lower pattern, disposed on the substrate and extending in the first direction; a plurality of first sheet-like patterns disposed on the first lower pattern and arranged in a second direction perpendicular to the upper surface of the substrate; a first gate electrode surrounding the plurality of first sheet-shaped patterns; a plurality of second sheet-like patterns, disposed on the second lower pattern and arranged in the second direction; a second gate electrode surrounding the plurality of second sheet-like patterns; as well as an insulating pattern separating the first lower pattern from the second lower pattern and directly contacting the plurality of first sheet patterns and the plurality of second sheet patterns, the insulating pattern comprising a linear insulating pattern and a plurality of protruding insulating patterns, wherein the linear insulating pattern extends along the second direction from a level higher than the uppermost height of the first gate electrode and the second gate electrode to a level lower than the uppermost surface of the first lower pattern and the second lower pattern, and Each of the plurality of protruding insulation patterns protrudes from a sidewall of the linear insulation pattern along the first direction.

12. The semiconductor device according to claim 11, wherein The linear insulating pattern contacts the first lower pattern and the second lower pattern, and The plurality of protruding insulation patterns are disposed over an upper surface of the first lower pattern.

13. The semiconductor device according to claim 11, wherein Each of the plurality of protruding insulation patterns includes an outer protruding insulation layer and an inner protruding insulation layer between the linear insulation pattern and the outer protruding insulation layer.

14. The semiconductor device according to claim 13, wherein: The inner protruding insulating layer includes an air gap.

15. A semiconductor device comprising: A substrate including a first region and a second region; a first lower pattern located in the first region and extending in a first direction; a second lower pattern located in the second region and extending in a second direction; A first active pattern stack, located on the first lower pattern, wherein the first active pattern stack includes a plurality of first sheet patterns; a second active pattern stack located on the second lower pattern, the second active pattern stack comprising a plurality of second sheet patterns; A first gate structure surrounding the plurality of first sheet-like patterns; a second gate structure surrounding the plurality of second sheet-like patterns; a first device isolation layer extending along a sidewall of the first gate structure and contacting the first lower pattern; as well as a second device isolation layer extending along a sidewall of the second gate structure and contacting the second lower pattern, in, The first device isolation layer includes a first portion located between an upper surface of the first lower pattern and an uppermost surface of the first active pattern stack, The second device isolation layer includes a second portion located between an upper surface of the second lower pattern and an uppermost surface of the second active pattern stack, The first portion of the first device isolation layer has a first width in the first direction, and The second portion of the second device isolation layer has a second width in the second direction that is greater than the first width.

16. The semiconductor device according to claim 15, wherein A width of the first device isolation layer at the upper surface of the first lower pattern in the first direction is equal to or greater than a width of the second device isolation layer at the upper surface of the second lower pattern.

17. The semiconductor device according to claim 15, wherein: A depth of a portion of the first device isolation layer contacting the first lower pattern is equal to or greater than a depth of a portion of the second device isolation layer contacting the second lower pattern.

18. The semiconductor device according to claim 15, wherein: The first gate structure contacts the first device isolation layer and includes an inner spacer protruding along the first direction.

19. The semiconductor device according to claim 15, wherein: The second width increases and then decreases in a direction away from the upper surface of the second lower pattern.

20. The semiconductor device according to claim 15, wherein The plurality of first sheet patterns are included in an NMOS region, and the plurality of second sheet patterns are included in a PMOS region.

Images