Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a channel structure located on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes located on the substrate and spaced apart from each other in the first direction on sidewalls of the channel structure; and a gate insulating layer located between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding sidewalls of the body gate layer; and a channel layer surrounding sidewalls of the charge storage structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0093370, filed on July 31, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to semiconductor devices and methods of operating the same, and more specifically, to semiconductor devices comprising a channel structure extending in a vertical direction, methods of operating the semiconductor device, and methods of manufacturing the semiconductor device. Background Technology

[0003] As the integration density of memory devices increases, memory devices with vertical transistor structures are being proposed to replace those with traditional planar transistor structures. Memory devices with vertical transistor structures can include channel structures extending vertically on a substrate. However, as the integration density of memory devices increases, the number of gate electrode layers stacked in the vertical direction also increases, making the fabrication process for memory devices increasingly difficult. Summary of the Invention

[0004] The inventive concept provides a semiconductor device that can have improved electrical characteristics while also having a high vertical height.

[0005] The inventive concept provides a method for operating a semiconductor device that can have improved electrical characteristics while also having a high vertical height.

[0006] According to one aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a channel structure located on a substrate and extending along a first direction perpendicular to a top surface of the substrate, the channel structure including a body gate layer extending along the first direction, a charge storage structure surrounding a sidewall of the body gate layer, and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes located on the substrate and spaced apart from each other along the first direction on the sidewall of the channel structure; and a gate insulating layer located between each of the plurality of gate electrodes and the channel structure.

[0007] According to another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a plurality of gate electrodes located on a substrate and spaced apart from each other along a first direction perpendicular to a top surface of the substrate; a channel structure located in a channel hole penetrating the plurality of gate electrodes and extending along the first direction, the channel structure including a channel layer located on an inner wall of the channel hole and a charge storage structure located on the channel layer located on the inner wall of the channel hole; and a gate insulating layer located between each of the plurality of gate electrodes and the channel layer, and covering a top surface and a bottom surface of each of the plurality of gate electrodes, wherein the channel layer is located between each of the plurality of gate electrodes and the charge storage structure.

[0008] According to another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a channel structure located on a substrate and extending along a first direction perpendicular to a top surface of the substrate, the channel structure including a body gate layer extending along the first direction, a charge storage structure surrounding a sidewall of the body gate layer, and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes located on the substrate and spaced apart from each other along the first direction on the sidewall of the channel structure; a gate insulating layer located between each of the plurality of gate electrodes and the channel structure; a bit line pad formed at a level higher than the level of the uppermost gate electrode of the plurality of gate electrodes and located on the channel layer; a bit line contact connected to the bit line pad; and a bit line connected to the bit line contact and extending along a second direction parallel to the top surface of the substrate. Attached Figure Description

[0009] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to some example embodiments;

[0011] Figure 2 This is a plan view illustrating a representative construction of a semiconductor device according to some example embodiments;

[0012] Figure 3 yes Figure 2 A schematic perspective view of part A1;

[0013] Figure 4A and Figure 4B yes Figure 2 A partial enlarged plan view of A2;

[0014] Figure 5 It is along Figure 2 A sectional view taken by line B1-B1';

[0015] Figure 6 It is along Figure 2 A sectional view taken by line B2-B2';

[0016] Figure 7 yes Figure 6 Enlarged view of part of the CX1;

[0017] Figure 8 A timing diagram is shown of the programming voltage applied to the programmed memory cell in an example programming operation of a semiconductor device according to some example embodiments;

[0018] Figure 9This is a circuit diagram illustrating the voltages applied to the programming string, the inhibit string, and the body gate line during programming operations according to some example embodiments;

[0019] Figure 10 It shows that it includes Figure 9 A schematic performance diagram of the components in the memory cell programmed in step 3;

[0020] Figure 11 This is a circuit diagram illustrating the voltages applied to the string gate line and body gate line to perform a read operation in an example read operation of a semiconductor device according to some example embodiments;

[0021] Figure 12 This is a circuit diagram illustrating the voltages applied to the string gate line and body gate line to perform erasure in an example erasure operation of a semiconductor device according to some example embodiments;

[0022] Figure 13 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0023] Figure 14 yes Figure 13 An enlarged sectional view of part of CX2;

[0024] Figure 15 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0025] Figure 16 yes Figure 15 Enlarged sectional view of part of CX3;

[0026] Figure 17 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0027] Figure 18 yes Figure 17 Enlarged sectional view of part of CX4;

[0028] Figure 19 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0029] Figure 20 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0030] Figures 21 to 30 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to some example embodiments, arranged in process order;

[0031] Figure 31 and Figure 32 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to some example embodiments, arranged in process sequence; and

[0032] Figures 33 to 38 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to some example embodiments, arranged in process sequence. Detailed Implementation

[0033] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0034] It will be understood that an element “on” another element may be above or below the other element. It will also be understood that an element “on” another element may be “direct” on the other element such that the elements are in direct contact with each other, or may be “indirect” on the other element such that the elements are isolated from each other by one or more insertion spaces and / or structures without direct contact.

[0035] For ease of description, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s). It will be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “below,” or “below” other elements or features will subsequently be positioned “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly. Additionally, when an element is referred to as being “between” two elements, the element may be the only element between the two elements, or there may be one or more other intermediate elements.

[0036] Figure 1 This is an equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to some example embodiments, specifically, Figure 1 This is an equivalent circuit diagram of a vertical NAND (VNAND) flash memory device with a vertical channel structure.

[0037] Reference Figure 1 The memory cell array MCA may include memory cell strings MCS11 to MCS33, word lines WL1 to WL8, ground select lines GSL1 to GSL3, string select lines SSL1 to SSL3, and common source line CSL.

[0038] Memory cell strings MCS11, MCS21, and MCS31 can be disposed between the first bit line BL1, the first body gate line BGL1, and the common source line CSL; memory cell strings MCS12, MCS22, and MCS32 can be disposed between the second bit line BL2, the second body gate line BGL2, and the common source line CSL; and memory cell strings MCS13, MCS23, and MCS33 can be disposed between the third bit line BL3, the third body gate line BGL3, and the common source line CSL. Each of the memory cell strings (e.g., MCS11) may include a series-connected string select transistor SST, a plurality of memory cells MCT1 to MCT8, and a ground select transistor GST.

[0039] The serial select transistor SST can be connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MCT1 to MCT8 can be connected to their respective word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0040] In some example embodiments, word lines of the same height (e.g., WL1) may be connected together, string select lines SSL1 to SSL3 may be separate from each other, and ground select lines GSL1 to GSL3 may also be separate from each other. Figure 1 The illustration shows three string select lines SSL1 through SSL3 sharing a word line of the same height, but the inventive concept is not limited thereto. In some examples, two string select lines may share a word line of the same height. In other examples, four string select lines may share a word line of the same height.

[0041] Figure 2 This is a plan view illustrating a representative construction of a semiconductor device 100 according to some example embodiments. Figure 3 yes Figure 2 A schematic perspective view of part A1, Figure 4A and Figure 4B yes Figure 2 A magnified plan view of part A2. Figure 5 It is along Figure 2 The sectional view taken by line B1-B1'. Figure 6 It is along Figure 2 The sectional view taken by line B2-B2'. Figure 7 yes Figure 6 A magnified view of part of the CX1. Figures 2 to 4B For ease of explanation and understanding, only a portion of the components of the semiconductor device 100 are shown schematically.

[0042] Reference Figures 2 to 7The substrate 110 may include a memory cell region (MCR), a connection region (CON), and a peripheral circuit region (PERI). A memory cell array (MCA) may be disposed on the memory cell region (MCR), and the memory cell array (MCA) may include NAND memory devices with a vertical channel structure, the NAND memory devices being referenced... Figure 1 The described method is driven. A peripheral circuit transistor 190T for driving the memory cell array MCA can be disposed on the peripheral circuit region PERI. The peripheral circuit transistor 190T may include a peripheral circuit active region 192, a peripheral circuit gate electrode 194 disposed on the peripheral circuit active region 192, and a peripheral circuit contact 196 connected to the peripheral circuit active region 192 and the peripheral circuit gate electrode 194. The connection region CON may be a region in which a pad PAD is formed for connecting the memory cell array MCA disposed in the memory cell region MCR to the peripheral circuit transistor 190T.

[0043] The substrate 110 may include a main surface 110M extending in a first direction (X direction) and a second direction (Y direction). The substrate 110 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), and / or silicon-germanium. The substrate 110 may include a bulk wafer or an epitaxial layer. In some example embodiments, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0044] On the memory cell region (MCR) of substrate 110, a plurality of first insulating layers 120 and a plurality of gate electrodes 130 may be alternately arranged in a third direction (Z direction) perpendicular to the main surface 110M of substrate 110. For example, the first insulating layers 120 and gate electrodes 130 may be alternately and repeatedly arranged on substrate 110. A second insulating layer 122 may be disposed on the uppermost gate electrode 130.

[0045] The plurality of gate electrodes 130 may include a metal layer 130M and conductive barrier layers 130UB surrounding the top, bottom, and side surfaces of the metal layer 130M. The conductive barrier layers 130UB may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), and / or combinations thereof. The metal layer 130M may include at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), their silicides, and / or their alloys. In some example embodiments, each of the plurality of gate electrodes 130 may have a thickness of about 1 nm to about 30 nm, or about 1 nm to about 15 nm, or about 15 nm to about 30 nm, or about 15 nm in the third direction (Z direction). However, the thickness of each of the plurality of gate electrodes 130 is not limited thereto.

[0046] When the terms “about” or “basic” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around the value. When a range is specified, the range includes all values ​​between them (e.g., increasing in increments of 0.1%).

[0047] In some example embodiments, the plurality of gate electrodes 130 may correspond to constituting memory cell strings MCS11 to MCS33 (see Figure 1 The memory cells 130 have ground selection lines GSL1 to GSL3, word lines WL1 to WL8, and serial selection lines SSL1 to SSL3. For example, the lowermost gate electrode 130 can function as ground selection lines GSL1 to GSL3, the uppermost gate electrode 130 can function as serial selection lines SSL1 to SSL3, and the remaining gate electrodes 130 can function as word lines WL1 to WL8. In some embodiments, the gate electrode 130 directly below the uppermost gate electrode 130 or directly above the lowermost gate electrode 130 can function as a dummy word line. Therefore, a memory cell string MCS11 to MCS33 can be configured in which the ground selection transistor GST, the serial selection transistor SST, and the memory cells MCT1 to MCT8 located between the ground selection transistor GST and the serial selection transistor SST are connected in series.

[0048] Multiple channel structures C140 can extend from the main surface 110M of the substrate 110 along a third direction (Z direction) within the memory cell region MCR, simultaneously penetrating multiple gate electrodes 130. The multiple channel structures C140 can be spaced apart from each other at a desired (or, optionally, predetermined) interval in a first direction (X direction), a second direction (Y direction), and a fourth direction (e.g., diagonal direction). The multiple channel structures C140 can be arranged in a zigzag or staggered shape.

[0049] Each of the plurality of channel structures C140 can be disposed in a channel hole C140H that penetrates the plurality of gate electrodes 130, the plurality of first insulating layers 120 and the second insulating layer 122. The channel layer 142, the charge storage structure 144 and the body gate layer 146 can be sequentially disposed on the inner wall of the channel hole C140H.

[0050] The channel layer 142 may be conformally formed on the inner wall of the channel hole C140H, and the channel layer 142 may include a bottom portion 142L that contacts the substrate 110. The bottom portion 142L of the channel layer 142 (or the bottom surface C140L of the channel structure C140) may be disposed at a level lower than the level of the main surface 110M of the substrate 110. For example, the bottom portion of the channel hole C140H may be recessed from the main surface 110M of the substrate 110, the bottom portion 142L of the channel layer 142 may be disposed at the bottom portion of the channel hole C140H, and the bottom portion 142L of the channel layer 142 may contact the top surface of the substrate 110 disposed at the bottom portion of the channel hole C140H.

[0051] The charge storage structure 144 may have a structure comprising a tunnel dielectric layer 144A, a charge storage layer 144B, and a barrier dielectric layer 144C sequentially formed on the sidewall 142IS of the channel layer 142. That is, the channel layer 142, the tunnel dielectric layer 144A, the charge storage layer 144B, and the barrier dielectric layer 144C may be sequentially disposed on the inner wall of the channel hole C140H. The relative thicknesses of the tunnel dielectric layer 144A, the charge storage layer 144B, and the barrier dielectric layer 144C included in the charge storage structure 144 are not limited to... Figure 7 The ones shown can be modified in various ways.

[0052] In an example embodiment, the tunnel dielectric layer 144A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, and / or tantalum oxide, etc. The charge storage layer 144B may be a region in which electrons passing through the tunnel dielectric layer 144A from the channel layer 142 can be stored, and may include silicon nitride, boron nitride, boron silicon nitride, and / or doped polysilicon with impurities. The barrier dielectric layer 144C may include silicon oxide, silicon nitride, and / or a metal oxide having a dielectric constant higher than that of silicon oxide. This metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and / or combinations thereof.

[0053] The body gate layer 146 may fill the remaining space on the charge storage structure 144 of the channel via C140H. In an example embodiment, the body gate layer 146 may include, but is not limited to, a doped polysilicon layer. When memory cells MCT1 to MCT8 (see...) are executed... Figure 1During data write, read, or erase operations, data can be transmitted via body gate lines BGL1 to BGL3 (see...). Figure 1 The desired (or, optionally, predetermined) voltage (or signal) is applied to the body gate layer 146.

[0054] In an example embodiment, the body gate layer 146 may have a pillar shape extending in the third direction (Z direction) within the channel via C140H. The top surface of the body gate layer 146 may be disposed at the same level as the top surface of the second insulating layer 122, and the bottom surface of the body gate layer 146 may be disposed at a level lower than the bottom surface of the lowermost gate electrode 130. The sidewalls 146S and the bottom surface of the body gate layer 146 may contact the charge storage structure 144. For example, as Figure 7 As shown, the charge storage structure 144 may surround the sidewall 146S and bottom surface of the body gate layer 146, and the channel layer 142 may surround the outer wall 144S of the charge storage structure 144. The gate electrode 130 may surround the outer wall of the channel layer 142, and the inner wall 142IS of the channel layer 142 may contact the outer wall 144S of the charge storage structure 144.

[0055] A gate insulating layer 132 may be located between the gate electrode 130 and the channel structure C140. The gate insulating layer 132 may be located between the gate electrode 130 and the channel layer 142, and between the gate electrode 130 and the first insulating layer 120, and may cover the top surface 130U and the bottom surface 130L of the gate electrode 130. In an example embodiment, the gate insulating layer 132 may include, but is not limited to, silicon oxide.

[0056] Bit line pad 150 can be disposed on the channel structure C140, and the bit line pad 150 is electrically connected to the channel layer 142. For example, as Figure 4A As shown, bit line pad 150 may have an annular shape, and opening 150OP may be defined by the inner wall of bit line pad 150. Bit line pad 150 may not be vertically stacked with body gate layer 146, so bit line pad 150 may not be electrically connected to body gate layer 146. For example, in a plan view, the outer wall of bit line pad 150 may have an elliptical shape, and the inner wall of bit line pad 150 may have a circular shape. In a plan view, the inner wall of bit line pad 150 (e.g., the boundary of opening 150OP) may be arranged to surround the sidewall of body gate layer 146 at a desired (or optionally predetermined) interval, so that bit line pad 150 and body gate layer 146 may be spaced apart from each other. In some example embodiments, the outer wall of bit line pad 150 may have at least one of a rounded rectangular shape, a polygonal shape, a circular shape, and an elliptical shape, and the inner wall of bit line pad 150 may have at least one of a rounded rectangular shape, a polygonal shape, a circular shape, and an elliptical shape.

[0057] The third insulating layer 124 can be disposed on the second insulating layer 122. The third insulating layer 124 can surround the sidewall of the bit line pad 150 and can be disposed at the same vertical level as the bit line pad 150. The fourth insulating layer 126 can be disposed on the third insulating layer 124.

[0058] Multiple bit lines 164 may extend along a second direction (Y direction) on the fourth insulating layer 126. Bit line contacts 162 may be disposed in bit line contact holes 162H penetrating the fourth insulating layer 126, and the bit line contacts 162 may electrically connect the bit line pads 150 to the bit lines 164. Multiple body gate lines 168 may extend along the second direction (Y direction) on the fourth insulating layer 126. Body gate contacts 166 may be disposed in body gate contact holes 166H penetrating the fourth insulating layer 126 and the third insulating layer 124, and the body gate contacts 166 may electrically connect the body gate lines 168 to the body gate layer 146. A fifth insulating layer 128 may be disposed on the fourth insulating layer 126 to surround the sidewalls of the multiple bit lines 164 and the multiple body gate lines 168.

[0059] In example embodiments, such as Figure 4A As shown, bit line contacts 162 may be offset from or spaced from the center of the channel structure C140, for example, in a first direction (X direction). Bit line pads 150 may have a first width w11 in the first direction (X direction) and a second width w12 smaller than the first width w11 in a second direction (Y direction). Therefore, bit line contacts 162 may be disposed on bit line pads 150 (e.g., at a location far from the center of the channel structure C140), body gate contacts 166 may be disposed on body gate layer 146 (e.g., at a location closer to the center of the channel structure C140 than bit line contacts 162), and multiple body gate lines 168 may be disposed at the same level as multiple bit lines 164. Two side-by-side bit lines 164 may be arranged alternately and repeatedly with two side-by-side body gate lines 168.

[0060] In example embodiments, such as Figure 4A As shown, when two channel structures C140 can be disposed between the string isolation layer 184 and the word line dicing region WLC in the second direction (Y direction), the first bit line 164_1 and the first body gate line 168_1 connected to the first channel structure C140_1 (as one of the two channel structures C140), and the second bit line 164_2 and the second body gate line 168_2 connected to the second channel structure C140_2 (as the other of the two channel structures C140), can extend parallel to each other in the second direction (Y direction). Therefore, the first bit line 164_1, the first body gate line 168_1, the second body gate line 168_2, and the second bit line 164_2 can be sequentially disposed in the first direction (X direction).

[0061] In some example embodiments, such as Figure 4B As shown, the first bit line 164_1 and the first body gate line 168_1 connected to the first channel structure C140_1 (as one of two channel structures C140 arranged side by side in the second direction (Y direction)) and the second bit line 164_2 and the second body gate line 168_2 connected to the second channel structure C140_2 (as the other of two channel structures C140) can extend parallel to each other in the second direction (Y direction), wherein the first bit line 164_1, the second body gate line 168_2, the first body gate line 168_1 and the second bit line 164_2 can be arranged sequentially in the first direction (X direction). In this case, the separation distance between the first bit line contact 162 connected to the first bit line 164_1 and the first body gate contact 166 connected to the first body gate line 168_1 can be relatively large, thus increasing the process margin in the process for forming the bit line contact hole 162H and the body gate contact hole 166H.

[0062] In some other example embodiments, with Figure 4A and Figure 4B As shown in the diagram, the multiple body gate lines 168 can extend in a second direction (Y direction) at different vertical levels, respectively, along with the multiple bit lines 164.

[0063] like Figure 2 As shown, multiple word line cut regions (WLCs) can extend on the substrate 110 in a first direction (X direction) parallel to the main surface 110M of the substrate 110. Multiple gate electrodes 130 disposed between a pair of word line cut regions (WLCs) can form a block, and the pair of word line cut regions (WLCs) can define the width of the multiple gate electrodes 130 in a second direction (Y direction).

[0064] Multiple common source pole lines 180, vertically stacked with multiple word line cutting areas WLC, can be disposed on the substrate 110 in the first direction (X direction). Insulating spacers 182 can be disposed on two sidewalls of the multiple common source pole lines 180. Figure 6 The diagram shows multiple common source lines 180 having a bottom surface disposed at a level lower than the main surface 110M of the substrate 110, but in some example embodiments, the multiple common source lines 180 may have a bottom surface disposed at the same level as the main surface 110M of the substrate 110.

[0065] Multiple common-source regions 112 can be disposed in the substrate 110 below the common-source line 180 in a first direction (X direction). The multiple common-source regions 112 can be impurity regions highly doped with n-type impurities. The multiple common-source regions 112 can serve as source regions for supplying current to memory cells. The multiple common-source regions 112 can be disposed at a location superimposed on multiple word line cut regions (WLCs).

[0066] like Figure 2 As shown, in the block, the uppermost gate electrode 130 can be separated into two parts in a plan view by a series isolation layer 184. Although not shown, the series isolation layer 184 can extend from the same level as the top surface of the second insulating layer 122 to a level below the bottom surface of the uppermost gate electrode 130.

[0067] Multiple gate electrodes 130 may extend in the connection region CON to form a pad portion PAD. As the multiple gate electrodes 130 move away from the main surface 110M of the substrate 110, the multiple gate electrodes 130 may extend in a shorter length in a first direction (X direction). The pad portion PAD may refer to the stepped portion of the multiple gate electrodes 130. A second insulating layer 122 may be disposed on the multiple gate electrodes 130 constituting the pad portion PAD, and multiple pad contacts 172 may be disposed in the connection region CON, simultaneously penetrating the second insulating layer 122 and connecting to the multiple gate electrodes 130.

[0068] like Figure 5 As shown, multiple dummy channel structures D140 can be disposed in dummy channel holes D140H of multiple gate electrodes 130 penetrating the connection region CON, and the multiple dummy channel structures D140 can extend from the main surface 110M of the substrate 110 in the third direction (Z direction). The dummy channel structures D140 can be formed to ensure the structural stability of the semiconductor device 100 in the manufacturing process of the semiconductor device 100. Each of the multiple dummy channel structures D140 can have the same structure as the channel structure C140. Each of the multiple dummy channel structures D140 can have the same width as the channel structure C140, or can have a width larger than the channel structure C140.

[0069] Since data storage in semiconductor devices is typically performed by injecting charge into a charge storage structure via Fowler-Nordheim tunneling (FN tunneling), with the charge storage structure positioned between the gate electrode and the channel layer, the charge storage structure and the channel layer are formed sequentially in the channel via. However, as the vertical height of semiconductor devices increases, the difficulty of forming cell contact layers at the bottom portion of the channel via using selective epitaxial growth (SEG) to electrically connect the channel layer and the substrate, or the difficulty of etching the storage structure at the bottom portion of the channel via, increases significantly, limiting the increase in the vertical height of semiconductor devices.

[0070] However, according to the above example embodiment, the channel layer 142, the charge storage structure 144, and the body gate layer 146 can be sequentially formed in the channel via C140H, and data storage can be performed by injecting charge into the charge storage structure 144 by applying voltages to the gate electrode 130 and the body gate layer 146 separately and independently. That is, complex manufacturing processes such as forming the cell contact layer at the bottom portion of the channel via by selective epitaxial growth (SEG) or etching the memory structure at the bottom portion of the channel via can be eliminated. Therefore, the semiconductor device 100 can achieve an increase in vertical height or high integration density. Furthermore, as described below, applying a programming voltage through the body gate layer 146 can significantly reduce interference between word lines, thus improving the cell operation characteristics or electrical characteristics of the semiconductor device 100.

[0071] In the following text, reference will be made to Figures 8 to 12 Describe an example driving method for semiconductor device 100.

[0072] Figure 8 A timing diagram showing the programming voltage applied to a memory cell being programmed in an example programming operation of semiconductor device 100 is shown. Figure 9 This is a circuit diagram showing the voltages applied to the programming string, the inhibit string, and the body gate line during programming operations. Figure 10 It shows in Figure 9 A schematic performance diagram of the components included in the memory cell programmed in step 3. Figure 11 This is a circuit diagram illustrating the voltage applied to the string and body gate lines that perform the read in an example read operation of semiconductor device 100. Figure 12 This is a circuit diagram showing the voltage applied to the string and body gate lines that are being erased during an example erase operation of semiconductor device 100.

[0073] exist Figures 8 to 12 In the following section, the setting of a bit line BL1 (see example) will be described using examples. Figure 1 ), a body gate line BGL1 (see Figure 1 ) and a word line WL1 (see Figure 1 One memory cell MCT1 between ) (see Figure 1 Programming, reading, and erasing operations.

[0074] First refer to Figures 8 to 9 Example programming operations for semiconductor device 100 can be performed by sequentially including steps 1 to 3.

[0075] In step 1, a voltage of 0V can be applied via the bit lines connected thereto to the string STRpg (hereinafter referred to as the "programming string") which includes the memory cell MCPG to be programmed. A power supply voltage Vcc can be applied via the bit lines to the string STRin (hereinafter referred to as the "ban string") connected to the remaining bit lines except those connected to the programming string STRpg. A voltage Vpass can be applied to all word lines WL(Unsel) and WL(Sel) (i.e., both the unselected word line WL(Unsel) and the selected word line WL(Sel)). A voltage of 0V can be applied to the body gate line BGpg (hereinafter referred to as the "programming body gate line") adjacent to the memory cell MCPG to be programmed. During step 1, electrons can be charged into the channel of the programming string STRpg.

[0076] In step 2, while a voltage Vpass is applied to the selected word line WL(Sel), a voltage of 0V can be applied to the unselected word line WL(Unsel) and the programmer gate line BGpg. During step 2, electrons can accumulate in the channel of the selected word line WL(Sel).

[0077] In step 3, a programming voltage Vpgm can be applied to the programming body gate line BGpg, and a voltage of 0V can be applied to the selected word line WL (Sel). Furthermore, the unselected word line WL (Unsel) and the bit lines connected to the programming string STRpg can be floated. In the example embodiment, the programming voltage Vpgm can have a higher value than the pass voltage Vpass. In step 3, as... Figure 10 As exemplarily illustrated, electrons can tunnel from the channel layer 142 of a memory cell MCPG formed by a selected word line WL(Sel) (e.g., a selected gate electrode 130) toward the body gate layer 146, and electrons can be injected into the charge storage structure 144 (e.g., charge storage layer 144B) between the channel layer 142 and the body gate layer 146. In some example embodiments, the programming voltage Vpgm may have a lower value than the programming voltage applied to the selected word line in a conventional semiconductor device, but is not limited thereto.

[0078] Reference Figure 11 Example read operations of semiconductor device 100 can be performed on a page-by-page basis. For example, a scan voltage Vsweep can be applied to the selected word line WL(Sel) of the string STRread to which a read operation will be performed, and a read voltage Vread can be applied to the unselected word line WL(Unsel), and a voltage of 0V can be applied to the body gate line BGread to which a read operation will be performed, thus enabling the read operation. In this case, a string select voltage Vssl and a ground select voltage Vgsl can be applied to the string select line SSL and ground select line GSL of the string STRread to which a read operation will be performed.

[0079] Reference Figure 12 Example erase operations of semiconductor device 100 can be performed on a block-by-block basis. For example, an erase voltage Vers can be applied to the well region PPW of the string STRers to which the erase operation will be performed, and a voltage of 0V can be applied to the body gate line BGers to which the erase operation will be performed. Thus, the erase operation of memory cell blocks can be performed by making all word lines WL float.

[0080] According to the above example embodiment, the semiconductor device 100 can sequentially apply a programming voltage Vpgm to the programming body gate line BGpg via steps 1 to 3, particularly during step 3, thus enabling the programming operation of the memory cell MCPG. In conventional semiconductor devices, programming operations are performed by applying a programming voltage to a selected word line and a pass voltage to an unselected word line. In this case, a voltage with a relatively large voltage difference is applied between adjacent word lines with a relatively small spacing, and cell operation failures may occur due to interference between adjacent word lines. However, according to the example embodiment, since a relatively low voltage (e.g., a pass voltage) can be applied to the word lines compared to the programming voltage applied to the body gate line, interference between word lines can be significantly reduced, and therefore the semiconductor device 100 can have improved cell operation characteristics or improved electrical characteristics.

[0081] Figure 13 This is a cross-sectional view showing a semiconductor device 100A according to an example embodiment. Figure 14 yes Figure 13 An enlarged sectional view of part of CX2. Figure 13 and Figure 14 In, with Figures 1 to 12 The same reference numerals in the figures indicate similar components.

[0082] Reference Figure 13 and Figure 14The channel structure C140A may further include a conductive barrier layer 148 between the charge storage structure 144 and the body gate layer 146. Therefore, the sidewalls 146S of the body gate layer 146 may be surrounded by the conductive barrier layer 148.

[0083] In an example embodiment, the body gate layer 146 may include at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), their silicides, and / or alloys thereof. The conductive barrier layer 148 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), and / or combinations thereof. Optionally, a high-k insulating layer (not shown) may be further formed between the conductive barrier layer 148 and the charge storage structure 144.

[0084] Figure 15 This is a cross-sectional view showing a semiconductor device 100B according to an example embodiment. Figure 16 yes Figure 15 An enlarged sectional view of part of CX3. Figure 15 and Figure 16 In, with Figures 1 to 14 The same reference numerals in the figures indicate similar components.

[0085] Reference Figure 15 and Figure 16 The gate insulating layer 132B may be located between the sidewall C140S of the channel structure C140B and the gate electrode 130B, and the gate insulating layer 132B may not be located between the gate electrode 130B and the first insulating layer 120. The top surface 130U and the bottom surface 130L of the gate electrode 130B may contact the first insulating layer 120, and the first insulating layer 120 may contact the sidewall C140S of the channel structure C140B (e.g., the outer wall of the channel layer 142).

[0086] In an example embodiment, the gate insulating layer 132B may include a thermal oxide layer formed by a thermal oxidation process. For example, after removing the sacrificial layer 310 (see... Figure 31 After forming the gate space 130GS, a gate insulating layer 132B can be formed on the sidewall of the channel layer 142 exposed to the gate space 130GS by performing a thermal oxidation process, but is not limited thereto.

[0087] Figure 17 This is a cross-sectional view showing a semiconductor device 100C according to an example embodiment. Figure 18 yes Figure 17 An enlarged sectional view of part of CX4. Figure 17 and Figure 18 In, with Figures 1 to 16 The same reference numerals in the figures indicate similar components.

[0088] Reference Figure 17 and Figure 18 The bottom portion of the channel structure C140C may be surrounded by a first semiconductor layer 174 and a second semiconductor layer 176. The first semiconductor layer 174 may comprise doped or undoped polysilicon, and the second semiconductor layer 176 may also comprise doped or undoped polysilicon. The first semiconductor layer 174 may serve as a common-source extension region and may be... Figure 1 The portion corresponding to the common source line CSL. The second semiconductor layer 176 can be used as a support layer to prevent the die stack from collapsing or falling off during the process of removing the sacrificial layer used to form the first semiconductor layer 174.

[0089] The channel structure C140C can penetrate the first semiconductor layer 174 and the second semiconductor layer 176 and can extend to a level below the main surface 110M of the substrate 110. The gate insulating layer 132C can be disposed on the inner wall of the channel via C140H and can be configured to surround the entire sidewall C140S and the entire bottom surface of the channel structure C140C, except for the portion of the sidewall C140S of the channel structure C140C surrounded by the first semiconductor layer 174. Therefore, the gate insulating layer 132C can be located between the channel layer 142 and the gate electrode 130B, and between the channel layer 142 and the first insulating layer 120, and the top surface 130U and bottom surface 130L of the gate electrode 130B can also contact the first insulating layer 120.

[0090] Figure 19 This is a cross-sectional view illustrating a semiconductor device 100D according to some example embodiments. Figure 19 In, with Figures 1 to 18 The same reference numerals in the figures indicate the same components.

[0091] Reference Figure 19 The body gate layer 146 may have an upper surface disposed at a level lower than the upper surface of the second insulating layer 122, and a sixth insulating layer 129 may be disposed on the body gate layer 146, the sixth insulating layer 129 filling the upper entrance of the channel via C140H, and the body gate contact 166 may penetrate the fourth insulating layer 126, the third insulating layer 124, and the sixth insulating layer 129 to connect to the body gate layer 146. For example, since the upper surface of the body gate layer 146 may be disposed at a level lower than the upper surface of the second insulating layer 122, undesirable electrical connections or short circuits between the bit line pad 150 and the body gate layer 146 can be reduced or prevented even when misalignment occurs in the patterning process for the bit line pad 150.

[0092] Figure 20 This is a cross-sectional view showing a semiconductor device 200 according to some example embodiments. Figure 20In, with Figures 1 to 19 The same reference numerals in the figures indicate the same components.

[0093] Reference Figure 20 The lower substrate 210 can be disposed at a vertical level lower than that of the substrate 110. An active region (not shown) can be defined within the lower substrate 210 by a device isolation layer 222, and a plurality of driving transistors 230T can be formed on the active region. The plurality of driving transistors 230T may include a driving circuit gate structure 232 and an impurity region 212, the impurity region 212 being disposed on the portions of the lower substrate 210 below and on both sides of the driving circuit gate structure 232.

[0094] Multiple interconnect layers 242, multiple contact plugs 246 connecting the multiple interconnect layers 242 to each other or connecting the multiple interconnect layers 242 to the driving transistor 230T, and a lower interlayer insulating layer 250 covering the multiple interconnect layers 242 and the multiple contact plugs 246 can be disposed on the lower substrate 210.

[0095] The substrate 110 may be disposed on the lower interlayer insulating layer 250. Multiple first insulating layers 120, multiple gate electrodes 130, channel structure C140, bit line 164 (see...) Figure 5 The body gate line 168 can be disposed on the substrate 110.

[0096] Figures 21 to 30 This is a schematic diagram illustrating a method of manufacturing a semiconductor device 100 according to some example embodiments, arranged in process sequence. Specifically, Figures 21 to 30 Is along Figure 2 The cross-section corresponding to the section cut by line B2-B2'. Figures 21 to 30 In, with Figures 1 to 20 The same reference numerals used in the figures indicate the same components.

[0097] Reference Figure 21 Multiple first insulating layers 120 and multiple sacrificial layers 310 may be alternately formed on the main surface 110M of the substrate 110. In an example embodiment, the multiple first insulating layers 120 may include insulating materials such as silicon oxide or silicon oxynitride, and the multiple sacrificial layers 310 may include silicon nitride, silicon oxynitride, or doped polysilicon with impurities.

[0098] Subsequently, although not shown, the connection region CON (see [reference]) can be patterned sequentially by patterning a plurality of first insulating layers 120 and a plurality of sacrificial layers 310. Figure 2 The padding PAD is formed in the middle (see Figure 2 In some example embodiments, the pad PAD can be formed as a stepped shape with a top surface level difference in a first direction (X direction).

[0099] Subsequently, the second insulating layer 122 can be formed to cover the uppermost sacrificial layer 310 and the pad PAD. The second insulating layer 122 may include insulating materials such as silicon oxide and silicon oxynitride.

[0100] Reference Figure 22 A mask pattern (not shown) can be formed on the second insulating layer 122, and then a portion of the second insulating layer 122, a portion of a plurality of first insulating layers 120, and a portion of a plurality of sacrificial layers 310 can be etched using the mask pattern as an etching mask to form a channel hole C140H. The channel hole C140H can extend to a level below the main surface 110M of the substrate 110.

[0101] Reference Figure 23 A channel layer 142, a tunnel dielectric layer 144A, a charge storage layer 144B, a barrier dielectric layer 144C, and a body gate layer 146 can be sequentially formed on the inner wall of the channel via C140H. Subsequently, a planarization process can be performed to remove portions of the channel layer 142, tunnel dielectric layer 144A, charge storage layer 144B, barrier dielectric layer 144C, and body gate layer 146 formed on the second insulating layer 122. Here, the tunnel dielectric layer 144A, charge storage layer 144B, and barrier dielectric layer 144C can be referred to as the charge storage structure 144. As a result of the planarization process, the body gate layer 146 can have a top surface configured to be substantially coplanar with the top surfaces of the charge storage structure 144, the channel layer 142, and the second insulating layer 122.

[0102] In the example embodiment, the bottom surface of the channel layer 142 can contact the top surface of the substrate 110 exposed at the bottom of the channel hole C140H. Therefore, complex manufacturing processes such as SEG processes, which are traditionally required, are not necessary, and the manufacturing process for forming the channel structure C140 can be relatively simple.

[0103] Reference Figure 24 A mask pattern (not shown) can be formed on the second insulating layer 122 and the channel structure C140, and a word line dicing opening 180H can be formed by removing the sacrificial layer 310 and the first insulating layer 120 using the mask pattern as an etching mask. The upper surface of the substrate 110 can be exposed at the bottom portion of the word line dicing opening 180H.

[0104] Reference Figure 25 This can remove multiple sacrificial layers 310 exposed by the word line cutting opening 180H (see...). Figure 24 This forms multiple gate spaces 130GS. The sidewalls of the channel layer 142 can be exposed in the gate spaces 130GS. In an example embodiment, the removal of the multiple sacrificial layers 310 can be performed by a wet etching process using a phosphoric acid solution as an etchant.

[0105] Reference Figure 26 A gate insulating layer 132 and a preliminary gate electrode layer 130P can be formed on the inner walls of the word line dicing opening 180H and multiple gate spaces 130GS. To form the preliminary gate electrode layer 130P, a conductive barrier layer 130UB (see...) can be formed sequentially. Figure 7 ) and metal layer 130M (see Figure 7 ).

[0106] Reference Figure 27 The portions of the gate insulating layer 132 and the preliminary gate electrode layer 130P disposed on the second insulating layer 122 and the inner wall of the word line cutting opening 180H can be removed, so that the gate insulating layer 132 and the gate electrode 130 can be formed in the gate space 130GS.

[0107] Subsequently, impurities can be injected into the substrate 110, which is once again exposed to the bottom portion of the word line cutout 180H, thereby forming a common source region 112 in the portion of the substrate 110 disposed on the bottom portion of the word line cutout 180H. Afterward, an insulating spacer 182 can be formed on the sidewall of the word line cutout 180H, and a common source line 180 can be formed on the insulating spacer 182 while simultaneously filling the interior of the word line cutout 180H.

[0108] Reference Figure 28 A conductive layer (not shown) can be formed on the channel structure C140 and the second insulating layer 122, and then the bit line pad 150 can be formed by patterning the conductive layer. The bit line pad 150 can be formed with, for example, Figure 4A The bit line pad 150 is annular in shape as shown, and its inner wall can surround the body gate layer 146 while being spaced apart from the body gate layer 146 by a desired (or, optionally predetermined) interval. Since the bit line pad 150 can be formed by patterning the conductive layer, the thickness of the second insulating layer 122 can be relatively thin compared to a semiconductor device according to a comparative example in which bit line pads are formed in a channel via C140H.

[0109] Reference Figure 29 A third insulating layer 124 can be formed on the bit line pad 150 and the second insulating layer 122. The top surface of the third insulating layer 124 can then be planarized until the top surface of the bit line pad 150 is exposed. Thereafter, a fourth insulating layer 126 can be formed to cover the third insulating layer 124 and the top surface of the bit line pad 150. In some example embodiments, when the third insulating layer 124 can have a top surface disposed at a level higher than the top surface of the bit line pad 150, the planarization of the third insulating layer 124 can be omitted, in which case the fourth insulating layer 126 may not be formed.

[0110] Subsequently, bit line contact holes 162H can be formed that penetrate the third insulating layer 124 and the fourth insulating layer 126 (see...). Figure 5 The bit line contact 162H and the body gate contact 166H are then filled with conductive material to form bit line contact 162 and body gate contact 166, respectively.

[0111] Reference Figure 30 Bit lines 164 and body gate lines 168, respectively connected to bit line contacts 162 and body gate contacts 166, can be formed on the fourth insulating layer 126.

[0112] Semiconductor device 100 can be manufactured by performing the above process.

[0113] In the semiconductor device according to the comparative example, a charge storage structure 144 (i.e., a barrier dielectric layer 144C, a charge storage layer 144B, and a tunnel dielectric layer 144A) is first formed in the channel hole C140H. Then, a portion of the charge storage structure 144 located at the bottom of the channel hole C140H is removed, and an anisotropic etching process or an etch-back process is then performed to expose the top surface of the substrate 110. Subsequently, a channel layer 142 is formed on the inner wall of the channel hole C140H. However, as the vertical height of the semiconductor device 100 increases, the aspect ratio of the channel hole C140H also increases, significantly increasing the difficulty of the anisotropic etching process or etch-back process regarding the bottom portion of the channel hole C140H. When the top surface of the substrate 110 is not sufficiently exposed at some of the bottom portions of the channel hole C140H (when the bottom portion of the charge storage structure 144 is partially removed), the electrical properties of the channel structure C140 formed in the channel hole C140H may not be excellent.

[0114] Furthermore, in the semiconductor device according to the comparative example, in order to obtain a low contact resistance between the channel structure C140 and the substrate 110, a semiconductor layer can be grown from the top surface of the substrate 110 exposed to the bottom portion of the channel via C140H to form a cell contact via a selective epitaxial growth (SEG) process. However, it may be difficult to grow a semiconductor layer with a uniform height via the SEG process; therefore, multiple channel structures C140 are likely to have non-uniform electrical characteristics.

[0115] However, according to the method for manufacturing the semiconductor device 100 according to the exemplary embodiment, the complex manufacturing process described above can be omitted by directly forming the channel layer 142 on the inner wall of the channel hole C140H. Furthermore, the difficulty of forming the bit line pads 150 can be reduced. Therefore, the semiconductor device 100 according to the exemplary embodiment can advantageously increase its height in the vertical direction and improve its integration level.

[0116] Figures 31 to 32 This is a schematic diagram illustrating a method for manufacturing a semiconductor device 100B according to some example embodiments, in the order of process steps.

[0117] First, it can be done by executing the reference. Figures 21 to 25 The process described is used to form word line cutouts 180H and multiple gate spaces 130GS.

[0118] Reference Figure 31 A gate insulating layer 132B can be formed on the surface of the channel layer 142 exposed to multiple gate spaces 130GS.

[0119] In an example embodiment, the process for forming the gate insulating layer 132B can be a thermal oxidation process, and the surface portion of the channel layer 142 can be converted to silicon oxide through a thermal oxidation process, thus forming the gate insulating layer 132B. Meanwhile, the gate insulating layer 132B may not be formed on the top and bottom surfaces of the first insulating layer 120 exposed to the gate space 130GS. For example, the gate insulating layer 132B may include a thermal oxide layer formed in a thermal oxidation process, and may include silicon oxide.

[0120] Reference Figure 32 A preliminary gate electrode layer 130P can be formed on the inner wall of multiple gate spaces 130GS and word line dicing openings 180H.

[0121] Afterwards, it can be done by executing the reference. Figures 27 to 30 The described process is used to manufacture semiconductor device 100B.

[0122] Figures 33 to 38 This is a schematic diagram illustrating a method for manufacturing a semiconductor device 100C according to some example embodiments, arranged in process sequence. Figures 33 to 35 Is along Figure 2 The sectional view corresponding to the section intercepted by line B2-B2'. Figures 36 to 38 Is with Figure 35 Enlarged sectional view of part of CX5.

[0123] Reference Figure 33 A first insulating layer 120 can be formed on the main surface 110M of the substrate 110. Then, a lower sacrificial layer 320 and a second semiconductor layer 176 can be sequentially formed on the first insulating layer 120. Then, a plurality of first insulating layers 120 and a plurality of sacrificial layers 310 can be alternately formed on the second semiconductor layer 176. The lower sacrificial layer 320 may include silicon nitride or silicon oxynitride, and the second semiconductor layer 176 may include doped polysilicon or undoped polysilicon.

[0124] Subsequently, portions of multiple sacrificial layers 310, multiple first insulating layers 120, a portion of the second semiconductor layer 176, and a portion of the lower sacrificial layer 320 can be etched to form a channel via C140H. A gate insulating layer 132C, a channel layer 142, a tunnel dielectric layer 144A, a charge storage layer 144B, a barrier dielectric layer 144C, and a body gate layer 146 can be sequentially formed in the channel via C140H. Then, portions of the channel layer 142, tunnel dielectric layer 144A, charge storage layer 144B, barrier dielectric layer 144C, and body gate layer 146 formed on the second insulating layer 122 can be removed by performing a planarization process. Thus, a channel structure C140C can be formed.

[0125] Reference Figure 34 A portion of a plurality of sacrificial layers 310, a portion of a plurality of first insulating layers 120, a portion of a second semiconductor layer 176, and a portion of a lower sacrificial layer 320 may be etched to form a word line dicing opening 180H, and then a cover insulating layer 330 may be formed covering the sidewalls of the word line dicing opening 180H. In an example embodiment, the cover insulating layer 330 may cover all sidewalls of the plurality of sacrificial layers 310 exposed by the word line dicing opening 180H and may expose the sidewalls of the lower sacrificial layer 320. For example, the cover insulating layer 330 may be formed using a material with poor step coverage characteristics, so that the cover insulating layer 330 may not be formed on the lower portion of the word line dicing opening 180H and the top surface of the substrate 110.

[0126] Reference Figure 35 and Figure 36 The lower sacrificial layer 320 exposed to the lower portion of the letter line cutting opening 180H can be removed (see...). Figure 34 Then, a lower opening 174H can be formed at the location where the lower sacrificial layer 320 has been removed. The sidewalls of the gate insulating layer 132C can be exposed through the lower opening 174H. In an example embodiment, the removal of the lower sacrificial layer 320 can be performed by a wet etching process using a phosphoric acid solution as an etchant.

[0127] Reference Figure 37 The portion of the gate insulating layer 132C exposed by the lower opening 174H can be removed to expose the sidewalls of the channel layer 142. The removal of the gate insulating layer 132C can be performed using a wet etching process. In the wet etching process, the portion of the gate insulating layer 132C between the channel layer 142 and the second semiconductor layer 176 can be exposed by the lower opening 174H and removed together, as can the portion of the gate insulating layer 132C between the channel layer 142 and the lowermost first insulating layer 120. However, the inventive concept is not limited to this.

[0128] Reference Figure 38 It is possible to cut an opening of 180H in the letter line (see...) Figure 35 The first semiconductor layer 174 is filled in the lower opening 174H between the bottommost first insulating layer 120 and the second semiconductor layer 176. The first semiconductor layer 174 can fill the interior of the lower opening 174H between the bottommost first insulating layer 120 and the second semiconductor layer 176, and can contact the sidewall C140S of the channel structure C140C.

[0129] Subsequently, the portion of the first semiconductor layer 174 formed on the inner wall of the word line dicing opening 180H can be removed by an etch-back process, and the top surface of the substrate 110 can be exposed again to the bottom portion of the word line dicing opening 180H.

[0130] Subsequently, the multiple sacrificial layers 310 exposed by the word line cutting opening 180H can be removed (see...). Figure 24 Multiple gate spaces 130GS are formed at locations where multiple sacrificial layers 310 can be removed, and then a preliminary gate electrode layer 130P can be formed on the inner walls of the multiple gate spaces 130GS.

[0131] After that, it can be done by executing the reference. Figures 27 to 30 The described process is used to manufacture semiconductor device 100C.

[0132] As described above, exemplary embodiments have been disclosed in the accompanying drawings and specification. Although specific terminology has been used to describe the exemplary embodiments herein, they are for the purpose of illustrating the inventive concept of this disclosure only and are not intended to limit the scope of the inventive concept as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent exemplary embodiments are possible based on the exemplary embodiments. Consequently, the true technical scope of this disclosure will be defined by the inventive concept of the appended claims.

[0133] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A channel structure is located on a substrate and extends along a first direction perpendicular to the top surface of the substrate, the channel structure comprising: a body gate layer extending along the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding a sidewall of the charge storage structure. Multiple gate electrodes are located on a substrate and spaced apart from each other along a first direction on the sidewalls of the channel structure; and A gate insulating layer is located between each of the plurality of gate electrodes and the channel structure. The channel layer is located on the inner wall of the channel hole that penetrates the plurality of gate electrodes and extends along the first direction. The charge storage structure is conformally formed on the channel layer along the inner wall of the channel hole.

2. The semiconductor device according to claim 1, wherein, The charge storage structure is located between the body gate layer and the channel layer.

3. The semiconductor device according to claim 1, wherein, The body gate layer is filled in the channel hole located on the charge storage structure.

4. The semiconductor device according to claim 1, wherein, The charge storage structure includes: A barrier dielectric layer is located on the sidewall of the body gate layer. A charge storage layer, located on top of a barrier dielectric layer, and The tunnel dielectric layer is located on the charge storage layer and contacts the channel layer.

5. The semiconductor device according to claim 1, wherein, The channel layer includes a bottom portion that contacts the top surface of the substrate, and The entire bottom surface of the charge storage structure is covered by the channel layer, so that the bottom surface of the charge storage structure does not contact the substrate.

6. The semiconductor device according to claim 1, further comprising: Multiple insulating layers, each insulating layer being located between two adjacent gate electrodes among the multiple gate electrodes. The gate insulating layer covers the top and bottom surfaces of each of the plurality of gate electrodes, and The multiple insulating layers contact the sidewalls of the channel structure.

7. The semiconductor device according to claim 1, further comprising: Multiple insulating layers, each insulating layer being located between two adjacent gate electrodes among the multiple gate electrodes. The gate insulating layer is located only between each of the plurality of gate electrodes and the channel structure, and The multiple insulating layers contact the sidewalls of the channel structure.

8. The semiconductor device according to claim 1, further comprising: Multiple insulating layers, each insulating layer being located between two adjacent gate electrodes among the multiple gate electrodes. Wherein, the gate insulating layer extends along the entire length of the sidewall of the channel structure in a first direction, and The multiple insulating layers do not contact the sidewalls of the channel structure.

9. The semiconductor device according to claim 1, further comprising: Bit line pads are positioned at a level higher than the level of the uppermost gate electrode among the plurality of gate electrodes, and the bit line pads are located on the channel layer, wherein the inner wall of the bit line pads defines an opening; Bit line contact, connected to bit line pad; and A body gate contact passes through the opening and is connected to the body gate layer.

10. The semiconductor device according to claim 9, wherein, The opening is vertically stacked with the body gate layer in the plan view, and The inner wall of the bit line pad surrounds the body gate layer.

11. The semiconductor device according to claim 9, further comprising: The bit line is connected to the bit line contact and extends in a second direction parallel to the top surface of the substrate; as well as A body gate line is connected to a body gate contact, the body gate line extending along a second direction.

12. The semiconductor device according to claim 1, wherein, The top surface of the body gate layer is at the same level as the top surface of the channel layer.

13. The semiconductor device according to claim 1, wherein, The top surface of the body gate layer is at a lower level than the top surface of the channel layer.

14. The semiconductor device according to claim 1, further comprising: A conductive barrier layer is located between the body gate layer and the charge storage structure.

15. A semiconductor device, the semiconductor device comprising: Multiple gate electrodes are located on a substrate and spaced apart from each other along a first direction perpendicular to the top surface of the substrate; A channel structure is located in a channel aperture penetrating the plurality of gate electrodes and extending along a first direction, the channel structure comprising: a channel layer located on the inner wall of the channel aperture; and a charge storage structure located on the channel layer on the inner wall of the channel aperture; and A gate insulating layer is located between each of the plurality of gate electrodes and the channel layer, and the gate insulating layer covers the top and bottom surfaces of each of the plurality of gate electrodes. The channel layer is located between each of the plurality of gate electrodes and the charge storage structure.

16. The semiconductor device according to claim 15, wherein, The channel structure also includes a body gate layer that fills the interior of the channel apertures on the charge storage structure.

17. The semiconductor device of claim 16, further comprising: Bit line pads are positioned at a level higher than the uppermost gate electrode among the plurality of gate electrodes and are located on the channel layer, wherein the inner wall of the bit line pad defines an opening; Bit line contact, connected to bit line pad; and A body gate contact passes through the opening and is connected to the body gate layer.

18. The semiconductor device of claim 17, further comprising: The bit line is connected to the bit line contact and extends in a second direction parallel to the top surface of the substrate; as well as A body gate line is connected to a body gate contact, the body gate line extending along a second direction.

19. The semiconductor device according to claim 16, wherein, The charge storage structure is located between the bulk gate layer and the channel layer. The channel layer includes a bottom portion that contacts the top surface of the substrate, and The entire bottom surface of the charge storage structure is covered by the channel layer, so that the bottom surface of the charge storage structure does not contact the substrate.

20. A semiconductor device, the semiconductor device comprising: A channel structure is located on a substrate and extends along a first direction perpendicular to the top surface of the substrate, the channel structure comprising: a body gate layer extending along the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding a sidewall of the charge storage structure. Multiple gate electrodes are located on a substrate and spaced apart from each other along a first direction on the sidewalls of the channel structure; A gate insulating layer is located between each of the plurality of gate electrodes and the channel structure; Bit line pads are formed at a level higher than that of the uppermost gate electrode among the plurality of gate electrodes and are located on the channel layer; Bit line contact, connected to bit line pad; and The bit line connects to the bit line contact and extends along a second direction parallel to the top surface of the substrate. The channel layer is located on the inner wall of the channel hole that penetrates the plurality of gate electrodes and extends along the first direction. The charge storage structure is conformally formed on the channel layer along the inner wall of the channel hole.

21. The semiconductor device according to claim 20, wherein, The inner wall of the bit line pad defines an opening, and the semiconductor device further includes: A body gate contact, passing through the opening and connected to the body gate layer; and A body gate line is connected to a body gate contact, the body gate line extending along a second direction.

22. The semiconductor device according to claim 20, wherein, The body gate layer comprises polysilicon or metal.

23. The semiconductor device of claim 20, further comprising: A conductive barrier layer is located between the body gate layer and the charge storage structure.

24. The semiconductor device of claim 20, further comprising: Multiple insulating layers, each insulating layer being located between two adjacent gate electrodes among the multiple gate electrodes. The gate insulating layer is located only between each of the plurality of gate electrodes and the channel structure, and The gate insulating layer includes a thermal oxide layer.

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