Image sensor, semiconductor structure for image sensor and manufacturing method thereof

Abstract

Various embodiments of the present disclosure relate to an image sensor including a charge release layer. A photodetector is disposed within a semiconductor substrate. An etch stop layer overlies the photodetector. A color filter overlies the etch stop layer. A dielectric grid structure surrounds the color filter. The charge release layer is sandwiched between the dielectric grid structure and the etch stop layer. The charge release layer surrounds the color filter and includes a conductive material. The charge release layer directly contacts the color filter.

Description

Technical Field

[0001] Embodiments of the present invention relate to an image sensor, a semiconductor structure for the image sensor, and a method for manufacturing the same. Background Art

[0002] Integrated Circuits (ICs) with image sensors are used in a wide variety of modern electronic devices, such as cameras and cell phones. Complementary metal-oxide semiconductor (CMOS) devices have become popular IC image sensors. Compared with charge-coupled devices (CCDs), CMOS image sensors are becoming increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Summary of the invention

[0003] Some embodiments of the present application provide an image sensor, comprising: a semiconductor substrate; a photodetector disposed within the semiconductor substrate; an etch stop layer overlying the photodetector; a color filter overlying the etch stop layer; a dielectric grid structure surrounding the color filter; and a charge release layer sandwiched between the dielectric grid structure and the etch stop layer, wherein the charge release layer surrounds the color filter and comprises a conductive material, and wherein the charge release layer directly contacts the color filter.

[0004] In addition, other embodiments of the present application provide a semiconductor structure for an image sensor, comprising: an integrated circuit, comprising a carrier substrate, a semiconductor substrate and an interconnect structure, wherein the interconnect structure is arranged between the semiconductor substrate and the carrier substrate, and wherein the photodetector is arranged in the semiconductor substrate; a dielectric grid structure, overlying the semiconductor substrate; color filters, recessed into the dielectric grid structure and respectively overlying the photodetectors, wherein the color filters have a refractive index greater than that of the dielectric grid structure; and a charge release layer, arranged between the dielectric grid structure and the semiconductor substrate, wherein the charge release layer laterally surrounds the color filter, wherein the top surface of the charge release layer is located above the top surface of the semiconductor substrate and the bottom surface of the charge release layer is located vertically between the interconnect structure and the top surface of the semiconductor substrate.

[0005] In addition, other embodiments of the present application provide a method for manufacturing a semiconductor structure for an image sensor, the method comprising: forming a photodetector in a semiconductor substrate; forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure has a conductive wiring layer; etching the semiconductor substrate to define a first opening in the semiconductor substrate; depositing an etch stop layer and a charge release layer on the semiconductor substrate and the interconnect structure, wherein the charge release layer overlies the etch stop layer, and wherein the charge release layer and the etch stop layer line at least a portion of the first opening; forming a conductive contact in the first opening, wherein the conductive contact extends through the charge release layer and the semiconductor substrate to contact the conductive wiring layer; depositing a grid dielectric layer on the photodetector; etching the grid dielectric layer and the charge release layer until reaching the upper surface of the etch stop layer, wherein etching the grid dielectric layer defines a dielectric grid structure and a plurality of color filter openings overlying the photodetector; and depositing a plurality of color filters in the plurality of color filter openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the embodiments of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of image sensors including a charge release layer disposed around a color filter are shown.

[0008] Figure 1B As shown by Figure 1A and Figure 1B The cutting line in Figure 1A A top view of some embodiments of an image sensor.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D Cross-sectional views of some embodiments of image sensors including a charge release layer disposed around a plurality of color filters are shown.

[0010] Figure 3A As shown by Figure 2A The dotted line in Figure 2A Top view of some alternative embodiments of a charge release layer.

[0011] Figure 3B and Figure 3C As shown by Figure 2A The dashed box in the Figure 2AA cross-sectional view of an alternative embodiment of a portion of an image sensor.

[0012] Figure 3D As shown by Figure 2D The dashed box in the Figure 2D A cross-sectional view of an alternative embodiment of a portion of an image sensor.

[0013] Figure 3E As shown by Figure 2A The dashed box in the Figure 2A A cross-sectional view of an alternative embodiment of a portion of an image sensor.

[0014] Figures 4 to 15 A series of cross-sectional views illustrating some embodiments of methods for forming an image sensor including a charge release layer disposed around a plurality of color filters.

[0015] Fig.16 Show Figures 4 to 15 Block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0016] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the embodiments of the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] The image sensor includes an array of photodetectors. Some image sensors include a semiconductor substrate, in which photodetectors are arranged, and a pixel device structure is arranged below the semiconductor substrate. The pixel device structure includes an internal connection structure and a pixel device (e.g., a source follower transistor, a reset transistor, a charge release transistor, etc.) disposed on the front surface of the semiconductor substrate. The pixel device can be electrically coupled to the photodetector through the internal connection structure. The color filter and the dielectric grid structure are respectively disposed on the back surface of the semiconductor substrate and overlying the photodetector. The dielectric grid structure surrounds the color filter in the lateral direction. The dielectric grid structure increases sensitivity (e.g., quantum efficiency (QE)) and reduces cross-talk through total internal reflection (total internal reflection) of the dielectric grid structure. However, depending on how the dielectric grid structure is formed, the dielectric grid structure can also reduce the quality of black images and / or dark images generated from the image sensor.

[0019] In some embodiments, the dielectric grid structure may be formed by performing an etching process (e.g., a dry etching process) in one or more dielectric layers overlying the photodetector. This exposes an upper surface of the etch stop layer and defines a plurality of color filter openings overlying the photodetector. A deposition process is performed to deposit color filters in the plurality of color filter openings over the upper surface of the etch stop layer. However, after performing the etching process, charge carriers (e.g., electrons) may be trapped in the dielectric grid structure. This may be caused in part by the etching process and / or the deposition process. The trapped charge carriers remain in the dielectric grid structure and may reduce the reliability and / or accuracy of the image generated from the image sensor. For example, if the image generated from the image sensor is considered a black image and / or a dark image, the trapped charge carriers may cause gray to appear in the black image and / or the dark image. In addition, the trapped charge carriers may increase the dark current and / or the number of white pixels in the image sensor. Furthermore, ultraviolet (UV) curing processes cannot remove trapped charge carriers from the dielectric grid structure.

[0020] In some alternative embodiments, the present application is directed to a dielectric grid structure that prevents trapped charge carriers from accumulating in the dielectric grid structure. For example, to remove trapped charge carriers in an image sensor, a charge release layer may be located below the dielectric grid structure. The charge release layer is formed between the dielectric grid structure and an etch stop layer. An etching process is performed on the dielectric grid structure and the charge release layer until an upper surface of the etch stop layer is exposed, thereby defining a plurality of color filter openings. A deposition process is performed to deposit color filters in the plurality of color filter openings, such that the charge release layer and the dielectric grid structure laterally surround the color filters. During and / or after the deposition process is performed, charge carriers (e.g., electrons) that may be trapped in the dielectric grid structure are released by the charge release layer. For example, the charge release layer may be electrically coupled to ground, thereby allowing charge carriers to travel from the dielectric grid structure to ground. This may, in part, increase the reliability and / or accuracy of images generated from the image sensor, remove gray from dark images (e.g., black images) generated from the image sensor, reduce dark current in the image sensor, and / or reduce the number of white pixels in the image sensor.

[0021] Reference Figure 1A , a cross-sectional view of some embodiments of image sensor 100 including charge release layer 112 surrounding color filter 116 is provided.

[0022] A photodetector 104 is disposed within the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 includes any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, silicon-germanium (SeGe), silicon on insulator (SOI), etc.) and / or has a first doping type (e.g., p-type doping). The photodetector 104 is configured to convert electromagnetic radiation 118 (e.g., photons) into an electrical signal. For example, the photodetector 104 may generate electron-hole pairs from the electromagnetic radiation 118. The photodetector 104 includes a second doping type (e.g., n-type doping) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. A stacked dielectric layer 108 is overlaid on the backside surface 102bs of the semiconductor substrate 102. The stacked dielectric layer 108 may include one or more oxide layers and is configured to protect the backside surface 102bs of the semiconductor substrate 102.

[0023] Overlying the stacked dielectric layer 108 is an etch stop layer 110 and overlying the etch stop layer 110 is a charge release layer 112. Overlying the charge release layer 112 is a dielectric grid structure 114. The charge release layer 112 may include a conductive material, such as titanium nitride. The dielectric grid structure 114 and the charge release layer 112 surround the color filter 116. The dielectric grid structure 114 is a dielectric material having a refractive index less than that of the color filter 116. Due to the lower refractive index, the dielectric grid structure 114 acts as a radiation guide to guide the electromagnetic radiation 118 to the corresponding photodetector 104. For example, electromagnetic radiation 118 within the color filter 116 that is incident on the boundary between the color filter 116 and the dielectric grid structure 114 will typically undergo total internal reflection. Thus, the dielectric grid structure 114 is configured to increase the sensitivity (e.g., quantum efficiency (QE)) of the image sensor 100 while reducing crosstalk between adjacent photodetectors. In addition, the color filter 116 is configured to block electromagnetic radiation 118 of a first frequency range while passing electromagnetic radiation 118 of a second frequency range to the underlying photodetector 104.

[0024] During formation of the image sensor 100, one or more etching processes may be performed on the dielectric grid structure 114 to define openings for the color filters 116. During the one or more etching processes, charge carriers 111 (e.g., electrons) may accumulate and / or become trapped in the dielectric grid structure 114. The trapped charge carriers 111 may reduce the reliability and / or accuracy of an image generated from the image sensor 100. Therefore, the charge release layer 112 is electrically coupled to the ground 106, such that the charge carriers 111 travel from the dielectric grid structure 114 to the ground 106 through the charge release layer 112. Therefore, the charge release layer 112 is configured to facilitate removal of the accumulated charge carriers 111 from the dielectric grid structure 114 and / or other adjacent structures / layers (e.g., the etch stop layer 110 and / or the stacked dielectric layer 108). By removing the charge carriers 111, the reliability and accuracy of the image generated from the image sensor 100 may be increased, dark current in the image sensor 100 may be reduced, and / or the number of white pixels in the image sensor 100 may be reduced. In yet other embodiments, the charge release layer 112 is directly electrically coupled to a charge release circuit (e.g., including a microcontroller) (not shown) configured to remove the trapped charge carriers 111 from the dielectric grid structure 114.

[0025] Reference Figure 1B ,supply Figure 1A A top view of some embodiments of image sensor 100 .

[0026] The charge release layer 112 encloses the outer perimeter of the color filter 116. When viewed from above, the color filter 116 may have, for example, a square shape, a rectangular shape, a circular shape, or an elliptical shape. In some embodiments, the charge release layer 112 directly contacts the outer perimeter of the color filter 116. The photodetectors 104 are spaced apart laterally between the inner sidewalls of the charge release layer 112.

[0027] Reference Figure 2A , provides a cross-sectional view of some embodiments of an image sensor 200a that includes a dielectric grid structure 114 laterally offset from a bonding structure 224 (referred to as a ground pad or ground terminal in some embodiments).

[0028] A semiconductor substrate 102 is overlaid on the carrier substrate 202. In some embodiments, the semiconductor substrate 102 and / or the carrier substrate 202 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. A plurality of photodetectors 104 are disposed in the semiconductor substrate 102. In some embodiments, the photodetectors 104 extend from a backside surface 102bs of the semiconductor substrate 102 to a point below the backside surface 102bs, respectively. In some further embodiments, the point is located at a frontside surface 102fs of the semiconductor substrate 102 opposite to the backside surface 102bs of the semiconductor substrate 102. An interconnect structure 205 is disposed along the frontside surface 102fs of the semiconductor substrate 102. The interconnect structure 205 includes an interconnect dielectric structure 204, a plurality of conductive wires 206, and a plurality of conductive vias 208. The semiconductor substrate 102 is coupled to the carrier substrate 202 through the interconnect structure 205. In some embodiments, the conductive wire 206 and / or the conductive via 208 may be or include, for example, aluminum, copper, aluminum copper, tungsten, etc. In some embodiments, the interconnect structure 205 may include, for example, one or more dielectric layers (eg, silicon dioxide).

[0029] A stacked dielectric layer 108 is overlaid on the backside surface 102bs of the semiconductor substrate 102. In some embodiments, the stacked dielectric layer 108 includes one or more dielectric layers, such as a first dielectric layer 108a, a second dielectric layer 108b, and a third dielectric layer 108c. In some embodiments, the first dielectric layer 108a may be, for example, or include oxide, metal oxide, aluminum oxide, etc., and / or may have a thickness of 40 angstroms or in a range of about 30 angstroms to about 50 angstroms. In some embodiments, the second dielectric layer 108b may be, for example, or include oxide, metal oxide, hafnium oxide, etc., and / or may have a thickness of 60 angstroms or in a range of about 50 angstroms to about 70 angstroms. In some other embodiments, the third dielectric layer 108c may be, for example, or include oxide, metal oxide, tantalum oxide, etc., and / or may have a thickness of 520 angstroms or in a range of about 470 angstroms to about 570 angstroms. The stacked dielectric layer 108 may be configured to protect the backside surface 102bs of the semiconductor substrate 102. A first insulating layer 209 (e.g., silicon dioxide) overlies the stacked dielectric layer 108. In some embodiments, the first insulating layer 209 extends over the backside surface 102bs of the semiconductor substrate 102 to the sidewalls of the semiconductor substrate 102. The bottom surface of the first insulating layer 209 may extend below the frontside surface 102fs of the semiconductor substrate 102 into the interconnect dielectric structure 204.

[0030] An etch stop layer 110 is overlaid on the first insulating layer 209. In some embodiments, the etch stop layer 110 may be, for example, or include a nitride (e.g., silicon nitride (Si3N4)), a carbide (e.g., silicon carbide), etc., and / or may have a thickness of 1500 angstroms or in a range of about 1000 angstroms to about 1500 angstroms. The etch stop layer 110 extends over the upper surface of the first insulating layer 209 to a point between the front side surface 102fs and the back side surface 102bs of the semiconductor substrate 102. A charge release layer 112 is overlaid on the etch stop layer 110, and the charge release layer 112 extends from over the semiconductor substrate 102 to a point between the front side surface 102fs and the back side surface 102bs of the semiconductor substrate 102. In some embodiments, the charge release layer 112 may be, for example, or include a conductive material, such as titanium nitride, tantalum nitride, titanium, etc. A second insulating layer 210 is overlaid on the charge release layer 112, and the second insulating layer 210 may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. A first conductive contact 218 (in some embodiments, referred to as a ground contact) is overlaid on the upper wiring layer 206a of the plurality of conductive wires 206. In some embodiments, the first conductive contact 218 extends through the semiconductor substrate 102 over the front side surface 102fs of the semiconductor substrate 102 to contact the upper wiring layer 206a. A second conductive contact 220 is overlaid on the upper wiring layer 206a, and the second conductive contact 220 extends through the semiconductor substrate 102 to reach the upper wiring layer 206a. In some other embodiments, the first conductive contact 218 and / or the second conductive contact 220 may be, for example, or include aluminum, copper, aluminum copper, tungsten, tantalum nitride, etc. In some embodiments, the first conductive contact 218 and / or the second conductive contact 220 may include the same material as the plurality of conductive wires 206 and / or the plurality of conductive vias 208. In still other embodiments, the first conductive contact 218 and the second conductive contact 220 include a different material than the charge release layer 112. In alternative embodiments, the first conductive contact 218 is laterally offset from and / or electrically isolated from the second conductive contact 220. In still other embodiments, a wafer acceptance test (WAT) is performed at the second conductive contact 220, in which a wafer prober (not shown) sends an electrical test signal to a device (e.g., a pixel transistor) (not shown) disposed on and / or within the semiconductor substrate 102. For example, the electrical test signal checks the functionality of the above-mentioned devices and identifies devices that do not meet design specifications.

[0031] The first insulating layer 209 may be configured to electrically isolate the semiconductor substrate 102 from the conductive layer extending through the semiconductor substrate 102 to the interconnect structure 205. Therefore, devices (e.g., the photodetector 104) disposed within, above, and / or below the semiconductor substrate 102 are electrically isolated from the conductive layer (e.g., the charge release layer 112, the first conductive contact 218, and / or the second conductive contact 220) extending through the backside surface 102bs of the semiconductor substrate 102.

[0032] A dielectric metal protection layer 212 is overlaid on the first conductive contact 218 and the second conductive contact 220. A first grid dielectric layer 214 is overlaid on the dielectric metal protection layer 212. A second grid dielectric layer 216 is overlaid on the first grid dielectric layer 214. The first grid dielectric layer 214 may be, for example, or include an oxide, such as silicon dioxide, and / or may have a thickness of 5600 angstroms or in a range of about 5400 angstroms to about 5800 angstroms. The second grid dielectric layer 216 may be, for example, or include silicon-oxy-nitride, etc., and / or may have a thickness of 1500 angstroms or in a range of about 1300 angstroms to about 1700 angstroms. A bonding structure 224 is overlaid on the first conductive contact 218, and the bonding structure 224 is configured to electrically couple the first conductive contact 218 to another integrated circuit (IC) (not shown) or some other external device. In some embodiments, the bonding structure 224 is electrically coupled to ground. In some embodiments, the bonding structure 224 includes a bonding pad 226 that contacts the first conductive contact 218. In addition, a solder bump 228 may be overlaid on the bonding pad 226. In some further embodiments, a bonding wire (not shown) is electrically coupled to the bonding pad 226 through the solder bump 228, wherein the bonding wire directly contacts the solder bump 228. In some further embodiments, a photoresist 242 is overlaid on the first conductive contact 218, and the photoresist 242 may be, for example, a blue photoresist configured to electrically couple the bonding structure 224 to an alignment region of another IC. In such an embodiment, an alignment mark (not shown) may be located below the photoresist 242.

[0033] The dielectric grid structure 114 is laterally offset from the bonding structure 224. The dielectric grid structure 114 includes a section of the first grid dielectric layer 214 and a section of the second grid dielectric layer 216 in the region 222. The region 222 is laterally offset from the first conductive contact 218 and overlies the photodetectors 104. The dielectric grid structure 114 is laterally located around and between the photodetectors 104 to define a plurality of color filter openings. A plurality of color filters 116 are arranged within the plurality of color filter openings and overlie the corresponding plurality of photodetectors 104. The charge release layer 112 is disposed between the dielectric grid structure 114 and the etch stop layer 110 such that the charge release layer 112 is laterally located around and between the photodetectors 104. The color filter 116 extends from the upper surface of the dielectric grid structure 114 to the upper surface of the etch stop layer 110 through the first and second grid dielectric layers 214, 216 and the charge release layer 112. Therefore, in some embodiments, the charge release layer 112 is discontinuous directly above each photodetector 104 and surrounds the color filter 116 in the lateral direction.

[0034] The charge release layer 112 extends above the upper surface of the etch stop layer 110 to the sidewall 218sw of the first conductive contact 218. In some embodiments, the sidewall of the charge release layer 112 disposed between the front side surface 102fs and the back side surface 102bs directly contacts the sidewall 218sw of the first conductive contact 218. In yet other embodiments, the first conductive contact 218 is electrically coupled to ground (e.g., through the bonding structure 224), so that the charge release layer 112 can remove the accumulated trapped charge carriers (e.g., electrons) in the dielectric grid structure 114 to ground. This can, in part, increase the reliability and / or accuracy of the image generated from the image sensor 200a.

[0035] In some embodiments, the charge release layer 112 has a first thickness t1 and a second thickness t2. The first thickness t1 is defined between the dielectric grid structure 114 and the upper surface of the etch stop layer 110 within the region 222. The second thickness t2 is defined between the upper surface of the etch stop layer 110 outside the region 222 and the lower surface of the second insulating layer 210. In some other embodiments, the first thickness t1 is less than the second thickness t2, or the first thickness t1 is approximately equal to the second thickness t2. In some embodiments, the first thickness t1 is less than the second thickness t2 because an over etch process is performed on the charge release layer 112 during the formation of the dielectric grid structure 114. The second thickness t2 may be, for example, in the range of about 500 angstroms to about 1,000 angstroms. In some embodiments, if the second thickness t2 is less than 500 angstroms, the charge release layer 112 may be removed in the region 222 during the over etch process, thereby reducing the reliability and / or accuracy of the image generated from the image sensor 200a. In such an embodiment, the ability of the charge release layer 112 to remove trapped charge carriers from the dielectric grid structure 114 may be reduced and / or eliminated. In yet other embodiments, if the second thickness t2 is greater than 1,000 angstroms, the time and cost associated with forming the image sensor 200a may be increased. In some embodiments, the bottom surface of the charge release layer 112 is vertically above the upper surface 218us ​​of the first conductive contact 218.

[0036] Reference Figure 2B , provide the basis Figure 1A and Figure 1B FIG. 2 is a cross-sectional view of an image sensor 200 b of some alternative embodiments of image sensor 100 .

[0037] like Figure 2B As shown in FIG. 1 , an isolation structure 230 is disposed in the semiconductor substrate 102. The first conductive contact 218 and the second conductive contact 220 extend through the isolation structure 230 to contact the upper wiring layer 206a. In some embodiments, the isolation structure 230 may be a dielectric material (e.g., silicon dioxide) and / or may be configured as a shallow trench isolation (STI) structure. The bottom surface of the first insulating layer 209 contacts the upper surface of the isolation structure 230. In some other embodiments, the bottom surface of the isolation structure 230 contacts the upper surface of the interconnect dielectric structure 204. The isolation structure 230 is configured to further increase the electrical isolation between the conductive layer and / or structure (e.g., the first conductive contact 218 and the second conductive contact 220 and / or the charge release layer 112) extending through the backside surface 102bs of the semiconductor substrate 102 and the device (e.g., the photodetector 104) disposed in and / or on the semiconductor substrate 102.

[0038] Reference Figure 2C , provide the basis Figure 1A and Figure 1B FIG. 2 is a cross-sectional view of an image sensor 200 c of some alternative embodiments of image sensor 100 .

[0039] like Figure 2C As shown in FIG. 2 , a plurality of microlenses 232 are disposed over the dielectric grid structure 114 in the region 222. The microlenses 232 overlie the corresponding photodetectors 104, respectively, and are configured to focus electromagnetic radiation (e.g., photons) toward the corresponding photodetectors 104, respectively. In addition, the sidewall 218sw of the first conductive contact 218 extending through the semiconductor substrate 102 is substantially straight. For example, the sidewall 218sw may be disposed along a substantially vertical line orthogonal to the front side surface 102fs of the semiconductor substrate 102. In some embodiments, the sidewall of the charge release layer 112 and / or the sidewall of the etch stop layer 110 directly contacts the sidewall 218sw.

[0040] Reference Figure 2D , provide the basis Figure 1A and Figure 1B FIG. 2 is a cross-sectional view of an image sensor 200 d of some alternative embodiments of image sensor 100 .

[0041] like Figure 2D As shown in , a plurality of semiconductor devices 240 may be disposed on and / or within the front side surface 102fs of the semiconductor substrate 102. The plurality of semiconductor devices 240 are electrically coupled to the conductive wiring 206 and the conductive vias 208. In some embodiments, the semiconductor devices 240 may be, for example, metal-oxide semiconductor field-effect transistors (MOSFETs). In such embodiments, the semiconductor devices 240 may correspond to pixel devices, such as source follower transistors, reset transistors, charge release transistors, and the like.

[0042] although Figure 2A , Figure 2B and Figure 2C The semiconductor substrate 102 is shown without the semiconductor device 240 disposed on the front side surface 102fs, however, it should be understood that Figure 2A , Figure 2B and Figure 2C The image sensor is not limited to this configuration. Instead, in an alternative embodiment, Figure 2A , Figure 2B and Figure 2C The image sensor can be configured to Figure 2DFor example, the semiconductor device 240 may be disposed in a Figure 2A , Figure 2B and Figure 2C On the front side surface 102fs of the semiconductor substrate 102.

[0043] Reference Figure 3A , provide the basis Figure 2A The dotted line Figure 2A A top view 300a of some embodiments of region 222.

[0044] like Figure 3A As shown in , the plurality of photodetectors 104 are arranged in an array including rows and columns. In addition, the color filters 116 are arranged in an array including rows and columns and are respectively located above the photodetectors 104. In some embodiments, when viewed from above, the color filters 116 respectively have a rectangular shape / square shape and / or a circular shape / elliptical shape (not shown). The charge release layer 112 surrounds the outer periphery of each color filter 116 in the lateral direction, wherein the charge release layer 112 has an inner sidewall corresponding to the shape of each color filter 116. In some embodiments, the charge release layer 112 directly contacts the outer sidewall of each color filter 116. In addition, the dielectric grid structure ( Figure 2A 114) directly overlies the charge release layer 112, and when viewed from above, the dielectric grid structure has the same shape and / or layout as the charge release layer 112 (not shown).

[0045] Reference Figure 3B , provide the basis Figure 2A The dashed box in Figure 2A A cross-sectional view of some embodiments of a portion of an image sensor 200a.

[0046] like Figure 3B As shown in , the charge release layer 112 extends along the upper surface of the etch stop layer 110 and contacts the sidewall 218sw of the first conductive contact 218. The charge release layer 112 includes a vertical segment overlying the horizontal segment, wherein the sidewall of the horizontal segment contacts the sidewall 218sw. In some embodiments, the vertical segment of the charge release layer 112 is separated from the first conductive contact 218 by the second insulating layer 210.

[0047] Reference Figure 3C , provide the basis Figure 2A The dashed box in Figure 2A Cross-sectional views of some alternative embodiments of a portion of image sensor 200a.

[0048] like Figure 3CAs shown in , the first conductive contact 218 includes a conductive body 218a surrounded by a conductive pad 218b. In some embodiments, the conductive body 218a includes a first material, and the conductive pad 218b includes a second material different from the first material. In some embodiments, the first material may be, for example, or include aluminum, copper, aluminum copper, etc., and / or the second material may be, for example, or include tantalum nitride, etc. In some embodiments, the charge release layer 112 includes the same material as the conductive pad 218b (e.g., tantalum nitride). In some other embodiments, the charge release layer 112 directly contacts the conductive pad 218b and is electrically coupled to the conductive body 218a through the conductive pad 218b.

[0049] Reference Figure 3D , provide the basis Figure 2D The dashed box in Figure 2D Cross-sectional views of some alternative embodiments of a portion of image sensor 200d.

[0050] like Figure 3D As shown in , the bonding structure 224 may be laterally offset from the sidewalls of the first conductive contact 218, the sidewalls of the dielectric metal cap layer 212, and / or the sidewalls of the first grid dielectric layer 214. In addition, the upper surface of the bonding structure 224 may be located below the top surface of the first conductive contact 218 in the vertical direction.

[0051] Reference Figure 3E , provide the basis Figure 2A The dashed box in Figure 2A Cross-sectional views of some alternative embodiments of region 222 of image sensor 200a. Figure 3E As shown in FIG. 2 , the charge release layer 112 is disposed between the dielectric grid structure 114 and the etch stop layer 110. In some embodiments, the charge release layer 112 and / or the dielectric grid structure 114 in the region 222 each include: Fig. 14B The side wall profile shown and / or described in .

[0052] Figures 4 to 15 Cross-sectional views 400 to 1500 illustrate some embodiments of methods of forming an image sensor including a charge release layer according to aspects of embodiments of the present disclosure. Figures 4 to 15 400 to 1500 shown in FIG. 1 , however, it should be understood that Figures 4 to 15 The structures shown in are not limited to the methods described, but can be independently separated from the methods described. Figures 4 to 15 It is described as a series of actions, however, it should be understood that these actions are not limited to the order of actions that can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted in whole or in part. In some embodiments, for example, Figures 4 to 15 To form Figure 2C Image sensor 200c.

[0053] like Figure 4 As shown in the cross-sectional view 400 of , a semiconductor substrate 102 is provided and is bonded to a carrier substrate 202 via an interconnect structure 205. Before performing the bonding process, the substrate 102 is rotated 180 degrees, wherein the front side surface 102fs of the semiconductor substrate 102 is located above the back side surface 102bs of the semiconductor substrate 102. An isolation structure 230 is formed on the front side surface 102fs of the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon on insulator (SOI) substrate, or some other suitable substrate. In some embodiments, before forming the isolation structure 230, an implant process is performed to dope the semiconductor substrate 102 with a first doping type (e.g., p-type). In some embodiments, the process for forming the isolation structure 230 may include: 1) selectively etching the semiconductor substrate 102 to form a trench in the semiconductor substrate 102 extending from the front side surface 102fs of the semiconductor substrate 102 into the semiconductor substrate 102; and 2) filling the trench with a dielectric material (e.g., silicon dioxide) (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.). A plurality of photodetectors 104 are formed in the semiconductor substrate 102. The photodetectors 104 are regions of the semiconductor substrate 102 that include a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the photodetectors 104 may be formed by a selective ion implantation process that selectively implants ions into the semiconductor substrate 102 using a masking layer (not shown) on the front side surface 102fs of the semiconductor substrate 102.

[0054] Figure 4As also shown in the cross-sectional view 400 of FIG. 4 , an interconnect structure 205 is formed on the front side surface 102fs of the semiconductor substrate 102. The interconnect structure 205 includes an interconnect dielectric structure 204, a plurality of conductive wires 206, and a plurality of conductive vias 208. In some embodiments, the interconnect dielectric structure 204 may be or may include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may be, for example, or include an oxide (e.g., silicon dioxide) or another suitable oxide. In some embodiments, the process for forming the interconnect structure 205 includes forming the conductive vias 208 and the conductive wires 206 by a single damascene process or a double damascene process. For example, the first layer of the conductive vias 208 and the first layer of the conductive wires 206 may be formed by a single damascene process, respectively. In addition, the process includes forming the remaining layers of the conductive wires 206 and the conductive vias 208 by repeatedly performing the double damascene process.

[0055] In some embodiments, the single damascene process includes: 1) depositing a dielectric layer; 2) patterning the dielectric layer to have an opening for a single-layer conductive feature (e.g., a layer of vias or wiring); and 3) filling the opening with a conductive material (e.g., aluminum, copper, aluminum copper, etc.) to form a single-layer conductive feature. The dielectric layer may, for example, correspond to the one or more ILD layers in the interconnect dielectric structure 204. In some embodiments, the dual damascene process includes: 1) depositing a dielectric layer; 2) patterning the dielectric layer to have an opening for two-layer conductive features (e.g., a layer of vias and a layer of wiring); and 3) filling the opening with a conductive material (e.g., aluminum, copper, aluminum copper, etc.) to form the two-layer conductive features. In some embodiments, after filling the opening with the conductive material, a planarization process (e.g., chemical-mechanical polishing (CMP)) may be performed on the conductive material until reaching the upper surface of the dielectric layer. In some embodiments, the conductive wiring 206 and / or the conductive via 208 may, for example, be or include aluminum, copper, aluminum copper, etc., respectively.

[0056] In addition, if Figure 4As shown in the cross-sectional view 400 of , the semiconductor substrate 102 is oriented so that the front side surface 102fs is located below the back side surface 102bs, and the interconnect structure 205 is bonded to the carrier substrate 202. In some embodiments, the bonding process may be, for example, a fusion bonding process or another suitable bonding process. A stacked dielectric layer 108 may be formed on the back side surface 102bs of the semiconductor substrate 102. The back side surface 102bs is opposite to the front side surface 102fs. In some embodiments, the stacked dielectric layer 108 includes a first dielectric layer 108a, a second dielectric layer 108b, and a third dielectric layer 108c. In some embodiments, the first dielectric layer 108a, the second dielectric layer 108b, and / or the third dielectric layer 108c may be formed by CVD, PVD, ALD, thermal oxidation, or another suitable deposition process. In some other embodiments, the first dielectric layer 108a, the second dielectric layer 108b, and the third dielectric layer 108c may each include a dielectric material different from each other. For example, the first dielectric layer 108a may include aluminum oxide, the second dielectric layer 108b may include hafnium oxide, and the third dielectric layer 108c may include tantalum oxide.

[0057] like Figure 5 As shown in the cross-sectional view 500 of , a first etching process is performed on the stacked dielectric layer 108 and the semiconductor substrate 102 to define a first opening 502. The first etching process exposes the upper surface of the isolation structure 230. In some embodiments, the first etching process includes: 1) forming a masking layer (not shown) on the stacked dielectric layer 108; 2) exposing the unmasked area of ​​the stacked dielectric layer 108 and the semiconductor substrate 102 to one or more etchants; and 3) performing a removal process to remove the masking layer. In some embodiments, the first etching process may include a wet etching process, a dry etching process, or another suitable etching process.

[0058] like Figure 6 As shown in the cross-sectional view 600 of FIG. 1 , a first insulating layer 209 is formed on the stacked dielectric layer 108, and the first opening ( Figure 5502) is used for padding. An etch stop layer 110 is formed on the upper surface of the first insulating layer 209. A charge release layer 112 is formed on the upper surface of the etch stop layer 110, and a second insulating layer 210 is formed on the upper surface of the charge release layer 112. In some embodiments, the first insulating layer 209 and the second insulating layer 210, the etch stop layer 110 and / or the charge release layer 112 can be formed by CVD, PVD, ALD, or another suitable deposition process, respectively. In some embodiments, the charge release layer 112 can be, for example, or include a conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, etc. In some embodiments, the charge release layer 112 can be formed to have a second thickness t2, and the second thickness t2 can be, for example, in the range of about 500 angstroms to about 1,000 angstroms.

[0059] like Figure 7 As shown in the cross-sectional view 700 of Figure 6 The second etching process is performed on the structure of the conductive wiring 206 to define the contact opening 702. The second etching process exposes the upper surface of the upper wiring layer 206a of the plurality of conductive wirings 206. In some embodiments, the second etching process includes: 1) forming a shielding layer (not shown) on the second insulating layer 210; 2) exposing the unshielded area of ​​the second insulating layer 210 and the corresponding underlying layer to one or more etchants until reaching the upper surface of the upper wiring layer 206a; and 3) performing a removal process to remove the shielding layer. In some embodiments, the second etching process may include a wet etching process, a dry etching process, or another suitable etching process.

[0060] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a conductive contact layer 802 is formed on the upper surface of the second insulating layer 210, and the conductive contact layer 802 at least partially fills the contact opening ( Figure 7 702). In some embodiments, the conductive contact layer 802 may be, for example, aluminum, copper, aluminum copper, tantalum nitride, etc. In some embodiments, the conductive contact layer 802 may include a conductive pad (not shown) overlying the conductive pad (e.g., Figure 3C 218a and 218b), wherein the conductive body is separated from the second insulating layer 210 by a conductive liner. In some other embodiments, the conductive contact layer 802 can be formed, for example, by PVD, CVD, electroless plating, sputtering, electroplating, or another suitable deposition process. In some other embodiments, the conductive contact layer 802 is formed in a manner that the charge release layer 112 directly contacts the conductive contact layer 802 and / or is electrically coupled to the conductive contact layer 802.

[0061] like Fig. 9 As shown in the cross-sectional view 900 of FIG. Figure 8802) to perform a third etching process to define the first conductive contact 218 and the second conductive contact 220. In some embodiments, the third etching process is performed in a manner that the first conductive contact 218 is separated from the second conductive contact 220 by a non-zero distance in the lateral direction, wherein the first conductive contact 218 and the second conductive contact 220 do not contact each other. In some embodiments, the third etching process includes: 1) in the conductive contact layer ( Figure 8 1) forming a shielding layer (not shown) on the conductive contact layer ( Figure 8 802) exposing the unshielded area of ​​the second insulating layer 210 to one or more etchants; and 3) performing a removal process to remove the shielding layer. In some embodiments, the third etching process may include performing a wet etching process, a dry etching process, or another suitable etching process. In some other embodiments, the third etching process may over-etch a portion of the second insulating layer 210 and remove a portion of the second insulating layer 210, such as Fig. 9 As shown by the dotted line 902 in FIG.

[0062] like Fig.10 As shown in the cross-sectional view 1000 of , a dielectric metal protection layer 212 is formed over the first conductive contact 218 and the second conductive contact 220 and the second insulating layer 210. In some embodiments, the dielectric metal protection layer 212 is configured to protect the top surface of the first conductive contact 218 and the top surface of the second conductive contact 220 during subsequent processing steps.

[0063] like Fig.11 As shown in the cross-sectional view 1100 of Fig.10 The structure of the present invention performs a fourth etching process to remove the dielectric metal protection layer 212 and the second insulating layer 210 from the first region 1102 and the second region 1104. The first region 1102 overlies the plurality of photodetectors 104, and the second region 1104 is laterally located between the first conductive contact 218 and the second conductive contact 220. In some embodiments, the fourth etching process includes: 1) forming a shielding layer (not shown) over the dielectric metal protection layer 212; 2) exposing the unshielded region of the dielectric metal protection layer 212 and the second insulating layer 210 to one or more etchants; and 3) performing a removal process to remove the shielding layer. In some embodiments, the fourth etching process may include performing wet etching, dry etching, or another suitable etching process. Furthermore, in some embodiments, the fourth etching process may over-etch and remove a portion of the charge release layer 112 in the first region 1102 and the second region 1104, wherein the charge release layer 112 has a first thickness t1 in the first region 1102 and the second region 1104. In some embodiments, the first thickness t1 is less than the second thickness t2.

[0064] like Fig.12 As shown in the cross-sectional view 1200 of , a fifth etching process is performed on the charge release layer 112 in the second region 1104, thereby electrically isolating the first conductive contact 218 from the second conductive contact 220. In some embodiments, the fifth etching process includes: 1) forming a shielding layer (not shown) on the charge release layer 112 and the dielectric metal protection layer 212; 2) exposing the unshielded area of ​​the charge release layer 112 to one or more etchants until the upper surface of the etch stop layer 110 is reached; and 3) performing a removal process to remove the shielding layer. In some embodiments, the fifth etching process may include performing wet etching, dry etching, or another suitable etching process. In some other embodiments, the fifth etching process completely removes the charge release layer 112 from the second region 1104.

[0065] like Fig.13 As shown in the cross-sectional view 1300, Fig.12 A first grid dielectric layer 214 is formed on the structure. A second grid dielectric layer 216 is formed on the first grid dielectric layer 214. In some embodiments, the first grid dielectric layer 214 includes a first dielectric material (e.g., silicon dioxide), and the second grid dielectric layer 216 includes a second dielectric material different from the first dielectric material (e.g., silicon oxynitride). In some embodiments, the first grid dielectric layer 214 and / or the second grid dielectric layer 216 can be formed by CVD, PVD, ALD, or another suitable deposition process.

[0066] like Fig.14A As shown in the cross-sectional view 1400a of , a sixth etching process is performed on the first and second grid dielectric layers 214, 216, and the charge release layer 112. This defines a plurality of color filter openings 1402 above the photodetector 104 and a photoresist opening 1404 above the first conductive contact 218. The sixth etching process stops on the etch stop layer 110, so that the etch stop layer 110 becomes an etching stop for the sixth etching process. In some embodiments, the sixth etching process includes: 1) forming a shielding layer (not shown) above the second grid dielectric layer 216; 2) exposing the unshielded areas of the first and second grid dielectric layers 214, 216, and the charge release layer 112 to one or more etchants; and 3) performing a removal process to remove the shielding layer. In some embodiments, the sixth etching process may include performing wet etching, dry etching, or another suitable etching process. In some embodiments, the sixth etching process removes a portion of the charge release layer 112 overlying each photodetector 104, thereby exposing the upper surface of the etch stop layer 110. Therefore, in such an embodiment, the charge release layer 112 has a thickness of Figure 3A The layout described and shown in the top view 300a of .

[0067] In addition, the sixth etching process defines a dielectric grid structure 114 in a region 222 overlying the photodetector 104. In the region 222, the dielectric grid structure 114 includes a segment of the first grid dielectric layer 214 and a segment of the second grid dielectric layer 216. In some embodiments, the sixth etching process may include performing dry etching and / or plasma etching that may deposit charge carriers 111 (e.g., electrons) in the dielectric grid structure 114.

[0068] Fig. 14B Show Fig.14A 1400b is a cross-sectional view of some alternative embodiments of a close-up of region 222. In some embodiments, Fig. 14B The region 222 is shown after the sixth etching process is performed. In this embodiment, for ease of illustration, the charge carriers ( Fig.14A 111).

[0069] The dielectric grid structure 114 and the charge release layer 112 may each have an inclined sidewall defining the color filter opening 1402. In some embodiments, an angle α is defined between the sidewall of the charge release layer 112 and the substantially straight line 1406. The substantially straight line 1406 may be perpendicular to the bottom surface of the charge release layer 112 and / or the top surface of the etch stop layer 110. In addition, the substantially straight line 1406 is adjacent to the sidewall of the charge release layer 112. In some embodiments, the angle α may be, for example, in a range of about 1 degree to about 5 degrees. In yet other embodiments, a grid structure angle may be defined between the sidewall of the dielectric grid structure 114 and a substantially straight line adjacent to the dielectric grid structure 114. The grid structure angle may be in a range of 1 degree to 15 degrees.

[0070] In some embodiments, the lower surface 114ls of the dielectric grid structure 114 has a first width w1, and the upper surface 114us of the dielectric grid structure 114 has a second width w2. In some embodiments, the first width w1 is in a range of about 250 nanometers to about 490 nanometers. In some other embodiments, the second width w2 is in a range of about 200 nanometers to 400 nanometers. In such embodiments, the difference between the first width w1 and the second width w2 is in a range of about 50 nanometers to about 90 nanometers. In addition, the height h1 of the dielectric grid structure 114 may be in a range of about 600 nanometers to about 800 nanometers.

[0071] like Fig.15 As shown in the cross-sectional view 1500, in the plurality of color filter openings ( Fig.14AA plurality of color filters 116 are formed in the photoresist opening ( 1402 ), wherein the color filters 116 are respectively overlaid on the corresponding photodetectors 104. The color filters 116 can be formed by CVD, PVD, ALD or another suitable deposition process. Fig.14A A photoresist 242 is formed in the first conductive contact 218, and the photoresist 242 may be, for example, a blue photoresist configured as an alignment region. In such an embodiment, an alignment mark (not shown) may be located below the photoresist 242 and / or disposed on the photoresist 242. In addition, a bonding structure 224 is formed on the first conductive contact 218, wherein the bonding structure 224 includes a solder bump 228 overlying the bonding pad 226. In some embodiments, a process for forming the bonding structure 224 may include: 1) patterning the first grid dielectric layer 214 and the second grid dielectric layer 216 and the dielectric metal protection layer 212 to expose the top surface of the first conductive contact 218; 2) selectively forming a bonding pad 226 on the first conductive contact 218, wherein in some embodiments, the sidewall of the bonding pad 226 is laterally offset from the sidewall of the first grid dielectric layer 214 and the sidewall of the second grid dielectric layer 216 by a non-zero distance; and 3) forming a solder bump 228 on the bonding pad 226. In some embodiments, step 2) in the aforementioned process may be achieved by forming the bonding pad 226 on the first conductive contact 218 and then selectively etching the bonding pad 226 through a masking layer (not shown). In some embodiments, the dielectric grid structure 114 and the charge release layer 112 may each include an inclined sidewall, such as Fig. 14B 1400b is shown and / or described in cross-sectional view 1400b.

[0072] In addition, if Fig.15 As shown in FIG. 1 , a plurality of microlenses 232 are formed on the plurality of color filters 116. The microlenses 232 may be formed by depositing a microlens material (e.g., by a spin coating method or a deposition process) on the color filters 116. A microlens template (not shown) having a curved upper surface is patterned over the microlens material. The microlenses are then formed by selectively etching the microlens material according to the microlens template.

[0073] In some embodiments, after forming the color filter 116, the charge release layer 112 is electrically coupled to ground so that the charge carriers can be removed from the dielectric grid structure 114 ( Fig.14A 111). This may partially increase the reliability and / or accuracy of the image generated from the light detector 104, and / or remove gray from the dark image (e.g., black image) generated from the light detector 104. The charge release layer 112 may be electrically coupled to ground via the first conductive contact 218 and / or the bonding structure 224. In some embodiments, the charge release layer 112 is electrically coupled to ground after the bonding structure 224 is formed.

[0074] Fig.16 A method 1600 of forming an image sensor according to an embodiment of the present disclosure is shown. Although method 1600 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may also be included.

[0075] At act 1602, an isolation structure and a plurality of photodetectors are formed in a semiconductor substrate. Figure 4 A cross-sectional view 400 corresponding to some embodiments of act 1602 is shown.

[0076] At act 1604, the semiconductor substrate is bonded to a carrier substrate via an interconnect structure. Figure 4 A cross-sectional view 400 corresponding to some embodiments of act 1604 is shown.

[0077] At act 1606 , the semiconductor substrate is patterned to define a first opening in the semiconductor substrate, exposing an upper surface of the isolation structure. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of act 1606 .

[0078] At act 1608, an etch stop layer is formed over the semiconductor substrate, and a charge release layer is formed over the etch stop layer. The etch stop layer and the charge release layer fill a portion of the first opening. Figure 6 Cross-sectional view 600 is shown corresponding to some embodiments of act 1608 .

[0079] At act 1610, a first conductive contact and a second conductive contact are formed to be laterally offset from the photodetector. The first conductive contact and the second conductive contact each extend through the semiconductor substrate and contact an upper wiring layer of the interconnect structure. Figures 7 to 9 Cross-sectional views 700 - 900 are shown corresponding to some embodiments of act 1610 .

[0080] At act 1612, a portion of the charge release layer that is laterally located between the first conductive contact and the second conductive contact is patterned. Thus, the first conductive contact is electrically isolated from the second conductive contact. Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 1612 .

[0081] At act 1614, a first grid dielectric layer and a second grid dielectric layer are formed over the photodetector. Fig.13 Cross-sectional view 1300 is shown corresponding to some embodiments of act 1614 .

[0082] At action 1616, the first and second grid dielectric layers and the charge release layer are patterned. This defines a plurality of color filter openings, defines a grid dielectric structure, and exposes an upper surface of the etch stop layer. After the patterning process is performed, charge carriers (e.g., electrons) are trapped in the grid dielectric structure. Fig.14A Cross-sectional view 1400a corresponding to some embodiments of act 1616 is shown.

[0083] At act 1618, a plurality of color filters are formed in the color filter openings. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 1618 .

[0084] At act 1620, the charge release layer is electrically coupled to ground through a first conductive contact, thereby removing charge carriers from the grid dielectric structure. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 1620 .

[0085] Thus, in some embodiments, the present disclosure is directed to an image sensor including a charge release layer disposed between a dielectric grid structure and a plurality of photodetectors. The charge release layer is electrically coupled to ground and configured to remove trapped charge carriers (eg, electrons) from the dielectric grid structure.

[0086] In some embodiments, the present application provides an image sensor, comprising: a semiconductor substrate; a photodetector disposed in the semiconductor substrate; an etch stop layer overlying the photodetector; a color filter overlying the etch stop layer; a dielectric grid structure surrounding the color filter; and a charge release layer sandwiched between the dielectric grid structure and the etch stop layer, wherein the charge release layer surrounds the color filter and comprises a conductive material, and wherein the charge release layer directly contacts the color filter.

[0087] According to some embodiments, the charge release layer is electrically coupled to a ground pad.

[0088] According to some embodiments, wherein the conductive material is titanium nitride, and wherein the etch stop layer comprises silicon nitride and the dielectric grid structure comprises silicon oxide.

[0089] According to some embodiments, a bottom surface of the color filter directly contacts a top surface of the etch stop layer, and wherein the dielectric grid structure directly contacts opposing sidewalls of the color filter.

[0090] According to some embodiments, wherein the charge release layer has a ring shape when viewed from above, the ring shape directly contacts an outer periphery of the color filter.

[0091] According to some embodiments, outer sidewalls of the photodetector are laterally spaced apart between inner sidewalls of the charge release layer.

[0092] According to some embodiments, inner sidewalls of the dielectric grid structure are aligned with inner sidewalls of the charge release layer.

[0093] According to some embodiments, an upper surface of the charge release layer directly contacts a bottom surface of the dielectric grid structure.

[0094] In some embodiments, the present application provides a semiconductor structure for an image sensor, the semiconductor structure comprising: an integrated circuit, comprising a carrier substrate, a semiconductor substrate and an interconnect structure, wherein the interconnect structure is arranged between the semiconductor substrate and the carrier substrate, and wherein a photodetector is arranged in the semiconductor substrate; a dielectric grid structure, overlying the semiconductor substrate; color filters, recessed into the dielectric grid structure and respectively overlying the photodetectors, wherein the color filters have a refractive index greater than that of the dielectric grid structure; and a charge release layer, arranged between the dielectric grid structure and the semiconductor substrate, wherein the charge release layer laterally surrounds the color filter, wherein a top surface of the charge release layer is located above the top surface of the semiconductor substrate and a bottom surface of the charge release layer is located vertically between the interconnect structure and the top surface of the semiconductor substrate.

[0095] According to some embodiments, the semiconductor structure further includes: a conductive contact extending from above the top surface of the semiconductor substrate to a conductive wiring layer in the interconnect structure, wherein the charge release layer extends continuously from above the photodetector to directly contact a sidewall of the conductive contact.

[0096] According to some embodiments, the charge release layer is electrically coupled to a ground pad through the conductive contact.

[0097] According to some embodiments, the charge release layer has a first horizontal segment, a vertical segment, and a second horizontal segment, the first horizontal segment overlying the top surface of the semiconductor substrate, the vertical segment extending from the first horizontal segment through the top surface of the semiconductor substrate to a point below the top surface of the semiconductor substrate, and the second horizontal segment extending from the vertical segment to the sidewall of the conductive contact.

[0098] According to some embodiments, the point is located above an upper surface of the conductive contact in a vertical direction.

[0099] According to some embodiments, the semiconductor structure further includes: an etch stop layer overlying the top surface of the semiconductor substrate and extending continuously along a lower surface of the charge release layer, wherein the etch stop layer contacts the sidewall of the conductive contact.

[0100] According to some embodiments, wherein the charge release layer includes a first conductive material and the conductive contact includes a second conductive material different from the first conductive material, and wherein the conductive wiring layer includes the second conductive material.

[0101] According to some embodiments, the charge release layer has a first thickness defined directly below the dielectric grid structure and a second thickness laterally offset from the dielectric grid structure, and wherein the first thickness is less than the second thickness.

[0102] In some embodiments, the present application provides a method for manufacturing a semiconductor structure for an image sensor, the method comprising: forming a photodetector in a semiconductor substrate; forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure has a conductive wiring layer; etching the semiconductor substrate to define a first opening in the semiconductor substrate; depositing an etch stop layer and a charge release layer on the semiconductor substrate and the interconnect structure, wherein the charge release layer overlies the etch stop layer, and wherein the charge release layer and the etch stop layer line at least a portion of the first opening; forming a conductive contact in the first opening, wherein the conductive contact extends through the charge release layer and the semiconductor substrate to contact the conductive wiring layer; depositing a grid dielectric layer on the photodetector; etching the grid dielectric layer and the charge release layer until reaching an upper surface of the etch stop layer, wherein etching the grid dielectric layer defines a dielectric grid structure and a plurality of color filter openings overlying the photodetector; and depositing a plurality of color filters in the plurality of color filter openings.

[0103] According to some embodiments, etching the grid dielectric layer forms an accumulation of charge carriers in the dielectric grid structure, and wherein the charge release layer is electrically coupled to ground to remove the charge carriers from the dielectric grid structure.

[0104] According to some embodiments, forming the conductive contact comprises: etching the etch stop layer and the charge release layer, wherein the etching of the etch stop layer and the charge release layer exposes the top surface of the conductive wiring layer; depositing a conductive contact layer on the semiconductor substrate, wherein the conductive contact layer fills at least a portion of the first opening; and etching the conductive contact layer, wherein the etching of the conductive contact layer defines the conductive contact, and wherein the conductive contact is laterally offset from the photodetector by a non-zero distance.

[0105] According to some embodiments, after depositing the conductive contact layer, the charge release layer directly contacts a sidewall of the conductive contact layer.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will understand that they can easily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An image sensor, characterized in that: include: Semiconductor substrate; A photodetector, disposed in the semiconductor substrate; an etch stop layer overlying the photodetector; a color filter overlying the etch stop layer; a dielectric grid structure surrounding the color filter; as well as a charge release layer interposed between the dielectric grid structure and the etch stop layer, wherein the charge release layer surrounds the color filter and comprises a conductive material, and wherein the charge release layer directly contacts the color filter; as well as A ground pad is located above the semiconductor substrate and laterally offset from the dielectric grid structure, wherein the charge release layer is electrically coupled to the ground pad.

2. The image sensor according to claim 1, characterized in that wherein the conductive material is titanium nitride, and wherein the etch stop layer comprises silicon nitride and the dielectric grid structure comprises silicon oxide.

3. The image sensor according to claim 1, characterized in that Wherein a bottom surface of the color filter directly contacts a top surface of the etch stop layer, and wherein the dielectric grid structure directly contacts opposite sidewalls of the color filter.

4. The image sensor according to claim 1, characterized in that Wherein the charge release layer has a ring shape when viewed from above, the ring shape directly contacts the outer periphery of the color filter.

5. The image sensor according to claim 1, characterized in that The outer sidewalls of the photodetector are laterally spaced apart between the inner sidewalls of the charge release layer.

6. The image sensor according to claim 1, characterized in that: The inner sidewall of the dielectric grid structure is aligned with the inner sidewall of the charge release layer.

7. The image sensor according to claim 1, characterized in that: The upper surface of the charge release layer directly contacts the bottom surface of the dielectric grid structure.

8. A semiconductor structure for an image sensor, characterized in that: include: An integrated circuit comprising a carrier substrate, a semiconductor substrate and an interconnect structure, wherein the interconnect structure is disposed between the semiconductor substrate and the carrier substrate, and wherein a photodetector is disposed in the semiconductor substrate; a dielectric grid structure overlying the semiconductor substrate; Color filters, recessed into the dielectric grid structure and respectively overlying the photodetectors, wherein the color filters have a refractive index greater than a refractive index of the dielectric grid structure; a charge release layer disposed between the dielectric grid structure and the semiconductor substrate, wherein the charge release layer laterally surrounds the color filter, wherein a top surface of the charge release layer is located above a top surface of the semiconductor substrate and a bottom surface of the charge release layer is located vertically between the interconnect structure and the top surface of the semiconductor substrate; as well as A ground pad is located above the semiconductor substrate and laterally offset from the dielectric grid structure, wherein the charge release layer is electrically coupled to the ground pad.

9. The semiconductor structure according to claim 8, characterized in that: Also includes: a conductive contact extending from above the top surface of the semiconductor substrate to a conductive wiring layer in the interconnect structure, The charge release layer continuously extends from above the photodetector to directly contact the sidewall of the conductive contact.

10. The semiconductor structure according to claim 9, characterized in that: The charge release layer is electrically coupled to the ground pad through the conductive contact.

11. The semiconductor structure according to claim 9, characterized in that: The charge release layer has a first horizontal segment, a vertical segment and a second horizontal segment, wherein the first horizontal segment overlies the top surface of the semiconductor substrate, the vertical segment extends from the first horizontal segment through the top surface of the semiconductor substrate to a point below the top surface of the semiconductor substrate, and the second horizontal segment extends from the vertical segment to the side wall of the conductive contact.

12. The semiconductor structure according to claim 11, characterized in that: The point is located above the upper surface of the conductive contact in a vertical direction.

13. The semiconductor structure according to claim 9, characterized in that: Also includes: An etch stop layer overlies the top surface of the semiconductor substrate and extends continuously along a lower surface of the charge release layer, wherein the etch stop layer contacts the sidewall of the conductive contact.

14. The semiconductor structure according to claim 9, characterized in that: wherein the charge release layer comprises a first conductive material and the conductive contact comprises a second conductive material different from the first conductive material, and wherein the conductive wiring layer comprises the second conductive material.

15. The semiconductor structure according to claim 8, characterized in that The charge release layer has a first thickness defined directly below the dielectric grid structure and a second thickness laterally offset from the dielectric grid structure, and wherein the first thickness is less than the second thickness.

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