Semiconductor device

Abstract

A semiconductor device including an active region on a substrate is provided. A plurality of channel layers are spaced apart on the active region. A gate structure is disposed. The gate structure intersects the active region and the plurality of channel layers. The gate structure surrounds the plurality of channel layers. Source / drain regions are disposed on the active region at least one side of the gate structure. The source / drain regions contact the plurality of channel layers. A lower insulating layer is disposed on the source / drain regions between side surfaces of the gate structure. A contact plug passes through the lower insulating layer. The contact plug contacts the source / drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source / drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate cap layer including different materials from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0092590, filed on July 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices comprising a gate isolation structure and a gate capping layer comprising materials that are different from each other. Background Technology

[0004] As the demand for high performance, high speed, and versatility in semiconductor devices increases, so too does the integration density of semiconductor devices. When fabricating semiconductor devices with micropatterns to keep pace with this trend towards higher integration density, micro-widths or micro-distances are required between these micropatterns. However, the shrinking size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs) can compromise their operational performance. Therefore, semiconductor devices including fin field-effect transistors (FinFETs) have also been developed, which incorporate channels with a three-dimensional structure. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor device including an active region located on a substrate is provided. A plurality of channel layers are spaced apart on the active region. A gate structure is disposed. The gate structure intersects the active region and the plurality of channel layers. The gate structure surrounds the plurality of channel layers. Source / drain regions are disposed on at least one side of the gate structure on the active region. The source / drain regions contact the plurality of channel layers. A lower insulating layer is disposed on the source / drain regions between the side surfaces of the gate structure. A contact plug passes through the lower insulating layer. The contact plug contacts the source / drain regions. An isolation structure intersects the active region on the substrate and is disposed between adjacent source / drain regions. Each gate structure includes a gate electrode and a gate capping layer comprising different materials from each other.

[0006] According to an exemplary embodiment of the present invention, the isolation structure and the lower insulating layer comprise materials different from each other.

[0007] According to an exemplary embodiment of the present invention, the isolation structure includes SiO, SiN, SiCN, SiOC, SiON and / or SiOCN.

[0008] According to an exemplary embodiment of the invention, the side surface of the isolation structure is in contact with the source / drain regions that are adjacent to each other.

[0009] According to an exemplary embodiment of the present invention, the lower end of the isolation structure is disposed below the lower end of the active region.

[0010] According to an exemplary embodiment of the present invention, each of the gate structures includes a spacer layer disposed on a side surface of the gate electrode.

[0011] According to an exemplary embodiment of the present invention, the upper surface of the spacer layer and the upper surface of the gate capping layer are substantially coplanar with each other.

[0012] According to an exemplary embodiment of the present invention, at least a portion of the spacer layer is disposed on the side surface of the isolation structure.

[0013] According to an exemplary embodiment of the present invention, an internal spacer layer is disposed on opposite sides of the gate structure in the first direction and on the lower surface of each of the plurality of channel layers. The internal spacer layer has an outer surface that is substantially coplanar with the outer surfaces of the plurality of channel layers.

[0014] According to an exemplary embodiment of the present invention, the isolation structure is in contact with the lower insulating layer and the source / drain region.

[0015] According to an exemplary embodiment of the present invention, a semiconductor device including an active region is provided. A plurality of transistors are spaced apart from each other in the active region along a first direction. Each of the plurality of transistors includes a channel structure located in the active region, a gate structure at least partially surrounding the channel structure, a source / drain region in contact with the channel structure in the active region, and an internal spacer layer disposed between the channel structures. An isolation structure extends toward the active region. The isolation structure contacts at least one of the gate structure, the channel structure, and the internal spacer layer. The isolation structure separates the plurality of transistors from each other. The gate structure includes a gate electrode and a gate capping layer located on the gate electrode. The upper surface of the isolation structure is configured to be higher than the upper surface of the gate electrode. The isolation structure and the gate capping layer comprise different materials from each other.

[0016] According to an exemplary embodiment of the present invention, the upper surface of the gate capping layer is substantially coplanar with the upper surface of the isolation structure.

[0017] According to an exemplary embodiment of the present invention, the gate structure includes a gate spacer layer located on a side surface of the gate electrode. Each of the gate spacer layers has an upper surface that is substantially coplanar with the upper surface of the isolation structure.

[0018] According to an exemplary embodiment of the invention, a portion of the side surface of the isolation structure contacts the side surface of each of the source / drain regions.

[0019] According to an exemplary embodiment of the present invention, the width of the upper surface of the isolation structure in the first direction is greater than the width of the gate electrode in the first direction.

[0020] According to an exemplary embodiment of the present invention, an isolation spacer layer is disposed on a side surface of the isolation structure and comprises the same material as the gate spacer layer.

[0021] According to an exemplary embodiment of the present invention, the contact plug contacts the upper portion of the source / drain region and overlaps with a portion of the gate spacer layer. At least one of the contact plugs contacts the edge of the upper surface of the isolation structure.

[0022] According to an exemplary embodiment of the present invention, a semiconductor device including an active region located on a substrate is provided. A gate structure including a gate electrode is disposed on the active region. A gate capping layer covers the upper portion of the gate electrode. Source / drain regions are disposed on at least one side of the gate electrode on the active region and contact a plurality of channel layers. An isolation structure extends in a first direction perpendicular to the upper surface of the substrate. The isolation structure is disposed on at least one side of the source / drain regions to separate adjacent source / drain regions. The isolation structure comprises a material different from the material of the gate capping layer.

[0023] According to an exemplary embodiment of the present invention, the lower end of the isolation structure is configured to be a first depth lower than the lower end of the active region.

[0024] According to an exemplary embodiment of the present invention, a gate spacer layer extends in the first direction. The gate spacer layer is disposed on at least one side of the gate electrode. An isolation spacer layer extends in the first direction. The isolation spacer layer is disposed on at least one side of the isolation structure. The isolation spacer layer is formed of the same material as the gate spacer layer. Attached Figure Description

[0025] The above and other aspects of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 This is a top view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0027] Figures 2 to 4 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0028] Figure 5A and Figure 5B This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0029] Figures 6 to 8 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention;

[0030] Figure 9 This is a partial cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention; and

[0031] Figures 10 to 24 This is a cross-sectional view illustrating the steps in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0032] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0033] Figure 1 This is a top view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0034] Figure 2 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 2 It shows along Figure 1 The cross sections taken from lines I-I' and II-II' of the semiconductor device in the image.

[0035] Reference Figure 1 and Figure 2 Semiconductor device 1000a may include a substrate 101. An active region 105 may be disposed on the substrate 101. A channel structure 140 including a plurality of channel layers 141, 142, and 143 may be disposed on the active region 105, vertically spaced apart from each other in a third direction (e.g., the Z direction). A source / drain region 150 may be configured to contact the plurality of channel layers 141, 142, and 143. A gate structure 160 may extend intersecting the active region 105. A contact plug 180 may be connected to the source / drain region 150, and an isolation structure 200a may be disposed between the source / drain regions 150. Semiconductor device 1000a may also include a device isolation layer 110.

[0036] Device isolation layer 110 may be disposed on opposite sides of active region 105 in a second direction (e.g., Y direction). Internal spacer layer 130 may be disposed on opposite sides of plurality of channel layers 141, 142, and 143 in a first direction (e.g., X direction). Lower insulating layer 190 may be disposed on the upper surface of source / drain region 150, and upper insulating layer 195 may be disposed on the upper surface of lower insulating layer 190. Gate structure 160 may include gate dielectric layer 162, gate electrode 165, gate spacer layer 164, and gate capping layer 166.

[0037] Semiconductor device 1000a may include a plurality of transistors, and a plurality of regions including each transistor may be defined. Additionally, a plurality of other regions may be defined in semiconductor device 1000a to separate the individual transistors. For example, in semiconductor device 1000a, a first transistor region TR1, a second transistor region TR2, and an isolation region SR located between the first transistor region TR1 and the second transistor region TR2 are defined on substrate 101. Each of the first transistor region TR1 and the second transistor region TR2 may include a channel structure 140 located on an active region 105, a gate structure 160 surrounding the channel structure 140, and a source / drain region 150 configured to contact the channel structure 140 on the active region 105. The first transistor region TR1 and the second transistor region TR2 may be an NMOS region and a PMOS region, respectively. Alternatively, the first transistor region TR1 and the second transistor region TR2 may be transistor regions of the same type. The isolation region SR may separate the first transistor region TR1 and the second transistor region TR2 from each other in a first direction (e.g., the X direction).

[0038] The isolation region SR may include an isolation spacer layer 164a and an isolation structure 200a. For example, the isolation spacer layer 164a may be disposed on opposite sides of the isolation structure 200a in a first direction (e.g., the X direction). The isolation structure 200a and the isolation spacer layer 164a may have a tapered shape.

[0039] In semiconductor device 1000a, active region 105 may have a fin structure. Gate electrode 165 may be disposed between active region 105 and channel structure 140, between multiple channel layers 141, 142 and 143 of channel structure 140, and on the upper part of channel structure 140. Therefore, semiconductor device 1000a may include a gate-all-around field-effect transistor formed by channel structure 140, source / drain region 150 and gate structure 160.

[0040] Substrate 101 may have an upper surface, the plane of which may be defined by a first direction (e.g., the X direction) and a second direction (e.g., the Y direction). Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, and / or a group II-VI compound semiconductor. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0041] Device isolation layer 110 may define active region 105 in substrate 101. Device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. In an exemplary embodiment of the present invention, device isolation layer 110 may further include a region having a step and extending deeper relative to the lower portion of substrate 101. Device isolation layer 110 may expose a portion of the upper portion of active region 105. In an exemplary embodiment of the present invention, device isolation layer 110 may have a curved upper surface having a higher horizontal height in the direction toward active region 105. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be, for example, an oxide, a nitride, and / or a combination thereof.

[0042] The active region 105 is defined by a device isolation layer 110 in the substrate 101 and may be configured to extend in a first direction (e.g., the X direction). The active region 105 may have a structure that protrudes from the substrate 101. The upper end of the active region 105 may be configured to protrude from the upper surface of the device isolation layer 110 to a predetermined height. The active region 105 may be formed as part of the substrate 101 or may include an epitaxial layer grown from the substrate 101.

[0043] However, a portion of the active region 105 on the substrate 101 may be recessed on the opposite side of the gate structure 160, and the source / drain region 150 may be disposed on the recessed active region 105. The active region 105 may include impurities or doped regions containing impurities. The recessed active region 105 may be bent downward toward the upper surface of the substrate 101 in a third direction (e.g., the Z direction).

[0044] The channel structure 140 may include two or more channel layers disposed on the active region 105 and spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., in a third direction, e.g., the Z direction), such as first to third channel layers 141, 142, and 143. The first to third channel layers 141, 142, and 143 may be connected to the source / drain region 150 and may be spaced apart from the top surface of the active region 105.

[0045] The first to third channel layers 141, 142, and 143 may have the same or similar width as the active region 105 in the second direction (e.g., the Y direction) and may have the same or similar width as the gate structure 160 in the first direction (e.g., the X direction). However, in an exemplary embodiment of the present invention, the first to third channel layers 141, 142, and 143 may have a reduced width in the first direction (e.g., the X direction) such that their side surfaces are disposed below the gate structure 160.

[0046] The first to third channel layers 141, 142, and 143 may be formed of a semiconductor material and may include, for example, silicon (Si), silicon-germanium (SiGe), and / or germanium (Ge). The first to third channel layers 141, 142, and 143 may be formed of, for example, the same material as the substrate 101. In an exemplary embodiment of the inventive concept, the first to third channel layers 141, 142, and 143 may include impurity regions formed in a region adjacent to the source / drain region 150. The number and shape of the channel layers 141, 142, and 143 constituting a single channel structure 140 may vary in exemplary embodiments of the inventive concept. For example, in an exemplary embodiment of the inventive concept, the channel structure 140 may also include a channel layer disposed on the upper surface of the active region 105.

[0047] Source / drain regions 150 may be disposed on the active region 105 on opposite sides of the channel structure 140. Source / drain regions 150 may be configured to cover the upper surface of the active region 105 and the side surfaces of each of the first to third channel layers 141, 142, and 143 of the channel structure 140. Source / drain regions 150 may be formed by recessing a portion of the upper part of the active region 105. In exemplary embodiments of the inventive concept, the recess and its depth may be varied. Source / drain regions 150 may be a semiconductor layer comprising silicon (Si) and may include impurities of different types and / or concentrations.

[0048] A gate structure 160 may be disposed on the active region 105 and the channel structure 140, and may extend in a second direction (e.g., the Y direction) intersecting the active region 105 and the channel structure 140. A channel region of the transistor may be formed in the active region 105 and the channel structure 140 intersecting the gate structure 160. The gate structure 160 includes a gate electrode 165, a gate dielectric layer 162 located between the gate electrode 165 and each of a plurality of channel layers 141, 142, and 143, a gate spacer layer 164 located on a side surface of the gate electrode 165, and a gate capping layer 166 located on an upper surface of the gate electrode 165.

[0049] A gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be configured to surround all surfaces of the gate electrode 165 except for the upper surface of the gate electrode 165. The upper surface of the gate electrode 165 may be covered by a gate capping layer 166. The gate dielectric layer 162 may extend in a third direction (e.g., the Z direction) between the gate electrode 165 and the gate spacer layer 164, but the extension of the gate dielectric layer 162 is not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, and / or high-k dielectrics. "High-k dielectric" may refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2). High-k dielectrics can be, for example, alumina (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) and / or praseodymium oxide (Pr2O3).

[0050] The gate electrode 165 can be configured to extend higher relative to the channel structure 140 in a third direction (e.g., the Z direction) while filling the space between the plurality of channel layers 141, 142, and 143 on the active region 105. The gate electrode 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by a gate dielectric layer 162. The gate electrode 165 may include a conductive material, such as a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), a metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo), and / or a semiconductor material such as doped polycrystalline silicon. The gate electrode 165 may have a multilayer structure comprising two or more layers.

[0051] The gate spacer layer 164 may be disposed on opposite sides of the gate electrode 165 in a first direction (e.g., the X direction) and may extend in a third direction (e.g., the Z direction) perpendicular to the upper surface of the substrate 101. The gate spacer layer 164 may insulate the source / drain region 150 and the gate electrode 165 from each other. In an exemplary embodiment of the inventive concept, the gate spacer layer 164 may have a multilayer structure. The gate spacer layer 164 may be formed of oxides, nitrides, and / or oxide oxynitrides. For example, the gate spacer layer 164 may be formed of a low-k dielectric.

[0052] A gate capping layer 166 may be disposed on the gate electrode 165. The gate capping layer 166 may be configured to extend along the upper surface of the gate electrode 165 in a second direction (e.g., the Y direction). The side surfaces of the gate capping layer 166 may be surrounded by the upper portion of the gate spacer layer 164. The upper surface of the gate capping layer 166 may be substantially coplanar with the upper surface of the gate spacer layer 164 and the upper surface of the lower insulating layer 190, which will be described later, but the inventive concept is not limited thereto. The gate capping layer 166 may comprise a material with a different etch selectivity relative to the lower insulating layer 190 or the upper insulating layer 195, which will be described later. The gate capping layer 166 may be formed of an oxide, nitride, or oxide oxynitride, and may include, for example, SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0053] The internal spacer layer 130 may be disposed parallel to the gate electrode 165 between the channel structures 140. For example, the internal spacer layer 130 may be disposed on opposite sides of the gate electrode 165 in a first direction (e.g., the X direction) and may contact adjacent channel structures 140 on the lower surface of each of the first to third channel layers 141, 142, and 143. The internal spacer layer 130 may have an outer surface that is substantially coplanar with the outer surfaces of the first to third channel layers 141, 142, and 143. For example, the outer surface of the internal spacer layer 130 and the outer surfaces of the channel layers 141, 142, and 143 may be aligned in a third direction (e.g., the Z direction). Below the third channel layer 143, the gate electrode 165 may be spaced apart from the source / drain region 150 by the internal spacer layer 130 for electrical isolation. Each internal spacer layer 130 may have a shape in which the side surface facing the gate electrode 165 is rounded inward toward the gate electrode 165, but the shape of each internal spacer layer 130 is not limited to this. The internal spacer layer 130 may be formed of oxides, nitrides and / or oxynitrides. For example, the internal spacer layer 130 may be formed of a low-k dielectric.

[0054] Contact plug 180 can be connected to source / drain region 150. For example, contact plug 180 can pass through upper insulating layer 195, source / drain region 150, and lower insulating layer 190, and can apply an electrical signal to source / drain region 150. Contact plug 180 can be disposed on source / drain region 150, such as... Figure 1 As shown. In an exemplary embodiment of the inventive concept, the length of the contact plug 180 in the second direction (e.g., the Y direction) may be greater than the length of the source / drain region 150. Depending on the aspect ratio, the contact plug 180 may have a sloping side surface with a lower width narrower than the upper width, but the shape of the side surface of the contact plug 180 is not limited thereto. The contact plug 180 may extend downward, for example, beyond the third channel 143. For example, the lower surface of the contact plug 180 may be lower than the lower surface of the third channel 143. The contact plug 180 may extend downward toward the substrate 101 to a height corresponding to, for example, the upper surface of the second channel layer 142, but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the contact plug 180 may be configured to contact and extend along the upper surface of the source / drain region 150 without causing the source / drain region 150 to be recessed. For example, the lower surface of the contact plug 180 and the upper surface of the source / drain region 150 may be coplanar. The contact plug 180 may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or metals such as aluminum (Al), tungsten (W), or molybdenum (Mo).

[0055] The lower insulating layer 190 may cover the source / drain region 150 and the gate structure 160, and may be configured to cover the device isolation layer 110 in a region of the semiconductor device 1000a. The lower insulating layer 190 may include, for example, oxides, nitrides, and / or oxide oxynitrides. For example, the lower insulating layer 190 may include a low-k dielectric.

[0056] The upper insulating layer 195 may be configured to cover the upper surface of the lower insulating layer 190 and the upper surface of the gate structure 160. The lower insulating layer 195 may include, for example, oxides, nitrides, and oxide oxynitrides. For example, the upper insulating layer 195 may include a low-k dielectric.

[0057] The isolation structure 200a may intersect the active region 105 on the substrate 101 and extend in a second direction (e.g., the Y direction). The isolation structure 200a may also extend in a direction perpendicular to the upper surface of the substrate 101 (i.e., in a third direction (e.g., the Z direction)). The isolation structure 200a may be disposed between adjacent source / drain regions 150. The upper surface of the isolation structure 200a may be substantially coplanar with the upper surface of the gate capping layer 166 and the upper surface of the gate spacer layer 164, and the upper end of the isolation structure 200a may be disposed at substantially the same height as the upper end of the gate capping layer 166, but its arrangement is not limited thereto.

[0058] In an exemplary embodiment of the present invention, depending on the aspect ratio, the isolation structure 200a may have an inclined side surface with a lower width narrower than the upper width, but the shape of the side surface of the isolation structure 200a is not limited thereto. The lower part of the isolation structure 200a may have a flat surface or may have a convex or sharp shape facing the substrate 101, but the shape of the lower part of the isolation structure 200a is not limited thereto.

[0059] In an exemplary embodiment of the present invention, such as Figure 1 As shown, the first width W1 of the upper surface of the isolation structure 200a in a first direction (e.g., the X direction) can be greater than the second width W2 of the gate electrode 165 in the first direction (e.g., the X direction). The upper surface of the isolation structure 200a can be configured to be higher than the upper surface of the gate electrode 165. The lower end of the isolation structure 200a can be configured to be lower than the lower end of the source / drain region 150. The lower end of the isolation structure 200a can be configured to be lower than the lower end of the active region 105 by a predetermined depth. For example, the isolation structure 200a can extend upward from the substrate 101 along a third direction (e.g., the Z direction) to pass through the active region 105, and the lower end of the isolation structure 200a can be configured to be lower than the lower end of the active region 105 by a first depth D1. For example, the lower end of the isolation structure 200a can partially pass through the substrate 101. In an exemplary embodiment of the present invention, the lower end of the isolation structure 200a may be configured to be lower than the lower end of the source / drain region 150 and higher than the lower end of the active region 105, but the configuration is not limited thereto.

[0060] Semiconductor device 1000a may further include an isolation spacer 164a, which is disposed at substantially the same horizontal height as gate spacer layer 164 and extends at the same height as gate spacer layer 164 in a third direction (e.g., Z direction) perpendicular to the upper surface of substrate 101. Isolation spacer 164a may be disposed on a side surface of isolation structure 200a and extend in a third direction (e.g., Z direction). Isolation spacer 164a may also be referred to herein as isolation spacer layer 164a. The shape of isolation spacer layer 164a may be the same as that obtained by removing a portion of gate spacer layer 164, for example, it may be the same as that obtained by removing a predetermined width from a side surface of gate spacer layer 164 in a first direction (e.g., X direction). For example, when viewed from a top view (e.g., Figure 1 Viewed in the image, the spacer layer 164a may have a portion overlapping with the isolation structure 200a, and therefore, one side surface of the spacer layer 164a may be inclined relative to the substrate 101. However, the shape of the spacer layer 164a is not limited thereto, and the spacer layer 164a may have a shape substantially the same as that of the gate spacer layer 164 (e.g., rectangular). The shape of the spacer layer 164a may be substantially the same as that of the gate spacer layer 164, or may be substantially the same as that obtained by modifying or further etching a portion of the gate spacer layer 164. In an exemplary embodiment of the inventive concept, the gate spacer layer 164 and the spacer layer 164a may have substantially the same width in a first direction (e.g., the X direction). However, the inventive concept is not limited thereto.

[0061] In an exemplary embodiment of the present invention, the spacer layer 164a may be disposed on opposite sides of the isolation structure 200a and may have a multilayer structure. The spacer layer 164a may be formed of oxides, nitrides, and / or oxynitrides. For example, the spacer layer 164a may include a low-k dielectric. In an exemplary embodiment of the present invention, the gate spacer layer 164 and the spacer layer 164a may include the same material.

[0062] In an exemplary embodiment of the present invention, the side surface of the isolation structure 200a may not contact the corresponding side surface of the adjacent source / drain region 150. Therefore, the portion of the channel structure 140 that contacts the side surface of the source / drain region 150 facing the isolation structure 200a, and the portion of the internal spacer layer 130 that contacts the side surface of the source / drain region 150 facing the isolation structure 200a, may be disposed as residues on the side surface of the isolation structure 200a.

[0063] An isolation structure 200a can be disposed between adjacent source / drain regions 150 to prevent the diffusion of impurities included in the adjacent source / drain regions 150. Adjacent isolation structures 200a can be spaced apart from each other in a first direction (e.g., the X direction) and can be disposed between transistors including channel structure 140, source / drain regions 150, and gate structure 160. Therefore, transistors can be separated from each other.

[0064] The isolation structure 200a may include insulating materials such as SiO, SiN, SiCN, SiOC, SiON and / or SiOCN.

[0065] The isolation structure 200a and the gate capping layer 166 may comprise different materials from each other. For example, the gate capping layer 166 may comprise SiN, and the isolation structure 200a may comprise SiOC, but the materials of the isolation structure 200a and the gate capping layer 166 are not limited thereto. The isolation structure 200a and the lower insulating layer 190 may comprise different materials from each other. For example, the lower insulating layer 190 may comprise an oxide such as SiO2, and the isolation structure 200a may comprise SiOC, but the materials of the isolation structure 200a and the lower insulating layer 190 are not limited thereto.

[0066] In the following text, reference will be made to Figures 3 to 9 Example embodiments of a semiconductor device conceived according to the present invention are described. Figures 3 to 9 In order to simplify the description, references to the above will be omitted. Figure 1 and Figure 2 The description is the same as the description in the explanation.

[0067] Figure 3 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0068] Reference Figure 3 , with reference to the above Figure 2 Different from the exemplary embodiments of the inventive concept described herein, the semiconductor device 1000b may include an isolation structure 200b. The isolation structure 200b may be disposed between adjacent source / drain regions 150, and both side surfaces of the isolation structure 200b may contact the respective source / drain regions 150. In an exemplary embodiment of the invention, portions of the channel structure 140 that contact the side surfaces of the source / drain regions 150 facing the isolation structure 200b, and portions of the internal spacer layer 164b that contact the side surfaces of the source / drain regions 150 facing the isolation structure 200b, may not remain on the side surfaces of the isolation structure 200b.

[0069] In an exemplary embodiment of the present invention, the spacer layer 164b may be disposed on both sides of the isolation structure 200b. The shape of the spacer layer 164b may be the same as that obtained by removing a predetermined width from one side surface of the gate spacer layer 164 in a first direction (e.g., the X direction). For example, the shape of each of the isolation structure 200b and the spacer layer 164b may be rectangular. The width of the spacer layer 164b in the first direction (e.g., the X direction) may be smaller than the width of the gate spacer layer 164 in the first direction (e.g., the X direction). However, the shape of the spacer layer 164b is not limited thereto and may be the same as the shape of the gate spacer layer 164.

[0070] In an exemplary embodiment of the present invention, the isolation region SR may include an isolation spacer layer 164b and an isolation structure 200b. The isolation structure 200b may be disposed between the first transistor region TR1 and the second transistor region TR2. Specifically, the isolation structure 200b may be disposed between adjacent first source / drain regions 150 and second source / drain regions 150. A portion of the side surface of the isolation structure 200b may contact the side surface of each of the first and second source / drain regions 150.

[0071] Figure 4 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0072] Reference Figure 4 , with reference to the above Figure 2 Different from the exemplary embodiments of the inventive concept described herein, semiconductor device 1000c may not include the internal spacer layer 130. Gate electrode 165 may extend along a first direction (e.g., the X direction) between the first to third channel layers 141, 142, and 143 of channel structure 140. Therefore, the two side surfaces of gate electrode 165 spaced apart in the first direction (e.g., the X direction) may be arranged perpendicularly to the two side surfaces of channel structure 140 spaced apart in the first direction (e.g., the X direction) and may be substantially coplanar with the two side surfaces of channel structure 140. For example, gate electrode 165 may have parallel side surfaces surrounded by the inner surface of gate dielectric layer 162. A portion of the outer surface of gate dielectric layer 162 surrounding the parallel side surface of gate electrode 165 may be aligned with the side surfaces of the first to third channel layers 141, 142, and 143 stacked thereon.

[0073] An isolation structure 200c may be disposed between adjacent first source / drain regions 150 and second source / drain regions 150. A portion of the side surface of the isolation structure 200c may contact the side surface of each of the first source / drain regions 150 and the second source / drain region 150.

[0074] Figure 5A and Figure 5B This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0075] Reference Figure 5A , with reference to the above Figure 2 Different from the exemplary embodiments of the inventive concept described herein, the semiconductor device 1000d may include an isolation structure 200d having a portion extending in a first direction (e.g., the X direction). For example, the outer surface of the upper portion of the isolation structure 200d may extend inwardly from each of the adjacent source / drain regions 150. Therefore, the isolation structure 200d may have a shape including a curved portion. For example, the lower portion of the isolation structure 200d may be wider than its upper portion in the first direction (e.g., the X direction). The horizontal height of the curved portion of the isolation structure 200d may be lower than the upper surface of the source / drain region 150. The curved portion of the isolation structure 200d may bend from the side surface of the spacer layer 164d to contact the lower surface of the spacer layer 164d. The side surface of the lower portion of the isolation structure 200d may contact the opposite sides of the adjacent source / drain regions 150.

[0076] Reference Figure 5B , with reference to the above Figure 2 The example embodiments of the inventive concept described are different; the semiconductor device 1000e may include an isolation structure 200e having a lower region configured below the source / drain region 150 and having a different shape. For example, as Figure 5B As shown, the side surface of the lower region of the isolation structure 200e may have a shape that protrudes into the lower region of the source / drain region 150. For example, the isolation structure 200e may have a diamond-shaped protrusion extending from its lower portion and at least partially through the substrate 101.

[0077] Figure 6 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0078] Reference Figure 6 , with reference to the above Figure 2Different from the exemplary embodiments of the inventive concept described herein, the semiconductor device 1000f may include contact plugs 180a, each contact plug 180a having a relatively large width in a first direction (e.g., the X direction). Therefore, a portion of the contact plug 180a may contact the edge of the upper surface of the isolation structure 200f. In an exemplary embodiment of the inventive concept, the contact plug 180a may have a shape that curves along the upper surface of the isolation structure 200f. For example, the contact plug 180a and the isolation structure 200f may each taper towards the substrate 101 in a third third direction (e.g., the Z direction), so that an isosceles triangular spacer layer 164f may be disposed on the source / drain region 150 and extend between adjacent side surfaces of the isolation structure 200f and the contact plug 180a. The apex of the isosceles triangular spacer layer 164f may be located at the lower surface of the upper insulating layer 195 where the contact plug 180a contacts the isolation structure 200f. Contact plug 180a can make contact with source / drain region 150. (Refer to the above.) Figure 2 The example embodiments of the inventive concept described are different, and the contact area between the contact plug 180a and the source / drain region 150 can be increased. The contact plug 180a may overlap with a portion of the gate spacer layer 164 and a portion of the isolation spacer layer 164f.

[0079] Figure 7 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0080] Reference Figure 7 , with reference to the above Figure 2 Different from the exemplary embodiment of the inventive concept described herein, the semiconductor device 1000h may include an isolation structure 200h that can contact the lower insulating layer 190 and the source / drain region 150. In this exemplary embodiment of the inventive concept, the isolation structure 200h may be disposed in a region where the channel structure 140 and the gate structure 160 are not provided. Therefore, the isolation spacer layer 164a (see...) Figure 2 It is not necessary to arrange it on the two side surfaces of the isolation structure 200h. For example, the isolation structure 200h can pass through the source / drain region 150 between adjacent channel structures 140.

[0081] Figure 8 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0082] Figure 8 A cross-section of a semiconductor device 1000i including a FinFET is shown, in which a gate structure 160 surrounds three surfaces of an active region, such as the upper surface of the active region 105 and the side surface of the active region 105 in a second direction (e.g., the Y direction). (Referring to the above references) Figure 2Different from the described example embodiments, semiconductor device 1000i may not include multiple channel layers. Semiconductor device 1000i may include a channel region, that is, the portion of active region 105 surrounded by gate structure 160.

[0083] The isolation structure 200i can extend through the gate structure 160 and the channel region, and the lower end of the isolation structure 200i can be configured to be lower than the lower end of the active region 105. The side surface of the isolation structure 200i may not contact the side surface of the adjacent source / drain region 150. However, with... Figure 8 Unlike the example shown, the side surface of the isolation structure 200i can contact the side surface of the adjacent source / drain region 150. According to an exemplary embodiment of the invention, the lower portion of the isolation structure 200i can have a flat surface, a convex shape, etc., but the shape of the lower portion of the isolation structure 200i is not limited to these and can be modified in various ways.

[0084] Figure 9 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0085] Reference Figure 9 The semiconductor device 1000j may include an active region 105a and a channel structure 140a, the width of each of the active region 105a and the channel structure 140a being equal to a reference. Figure 2 The widths differ in the example embodiments of the inventive concept described. Since each of the active region 105a and the channel structure 140a can have a relatively small width, the cross-section of each of the plurality of channel layers 141a, 142a and 143a of the channel structure 140a in the second direction (e.g., the Y direction) can have a circular or an elliptical shape with a small difference between the length of the major axis and the length of the minor axis.

[0086] For example, in reference Figure 2 In the exemplary embodiments of the inventive concept described, the width of each of the plurality of channel layers 141, 142, and 143 in the second direction (e.g., the Y direction) can be approximately 20 nm to approximately 50 nm. In this exemplary embodiment of the inventive concept, the width of each of the plurality of channel layers 141a, 142a, and 143a in the second direction (e.g., the Y direction) can be approximately 3 nm to approximately 12 nm. As described above, in the exemplary embodiments of the inventive concept, the width and width-dependent shape of the active region 105a and the channel structure 140a can be varied.

[0087] Figures 10 to 24 This is a cross-sectional view illustrating the steps in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. (Refer to...) Figures 10 to 24 To describe the manufacture of exemplary embodiments of the present invention Figure 2Methods for semiconductor devices.

[0088] Reference Figure 10 The sacrificial layer 120 and the channel layers 141, 142 and 143 can be stacked alternately on the substrate 101. For example, the channel layers 141, 142 and 143 can be stacked sequentially on the bottommost sacrificial layer 120, wherein an additional sacrificial layer 120 is disposed between the channel layers 141, 142 and 143.

[0089] The sacrificial layer 120 may be a layer that is replaced by the gate dielectric layer 162 and the gate electrode 165 through subsequent processes, such as... Figure 2 As shown. The sacrificial layer 120 may be formed of a material with a different etch selectivity relative to the channel layers 141, 142, and 143. The channel layers 141, 142, and 143 may include materials different from those of the sacrificial layer 120. The sacrificial layer 120 and the channel layers 141, 142, and 143 include semiconductor materials such as silicon (Si), silicon germanium (SiGe), and / or germanium (Ge), but may include materials different from each other. The sacrificial layer 120 and the channel layers 141, 142, and 143 may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the channel layers 141, 142, and 143 may include silicon (Si).

[0090] The sacrificial layer 120 and channel layers 141, 142, and 143 can be formed by performing an epitaxial growth process using substrate 101 as a seed. The thickness of each of the sacrificial layer 120 and channel layers 141, 142, and 143 can be approximately 1 angstrom. Up to approximately 100 nm. In an exemplary embodiment of the invention, the number of channel layers 141, 142, and 143, which are stacked alternately with the sacrificial layer 120, can be varied.

[0091] Reference Figure 11 An active structure can be formed by removing a portion of the stacked structure of the sacrificial layer 120 and the channel layers 141, 142 and 143, as well as a portion of the substrate 101.

[0092] The active structure may include sacrificial layers 120 and channel layers 141, 142 and 143 stacked alternately on top of each other, and may also include an active region 105 formed by removing a portion of the substrate 101 to protrude from the upper surface of the substrate 101. The active structure may be formed as a line extending in a first direction (e.g., the X direction) and may be spaced apart from each other in a second direction (e.g., the Y direction).

[0093] In the region where a portion of the substrate 101 has been removed, a device isolation layer 110 can be formed by filling with an insulating material and recessing the insulating material to make the active region 105 protrude. The upper surface of the device isolation layer 110 may be lower than the upper surface of the active region 105.

[0094] Reference Figure 12 A sacrificial gate structure 170 and a gate spacer layer 164 can be formed on the active structure.

[0095] The sacrificial gate structure 170 can be a sacrificial structure formed in a region on the channel structure 140 by subsequent processes where the gate dielectric layer 162 and the gate electrode 165 are disposed. Figure 2 As shown. The sacrificial gate structure 170 may include a first sacrificial gate layer 172 and a second sacrificial gate layer 175 stacked in sequence, and a gate mask patterning layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be patterned using the gate mask patterning layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively, but are not limited thereto. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be formed as a single layer. For example, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The gate mask patterning layer 176 may include silicon oxide and / or silicon nitride. The sacrificial gate structure 170 may have a linear shape extending in a direction intersecting the active structure. The sacrificial gate structures 170 may extend in a second direction (e.g., the Y direction) and may be spaced apart from each other in a first direction (e.g., the X direction).

[0096] A gate spacer layer 164 may be formed on both sidewalls of the sacrificial gate structure 170. The gate spacer layer 164 can be formed by forming a layer of uniform thickness along the upper and side surfaces of the sacrificial gate structure 170 and the active structure, and then anisotropically etching the layer. The gate spacer layer 164 may be formed of a low-k dielectric and may include SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0097] Reference Figure 13 The exposed sacrificial layer 120 and exposed channel layers 141, 142 and 143 can be removed between the sacrificial gate structures 170 to form a recessed region RC, thereby forming the channel structure 140.

[0098] The sacrificial gate structure 170 and the gate spacer layer 164 can be used as masks to remove the exposed sacrificial layer 120 and the exposed channel layers 141, 142, and 143. Therefore, the channel layers 141, 142, and 143 have a finite length in a first direction (e.g., the X direction) and can form the channel structure 140. As in Figure 13 As described in the example embodiment of the inventive concept depicted, a portion of the sacrificial layer 120 and the channel structure 140 may be removed below the sacrificial gate structure 170, such that two side surfaces of the sacrificial gate structure 170 and the gate spacer layer 164 may be disposed below the sacrificial gate structure 170 and the gate spacer layer 164 in a first direction (e.g., the X direction).

[0099] Reference Figure 14 A portion of the exposed sacrificial layer 120 can be removed from the side surface of the exposed sacrificial layer 120.

[0100] The sacrificial layer 120 can be selectively etched relative to the channel structure 140 using, for example, a wet etching process to remove a portion of its side surface to a predetermined depth in a first direction (e.g., the X direction). The sacrificial layer 120 may have side surfaces that are recessed due to the side surface etching. However, the shape of the side surfaces of the sacrificial layer 120 is not limited to... Figure 14 The shape shown.

[0101] Reference Figure 15 An internal spacer layer 130 can be formed in the area where the sacrificial layer 120 is removed.

[0102] The internal spacer layer 130 can be formed by filling the area where the sacrificial layer 120 is removed with insulating material and removing the insulating material deposited on the outside of the channel structure 140. The internal spacer layer 130 can be formed of the same material as the gate spacer layer 164, but the material of the internal spacer layer 130 is not limited to this. For example, the internal spacer layer 130 may include SiN, SiCN, SiOCN, SiBCN, and / or SiBN.

[0103] Reference Figure 16 Source / drain regions 150 can be formed on the opposite side of the active region 105 that is adjacent to the sacrificial gate structure 170.

[0104] The source / drain region 150 can be formed by performing an epitaxial growth process. The source / drain region 150 can be connected to multiple channel layers 141, 142, and 143 of the channel structure 140 via its side surfaces, and can contact the internal spacer layer 130 between the channel layers 141, 142, and 143. The source / drain region 150 may include impurities formed by in-situ doping and may include multiple layers having different doping elements and / or different doping concentrations.

[0105] Reference Figure 17 The lower insulating layer 190 can be formed, and the sacrificial layer 120 and the sacrificial gate structure 170 can be removed.

[0106] The lower insulating layer 190 can be formed by forming an insulating layer to cover the sacrificial gate structure 170 and the source / drain region 150 and performing a planarization process.

[0107] The sacrificial layer 120 and the sacrificial gate structure 170 can be selectively removed relative to the gate spacer layer 164, the lower insulating layer 190, and the channel structure 140. After forming the upper gap region UR by removing the sacrificial gate structure 170, the lower gap region LR can be formed by removing the sacrificial layer 120 exposed through the upper gap region UR. For example, when the sacrificial layer 120 comprises silicon germanium (SiGe) and the channel structure 140 comprises silicon (Si), the sacrificial layer 120 can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source / drain region 150 can be protected by the lower insulating layer 190 and the internal spacer layer 130.

[0108] Reference Figure 18 A gate structure 160 can be formed in the upper gap region UR and the lower gap region LR.

[0109] The gate dielectric layer 162 can be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. After the gate electrode 165 can be formed to completely fill the upper gap region UR and the lower gap region LR, the gate electrode 165 can be removed from the upper part of the gate electrode 165 to a predetermined depth in the upper gap region UR. A gate capping layer 166 can be formed in the region of the upper gap region UR where the gate electrode 165 has been removed. Therefore, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 can be formed.

[0110] At least one gate structure in the gate structure 160 may be a dummy gate structure 160' having a portion to be removed in a subsequent process. At least one channel structure in the channel structure 140 may be a dummy channel structure 140' corresponding to the dummy gate structure 160', the dummy channel structure 140' having a portion to be removed together with the dummy gate structure 160' in a subsequent process.

[0111] Reference Figure 19 A first mask pattern layer 191 can be formed on the gate structure 160 and the lower insulating layer 190, and a trench can be formed extending downward through the first mask pattern layer 191, the dummy gate structure 160', and the dummy channel structure 140' to below the lower end of the active region 105. Therefore, a portion of the dummy gate structure 160' and a portion of the dummy channel structure 140' can be removed.

[0112] The first mask pattern layer 191 may include a silicon-containing compound. For example, the first mask pattern layer 191 may include tetraethyl orthosilicate (TEOS).

[0113] The trench T may extend intersecting the active region 105 in a second direction (e.g., the Y direction). Depending on the aspect ratio, the trench T may have sloping side surfaces with a lower width narrower than the upper width. The lower portion of the trench T may have a flat surface and may have a raised or sharp shape relative to the substrate 101, but its shape is not limited thereto. The lower end of the trench T may be set to be lower than the lower end of the active region 105 by a predetermined depth, such as a first depth D1.

[0114] As trench T is formed, while a portion of the dummy gate spacer layer 164' of the dummy gate structure 160' is removed, the unremoved portion of the dummy gate spacer layer 164' can be retained as an isolation spacer 164a on the side surface of trench T.

[0115] Reference Figure 20 A preliminary isolation structure 200' can be formed to fill the trench T and cover the upper part of the first mask pattern layer 191. The preliminary isolation structure 200' may include a material different from the material of the gate cover layer 166.

[0116] Reference Figure 21 A portion of the first mask pattern layer 191 and a portion of the preliminary isolation structure 200' can be removed using a chemical mechanical polishing (CMP) process. The CMP process can be stopped by detecting the boundary between layers comprising materials different from each other. Therefore, the height from the boundary to the surface on which the CMP process is stopped can be adjusted. To prevent semiconductor device failure in subsequent processes, this height is required to be less than a predetermined value. In an exemplary embodiment of the present invention, this requirement can be met because the CMP process can be stopped by sensing the boundary between the first mask pattern layer 191 and the gate capping layer 166. For example, according to an exemplary embodiment of the present invention, since the preliminary isolation structure 200' comprises a material different from that of the gate capping layer 166, the boundary between the first mask pattern layer 191 and the gate capping layer 166 can be accurately detected during the CMP process. For example, the preliminary isolation structure 200' and the first mask pattern layer 191, disposed at a horizontal height higher than the boundary between the first mask pattern layer 191 and the gate capping layer 166, can be removed. Therefore, it is possible to prevent the undesirable formation of contact holes H caused by residues of the initial isolation structure 200' in subsequent processes, and to form contact plugs 180 with uniform width.

[0117] Reference Figures 22 to 24The upper insulating layer 195 and the second mask pattern 196 can be formed sequentially to cover the upper part of the gate structure 160, the upper part of the lower insulating layer 190 and the upper part of the isolation structure 200a.

[0118] A contact hole H can be formed that passes through the second mask pattern 196, the upper insulating layer 195 and the lower insulating layer 190 and is recessed into the upper part of the source / drain region 150.

[0119] A conductive material fills the contact hole H to form a contact plug 180. The lower surface of the contact hole H may be recessed into the source / drain region 150 or may be bent along the upper surface of the source / drain region 150. In exemplary embodiments of the present invention, the shape and arrangement of the contact plug 180 may be varied.

[0120] In the semiconductor device of an exemplary embodiment of the present invention, the dielectric material of the isolation structure is different from the dielectric material of the gate capping layer and / or the dielectric material of the lower insulating layer.

[0121] Therefore, the upper surface of the gate cap can be precisely inspected during the CMP process, and dielectric material residue from the isolation structure can be prevented from remaining in the upper regions of the source / drain regions where contact holes are formed. As a result, the electrical characteristics of the semiconductor device can be improved.

[0122] Although exemplary embodiments of the invention have been shown and described above, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: An active region extends on the substrate along a first direction and protrudes from the substrate in a vertical direction perpendicular to the upper surface of the substrate; Multiple channel layers, the multiple channel layers being vertically spaced apart from each other in the active region; A gate structure extending on the substrate in a second direction perpendicular to the first direction, the gate structure intersecting the active region and the plurality of channel layers, the gate structure at least partially surrounding the plurality of channel layers; Source / drain regions are disposed on the active region on at least one side of the gate structure, and the source / drain regions are in contact with the plurality of channel layers; A lower insulating layer is disposed on the source / drain region between the side surfaces of the gate structure; A contact plug that passes through the lower insulating layer and contacts the source / drain region; and An isolation structure extends on the substrate along the second direction, intersecting with the active region, and is disposed between adjacent source / drain regions. The contact plug extends below the top surface of the source / drain region. Wherein, the lower part of the isolation structure has a first width smaller than the upper part of the isolation structure, and the upper part extends upward from the lower part. The lower portion of the isolation structure is recessed into the active region to a depth greater than the thickness of one of the plurality of channel layers in the vertical direction, so as to contact the side surface of the active region. Each of the gate structures includes a gate electrode and a gate capping layer located on the gate electrode, and the isolation structure comprises a material different from the gate capping layer. The isolation structure and the lower insulating layer are made of different materials. The upper surface of the isolation structure and the upper surface of the lower insulating layer are coplanar.

2. The semiconductor device according to claim 1, wherein, The isolation structure comprises SiOC, and the gate capping layer comprises SiN.

3. The semiconductor device according to claim 1, wherein, The isolation structure includes SiO, SiN, SiCN, SiOC, SiON and / or SiOCN.

4. The semiconductor device according to claim 1, wherein, The side surface of the isolation structure is in contact with the source / drain regions that are adjacent to each other.

5. The semiconductor device according to claim 1, further comprising: A device isolation layer that defines the active region and covers the upper surface of the substrate. The lower end of the isolation structure is set to a horizontal height lower than the lower end of the device isolation layer.

6. The semiconductor device according to claim 1, wherein, Each of the gate structures further includes a spacer layer disposed on the side surface of the gate electrode.

7. The semiconductor device according to claim 6, wherein, The upper surfaces of the spacer layer, the gate capping layer, and the isolation structure are substantially coplanar with each other.

8. The semiconductor device according to claim 6, wherein, At least a portion of the spacer layer is disposed on the side surface of the isolation structure.

9. The semiconductor device according to claim 1, further comprising: An internal spacer layer is disposed on opposite sides of the gate structure in the first direction and on the lower surface of each of the plurality of channel layers, the internal spacer layer having an outer surface substantially coplanar with the outer surfaces of the plurality of channel layers.

10. The semiconductor device according to claim 1, wherein, The isolation structure is in contact with the lower insulating layer and the source / drain region.

11. A semiconductor device, comprising: An active region protrudes from the substrate in a vertical direction perpendicular to the upper surface of the substrate; A plurality of transistors spaced apart from each other in a first direction on the active region, each of the plurality of transistors including a channel structure on the active region, a gate structure at least partially surrounding the channel structure, a source / drain region on the active region in contact with the channel structure, and an internal spacer layer disposed between the channel structures. A lower insulating layer is disposed on the source / drain region between the side surfaces of the gate structure; and An isolation structure extending toward the active region separates the plurality of transistors from each other. Wherein, the lower part of the isolation structure has a first width smaller than the upper part of the isolation structure, and the upper part extends upward from the lower part. The lower portion of the isolation structure is recessed into the active region to a depth greater than the thickness in the vertical direction of one of the plurality of channel layers included in the channel structure, so as to contact the side surface of the active region. The gate structure includes a gate electrode and a gate capping layer located on the gate electrode, wherein the upper surface of the isolation structure is configured to be higher than the upper surface of the gate electrode. The isolation structure is in contact with at least one of the gate structure, the channel structure, and the internal spacer layer. The isolation structure comprises a material different from the gate capping layer. The isolation structure and the lower insulating layer are made of different materials, and the upper surface of the isolation structure and the upper surface of the lower insulating layer are coplanar.

12. The semiconductor device according to claim 11, wherein, The upper surface of the gate capping layer is substantially coplanar with the upper surface of the isolation structure.

13. The semiconductor device according to claim 11, wherein, The gate structure further includes a gate spacer layer located on the side surface of the gate electrode, and Each of the gate spacer layers has an upper surface that is substantially coplanar with the upper surface of the isolation structure.

14. The semiconductor device according to claim 11, wherein, A portion of the side surface of the isolation structure contacts the side surface of each of the source / drain regions.

15. The semiconductor device according to claim 12, wherein, The width of the upper surface of the isolation structure in the first direction is greater than the width of the gate electrode in the first direction.

16. The semiconductor device of claim 13, further comprising: An isolation spacer layer is disposed on a side surface of the isolation structure and comprises the same material as the gate spacer layer.

17. The semiconductor device of claim 16, further comprising: A contact plug that contacts the upper portion of the source / drain region and overlaps with a portion of the gate spacer layer. Wherein, at least one of the contact plugs contacts the edge of the upper surface of the isolation structure, and The contact plug extends below the top surface of the source / drain region.

18. A semiconductor device, comprising: An active region, the active region being located on the substrate and protruding from the substrate in a vertical direction perpendicular to the upper surface of the substrate; Multiple channel layers, the multiple channel layers being perpendicularly spaced from each other on the active region; A gate structure, the gate structure including a gate electrode, the gate structure being disposed on the active region; A gate capping layer that covers the upper part of the gate electrode; Source / drain regions, wherein the source / drain regions are disposed on at least one side of the gate electrode in the active region; A lower insulating layer is disposed on the source / drain region between the side surfaces of the gate structure; and An isolation structure extending in the vertical direction, the isolation structure being disposed on at least one side of the source / drain regions to separate adjacent source / drain electrodes. Wherein, the lower part of the isolation structure has a first width smaller than the upper part of the isolation structure, and the upper part extends upward from the lower part. The lower portion of the isolation structure is recessed into the active region to a depth greater than the thickness of one of the plurality of channel layers in the vertical direction, so as to contact the side surface of the active region. The isolation structure comprises a material different from the material of the gate capping layer. The isolation structure and the lower insulating layer are made of different materials. The upper surface of the isolation structure and the upper surface of the lower insulating layer are coplanar.

19. The semiconductor device of claim 18, further comprising: A device isolation layer that defines the active region and covers the upper surface of the substrate; as well as A contact plug that contacts the source / drain region and extends below the top surface of the source / drain region. Wherein, the lower end of the isolation structure is set to a horizontal height lower than the lower end of the device isolation layer, and The isolation structure includes SiOC, and the gate capping layer includes SiN.

20. The semiconductor device of claim 18, further comprising: A gate spacer layer extending in the vertical direction, the gate spacer layer being disposed on at least one side of the gate electrode; and An isolation spacer layer extending in the vertical direction, the isolation spacer layer being disposed on at least one side of the isolation structure. The spacer layer is formed of the same material as the gate spacer layer.

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