Multiphase high conversion ratio switched capacitor power converter

Abstract

A method for multiphase high-conversion-ratio switched-capacitor power conversion includes sequentially forming one of four sub-circuits during corresponding timing phases, wherein each sub-circuit includes up to three capacitors. The conversion between the input voltage and the output voltage is achieved by sequentially connecting the input, output, ground, the top plate of the first capacitor, and the bottom plate of the first capacitor to the top plate of the second capacitor and the bottom plate of the second capacitor for each corresponding timing phase.

Description

Technical Field

[0001] This disclosure relates generally to power conversion, and more specifically to switched capacitor power conversion with a reduced number of floating capacitors. Background Technology

[0002] Switched capacitor power converters (SCPCs) have emerged as a popular alternative to inductive converters. A key advantage of SCPCs is that they use only switches and capacitors, unlike inductive converters which require inductors. Inductors tend to be larger, more expensive, and more difficult to integrate onto silicon compared to capacitor-based converters. SCPCs are more attractive in many applications, especially those requiring fully integrated or miniaturized solutions.

[0003] The main drawback of SCPCs is that the possible voltage conversion ratio is discrete and limited by the number of capacitors, unlike inductive converters where the conversion ratio is a continuous function of the duty cycle of the switching signal. The efficiency of SCPCs can be improved by using the correct voltage conversion ratio; therefore, a larger number of capacitors will ultimately result in higher power efficiency. If the SCPC is fully integrated (e.g., both the switch and capacitor are on-chip), the number of capacitors and switches becomes less critical because, in integrated implementations, the number of components is less important than their size. However, the required capacitor size is proportional to the required output power, preventing full integration in higher power applications. For external floating capacitors, package size and the number of external capacitors are factors limiting integration density. The number of package pins also increases with the number of external floating capacitors, increasing the cost and area of ​​the integrated solution. Summary of the Invention

[0004] According to one aspect of the present invention, an apparatus is provided, comprising:

[0005] A first capacitor, the first capacitor including a first top plate and a first bottom plate;

[0006] The second capacitor includes a second top plate and a second bottom plate;

[0007] The third capacitor includes a third top plate and a third bottom plate;

[0008] Input, the input including input voltage;

[0009] Output, the output including output voltage; and

[0010] A plurality of switches, the plurality of switches including an S1pVin switch connected between the input and the first top plate, an S2p1n switch connected between the first bottom plate and the second top plate, an S3p2n switch connected between the second bottom plate and the third top plate, an S3nG switch connected between the third bottom plate and ground, an S1p2p switch connected between the first top plate and the second top plate, an S2nG switch connected between the second bottom plate and the ground, an S3p1p switch connected between the first top plate and the third top plate, an S3nVo switch connected between the output and the third bottom plate, an S1nVo switch connected between the output and the first bottom plate, an S1n3p switch connected between the first bottom plate and the third top plate, an S2nVo switch connected between the output and the second bottom plate, and an S1nG switch connected between the first bottom plate and the ground.

[0011] According to one or more embodiments of the present invention, during a first phase, the output is connected to the first base plate, the first top plate is connected to the second top plate, and the second base plate is connected to the ground.

[0012] During the second phase, the output is connected to the second base plate, the second top plate is connected to the first top plate, the first base plate is connected to the third top plate, and the third base plate is connected to the ground.

[0013] During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the ground.

[0014] During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second base plate, the second top plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage and the output voltage is one-tenth of the input voltage.

[0015] According to one or more embodiments of the present invention, the third phase follows the fourth phase, the second phase follows the third phase, the first phase follows the second phase, wherein the input voltage is converted from the output voltage, and the input voltage is ten times greater than the output voltage.

[0016] According to one or more embodiments of the present invention, during a first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input.

[0017] During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third bottom plate, and the third top plate is connected to the input.

[0018] During the third phase, the output is connected to the third top plate, the third bottom plate is connected to the first top plate, and the first bottom plate is connected to the ground.

[0019] During the fourth phase, the output is connected to the first base plate, the first top plate is connected to the third top plate, the third base plate is connected to the second top plate, and the second base plate is connected to the ground, wherein the output voltage is converted from the input voltage and the output voltage is seven-tenths of the input voltage.

[0020] According to one or more embodiments of the present invention, during a first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input.

[0021] During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third top plate, and the third bottom plate is connected to the ground.

[0022] During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the input.

[0023] During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second top plate, the second base plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage.

[0024] According to one or more embodiments of the present invention, the output voltage is converted from the input voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 3, 7 and 9 and a denominator representing the input voltage and equal to 10.

[0025] According to one or more embodiments of the present invention, the output voltage is converted from the input voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 2, 4, 5, 7 and 8 and a denominator representing the input voltage and equal to 9.

[0026] According to one or more embodiments of the invention, a controller is further included, the controller being configured to control a corresponding subset of the plurality of switches for each of the four non-overlapping phases.

[0027] According to one or more embodiments of the present invention, each of the plurality of switches is a field-effect transistor.

[0028] According to one or more embodiments of the present invention, the gate of at least one of the plurality of switches is connected to a multiplexer configured to multiplex more than one timing phase signal from a controller.

[0029] According to a second aspect of the present invention, a method for multiphase high-conversion-ratio switched capacitor power conversion is provided, the method comprising:

[0030] During the corresponding timing phase, one of four sub-circuits is formed sequentially, wherein each sub-circuit includes at most three capacitors; and

[0031] The input voltage of the input and the output voltage of the output are converted by sequentially connecting one of the top plate and the bottom plate of the first capacitor of the three capacitors to one of the top plate and the bottom plate of the second capacitor of the three capacitors for each corresponding timing phase.

[0032] According to one or more embodiments of the present invention, the input voltage is converted into the output voltage, wherein the first sub-circuit is formed in the case of a first timing phase, the second sub-circuit is formed in the case of a second timing phase, the third sub-circuit is formed in the case of a third timing phase, and the fourth sub-circuit is formed in the case of a fourth timing phase.

[0033] According to one or more embodiments of the present invention, the output voltage is converted into the input voltage, wherein the first sub-circuit is formed in the case of a fourth timing phase, the second sub-circuit is formed in the case of a third timing phase, the third sub-circuit is formed in the case of a second timing phase, and the fourth sub-circuit is formed in the case of a first timing phase.

[0034] According to one or more embodiments of the invention, the input voltage is further converted to the output voltage using a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 3, 7, and 9, and a denominator representing the input voltage and equal to 10.

[0035] According to one or more embodiments of the invention, the input voltage is further converted to the output voltage using a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 2, 4, 5, 7, and 8, and a denominator representing the input voltage and equal to 9.

[0036] According to one or more embodiments of the present invention, it further includes generating each timing phase in the respective timing phases using a controller.

[0037] According to a third aspect of the present invention, a system is provided, comprising:

[0038] Three capacitors;

[0039] Input, the input including input voltage;

[0040] The output includes an output voltage converted from the input voltage; and

[0041] A controller configured to sequentially form each of four sub-circuits during corresponding non-overlapping timing phases, wherein each of the four sub-circuits includes one of the top plate of the first capacitor of the three capacitors and the bottom plate of the first capacitor of the three capacitors, the one being switchably connected to one of the input, the output, ground, the top plate of the second capacitor of the three capacitors, and the bottom plate of the second capacitor of the three capacitors.

[0042] According to one or more embodiments of the present invention, the system is a secondary switched capacitor power converter connected between a primary power converter and a primary power converter configured to convert a power supply voltage to the input voltage.

[0043] According to one or more embodiments of the present invention, the controller is configured to switchably connect two of the three capacitors together during a first timing phase and a third timing phase, and to switchably connect three of the three capacitors together during a second timing phase and a fourth timing phase.

[0044] According to one or more embodiments of the present invention, the controller is programmable and configured to switchably connect at least two of the three capacitors in each of the four non-overlapping timing phases to achieve one of a plurality of conversion ratios defined by the output voltage divided by the input voltage. Attached Figure Description

[0045] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals denote similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0046] Figure 1 This is a schematic diagram of a switched capacitor power converter (SCPC) according to an exemplary embodiment of the present disclosure.

[0047] Figure 2 It is during the first switching phase of the buck converter. Figure 1 A schematic diagram of the SCPC.

[0048] Figure 3 It is during the second switching phase of the buck converter. Figure 1 A schematic diagram of the SCPC.

[0049] Figure 4 It is during the third switching phase of the buck converter. Figure 1 A schematic diagram of the SCPC.

[0050] Figure 5 It is during the fourth switching phase of the buck converter. Figure 1 A schematic diagram of the SCPC.

[0051] Figure 6 Is Figures 2 to 5 The four switching phases shown in the figure Figure 1 A schematic diagram of the state of the capacitors in the SCPC.

[0052] Figure 7 It is during each of the four switching phases. Figure 1 A table of accumulated charge at the capacitors, inputs, and outputs of the SCPC.

[0053] Figure 8 This is according to another exemplary embodiment of the present disclosure during the four switching phases of buck conversion. Figure 1 A schematic diagram of the state of the capacitors in the SCPC.

[0054] Figure 9 This is according to another exemplary embodiment of the present disclosure during the four switching phases of buck conversion. Figure 1 A schematic diagram of the state of the capacitors in the SCPC.

[0055] Figure 10 This is a flowchart of a method for multiphase high conversion ratio switched capacitor power conversion according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0056] The embodiments described herein provide a novel SCPC topology with a wide conversion ratio using a four-phase switching cycle with three floating capacitors. For a given conversion ratio (e.g., the ratio of the SCPC's output voltage to its input voltage), the SCPC requires a number of floating capacitors. Equation (1) below gives the possible conversion ratio "M" of the SCPC with "Nc" floating capacitors, where "P" and "Q" are positive integers:

[0057] M = [1 ≤ P ≤ 2^Nc] / [1 ≤ Q ≤ 2^Nc] Equation (1)

[0058] In a two-phase SCPC topology, the number of capacitors can be particularly limited if the corresponding capacitance values ​​are relatively large (e.g., tens of nF). Typically, large capacitors need to be implemented as discrete components outside the monolithic integrated circuit (IC), undesirably increasing the IC's pin count. In one example embodiment, the requirement for large capacitors is determined by the power level that needs to be converted by the SCPC.

[0059] In one example of a two-phase SCPC, with a conversion ratio M = 1 / 10 (e.g., the output voltage is 10 times lower than the input voltage), at least five floating capacitors are required, as determined by the Fibonacci limit. For more modern multi-phase SCPCs, this conversion ratio can be achieved using four floating capacitors. Using the novel four-phase topology described herein, only three floating capacitors are needed to provide comparable performance. Furthermore, reducing the number of floating capacitors to three also reduces the number of required component pins, resulting in a more compact solution in pin-constrained and / or component-constrained applications. A conversion ratio M = 1 / 10 is particularly useful as a secondary converter in systems operating from a 110V AC supply, stepping the primary voltage down to 33V, and then further converting it to 3.3V using the SCPC to power an IC. Moreover, the variations of the SCPC topology described herein provide increased granularity in circuits based on multi-ratio SCPCs.

[0060] Figure 1 An example embodiment 10 of the SCPC according to this disclosure is shown. Embodiment 10 converts an input voltage at input 12 to an output voltage at output 14, wherein both the input voltage and the output voltage are referenced to a ground potential at ground 16. In one embodiment, the ground potential is zero volts; however, this disclosure is applicable to other ground potential values. Embodiment 10 includes a first capacitor 20 having a first top plate 22 and a first bottom plate 24. Embodiment 10 includes a second capacitor 30 having a second top plate 32 and a second bottom plate 34. Embodiment 10 includes a third capacitor 40 having a third top plate 42 and a third bottom plate 44.

[0061] Example 10 includes multiple switches to transfer charge between input 12 and output 14 (and thus convert the input voltage to the output voltage). This charge transfer is performed using four sequentially timing phases (e.g., “phases”) by sequentially configuring connections between two or more of the three capacitors 20, 30, and 40, the input, the output, and ground. For convenience, the multiple switches are named after the two nodes to which the respective switches are connected. For example, switch S1pvin connects the input (Vin) to the first top plate 22 (or positive plate) of the first capacitor 20.

[0062] S1pvin switch 50 is connected between input 12 and the first top plate 22. S2p1n switch 52 is connected between the first bottom plate 24 and the second top plate 32. S3p2n switch 54 is connected between the second bottom plate 34 and the third top plate 42. S3nG switch 56 is connected between the third bottom plate 44 and ground 16. S1p2p switch 60 is connected between the first top plate 22 and the second top plate 32. S2nG switch 62 is connected between the second bottom plate 34 and ground 16. S3p1p switch 64 is connected between the first top plate 22 and the third top plate 42. S3nvo switch 66 is connected between output 14 and the third bottom plate 44. S1nvo switch 70 is connected between output 14 and the first bottom plate 24. S1n3p switch 72 is connected between the first bottom plate 24 and the third top plate 42. S2nvo switch 74 is connected between output 14 and the second bottom plate 34. S1nG switch 76 is connected between the first base plate 24 and ground 16.

[0063] Continue to refer to Figure 1 In this case, Figures 2 to 4 The switch connections for each of the four phases are shown to implement an SCPC configured to down-convert an input voltage (e.g., 10V) by a tenth to form an output voltage (e.g., 1V). Figure 2 The diagram shows the first phase 80 (e.g., phase 1). Figure 1 The connectivity of embodiment 10. Specifically, output 14 is connected to the first base plate 24 via S1nVo switch 70. The first top plate 22 is connected to the second top plate 32 via switch S1p2p 60. The second base plate 34 is connected to ground 16 via S2nG switch 62.

[0064] Figure 3 This shows the second phase 82 (e.g., phase 2). Figure 1 The connectivity of embodiment 10. Specifically, output 14 is connected to the second base plate 34 via S2nVo switch 74. The second top plate 32 is connected to the first top plate 22 via switch S1p2p 60. The first base plate 24 is connected to the third top plate 42 via S1n3p switch 72. The third base plate 44 is connected to ground 16 via S3nG switch 56.

[0065] Figure 4 The diagram shows the third phase 84 (e.g., phase 3). Figure 1 The connectivity of embodiment 10. Specifically, output 14 is connected to the third base plate 44 via S3nVo switch 66. The third top plate 42 is connected to the first top plate 22 via S3p1p switch 64. The first base plate 24 is connected to ground 16 via S1nG switch 76.

[0066] Figure 5 The diagram shows the fourth phase 86 (e.g., phase 4). Figure 1 The connectivity of embodiment 10. Specifically, output 14 is connected to the third base plate 44 via S3nVo switch 66. The third top plate 42 is connected to the second base plate 34 via switch S3p2n 54. The second top plate 32 is connected to the first base plate 24 via S2p1p switch 52. The first top plate 22 is connected to input 12 via S1pVin switch 50.

[0067] It should be understood that, Figure 1 Example 10 is shown as Figures 2 to 4 A downconverter in the form of a converter. In one embodiment, referring to equation (1) above, the conversion ratio is 1 / 10 to convert a 10V input to a 1V output. By changing the order of the timing phases (e.g., replacing phases 1, 2, 3, and 4 with phases 4, 3, 2, and 1), embodiment 10 becomes an upconverter configured to convert the output voltage on output 14 to the input voltage on input 12. In an example embodiment, each of the four phases 80, 82, 84, and 86 is a non-overlapping phase with a switching frequency of 1MHz and a phase duration of less than 250 nanoseconds. In an example embodiment, each of the capacitors 20, 30, and 40 has a nominal capacitance of one microfarad, and each switch has a 1 Ohm “on” resistance. In another example embodiment, Figure 1 The SCPC shown is a secondary power converter following the primary power converter, where the primary power converter is configured to convert the supply voltage (e.g., 110Vac) to an intermediate voltage (e.g., 33Vdc). The SCPC converts the 33Vdc intermediate voltage to 3.3Vdc to suitably power the IC.

[0068] Continue to refer to Figures 1 to 5 In this case, Figure 6Example embodiment 10 of an SCPC configured as a downconverter with a conversion ratio of 1 / 10 is also described. During the first phase 80, output 14 is connected to a first base plate 24. A first top plate 22 is connected to a second top plate 32. A second base plate 34 is connected to ground 16. During the first phase 80, charge “q1” (not shown) is transferred from ground 16 to output 14.

[0069] During the second phase 82, output 14 is connected to the second base plate 34. The second top plate 32 is connected to the first top plate 22. The first base plate 24 is connected to the third top plate 42. The third base plate 44 is connected to ground 16. During the second phase 82, charge "q2" (not shown) is transferred from ground 16 to output 14.

[0070] During the third phase 84, output 14 is connected to the third base plate 44. The third top plate 42 is connected to the first top plate 22. The first base plate 24 is connected to ground 16. During the third phase 84, charge "q3" (not shown) is transferred from ground 16 to output 14.

[0071] During the fourth phase 86, output 14 is connected to the third base plate 44. The third top plate 42 is connected to the second base plate 34. The second top plate 32 is connected to the first base plate 24. The first top plate 22 is connected to input 12. During the fourth phase 86, charge "q4" (not shown) is transferred from input 12 to output 14.

[0072] For each of the four phases 80, 82, 84, and 86, assuming the SCPC is lightly loaded or properly protected from its load, the voltage across each capacitor 20, 30, and 40 remains stable. In steady state, the voltage across each capacitor remains stable for each phase of the four phase cycles. Figure 6 In an example embodiment, the first capacitor 20 is maintained at 3V on the first top plate 22 and the first bottom plate 24. The second capacitor 30 is maintained at 4V on the second top plate 32 and the second bottom plate 34. The third capacitor 40 is maintained at 2V on the third top plate 42 and the third bottom plate 44. Figure 6 As shown, each of the four phases 80, 82, 84, and 86 satisfies Kirchhoff's voltage law. For example, with respect to the first phase 80, the voltage between ground 16 and the second top plate 32 (or the first top plate 22) is -4V. The voltage between the first top plate 22 and the first bottom plate is +3V. The voltage at output 14 is +1V, therefore -4V + 3V + 1V = 0V.

[0073] refer to Figure 7 And continue to refer to Figure 6This also shows that charge balance is satisfied. More specifically, charge balance means that there is no net charge pumping or decay of any of the three capacitors 20, 30, and 40 between the four phase cycles. This is achieved through the... Figure 6 The charges q1, q2, q3, and q4 described in the diagram (corresponding to the four phases 80, 82, 84, and 86) are summed, and for each capacitor and taking into account the polarity of each capacitor connection in the capacitor connection, four equations with three unknowns are determined. For the normalization analysis, q4 is set to 1 unit. For the first capacitor 20, the charge balance during the four corresponding phases is q1 - q2 - q3 + q4 = 0. For example, during the first phase 80, q1 is positive because q1 flows from the first top plate 22 to the first bottom plate 24. Conversely, during the second phase 82, q2 is negative because q2 flows from the first bottom plate 24 to the first top plate 22. Similar to the derivation for the first capacitor 20, the charge balance of the second capacitor 30 is given by -q1 + q2 + 0 + q4 = 0, and the charge balance of the third capacitor 40 is given by 0 - q2 + q3 + q4 = 0. Solving these four equations yields q4 = 1, q3 = 2, q2 = 3, and q1 = 4, as defined by the four phases 80, 82, 84, and 86. Figure 7 The corresponding columns are shown. By summing the charge units in each row defined by capacitors 20, 30, and 40, the net charge difference between conversion cycles is found to be 0. Similarly, Figure 7 The cumulative charge of 1 unit at input 12 and the cumulative charge of 10 units at output 14 are shown.

[0074] and Figures 1 to 6 Compared to the buck converter shown, other topologies can be implemented. In one example, each topology is inverted from a buck converter to a boost converter. In other embodiments, for a conversion ratio M = k / 10, k is one of 3, 7, or 9. In other embodiments, for a conversion ratio M = k / 9, k is one of 1, 2, 4, 5, 7, or 8. Figure 8 and Figure 9 Two variations of the buck converter are shown, each with a conversion ratio (M) of 7 / 10, an input voltage of 10V, and an output voltage of 7V. In one embodiment, a controller (not shown) controls... Figure 1 Example 10 generates four timing phases and switches them to dynamically adjust the conversion ratio.

[0075] Continue to refer to Figure 1 In this case, Figure 8Example embodiment 10 of an SCPC configured as a downconverter with a conversion ratio of 7 / 10 is also described. During the first phase 80, output 14 is connected to the first base plate 24. The first top plate 22 is connected to the second base plate 34. The second top plate 32 is connected to input 12.

[0076] During the second phase 82, output 14 is connected to the second top plate 32. The second bottom plate 34 is connected to the first top plate 22. The first bottom plate 24 is connected to the third bottom plate 44. The third top plate 42 is connected to input 12.

[0077] During the third phase 84, output 14 is connected to the third top plate 42. The third bottom plate 44 is connected to the first top plate 22. The first bottom plate 24 is connected to ground 16.

[0078] During the fourth phase 86, output 14 is connected to the first base plate 24. The first top plate 22 is connected to the third top plate 42. The third base plate 44 is connected to the second top plate 32. The second base plate 34 is connected to ground 16.

[0079] Continue to refer to Figure 1 In this case, Figure 9 Example embodiment 10 of an SCPC configured as a downconverter with a conversion ratio of 7 / 10 is also described. During the first phase 80, output 14 is connected to the first base plate 24. The first top plate 22 is connected to the second base plate 34. The second top plate 32 is connected to input 12.

[0080] During the second phase 82, output 14 is connected to the second top plate 32. The second bottom plate 34 is connected to the first top plate 22. The first bottom plate 24 is connected to the third top plate 42. The third bottom plate 44 is connected to ground 16.

[0081] During the third phase 84, output 14 is connected to the third base plate 44. The third top plate 42 is connected to the first top plate 22. The first base plate 24 is connected to input 12.

[0082] During the fourth phase 86, output 14 is connected to the third base plate 44. The third top plate 42 is connected to the second top plate 32. The second base plate 34 is connected to the first base plate 24. The first top plate 22 is connected to input 12.

[0083] Figure 10 A method 90 for multiphase power conversion using an SCPC with a high conversion ratio is shown. At 92, four sub-circuits are formed during corresponding timing phases 80, 82, 84, and 86 (see, for example, [link to relevant documentation]). Figures 2 to 5Each sub-circuit includes up to three capacitors (e.g., capacitors 20, 30, and 40). At 94, the input voltage is converted to the output voltage by sequentially connecting one of the bottom plate 24, 34, or 44 or the top plate 22, 32, or 42 of the first capacitor to one of the top plate 22, 32, or 42 or the bottom plate 24, 34, or 44 of the second capacitor during each of the corresponding timing phases 80, 82, 84, and 86.

[0084] As will be understood, the disclosed embodiments include at least the following. In one embodiment, a device includes a first capacitor, the first capacitor including a first top plate and a first bottom plate. A second capacitor includes a second top plate and a second bottom plate. A third capacitor includes a third top plate and a third bottom plate. An input includes an input voltage. An output includes an output voltage. A plurality of switches include an S1pVin switch connected between the input and the first top plate. An S2p1n switch is connected between the first bottom plate and the second top plate. An S3p2n switch is connected between the second bottom plate and the third top plate. An S3nG switch is connected between the third bottom plate and ground. An S1p2p switch is connected between the first top plate and the second top plate. An S2nG switch is connected between the second bottom plate and the ground. An S3p1p switch is connected between the first top plate and the third top plate. An S3nVo switch is connected between the output and the third bottom plate. An S1nVo switch is connected between the output and the first bottom plate. An S1n3p switch is connected between the first bottom plate and the third top plate. The S2nVo switch is connected between the output and the second base plate. The S1nG switch is connected between the first base plate and the ground.

[0085] Alternative embodiments of the device include one or any combination of the following features: During a first phase, the output is connected to the first base plate, the first top plate is connected to the second top plate, and the second base plate is connected to the ground; during a second phase, the output is connected to the second base plate, the second top plate is connected to the first top plate, the first base plate is connected to the third top plate, and the third base plate is connected to the ground; during a third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the ground; and during a fourth phase, the output is connected to the third base plate, the third top plate is connected to the second base plate, the second top plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is one-tenth of the input voltage. The third phase follows the fourth phase, the second phase follows the third phase, and the first phase follows the second phase, wherein the input voltage is converted from the output voltage, and the input voltage is ten times greater than the output voltage. During a first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During a second phase, the output is connected to the second top plate, the second base plate is connected to the first top plate, the first base plate is connected to the third base plate, and the third top plate is connected to the input. During a third phase, the output is connected to the third top plate, the third base plate is connected to the first top plate, and the first base plate is connected to ground. During a fourth phase, the output is connected to the first base plate, the first top plate is connected to the third top plate, the third base plate is connected to the second top plate, and the second base plate is connected to ground. The output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage. During a first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During a second phase, the output is connected to the second top plate, the second base plate is connected to the first top plate, the first base plate is connected to the third top plate, and the third base plate is connected to ground. During a third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the input. During a fourth phase, the output is connected to the third base plate, the third top plate is connected to the second top plate, the second base plate is connected to the first base plate, and the first top plate is connected to the input. The output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage.The output voltage is converted from the input voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 3, 7, and 9, and a denominator representing the input voltage and equal to 10. The output voltage is also converted from the input voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 2, 4, 5, 7, and 8, and a denominator representing the input voltage and equal to 9. The controller is configured to control a corresponding subset of the plurality of switches for each of the four non-overlapping phases. Each of the plurality of switches is a field-effect transistor. The gate of at least one of the plurality of switches is connected to a multiplexer configured to multiplex more than one timing phase signal from the controller.

[0086] In another embodiment, a method for multiphase high-conversion-ratio switched-capacitor power conversion is provided, the method comprising sequentially forming one of four sub-circuits during respective timing phases, wherein each sub-circuit includes up to three capacitors. The conversion between an input voltage and an output voltage is performed by sequentially connecting an input, an output, a ground, a top plate of a first capacitor, and a bottom plate of a first capacitor to a top plate of a second capacitor and a bottom plate of a second capacitor for each respective timing phase.

[0087] Alternative embodiments of the method for multiphase high-conversion-ratio switched capacitor power conversion include one or any combination of the following features. The input voltage is converted to the output voltage, wherein a first sub-circuit is formed in the case of a first timing phase, a second sub-circuit is formed in the case of a second timing phase, a third sub-circuit is formed in the case of a third timing phase, and a fourth sub-circuit is formed in the case of a fourth timing phase. The output voltage is converted to the input voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 3, 7, and 9, and a denominator representing the input voltage and equal to 10. The input voltage is converted to the output voltage with a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 2, 4, 5, 7, and 8, and a denominator representing the input voltage and equal to 9. Each timing phase in the respective timing phase is generated by a controller.

[0088] In another embodiment, a system includes three capacitors. The input includes an input voltage. The output includes an output voltage converted from the input voltage. A controller is configured to sequentially form each of four sub-circuits during corresponding non-overlapping timing phases, wherein each of the four sub-circuits includes one of the top plate and the bottom plate of a first capacitor of the three capacitors, the latter being switchably connected to one of the input, the output, ground, the top plate of a second capacitor of the three capacitors, and the bottom plate of the second capacitor of the three capacitors.

[0089] Alternative embodiments of the system include one or any combination of the following features. The system is a secondary switched-capacitor power converter connected between primary power converters configured to convert a supply voltage to the input voltage. The controller is configured to switchably connect two of the three capacitors together during a first timing phase and a third timing phase, and to switchably connect three of the three capacitors together during a second timing phase and a fourth timing phase. The controller is programmable and configured to switchably connect at least two of the three capacitors in each of the four non-overlapping timing phases to achieve one of a plurality of conversion ratios defined by the output voltage divided by the input voltage.

[0090] Although the invention has been described herein with reference to specific embodiments, various modifications and alterations may be made without departing from the scope of the invention as set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Any benefits, advantages, or problem solutions described herein with reference to specific embodiments are not intended to be construed as key, essential, or necessary features or elements of any or all claims.

[0091] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the chronological or other priority of such elements.

Claims

1. A switched capacitor power converter, characterized in that, include: A first capacitor, the first capacitor including a first top plate and a first bottom plate; The second capacitor includes a second top plate and a second bottom plate; The third capacitor includes a third top plate and a third bottom plate; Input, the input including input voltage; The output includes the output voltage; as well as A plurality of switches, the plurality of switches including an S1pVin switch connected between the input and the first top plate, an S2p1n switch connected between the first bottom plate and the second top plate, an S3p2n switch connected between the second bottom plate and the third top plate, an S3nG switch connected between the third bottom plate and ground, an S1p2p switch connected between the first top plate and the second top plate, an S2nG switch connected between the second bottom plate and the ground, an S3p1p switch connected between the first top plate and the third top plate, an S3nVo switch connected between the output and the third bottom plate, an S1nVo switch connected between the output and the first bottom plate, an S1n3p switch connected between the first bottom plate and the third top plate, an S2nVo switch connected between the output and the second bottom plate, and an S1nG switch connected between the first bottom plate and the ground; A controller is configured to control a corresponding subset of the plurality of switches for each of the four non-overlapping phases according to one of the following (1) to (3): (1) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second top plate, and the second base plate is connected to the ground. During the second phase, the output is connected to the second base plate, the second top plate is connected to the first top plate, the first base plate is connected to the third top plate, and the third base plate is connected to the ground. During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the ground. During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second base plate, the second top plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is one-tenth of the input voltage; (2) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third bottom plate, and the third top plate is connected to the input. During the third phase, the output is connected to the third top plate, the third bottom plate is connected to the first top plate, and the first bottom plate is connected to the ground. During the fourth phase, the output is connected to the first base plate, the first top plate is connected to the third top plate, the third base plate is connected to the second top plate, and the second base plate is connected to the ground, wherein the output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage; (3) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third top plate, and the third bottom plate is connected to the ground. During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the input. During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second top plate, the second base plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage.

2. The switched capacitor power converter according to claim 1, characterized in that, The third phase follows the fourth phase, the second phase follows the third phase, and the first phase follows the second phase, wherein the input voltage is converted from the output voltage, and the input voltage is ten times greater than the output voltage.

3. The switched capacitor power converter according to claim 1, characterized in that, The output voltage is converted from the input voltage by a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 3, 7, and 9, and a denominator representing the input voltage and equal to 10.

4. The switched capacitor power converter according to claim 1, characterized in that, The output voltage is converted from the input voltage by a conversion ratio defined by a numerator representing the output voltage and equal to one of 1, 2, 4, 5, 7, and 8, and a denominator representing the input voltage and equal to 9.

5. The switched capacitor power converter according to claim 1, characterized in that, Additionally, a controller is included, which is configured to control a corresponding subset of the plurality of switches for each of the four non-overlapping phases.

6. A method for operating a switched capacitor power converter, the switched capacitor power converter comprising: A first capacitor, the first capacitor including a first top plate and a first bottom plate; The second capacitor includes a second top plate and a second bottom plate; The third capacitor includes a third top plate and a third bottom plate; Input, the input including input voltage; The output includes the output voltage; The method includes one of the following (1) to (3): (1) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second top plate, and the second base plate is connected to ground. During the second phase, the output is connected to the second base plate, the second top plate is connected to the first top plate, the first base plate is connected to the third top plate, and the third base plate is connected to the ground. During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the ground. During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second base plate, the second top plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is one-tenth of the input voltage; (2) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third bottom plate, and the third top plate is connected to the input. During the third phase, the output is connected to the third top plate, the third bottom plate is connected to the first top plate, and the first bottom plate is connected to the ground. During the fourth phase, the output is connected to the first base plate, the first top plate is connected to the third top plate, the third base plate is connected to the second top plate, and the second base plate is connected to the ground, wherein the output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage; (3) During the first phase, the output is connected to the first base plate, the first top plate is connected to the second base plate, and the second top plate is connected to the input. During the second phase, the output is connected to the second top plate, the second bottom plate is connected to the first top plate, the first bottom plate is connected to the third top plate, and the third bottom plate is connected to the ground. During the third phase, the output is connected to the third base plate, the third top plate is connected to the first top plate, and the first base plate is connected to the input. During the fourth phase, the output is connected to the third base plate, the third top plate is connected to the second top plate, the second base plate is connected to the first base plate, and the first top plate is connected to the input, wherein the output voltage is converted from the input voltage, and the output voltage is seven-tenths of the input voltage.

7. A power conversion system, characterized in that, include: The switched capacitor power converter according to any one of claims 1 to 5.

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