Display driving circuit for accelerating voltage output of counter data lines

Abstract

A display driving circuit includes: a gamma generator configured to output gamma voltages having different voltage levels to nodes; and a selector configured to select one of the nodes to which the gamma voltage is output and output the voltage of the selected node among the nodes. The display driving circuit further includes: a voltage regulator configured to selectively input a first current to the selected node among the nodes and output a second current from the selected node among the nodes based on the voltage of the selected node among the nodes, so as to adjust the voltage level of the voltage of the selected node among the nodes to the voltage level of the corresponding gamma voltage output to the selected node among the nodes among the gamma voltages.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0094993, filed on August 5, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display driving circuit, and more particularly, to a source driver for accelerating the voltage output to a data line. Background art

[0004] A display device can provide an image to a user. For example, a display device may include an electronic device such as a smartphone, a tablet computer, a portable multimedia player, a laptop personal computer, a wearable device, and the like.

[0005] Recently, the demand for high - resolution images such as high - definition (HD) images and ultra - high - definition (UHD) images in display devices is increasing. As the resolution of a display panel increases from high - definition (HD) to ultra - high - definition (UHD), the line time decreases. Therefore, a source driver needs to adjust the level of an output voltage to a target level within a shorter time period. Summary of the invention

[0006] According to an embodiment, a display driving circuit includes: a gamma generator configured to output gamma voltages having different voltage levels to nodes; and a selector configured to select one of the nodes to which the gamma voltages are output and output the voltage of the selected node among the nodes. The display driving circuit further includes: a voltage regulator configured to selectively input a first current to the selected node among the nodes and output a second current from the selected node among the nodes based on the voltage of the selected node among the nodes, so as to adjust the voltage level of the voltage of the selected node among the nodes to the voltage level of the corresponding gamma voltage output to the selected node among the nodes among the gamma voltages.

[0007] According to an embodiment, a display driving circuit includes a gamma generator configured to output a first gamma voltage having a first voltage level to a first node and output a second gamma voltage having a second voltage level to a second node, the second voltage level being higher than the first voltage level. The display driving circuit further includes: a selector configured to output a second node voltage of the second node to which the second gamma voltage is output after outputting a first node voltage of the first node to which the first gamma voltage is output; and a voltage regulator configured to input a first current to the second node to which the second gamma voltage is output based on the voltage level of the second node voltage being lower than a first reference level. The first reference level is between a level higher than the second voltage level by a threshold level and a level lower than the second voltage level by a threshold level.

[0008] According to an embodiment, a display driving circuit includes a gamma generator configured to output a first voltage having a first voltage level to a first node and output a second voltage having a second voltage level to a second node, the second voltage level being higher than the first voltage level. The display driving circuit further includes: a selector configured to output a first node voltage of the first node to which the first voltage is output after outputting a second node voltage of the second node to which the second voltage is output; and a voltage regulator configured to output a first current from the first node to which the first voltage is output based on the voltage level of the first node voltage being higher than a first reference level. The first reference level is between a level higher than the first voltage level by a threshold level and a level lower than the first voltage level by a threshold level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a configuration of an electronic device including a display driving circuit according to an embodiment.

[0010] Figure 2 is a block diagram showing a configuration of a source driver according to an embodiment.

[0011] Figure 3 is a block diagram showing a voltage regulator according to an embodiment.

[0012] Figure 4 is a graph describing an operation of the source driver.

[0013] Figure 5 is a graph describing an operation effect of the source driver according to an embodiment.

[0014] Figure 6 is a block diagram showing a voltage regulator according to an embodiment.

[0015] Figure 7It is a flowchart describing the operation of a voltage regulator according to an embodiment.

[0016] Figure 8 It is a flowchart describing the operation of a voltage regulator according to an embodiment.

[0017] Figure 9 It is a block diagram showing the detailed configuration of a voltage regulator according to an embodiment.

[0018] Figure 10 It is a block diagram showing a voltage regulator according to an embodiment.

[0019] Figure 11 It is a block diagram showing a voltage regulator according to an embodiment.

[0020] Figure 12 It is a block diagram showing a voltage regulator according to an embodiment.

[0021] Figure 13 It is a block diagram showing a voltage regulator according to an embodiment.

[0022] Figure 14 It is a block diagram showing the configuration of an electronic device including a display driver circuit according to an embodiment. Detailed Description of the Invention

[0023] An embodiment provides a display driver circuit for accelerating the voltage output to a data line.

[0024] Hereinafter, embodiments will be described clearly and in detail so that those skilled in the art can implement the inventive concept.

[0025] Figure 1 It is a block diagram showing the configuration of an electronic device including a display driving circuit according to an embodiment.

[0026] The electronic device may include a display driver circuit 1000 and a display panel 2000. The electronic device may be a display device providing an image display function. For example, the electronic device may include one of electronic devices such as a smartphone, a tablet PC, a portable multimedia player, a laptop personal computer, a camera, an e - book reader, and a wearable device, etc.

[0027] The display driver circuit 1000 may include a timing controller 100, a gate driver 200, and a source driver 300. However, the embodiment is not limited thereto, and the timing controller 100 may be implemented on an integrated circuit chip different from the display driver circuit 1000.

[0028] The timing controller 100 may receive data and a timing signal from an external device (e.g., an application processor). The data received by the timing controller 100 may be data associated with an image displayed on the display panel 2000. The timing signal received by the timing controller 100 may be a signal for driving the gate driver 200 and the source driver 300. The timing controller 100 may generate data DATA, control signals CTRL1 and CTRL2, and a selection signal CLS based on the data and the timing signal.

[0029] The gate driver 200 may receive the control signal CTRL1. The gate driver 200 may sequentially output a gate-on signal to each of the gate lines GL1 to GL4 in response to the control signal CTRL1.

[0030] The source driver 300 may receive the data DATA, the control signal CTRL2, and the selection signal CLS. The source driver 300 may convert the data DATA into an image signal in response to the control signal CTRL2 and the selection signal CLS.

[0031] The source driver 300 may include level shifters 310 to 360, selectors 311 to 361, output amplifiers 312 to 362, a gamma generator 400, and a voltage regulator 500.

[0032] The level shifters 310, 320, 340 to 360, the selectors 311, 321, 341 to 361, and the output amplifiers 312, 322, 342 to 362 may provide operations substantially the same as the operations of the level shifter 330, the selector 331, and the output amplifier 332, respectively. Thus, for a better understanding of the embodiments, the operations of the level shifter 330, the selector 331, and the output amplifier 332 will be described in detail below.

[0033] The level shifter 330 may receive the data DATA. The level shifter 330 may generate a grayscale signal indicating the grayscale of the data DATA. The gamma generator 400 may generate a plurality of gamma voltages. The plurality of gamma voltages may each have a different voltage level. The selector 331 may receive the grayscale signal and the plurality of gamma voltages.

[0034] Selector 331 may sequentially output the gamma voltages corresponding to the grayscale signals among multiple gamma voltages. Specifically, the grayscale signal may be a digital signal. In this case, the grayscale signal may be composed of bits. For example, the grayscale signal may be a signal in which a first bit set and a second bit set are sequentially arranged. The first bit set and the second bit set may correspond to a first gamma voltage having a first voltage level and a second gamma voltage having a second voltage level, respectively. When receiving the grayscale signal, selector 331 may output the first gamma voltage in response to the first bit set, and then output the second gamma voltage in response to the second bit set.

[0035] Selector 331 may sequentially output gamma voltages (e.g., a first gamma voltage and a second gamma voltage) to output amplifier 332. Output amplifier 332 may output an image signal to data line DL3 in response to the received gamma voltage.

[0036] As the number of data lines DL1 to DL6 and gate lines GL1 to GL4 included in display panel 2000 increases, output amplifier 332 needs to output an image signal at high speed. To enable output amplifier 332 to output an image signal at high speed, selector 331 needs to output the gamma voltage corresponding to the grayscale signal at high speed. Based on voltage regulator 500, selector 331 according to an embodiment may output the gamma voltage corresponding to the grayscale signal at high speed. Specifically, voltage regulator 500 may quickly pull down or pull up the level of the voltage input to selector 331 to a target level.

[0037] Specifically, after outputting a first gamma voltage having a first voltage level from selector 331, voltage regulator 500 may operate to quickly adjust the level of the output voltage of selector 331 to a second voltage level. Accordingly, the line time of display driving circuit 1000 may be reduced. The line time may be associated with the time for inputting an input signal to a pixel in one of data lines DL1 to DL6. Although only one voltage regulator 500 is shown in Figure 1 the embodiment is not limited thereto. Source driver 300 may include one or more voltage regulators 500, and voltage regulator 500 may be located between some of selectors 311 to 361. The configuration and operation of voltage regulator 500 will be described in detail with reference to Figures 2 to 13 the following.

[0038] Display panel 2000 may include: gate lines GL1 to GL4 arranged in a horizontal direction (or row direction), data lines DL1 to DL6 arranged in a vertical direction (or column direction), and pixels (PX). Pixel PX may be located in an area where gate lines GL1 to GL4 and data lines DL1 to DL6 intersect each other. In Figure 1Among them, six data lines DL1 to DL6 and four gate lines GL1 to GL4 are shown, but the embodiments are not limited thereto. The electronic device may include a plurality of data lines and a plurality of gate lines.

[0039] The display panel 2000 may receive a gate-on signal and an image signal. The pixels PX may receive the image signals respectively. The pixels among the pixels PX that are located in the gate lines through which the gate-on signal is received may output optical signals corresponding to the image signals. The display panel 2000 may display an image to a user based on the optical signals output from the pixels.

[0040] Figure 2 is a block diagram showing a configuration of a source driver according to an embodiment. Components of the source driver 300a may provide operations similar to those of Figure 1 the source driver 300.

[0041] The source driver 300a may include level shifters 310 to 330, selectors 311 to 331, output amplifiers 312 to 332, a gamma generator 400, voltage regulators 500 to 502, and parasitic circuits 600 to 602. In Figure 2 it, only the components located on the left side of the gamma generator 400 are shown, but the embodiments are not limited thereto. The level shifters, selectors, output amplifiers, voltage regulators, and parasitic circuits may also be located on the right side of the gamma generator 400, similar to Figure 1 the case shown in.

[0042] The source driver 300a may include three voltage regulators 500 to 502. However, the embodiments are not limited thereto, and the source driver 300a may include one or more voltage regulators to output an image signal at high speed. Additionally, the source driver 300a may selectively include some of the three voltage regulators 500 to 502.

[0043] As described with reference to Figure 1 the description of, the operations of the level shifter 330, the selector 331, and the output amplifier 332 will be described in detail with reference to Figure 2 The level shifters 310 and 320, the selectors 311 and 321, and the output amplifiers 312 and 322 may respectively provide operations substantially the same as those of the level shifter 330, the selector 331, and the output amplifier 332.

[0044] In the following description, it is assumed that the selector 331 outputs a first gamma voltage having a first voltage level for a period of time and then outputs a second gamma voltage having a second voltage level for a period of time. The selector 331 can output the first gamma voltage and then output the second gamma voltage in response to a grayscale signal in which a first bit set and a second bit set are sequentially arranged. In the following description, for better understanding of the embodiments, the level shifter 330 is shown as outputting the second bit set after a period of time after outputting the first bit set. When the second bit set is received, the selector 331 starts an operation for outputting the second gamma voltage. For better understanding of the embodiments, the voltage intended to be input from the selector 331 to the output amplifier 332 is represented as a target voltage. Additionally, the level of the target voltage is represented as a target level.

[0045] The source driver 300a may include parasitic circuits 600 to 602. Due to the parasitic circuits 600 to 602, there may be a delay in transmitting the gamma voltage generated by the gamma generator 400 to the output amplifiers 312 to 332. The parasitic circuits 600 to 602 may each include a parasitic resistor and a parasitic capacitor. In the following description, for ease of description, the voltage drop due to the resistance of the parasitic circuit 600 is ignored.

[0046] When the selector 331 outputs the first gamma voltage, the voltage level of the node n0 may be the first voltage level. In the following description, the level of the voltage of the node n0 is represented as the voltage level of the node n0. When the selector 331 outputs the first gamma voltage, the charge corresponding to the first gamma voltage may be charged in the capacitor of the parasitic circuit 600. Therefore, after the selector 331 receives the second bit set, there may be a delay in adjusting the voltage level of the node n0 from the first voltage level to the second voltage level. Additionally, the charge may be charged in the capacitors of the parasitic circuits 601 and 602. The charge charged in the capacitors of the parasitic circuits 601 and 602 may be associated with the gamma voltages input to the output amplifiers 312 and 322. The delay may continue until the voltage of the node n0 is adjusted by the charge charged in the capacitors of the parasitic circuits 601, 602, and 600. The voltage regulator 500 can shorten the delay time that occurs when the voltage level of the node n0 is adjusted from the first voltage level to the second voltage level. The operation of the voltage regulator 500 for shortening the delay time will be described in detail with reference to Figure 3 Describe in detail the operation of the voltage regulator 500 for shortening the delay time.

[0047] Parasitic circuits may also exist between the selectors 311 and 321 and the output amplifiers 312 and 322. Therefore, the delay may continue until the target voltage is input to the output amplifiers 312 and 322. The voltage regulators 500 and 501 may shorten the delay time for inputting the target voltage to the output amplifier 322. Additionally, the voltage regulators 500, 501, and 502 may shorten the delay time for inputting the target voltage to the output amplifier 312.

[0048] The number and position of the voltage regulators included in the source driver 300a may be determined by comprehensively considering the size, price, effect, etc. of the voltage regulators. In order to quickly output the image signal to the data lines DL1 to DL3, the area of the source driver 300a may be reduced by using the voltage regulators 500 to 502 instead of using multiple gamma generators. Additionally, by using the voltage regulators 500 to 502 to reduce the time taken for the gamma voltage output from the gamma generator 400 to be transmitted to the output amplifier 312, the time difference between the time when the image signal is output to the data line DL1 and the time when the image signal is output to the data line DL2 may be reduced. That is, the source driver 300a according to the embodiment may uniformly adjust the time for outputting the voltage to the data lines.

[0049] Figure 3 is a block diagram showing a voltage regulator according to an embodiment.

[0050] Reference Figure 3 is made to describe in detail the voltage regulator 500 located between the gamma generator 400 and the selector 331. Therefore, for a better understanding of the embodiment, only some of the components of the source driver 300a shown in Figure 3 are shown in Figure 2 for the sake of simplicity.

[0051] The gamma generator 400 may output multiple gamma voltages v1 to v3 to the selector 331. The levels of the gamma voltages v1 to v3 may be a first voltage level, a second voltage level, and a third voltage level, respectively. The first voltage level may be lower than the second voltage level, and the second voltage level may be lower than the third voltage level. In Figure 3 only three gamma voltages v1 to v3 are given, but the embodiment is not limited thereto.

[0052] Selector 331 can be connected to gamma generator 400 through a plurality of connection lines w1 to w3. The plurality of connection lines w1 to w3 can be electric wires for transmitting electrical signals. Gamma voltages v1 to v3 output from gamma generator 400 can be input to selector 331 through the plurality of connection lines w1 to w3 respectively. Voltage regulator 500 can be located on the plurality of connection lines w1 to w3. Voltage regulator 500 can include voltage regulators 510 to 530. Specifically, voltage regulators 510 to 530 can be located on the plurality of connection lines w1 to w3 respectively.

[0053] Voltage regulators 510 to 530 are located Figure 3 on the plurality of connection lines w1 to w3 therein, but the embodiment is not limited thereto. Voltage regulator 500 can selectively include one or more of voltage regulators 510 to 530.

[0054] Each of voltage regulators 510 to 530 can provide an operation similar to that of voltage regulator 500. Voltage regulators 510 to 530 can reduce the delay time until the voltage level at node n0 is regulated to the target voltage level.

[0055] Level shifter 330 can output grayscale signal gs0. Grayscale signal gs0 can be a signal in which first bit set bs1, second bit set bs2, and third bit set bs3 are sequentially arranged. Bit sets bs1 to bs3 can correspond to gamma voltages v1 to v3 respectively. When the input bit set is received, selector 331 can start an operation for outputting a gamma voltage corresponding to the bit set.

[0056] Selector 331 can include a multiplexer for selectively outputting one of gamma voltages v1 to v3 input from the plurality of connection lines w1 to w3. However, the embodiment is not limited thereto, and selector 331 can be implemented by a combination of one or more decoders and one or more multiplexers. For example, when second bit set bs2 is input to selector 331 after first bit set bs1 is input to selector 331, selector 331 can start an operation for outputting second gamma voltage v2. When the first gamma voltage is output from selector 331, the voltage level at node n0 can be the first voltage level. Voltage regulator 520 can reduce the delay time until the voltage level at node n0 is regulated from the first voltage level to the second voltage level. That is, voltage regulators 510 to 530 can reduce the delay time until the voltage levels at node n0 are regulated to the first voltage level, the second voltage level, and the third voltage level respectively.

[0057] Figure 4It is a graph showing the operation of the source driver. The x-axis of the graph can represent time [s], and the y-axis of the graph represents voltage [v].

[0058] Before time t0, Figure 3 the selector 331 can output the first gamma voltage v1. At time t0, the selector 331 can receive Figure 3 the second bit set bs2. Therefore, the selector 331 can start operating to output the second gamma voltage v2 at time t0.

[0059] The graph illustration 710 shows the voltage level of the node n1 under ideal conditions Figure 3 Under ideal conditions, once the second bit set bs2 is input to the selector 331, the output amplifier 332 can output the second gamma voltage v2.

[0060] When Figure 3 the voltage regulator 520 does not operate, Figure 3 the voltage level of the node n0 is regulated to the second voltage level more slowly. The graph illustration 711 shows the voltage level of the node n0 when the voltage level of the node n0 is regulated to the second voltage level more slowly. The graph illustration 712 shows Figure 3 the voltage level of the node n1. Since the voltage level of the node n0 is regulated to the second voltage level more slowly, the voltage level of the node n1 is also regulated to the second voltage level more slowly.

[0061] Figure 5 It is a graph showing the operation effect of the source driver according to an embodiment.

[0062] As described in reference Figure 4 before time t0, Figure 3 the selector 331 can output the first gamma voltage v1. At time t0, the selector 331 can receive Figure 3 the second bit set bs2. Therefore, the selector 331 can start operating to output the second gamma voltage v2 at time t0.

[0063] As described in reference Figure 4 the graph illustration 710 shows the voltage level of the node n1 under ideal conditions Figure 3 of.

[0064] When Figure 3 the voltage regulator 520 operates, Figure 3 the voltage level of the node n0 can be regulated to the second voltage level more quickly. The graph illustration 713 shows the voltage level of the node n0 when the voltage level of the node n0 is regulated to the second voltage level more quickly. The graph illustration 714 shows Figure 3The voltage level of node n1. Since the voltage level of node n0 is rapidly adjusted to the second voltage level, the voltage level of node n1 can also be rapidly adjusted to the second voltage level.

[0065] As described in reference Figure 2 and Figure 3 The source driver 300a can more rapidly adjust the level of the voltage input to the output amplifier 332 (the voltage level of node n0) to the second voltage level by using the voltage regulator 520. That is, in reference Figure 4 and Figure 5 , the source driver 300a can rapidly adjust the level of the voltage output from the output amplifier 332 (the voltage level of node n1) by rapidly adjusting the level of the voltage input to the output amplifier 332 (the voltage level of node n0).

[0066] However, the operation effect of the source driver 300a is not limited to the operation effect described in reference Figure 4 . When the source driver 300a outputs the second gamma voltage v2 and then outputs the first gamma voltage v1, the source driver 300a can also rapidly adjust the voltage level of node n0 to the first voltage level. That is, the source driver 300a can rapidly adjust the voltage level of node n0 to the target level.

[0067] Figure 6 is a block diagram showing a voltage regulator according to an embodiment.

[0068] The voltage regulator 510 may include a sensing circuit 511, a voltage source 512, and an input circuit 513. Figure 6 The voltage regulator 520 may include sensing circuits 521 and 524, voltage sources 522 and 525, an input circuit 523, and an output circuit 526. In the following description, the configuration including the sensing circuit 521, the voltage source 522, and the input circuit 523 is denoted as the voltage regulator 520a. The configuration including the sensing circuit 524, the voltage source 525, and the output circuit 526 is denoted as the voltage regulator 520b. The voltage regulator 530 may include a sensing circuit 531, a voltage source 532, and an output circuit 533.

[0069] However, the embodiment is not limited thereto, and the voltage regulator 510 may not include the voltage source 512 and the input circuit 513. The voltage regulator 520 may not include the voltage sources 522 and 525, the input circuit 523, and the output circuit 526. The voltage regulator 530 may not include the voltage source 532 and the output circuit 533.

[0070] In the following, for a better understanding of the embodiments, the operations of the sensing circuits 521 and 524, the voltage sources 522 and 525, the input circuit 523, and the output circuit 526 will be described in detail. The sensing circuit 511 and the input circuit 513 may provide operations similar to those of the sensing circuit 521 and the input circuit 523. The sensing circuit 531 and the output circuit 533 may provide operations similar to those of the sensing circuit 524 and the output circuit 526.

[0071] When the first bit set bs1 and the second bit set bs2 are received sequentially, the selector 331 may output the first gamma voltage v1 and the second gamma voltage v2 sequentially. The voltage regulator 520a may rapidly regulate the voltage level of the node n0 from the first voltage level to the second voltage level. That is, the voltage regulator 520a may be used to rapidly increase the voltage level of the node n0.

[0072] The input circuit 523 may output the current I0 from the power supply node to the sensing circuit 521. The voltage of the power supply node may be the power supply voltage VDD. The level of the power supply voltage VDD may be higher than the third voltage level. The sensing circuit 521 may receive the current I0. The voltage source 522 may output the reference voltage vn0 to the sensing circuit 521. The sensing circuit 521 may compare the voltage of the node n2 with the voltage of the reference voltage vn0. The sensing circuit 521 may compare the voltage level of the node n2 with the first reference level of the reference voltage vn0. When the voltage level of the node n2 is lower than the first reference level, the sensing circuit 521 may output the current I0 to the node n2. When the voltage level of the node n2 is higher than or equal to the first reference level, the sensing circuit 521 may not output the current I0 to the node n2.

[0073] The first reference level may be determined based on the second voltage level. Specifically, the first reference level may be a level between a level higher than the second voltage level by the threshold level and a level lower than the second voltage level by the threshold level. As an example, the threshold level may be 1 volt.

[0074] The sensing circuit 521 outputs the current I0 to the node n2, thereby rapidly increasing the voltage level of the node n2 to the first reference level. After the voltage regulator 520a increases the voltage level of the node n2 to the first reference level, the voltage level of the node n2 may be increased to the second voltage level by the gamma generator 400. The first reference level may be a level higher than the second voltage level by the threshold level. In this case, the voltage regulator 520a may increase the voltage level of the node n2 to the second voltage level more rapidly.

[0075] That is, the voltage regulator 520a outputs a current I0 to the node n2, thereby rapidly increasing the voltage level of the node n2 to a second voltage level. Rapidly increasing the voltage level of the node n2 means rapidly increasing the voltage level of the node n0 to the second voltage level. Similar to the voltage regulator 520a, the voltage regulator 510 can rapidly adjust the voltage level of the node n0 to a first voltage level.

[0076] As described in the reference Figure 2 When the selector 331 starts the operation for outputting the second gamma voltage v2, the capacitor of the parasitic circuit 600 can be charged with the charge corresponding to the first voltage level of the first gamma voltage. The sensing circuit 521 can shorten the delay caused by the capacitor of the parasitic circuit 600.

[0077] When the third bit set bs3 and the second bit set bs2 are sequentially received, the selector 331 can sequentially output the third gamma voltage v3 and the second gamma voltage v2. The voltage regulator 520b can rapidly adjust the voltage level of the node n0 from a third voltage level to a second voltage level. That is, the voltage regulator 520b can be used to rapidly decrease the voltage level of the node n0.

[0078] The voltage source 525 can output a reference voltage vp0 to the sensing circuit 524. The sensing circuit 524 can compare the voltage of the node n2 with the reference voltage vp0. The sensing circuit 524 can compare the second reference level of the reference voltage vp0 with the voltage level of the node n2. When the voltage level of the node n2 is higher than the second reference level, the sensing circuit 524 can output a current I1 from the node n2 to the output circuit 526. The output circuit 526 can output the current I1 to the ground. The voltage of the ground can be the ground voltage VSS. The level of the ground voltage VSS can be lower than the first voltage level. When the voltage level of the node n2 is lower than or equal to the second reference level, the sensing circuit 521 can not output the current I1 to the output circuit 526.

[0079] The second reference level can be determined based on the second voltage level. Specifically, the second reference level can be a level between a level higher than the second voltage level by a threshold level and a level lower than the second voltage level by the threshold level. As an example, the threshold level can be 1 volt.

[0080] The sensing circuit 524 outputs a current I1 from node n6, thereby rapidly reducing the voltage level of node n2 to a second reference level. After the voltage regulator 520b reduces the voltage level of node n2 to the second reference level, the voltage level of node n2 can be reduced to a second voltage level by the gamma generator 400. The second reference level can be a level that is lower than the second voltage level by a threshold level. In this case, the voltage regulator 520b can reduce the voltage level of node n2 to the second voltage level more rapidly.

[0081] That is, the voltage regulator 520b outputs a current I1 from node n2, thereby rapidly reducing the voltage level of node n2 to the second voltage level. Rapidly reducing the voltage level of node n2 to the second voltage level means rapidly reducing the voltage level of node n0 to the second voltage level. Similar to the voltage regulator 520b, the voltage regulator 530 can rapidly adjust the voltage level of node n0 to a third voltage level.

[0082] When the selector 331 starts the operation for outputting the second gamma voltage v2, a charge corresponding to the third voltage level of the third gamma voltage can be used to charge the capacitor of the parasitic circuit 600. The sensing circuit 521 can shorten the delay caused by the capacitor of the parasitic circuit 600.

[0083] Different from Figure 6 as shown in, the voltage regulator 510 may also include components that provide an operation similar to that of the voltage regulator 520b. However, when the first voltage level is the lowest level among the levels of the gamma voltages generated by the gamma generator 400, the voltage regulator 510 may not include additional components.

[0084] Different from Figure 6 as shown in, the voltage regulator 530 may also include components that provide an operation similar to that of the voltage regulator 520a. However, when the third voltage level is the highest level among the levels of the gamma voltages generated by the gamma generator 400, the voltage regulator 530 may not include additional components.

[0085] In addition, by including only one or more of the voltage regulators 510, 520a, 520b, and 530, the voltage regulator 500 can rapidly adjust the voltage level of node n0 to a target level.

[0086] Figure 7 is a flowchart illustrating the operation of a voltage regulator according to an embodiment. Referring to Figure 7 , will be described Figure 6 the operation of the voltage regulator 520a.

[0087] As described with reference to Figure 6 as described, whenFigure 6 When the voltage level of node n0 of Figure 7 is adjusted from a level higher than the second voltage level to the second voltage level, the voltage regulator 520a can be used. Therefore, in the reference

[0088] In operation S110, Figure 6 the selector 331 of Figure 6 can receive the grayscale signal gs0. Specifically,

[0089] the selector 331 of Figure 6 can receive the second bit set bs2 included in the grayscale signal gs0. When receiving the second bit set bs2, the selector 331 can start the operation for outputting the second gamma voltage v2 to node n0.

[0090] When the voltage level of node n2 is lower than the first reference level, the process proceeds to operation S130. In operation S130, the sensing circuit 521 can output the current I0 to node n2. The current I0 can be output from the power supply node. The sensing circuit 521 can receive the current I0 output from the power supply node through Figure 6 the input circuit 513 of

[0091] In this case, the voltage level of node n2 can rapidly increase to the first reference level through the current I0. Of course, the second gamma voltage v2 can also be used to increase the voltage level of node n2 to the first reference level.

[0092] Figure 8 is a flowchart describing the operation of the voltage regulator according to an embodiment. Referring to Figure 8 will describe Figure 6 the operation of the voltage regulator 520b of

[0093] As described in the reference Figure 6 when the voltage level of node n0 of Figure 6 is adjusted from a level lower than the second voltage level to the second voltage level, the voltage regulator 520b can be used. Therefore, in the referenceFigure 8 In the description, it is assumed that the voltage level of node n0 is adjusted to a level lower than the second voltage level.

[0094] In operation S210, Figure 6 selector 331 of can receive grayscale signal gs0. Specifically, Figure 6 selector 331 of can receive second bit set bs2 included in grayscale signal gs0. When receiving second bit set bs2, selector 331 can start an operation for outputting second gamma voltage v2 to node n0.

[0095] In operation S220, Figure 6 sensing circuit 524 of can compare the voltage of node n2 with reference voltage vp0 to determine whether to output current I1 to ground.

[0096] When the voltage level of node n2 is higher than the second reference level, the process proceeds to operation S230. In operation S230, sensing circuit 524 can output current I1 from node n2. The current I1 output from node n2 can pass through Figure 6 output circuit 526 of and is transmitted to ground. In this case, the voltage level of node n2 can rapidly decrease to the second reference level through current I1. Of course, second gamma voltage v2 can also be used to decrease the voltage level of node n2 to the second reference level.

[0097] When the voltage level of node n2 is lower than the second reference level, the process proceeds to operation S240. In operation S240, sensing circuit 524 can not output current I1 from node n2. In this case, the voltage level of node n2 can be a level between the second reference level and the second voltage level. Second gamma voltage v2 can be output to node n2. Due to second gamma voltage v2, the voltage level of node n2 can decrease to the second voltage level.

[0098] Figure 9 is a block diagram showing a detailed configuration of a voltage regulator according to an embodiment. Components 521a, 523a, 524a, and 526a can provide operations substantially the same as those of Figure 6 components 521, 523, 524, and 526 of.

[0099] The input circuit 523a may include a transistor TR1. However, the embodiment is not limited thereto, and the input circuit 523a may include a resistor instead of the transistor TR1. Specifically, the transistor TR1 may be a PMOS transistor. The ground voltage VSS may be input to the gate terminal of the transistor TR1. The source terminal of the transistor TR1 may be connected to the power supply node, and the drain terminal of the transistor TR1 may be connected to the sensing circuit 521a. Since the level of the power supply voltage VDD is higher than the level of the ground voltage VSS, the current I0 may be output from the power supply node to the sensing circuit 521a through the transistor TR1.

[0100] The sensing circuit 521a may include a transistor TR2. Specifically, the transistor TR2 may be an NMOS transistor. The gate terminal of the transistor TR2 may be connected to the voltage source 522. The reference voltage vn0 may be input to the gate terminal of the transistor TR2. The drain terminal of the transistor TR2 may be connected to the input circuit 523a, and the source terminal of the transistor TR2 may be connected to the node n2. When the voltage level of the node n2 is lower than the first reference level of the reference voltage vn0, the current I0 may be output to the node n2 through the transistor TR2. Specifically, the voltage level of the node n2 may be lower than the voltage level obtained by subtracting the threshold voltage from the reference voltage vn0. However, for ease of description, when the voltage level of the node n2 is lower than the first reference level, it is indicated that the current I0 is output to the node n2. However, since the actual situation is that the current I0 is output when the voltage level of the node n2 is lower than the voltage level obtained by subtracting the threshold voltage from the reference voltage vn0, the first reference level may be set to a level higher than the second voltage level. When the voltage level of the node n2 is lower than the second voltage level, the voltage level of the node n2 may be rapidly increased to the second voltage level by the current I0 and the second gamma voltage v2.

[0101] The sensing circuit 524a may include a transistor TR3. Specifically, the transistor TR3 may be a PMOS transistor. The gate terminal of the transistor TR3 may be connected to a voltage source 525. A reference voltage vp0 may be input to the gate terminal of the transistor TR3. The drain terminal of the transistor TR3 may be connected to the output circuit 526a, and the source terminal of the transistor TR3 may be connected to the node n2. When the voltage level of the node n2 is higher than a second reference level of the reference voltage vp0, a current I1 may be output from the node n2 to the output circuit 526a through the transistor TR3. Specifically, the voltage level of the node n2 may be higher than the voltage level obtained by adding a threshold voltage to the reference voltage vp0. However, for ease of description, when the voltage level of the node n2 is higher than the second reference level, an output current I1 is indicated. However, since the actual situation is that the output current I1 when the voltage level of the node n2 is higher than the voltage level obtained by adding the threshold voltage to the reference voltage vp0, the second reference level may be set to a level lower than the second voltage level.

[0102] The output circuit 526a may include a transistor TR4. However, the embodiment is not limited thereto, and the output circuit 526a may include a resistor instead of the transistor TR4. Specifically, the transistor TR4 may be an NMOS transistor. A power supply voltage VDD may be input to the gate terminal of the transistor TR4. The source terminal of the transistor TR4 may be grounded, and the drain terminal of the transistor TR4 may be connected to the sensing circuit 524a. Since the level of the power supply voltage VDD is higher than the level of the ground voltage VSS, the current I1 may be output to the ground through the transistor TR4.

[0103] When the voltage level of the node n2 is higher than the second voltage level, through the current I1, the voltage level of the node n2 may rapidly decrease to the second voltage level.

[0104] Figure 10 is a block diagram showing a voltage regulator according to an embodiment. Different from Figure 9 in, in Figure 10 a reference voltage vn0 and vp0 are output from the voltage generator 522a. However, in addition to outputting the reference voltage vn0 and vp0 from the voltage generator 522a, Figure 10 the components shown in Figure 9 provide operations similar to those of the components shown in

[0105] The voltage generator 522a may receive power supply voltages vs1 to vs9. The power supply voltages vs1 to vs9 may be analog voltages or digital voltages. It may be by Figure 2The components of the source driver 300a provide the power supply voltages vs1 to vs9, or the power supply voltages vs1 to vs9 can be provided from outside the source driver 300a. Although nine power supply voltages vs1 to vs9 are shown in Figure 10 , the embodiment is not limited thereto. The voltage generator 522a can receive a plurality of power supply voltages.

[0106] The voltage generator 522a can receive the control signal cs0. The voltage generator 522a can output the reference voltage vn0 or the reference voltage vp0 in response to the control signal cs0. The voltage generator 522a can adjust the first reference level of the reference voltage vn0 or the second reference level of the reference voltage vp0 based on the information included in the control signal cs0. However, the first reference level can be greater than or equal to the second voltage level, and the second reference level can be less than or equal to the second voltage level.

[0107] The sensing circuit 521a can determine whether to output the current I0 by comparing the first reference level with the voltage level of the node n2. The first reference level can be adjusted based on the control signal cs0. For example, the first reference level can also vary according to the operation mode of the source driver 300a. In the operation mode for adjusting the voltage level of the node n2 to the second voltage level as quickly as possible, the first reference level can be adjusted to the second voltage level. That is, the sensing circuit 521a can operate based on the reference voltage vn0, which has different levels according to the operation mode of the source driver 300a.

[0108] Specifically, the reference voltage vn0 can be input to the gate terminal of the transistor TR2. When the voltage level of the node n2 is lower than the first reference level of the reference voltage vn0, the transistor TR2 can output the current I0. When the voltage level of the node n2 is higher than the first reference level of the reference voltage vn0, the transistor TR2 can not output the current I0.

[0109] In addition, the sensing circuit 524a can compare the adjusted second reference level with the voltage level of the node n2 to determine whether to output the current I1. The second reference level can be adjusted based on the control signal cs0. For example, in the operation mode for adjusting the voltage level of the node n2 to the second voltage level as quickly as possible, the first reference level can be adjusted to the second voltage level. That is, the sensing circuit 524a can operate based on the reference voltage vp0, which has different levels according to the operation mode of the source driver 300a.

[0110] Specifically, a reference voltage vp0 can be input to the gate terminal of transistor TR3. When the voltage level of node n2 is higher than a second reference level of the reference voltage vp0, transistor TR3 can output a current I1. When the voltage level of node n2 is lower than the second reference level of the reference voltage vp0, transistor TR3 may not output the current I1.

[0111] Figure 11 is a block diagram showing a voltage regulator according to an embodiment. Different from Figure 9 in, in Figure 11 sensing circuits 521a and 524a receive a second gamma voltage v2. However, except that sensing circuits 521a and 524a receive the second gamma voltage v2 instead of the reference voltages vn0 and vp0, Figure 11 the components shown in Figure 9 provide operations similar to those of the components shown in

[0112] Gamma generator 400 can output the second gamma voltage v2 to node n3. Hereinafter, for ease of explanation, it is assumed that the voltage level of node n3 is maintained at a second voltage level. It is also assumed that the second gamma voltage v2 is output from node n3.

[0113] Sensing circuit 521a can be connected to node n3. Sensing circuit 521a can receive the second gamma voltage v2 from node n3. Sensing circuit 521a can compare the second voltage level with the voltage level of node n2 to determine whether to output a current I0. Specifically, the gate terminal of transistor TR2 can be connected to node n3. When the voltage level of node n2 is lower than the second voltage level, transistor TR2 can output a current I0. When the voltage level of node n2 is higher than the second voltage level, transistor TR2 may not output the current I0.

[0114] Sensing circuit 524a can be connected to node n3. Sensing circuit 524a can receive the second gamma voltage v2 from node n3. Sensing circuit 524a can compare the second voltage level with the voltage level of node n2 to determine whether to output a current I1. Specifically, the gate terminal of transistor TR3 can be connected to node n3. When the voltage level of node n2 is higher than the second voltage level, transistor TR3 can output a current I1. When the voltage level of node n2 is lower than the second voltage level, transistor TR3 may not output the current I1.

[0115] That is, referring to Figure 11 the described embodiment may not include a separate voltage source for providing the reference voltages vn0 and vp0. According to the embodiment described with reference to Figure 11 since gamma generator 400 is used to provide the reference voltages vn0 and vp0, the area, cost, etc. of the voltage source can be reduced.

[0116] Figure 12 is a block diagram showing a voltage regulator according to an embodiment. Different from that shown in Figure 11 , a buffer 528 is also shown in Figure 12 . However, except that the second gamma voltage v2 is received by the sensing circuits 521a and 524a through the buffer 528, Figure 11 the components shown in Figure 10 can provide operations similar to those shown in

[0117] The gamma generator 400 can output the second gamma voltage v2 to the node n3.

[0118] The positive input terminal of the buffer 528 can be connected to the node n3. That is, the second gamma voltage v2 can be received by the positive input terminal of the buffer 528. The negative input terminal of the buffer 528 can be connected to the node n4. The node n4 can be connected to the output terminal of the buffer 528. That is, the negative input terminal of the buffer 528 can be connected to the output terminal of the buffer 528.

[0119] Therefore, the buffer 528 can output the second gamma voltage v2 to the node n4 through a feedback operation. The node n4 can be connected to the node n5. Assuming no voltage drop occurs between the node n4 and the node n5. Therefore, the voltage level of the node n5 can be the same as the voltage level of the node n4. That is, the second gamma voltage v2 can be output from the node n5 to the sensing circuits 521a and 524a.

[0120] The sensing circuit 521a can be connected to the node n5. The sensing circuit 521a can receive the second gamma voltage v2 from the node n5. The sensing circuit 521a can compare the second voltage level with the voltage level of the node n2 to determine whether to output the current I0. Specifically, the gate terminal of the transistor TR2 can be connected to the node n5. When the voltage level of the node n2 is lower than the second voltage level, the transistor TR2 can output the current I0. When the voltage level of the node n2 is higher than the second voltage level, the transistor TR2 can not output the current I0.

[0121] The sensing circuit 524a can be connected to the node n5. The sensing circuit 524a can receive the second gamma voltage v2 from the node n5. The sensing circuit 524a can compare the second voltage level with the voltage level of the node n2 to determine whether to output the current I1. Specifically, the gate terminal of the transistor TR3 can be connected to the node n5. When the voltage level of the node n2 is higher than the second voltage level, the transistor TR3 can output the current I1. When the voltage level of the node n2 is lower than the second voltage level, the transistor TR3 can not output the current I1.

[0122] Reference Figure 12 The described embodiment may also include a buffer 528. Accordingly, the second gamma voltage v2 can be provided to the sensing circuits 521a and 524a more stably.

[0123] Figure 13 is a block diagram showing a voltage regulator according to an embodiment.

[0124] Reference Figure 13 , different from the description of the reference Figure 6 , voltage regulators 520c and 520d including comparators 521b and 524b will be described. However, except for the operations associated with the comparators 521b and 524b, the voltage regulators 520c and 520d provide operations similar to those of the Figure 6 voltage regulators 520a and 520b. Repeated descriptions will be omitted hereinafter, and the operations related to the comparators 521b and 524b will be mainly described.

[0125] The voltage regulator 520c may include a comparator 521b, a voltage source 522, and an input circuit 523b.

[0126] The comparator 521b may receive a reference voltage vn0 from the voltage source 522. The comparator 521b may compare the voltage level of node n6 with the reference voltage vn0. In the following description, it is assumed that the voltage level of node n6 is the same as the voltage level of node n7. As described in the reference Figure 3 , the voltage levels of node n6 and node n7 may be affected by the parasitic circuit 600, and thus the second voltage level of the second gamma voltage v2 may not be maintained.

[0127] When the first reference level is higher than the voltage level of node n6, the comparator 521b may output a control signal cs1. When receiving the control signal cs1, the input circuit 523b may output a current I0 to node n7. As an example, the input circuit 523b may include a current source. As another example, the input circuit 523b may include a device such as a resistor or a transistor, and in this case, the current I0 may be output to node n7 based on the power supply voltage VDD.

[0128] When the first reference level is less than or equal to the voltage level of node n6, the comparator 521b may not output the control signal cs1. When not receiving the control signal cs1, the input circuit 523b may not output the current I0 to node n7.

[0129] However, the embodiments are not limited thereto, and when the first reference level is higher than the voltage level of node n6, comparator 521b may output a control signal cs1 having a first logic value. In this case, input circuit 523b may output current I0 to node n7 in response to control signal cs1 having a first logic value. When the first reference level is less than or equal to the voltage level of node n6, comparator 521b may output a control signal cs1 having a second logic value. In this case, in response to control signal cs1 having a second logic value, input circuit 523b may not output current I0 to node n7.

[0130] However, the embodiments are not limited thereto, and voltage regulators 520c and 520d may not include voltage sources 522 and 525. In this case, similar to the reference Figures 10 to 12 described, voltage regulators 520c and 520d may receive reference voltages vn0 and vp0. Specifically, similar to the reference Figure 10 described, voltage regulators 520c and 520d may receive reference voltages vn0 and vp0 from Figure 10 voltage generator 522a of. Similar to the reference Figure 11 described, voltage regulators 520c and 520d may receive a second gamma voltage v2 instead of reference voltages vn0 and vp0. In this case, voltage regulators 520c and 520d may determine whether to output currents I0 and I1 by comparing the second voltage level of second gamma voltage v2 with the voltage level of node n6. Similar to the reference Figure 12 described, voltage regulators 520c and 520d may include Figure 12 buffer 528 of. In this case, by using buffer 528, voltage regulators 520c and 520d receive second gamma voltage v2 instead of reference voltages vn0 and vp0, and receive second gamma voltage v2 more stably.

[0131] Figure 14 is a block diagram showing the configuration of an electronic device including a display driver circuit according to an embodiment. For example, electronic device 10000 may be implemented as one of various types of electronic devices, such as a smartphone, a tablet personal computer, a laptop personal computer, an e-book reader, an MP3 player, a wearable device, etc.

[0132] Electronic device 10000 may include various electronic circuits. For example, the electronic circuits of electronic device 10000 may include display device 1800, image processing block 1100, communication block 1200, audio processing block 1300, buffer memory 1400, non-volatile memory 1500, user interface 1600, and main processor 1700.

[0133] The display device 1800 may receive data from an external device (e.g., the main processor 1700). Based on the received data, the display driver circuit 1000 included in the display device 1800 may display an image on the display panel 2000.

[0134] The display driver circuit 1000 may output an image signal to the display panel 2000 such that the image is displayed on the display panel 2000. Outputting the image signal to the display panel 2000 means outputting a voltage corresponding to the image signal to the display panel 2000. By using the voltage regulator 500, the display driver circuit 1000 may quickly output a voltage corresponding to the image signal.

[0135] The image processing block 1100 may receive light through the lens 1110. Based on the received light, the image sensor 1120 and the image signal processor 1130 included in the image processing block 1100 may generate image data related to an external object.

[0136] The communication block 1200 may exchange signals with an external device / system through the antenna 1210. Based on various wireless communication protocols, the transceiver 1220 and the modem 1230 (modulator / demodulator) of the communication block 1200 may process the signals exchanged with the external device / system.

[0137] By using the audio signal processor 1310, the audio processing block 1300 may process sound information to reproduce and output audio. The audio processing block 1300 may receive an audio input through the microphone 1320. The audio processing block 1300 may output the reproduced audio through the speaker 1330.

[0138] The buffer memory 1400 may store data for the operation of the electronic device 10000. For example, the buffer memory 1400 may temporarily store data processed or to be processed by the main processor 1700. For example, the buffer memory 1400 may include volatile memories such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. and / or non-volatile memories such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.

[0139] The non-volatile memory 1500 can store data regardless of the power supply. For example, the non-volatile memory 1500 can include any one or any combination of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. For example, the non-volatile memory 1500 can include a removable memory such as a Secure Digital (SD) card and / or an embedded memory such as an embedded multimedia card (eMMC).

[0140] The user interface 1600 can mediate communication between the user and the electronic device 10000. For example, the user interface 1600 can include an input interface, such as a keypad, buttons, a touch screen, a touchpad, a gyro sensor, a vibration sensor, an acceleration sensor, etc. For example, the user interface 1600 can include an output interface, such as a motor, an LED lamp.

[0141] The main processor 1700 can control the overall operation of the components of the electronic device 10000. The main processor 1700 can process various operations to operate the electronic device 10000. For example, the main processor 1700 can be implemented as an arithmetic processing unit / circuit including one or more processor cores, such as a general-purpose processor, a dedicated processor, an application processor, a microprocessor, etc.

[0142] For example, the main processor 1700 can send data to the display driver circuit 1000. Based on the data, the display driver circuit 1000 can drive the display panel 2000 to display an image on the display panel 2000.

[0143] As another example, the user can set the operation mode of the display device 1800 through the user interface 1600. Based on the operation mode set by the user, the main processor 1700 can control the type of data sent to the display driver circuit 1000 or the speed of the data sent to the display driver circuit 1000. Based on the type of the received data or the speed of the received data, the display driver circuit 1000 can control the path of processing the data.

[0144] However, providing Figure 14 the components shown in Figure 14 is not intended to limit the embodiments in order to enable better understanding. The electronic device 10000 may not include Figure 14 one or more of the components shown in

[0145] and may additionally or alternatively include at least one component not shown in

[0146] As is common in the field of inventive concepts, embodiments are described around functional blocks, units, and / or modules and shown in the drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., where the electronic (or optical) circuits can be formed using semiconductor-based manufacturing technology or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, the blocks, units, and / or modules can be programmed with software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions. In addition, without departing from the scope of the inventive concept, each block, unit, and / or module of the embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules. In addition, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0147] The above content is for implementing the embodiments of the inventive concept. The inventive concept can include not only the above embodiments, but also embodiments that can be simply or easily changed in design. Additionally, the inventive concept can also include technologies that are easily changed to use the embodiments for implementation. Therefore, the scope of the inventive concept is not limited to the described embodiments, but can be defined by the claims and their equivalents.

Claims

1. A display driving circuit, comprising: a gamma generator configured to output gamma voltages having different voltage levels to nodes; a selector configured to: select one of the nodes to which the gamma voltage is output; and output the voltage of the selected node among the nodes; and a voltage regulator electrically connected between an output terminal of the gamma generator and an input terminal of the selector, and configured to: selectively input a first current to the selected node among the nodes or output a second current from the selected node among the nodes based on the voltage of the selected node among the nodes, so as to adjust the voltage level of the voltage of the selected node among the nodes to the voltage level of the corresponding gamma voltage output to the selected node among the nodes in the gamma voltages.

2. The display driving circuit according to claim 1, wherein the voltage regulator is further configured to: input the first current to the selected node among the nodes to pull up the voltage level of the selected node based on the voltage level of the voltage of the selected node among the nodes being lower than a first reference level; and output the second current from the selected node among the nodes to pull down the voltage level of the selected node based on the voltage level of the voltage of the selected node among the nodes being higher than a second reference level.

3. The display driving circuit according to claim 2, wherein the first reference level and the second reference level are between a level higher than the voltage level of the corresponding gamma voltage in the gamma voltages by a threshold level and a level lower than the voltage level of the corresponding gamma voltage in the gamma voltages by the threshold level.

4. The display driving circuit according to claim 3, wherein the first reference level is higher than the voltage level of the corresponding gamma voltage in the gamma voltages by the threshold level, and wherein the second reference level is lower than the voltage level of the corresponding gamma voltage in the gamma voltages by the threshold level.

5. A display driving circuit, comprising: a gamma generator configured to: output a first gamma voltage having a first voltage level to a first node; and output a second gamma voltage having a second voltage level higher than the first voltage level to a second node; a selector configured to output a second node voltage of the second node to which the second gamma voltage is output after outputting a first node voltage of the first node to which the first gamma voltage is output; and a voltage regulator electrically connected between an output terminal of the gamma generator and an input terminal of the selector, and configured to: input a first current to the second node to which the second gamma voltage is output based on the voltage level of the second node voltage being lower than a first reference level, wherein the first reference level is between a level higher than the second voltage level by a threshold level and a level lower than the second voltage level by the threshold level.

6. The display driving circuit according to claim 5, wherein the voltage regulator is further configured to: based on the voltage level of the second node voltage being lower than the first reference level, input the first current to the second node that outputs the second gamma voltage thereto to pull up the voltage level of the second node voltage, so that the second node voltage has the second voltage level through the second gamma voltage and the first current.

7. The display driving circuit according to claim 5, wherein the voltage regulator includes an NMOS transistor, and the NMOS transistor is configured to input the first current to the second node that outputs the second gamma voltage thereto, and wherein the first reference level is the level of the gate voltage of the NMOS transistor.

8. The display driving circuit according to claim 7, wherein the voltage regulator further includes a PMOS transistor, and the PMOS transistor is configured to input the first current into the NMOS transistor.

9. The display driving circuit according to claim 5, wherein the gamma generator is further configured to: output a third gamma voltage having a third voltage level higher than the second voltage level to a third node, wherein the selector is further configured to: after outputting the third node voltage of the third node that outputs the third gamma voltage thereto, output the second node voltage of the second node that outputs the second gamma voltage thereto, wherein the voltage regulator is further configured to: based on the voltage level of the second node voltage being higher than a second reference level, output a second current from the second node that outputs the second gamma voltage thereto, and wherein the second reference level is between a level higher than the second voltage level by the threshold level and a level lower than the second voltage level by the threshold level.

10. The display driving circuit according to claim 9, further comprising a voltage generator, and the voltage generator is configured to: combine a plurality of voltages; and based on the combined plurality of voltages, provide a first reference voltage having the first reference level and a second reference voltage having the second reference level to the voltage regulator.

11. The display driving circuit according to claim 10, wherein the voltage generator includes a multiplexer, and the multiplexer is configured to: receive the plurality of voltages; and output the first reference voltage and the second reference voltage based on the received plurality of voltages.

12. The display driving circuit according to claim 10, wherein the voltage generator is further configured to: adjust the first reference level and the second reference level based on a control signal.

13. A display driving circuit, comprising: a gamma generator configured to: output a first voltage having a first voltage level to a first node; and output a second voltage having a second voltage level to a second node, the second voltage level being higher than the first voltage level; A selector, configured to: output a first node voltage of a first node to which the first voltage is output after outputting a second node voltage of a second node to which the second voltage is output; and A voltage regulator, electrically connected between an output end of the gamma generator and an input end of the selector, and configured to: output a first current from the first node to which the first voltage is output based on a voltage level of the first node voltage being higher than a first reference level; wherein the first reference level is between a level higher than the first voltage level by a threshold level and a level lower than the first voltage level by the threshold level.

14. The display driving circuit according to claim 13, wherein the voltage regulator is further configured to: output the first current from the first node to which the first voltage is output to a ground to pull down the voltage level of the first node voltage based on the voltage level of the first node voltage being higher than the first reference level, such that the first node voltage has the first voltage level through the first voltage and the first current.

15. The display driving circuit according to claim 13, further comprising a voltage source configured to provide a first reference voltage having the first reference level to the voltage regulator, wherein the voltage regulator is further configured to compare the first node voltage with the provided first reference voltage to determine whether to output the first current from the first node.

16. The display driving circuit according to claim 13, wherein the first reference level is the first voltage level, and wherein the voltage regulator is further configured to: receive the output first voltage from the gamma generator; and compare the first node voltage with the received first voltage to determine whether to output the first current from the first node.

17. The display driving circuit according to claim 16, further comprising a buffer configured to: receive the output first voltage from the gamma generator; and output the received first voltage to the voltage regulator.

18. The display driving circuit according to claim 13, wherein the voltage regulator includes a PMOS transistor configured to output the first current from the first node to which the first voltage is output, and wherein the first reference level is a level of a gate voltage of the PMOS transistor.

19. The display driving circuit according to claim 18, wherein the voltage regulator further includes an NMOS transistor configured to output the first current output from the PMOS transistor to a ground.

20. The display driving circuit according to claim 18, wherein the voltage regulator further includes a comparator configured to compare the voltage level of the first node voltage with the first reference level to output a control signal; and The output circuit is configured to output the first current from the first node that outputs the first voltage to it to ground based on the output control signal.

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