semiconductor packaging devices

Abstract

A semiconductor package device may include a first package substrate, a first semiconductor chip located on the first package substrate, an interposer located on the first semiconductor chip, a warpage prevention member located on the interposer, a molding member located on the interposer and the first package substrate, and a second package substrate located on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0095025 filed on August 5, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package device, and in particular, to a semiconductor package device including an interposer. Background Art

[0004] A semiconductor package including a semiconductor chip can allow the semiconductor chip to be used as part of an electronic product. Typically, a semiconductor package may include a printed circuit board (PCB) and a semiconductor chip mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, much research is underway to improve the electrical characteristics and operational reliability of semiconductor packages. Summary of the Invention

[0005] Embodiments of the inventive concept provide a semiconductor package device configured to suppress a warpage problem and have improved thermal performance.

[0006] According to an embodiment of the present inventive concept, a semiconductor package device may include: a first package substrate; a first semiconductor chip located on the first package substrate; an interposer located on the first semiconductor chip; a warpage prevention member located on the interposer; a molding member located on the interposer and the first package substrate; and a second package substrate located on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

[0007] According to an embodiment of the present inventive concept, a semiconductor package device may include: a first package substrate; a first semiconductor chip located on the first package substrate; an interposer located on the first semiconductor chip; a molding member located on the interposer, the first semiconductor chip, and the first package substrate; a warpage prevention member and a plurality of connection terminals located on the interposer; and a second package substrate located on the warpage prevention member and in electrical contact with the plurality of connection terminals. At least a portion of a top surface of the molding member may be spaced apart from the second package substrate, and a first thickness of the connection terminals may be greater than a thickness of the warpage prevention member in a direction perpendicular to the top surface of the first package substrate.

[0008] According to an embodiment of the present invention, a semiconductor package device may include: a first package; a second package located on the first package; and a plurality of connection terminals electrically connecting the first package to the second package. The first package may include: a first package substrate; a first semiconductor chip located on the first package substrate; an interposer located on the first semiconductor chip; a first adhesive layer interposed between the first semiconductor chip and the interposer; a warpage prevention member located on the interposer; a second adhesive layer located between the warpage prevention member and the interposer; and a first molding member located on the interposer and the first package substrate. The second package may include: a second package substrate connected to the plurality of connection terminals; a second semiconductor chip located on the second package substrate, the second semiconductor chips being spaced apart from each other; and a second molding member located in a region between the second semiconductor chips and on side surfaces of the second semiconductor chips. At least a portion of an upper portion of the first molding member may be spaced apart from the second package substrate, and the first molding member may not be present at the top surface of the warpage prevention member. The warpage prevention member may have a thickness in a direction perpendicular to a top surface of the first package substrate, and a thermal expansion coefficient of the warpage prevention member is greater than a thermal expansion coefficient of the interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which represent non-limiting example embodiments as described herein.

[0010] Figure 1A is a plan view illustrating a semiconductor package device according to some embodiments of the inventive concept.

[0011] Figure 1B It is along Figure 1A A cross-sectional view taken along line II'.

[0012] Figure 2 is a cross-sectional view illustrating a semiconductor package device according to some embodiments of the inventive concept.

[0013] Figures 3A to 3D is a cross-sectional view illustrating a method of manufacturing a semiconductor package device according to some embodiments of the inventive concept.

[0014] Figure 4A is a plan view illustrating a semiconductor package device according to some embodiments of the inventive concept.

[0015] Figure 4B yes Figure 4A sectional view of a semiconductor package device shown in FIG.

[0016] Figure 5A is a plan view illustrating a semiconductor package device according to some embodiments of the inventive concept.

[0017] Figure 5B yes Figure 5A sectional view of a semiconductor package device shown in FIG.

[0018] Figure 6A is a plan view illustrating a semiconductor package device according to some embodiments of the inventive concept.

[0019] Figure 6B yes Figure 6A sectional view of a semiconductor package device shown in FIG.

[0020] 7A to 7D is a cross-sectional view illustrating a method of manufacturing a semiconductor package device according to some embodiments of the inventive concept.

[0021] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or performances covered by the example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0022] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.The same reference numerals or the same reference numerals may refer to the same elements or components throughout the specification.

[0023] As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It will be understood that when an element is referred to as being "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, "in contact with" another element, etc., the element may be directly on the other element, directly attached to the other element, directly connected to the other element, directly coupled to the other element, or directly in contact with the other element, or there may be an intermediate element. On the contrary, for example, when an element is referred to as being "directly on" another element, "directly attached" to another element, "directly connected" to another element, "directly coupled" to another element, or "in direct contact with" another element, there is no intermediate element. It should be noted that, although not specifically described with respect to one embodiment, the various aspects described with respect to the one embodiment may be incorporated into different embodiments. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0024] Figure 1A is a plan view illustrating a semiconductor package device according to some embodiments of the inventive concept. Figure 1B It is along Figure 1A In order to reduce the complexity of the drawings, Figure 1A Omit Figure 1B Some elements shown in FIG.

[0025] Reference Figure 1A and Figure 1B According to some embodiments of the present invention, a semiconductor package device 1000 may include a first package PK1 and a second package PK2 located on the first package PK1. The first package PK1 and the second package PK2 may be electrically connected to each other via connection terminals CT interposed between the first package PK1 and the second package PK2.

[0026] The first package PK1 may include a first package substrate 101 , a first semiconductor chip 102 , an interposer 103 , and a warpage preventing member 104 .

[0027] The first package substrate 101 may include, for example, a printed circuit board (PCB) substrate. A plurality of solder balls SB may be provided on the bottom surface of the first package substrate 101. The solder balls SB may be provided in an edge portion of the first package substrate 101 (ie, as shown in FIG. Figure 1B 1. The exterior of the package substrate 101 is shown in a cross-sectional view of FIG. 1. The solder balls SB may be used as connection terminals when the semiconductor package device 1000 is attached to a motherboard.

[0028] The first semiconductor chip 102 may include, for example, an application processor (AP) chip. The first semiconductor chip 102 may be electrically connected to the first package substrate 101 via a plurality of bumps BP attached to the bottom surface of the first semiconductor chip 102. The bottom surface of the first semiconductor chip 102 may serve as an active surface. The top surface of the first semiconductor chip 102 may be an inactive surface. The first semiconductor chip 102 may be mounted on the first package substrate 101 in a flip-chip bonding manner.

[0029] An underfill layer UF may be provided in a gap between the first semiconductor chip 102 and the first packaging substrate 101 to seal or encapsulate the bumps BP. The underfill layer UF may be formed of or include an insulating polymer material (eg, epoxy resin).

[0030] The plug 103 may be disposed on the first semiconductor chip 102. The plug 103 may be a silicon plug. The plug 103 may have a top surface and a bottom surface facing each other. Figure 1BAs shown in the cross-sectional view of , a bottom surface of the interposer 103 may face the first semiconductor chip 102 .

[0031] In some embodiments, the planar area of ​​the insert 103 may be larger than the planar area of ​​the first semiconductor chip 102. When viewed in a plan view, at least a portion of an edge portion of the insert 103 may overlap with the first semiconductor chip 102. Figure 1B As shown in FIG, at least a portion of the edge portion of the interposer 103 may not overlap the first semiconductor chip 102 in a vertical direction D2 that is substantially perpendicular to the upper surface of the first package substrate 101 .

[0032] The first adhesive layer AF1 may be provided between the first semiconductor chip 102 and the interposer 103. The first adhesive layer AF1 may be used to attach the interposer 103 to the first semiconductor chip 102. The first adhesive layer AF1 may be provided in a manner such as Figure 1B The bottom surface of the interposer 103 extends along the edge portion of the interposer 103 in the D1 direction shown in FIG. 1 (ie, a portion of the interposer 103 that does not overlap the first semiconductor chip 102 in the D2 direction).

[0033] A redistribution layer (not shown) may be provided on the interposer 103. The redistribution layer (not shown) may include an insulating layer (not shown) and redistribution patterns CL. The redistribution patterns CL may include via plugs (not shown) and interconnection lines (not shown).

[0034] A plurality of first pads PD1 and a plurality of second pads PD2 may be provided on the top surface of the plug-in 103. Compared to the first pads PD1, the second pads PD2 may be provided near the edge of the plug-in 103 in the D1 direction. The first pads PD1 may be pads that contact the connection terminal CT. The connection terminal CT may be vertically connected to the first pads PD1 (i.e., in the D2 direction). The first pads PD1 may be electrically connected to the second pads PD2 through a redistribution pattern CL. The second pads PD2 may be electrically connected to the first package substrate 101 through a first bonding wire WL1.

[0035] The warpage prevention member 104 may be provided on the interposer 103. The warpage prevention member 104 may be formed of or include a material having a higher coefficient of thermal expansion (CTE) than that of the interposer 103. In addition, the warpage prevention member 104 may be formed to have a higher thermal conductivity than that of the interposer 103. The warpage prevention member 104 may include, for example, a copper tape.

[0036] The heat generated by the second package PK2 when mounted on the first package PK1 or when the semiconductor package device is mounted on a motherboard may cause warping. The coefficient of thermal expansion of the interposer 103 may be lower than that of the first package substrate 101. As a result, warping may occur due to this difference in the coefficients of thermal expansion between the first package substrate 101 and the interposer 103. Because the warpage prevention member 104, which has a higher coefficient of thermal expansion (CTE), is provided on the interposer 103, it also allows the upper portion of the interposer 103 to expand, which can reduce warpage during the mounting process. In addition, because the thermal conductivity of the warpage prevention member 104 is greater than that of the interposer 103, the warpage prevention member 104 can dissipate heat from the interposer 103 to the outside (i.e., outside the semiconductor package device), which can suppress or prevent the internal temperature of the semiconductor package device 1000 from rising to an excessively high level. Furthermore, as will be described below, the aforementioned effects can be achieved by configuring the warpage prevention member 104 to have a specific thickness.

[0037] The warping prevention member 104 may have a width Δ1041 in a first direction D1 parallel to the top surface of the first package substrate 101. The insert 103 may have a width Δ1031 in the first direction D1. The width Δ1041 of the warping prevention member 104 in the first direction D1 may be smaller than the width Δ1031 of the insert 103 in the first direction D1. The width Δ1041 of the warping prevention member 104 in the first direction D1 may be greater than or equal to 0.3 times the width Δ1031 of the insert 103 in the first direction D1. The width Δ1041 of the warping prevention member 104 in the first direction D1 may be, for example, 5 mm.

[0038] The warpage prevention member 104 may have a thickness Δ1042 in a second direction D2 perpendicular to the top surface of the first package substrate 101. The thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may correspond to the thickness of the warpage prevention member 104. The thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may be greater than the thickness Δ1032 of the interposer 103 in the second direction D2. The thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may be in a range of 100 μm to 150 μm.

[0039] The thickness ΔCT of the connection terminal CT in the second direction D2 may be equal to or greater than the thickness Δ1042 of the warpage preventing member 104 in the second direction D2. A difference between the thickness ΔCT of the connection terminal CT in the second direction D2 and the thickness Δ1042 of the warpage preventing member 104 in the second direction D2 may be less than or equal to 30 μm.

[0040] The second adhesive layer AF2 may be disposed between the warpage preventing member 104 and the insert 103. Each of the top and bottom surfaces of the second adhesive layer AF2 may have an area corresponding to the bottom surface of the warpage preventing member 104. The second adhesive layer AF2 may overlap the warpage preventing member 104 in the second direction D2. The thickness of the second adhesive layer AF2 may be, for example, 10 μm.

[0041] The first molding member 105 may be provided to at least partially cover the interposer 103 , the first semiconductor chip 102 , and the first package substrate 101 . The first molding member 105 may include a plurality of holes HL . The holes HL may be provided to at least partially expose the first pads PD1 on the interposer 103 .

[0042] The first molding member 105 may cover at least a portion of the side surface of the warpage preventing member 104. The first molding member 105 may not cover the top surface of the warpage preventing member 104 or extend onto the top surface of the warpage preventing member 104. Figure 1B , the top surface 104T of the warpage prevention member 104 may be disposed at a level equal to or higher than the top surface 105T of the first molding member 105. At least a portion of each of the side surfaces of the warpage prevention member 104 may be exposed by the first molding member 105.

[0043] At least a portion of a top surface of the first molding member 105 may be spaced apart from a bottom surface of a second package substrate 201 to be described below.

[0044] At least a portion of the top surface 104T of the warpage preventing member 104 may be spaced apart from the bottom surface PK2L of the second package PK2. A distance ΔGP between the top surface 104T of the warpage preventing member 104 and the bottom surface PK2L of the second package PK2 in the second direction D2 may be in a range of 10 μm to 30 μm. In some embodiments, a portion of the top surface 104T of the warpage preventing member 104 may be in physical contact with the bottom surface PK2L of the second package PK2.

[0045] The second package PK2 may include a second package substrate 201, a plurality of second semiconductor chips 202a, and a second molding member 205. The second package substrate 201 may be, for example, a PCB substrate. The second package substrate 201 may have a thickness Δ201 in the second direction D2. The thickness Δ201 of the second package substrate 201 in the second direction D2 may be less than the thickness Δ101 of the first package substrate 101 in the second direction D2.

[0046] The respective second semiconductor chips 202a may be arranged on the second packaging substrate 201 so as to be spaced apart from each other. Each of the second semiconductor chips 202a may include, for example, a memory chip. The top surface of the second semiconductor chip 202a may serve as an active surface. The bottom surface of the second semiconductor chip 202a may be an inactive surface. The second semiconductor chip 202a and the second packaging substrate 201 may be electrically connected to each other via second bonding wires WL2, which are arranged to connect the top surface of the second semiconductor chip 202a and the top surface of the second packaging substrate 201. In other words, the second semiconductor chip 202a may be mounted on the second packaging substrate 201 in a wire bonding manner.

[0047] The second package PK2 may further include a plurality of third semiconductor chips 202b. Each of the third semiconductor chips 202b may be disposed on the second semiconductor chip 202a. The third semiconductor chips 202b may each include, for example, a memory chip. An adhesive film (not shown) may be disposed between the third semiconductor chip 202b and the corresponding semiconductor chip in the second semiconductor chip 202a. The top surface of the third semiconductor chip 202b may serve as an active surface. The bottom surface of the third semiconductor chip 202b may be an inactive surface. The third semiconductor chip 202b and the second package substrate 201 may be electrically connected to each other via a third bonding wire WL3, which is disposed to connect the top surface of the third semiconductor chip 202b and the top surface of the second package substrate 201. In other words, the third semiconductor chip 202b may be mounted on the second package substrate 201 in a wire bonding manner.

[0048] The second molding member 205 may be provided to at least partially cover the second package substrate 201, the second semiconductor chips 202a, and the third semiconductor chips 202b. For example, the second molding member 205 may at least partially cover the region between the second semiconductor chips 202a and the side surfaces of each of the second semiconductor chips 202a. The second molding member 205 may at least partially cover the region between the third semiconductor chips 202b and the top and side surfaces of each of the third semiconductor chips 202b.

[0049] Figure 2 is a cross-sectional view illustrating a semiconductor package device 1001 according to some embodiments of the present inventive concept. Figure 1A and Figure 1B elements described herein without repeating their description.

[0050] Reference Figure 2The warpage prevention member 104 may include silicon. The warpage prevention member 104 may be a silicon stack. Silicon may be used instead of copper tape. Because silicon can effectively dissipate heat supplied from the first semiconductor chip 102 to the interposer 103 to the outside of the semiconductor package device 1001, the use of silicon can improve the heat dissipation characteristics of the semiconductor package device 1001.

[0051] Figures 3A to 3D is a cross-sectional view illustrating a method of manufacturing a semiconductor package device according to some embodiments of the inventive concept.

[0052] Reference Figure 3A A first package substrate 101 with an insert 103 and a first semiconductor chip 102 mounted thereon may be prepared. Solder balls SB may be provided on the bottom surface of the first package substrate 101. Bumps BP may be provided between the first semiconductor chip 102 and the first package substrate 101. An underfill layer UF may be provided to fill gaps between the bumps BP. The insert 103 may include a first pad PD1, a second pad PD2, and a redistribution pattern CL. A first adhesive layer AF1 may be provided between the insert 103 and the first semiconductor chip 102.

[0053] The warpage prevention member 104 can be mounted on the insert 103 via the second adhesive layer AF2. The warpage prevention member 104 can include, for example, copper tape. The copper tape can be prepared so that its width Δ1041 in the first direction D1 is approximately 5 mm. The copper tape can be prepared so that its thickness Δ1042 in the second direction D2 is in the range of 100 μm to 150 μm. However, embodiments of the present inventive concept are not limited to this example; the width Δ1041 of the copper tape in the first direction D1 and the thickness Δ1042 of the copper tape in the second direction D2 can vary.

[0054] Reference Figure 3B , the first molding member 105 may be formed to at least partially cover the first package substrate 101 .

[0055] During the formation of the first molding member 105, the top surface of the warpage preventing member 104 (i.e., the surface opposite the surface bonded to the second adhesive layer AF2) may be protected by a mask (not shown) disposed on the top surface of the warpage preventing member 104. In other words, the first molding member 105 may not be formed on the region MSK of the first packaging substrate 101 where the warpage preventing member 104 is disposed. The first molding member 105 may be partially formed on the region OP of the first packaging substrate 101 exposed by the mask (not shown). The first molding member 105 may be formed so that the level of its top surface 105T is equal to or lower than the level of the top surface 104T of the warpage preventing member 104. The mask (not shown) may be removed after the first molding member 105 is formed.

[0056] Reference Figure 3C , a hole HL may be formed in the first molding member 105. The hole HL may be formed by a laser drilling process. The first pad PD1 of the interposer 103 may be at least partially exposed through the hole HL.

[0057] Reference Figure 3D and Figure 1B , the second package PK2 can be mounted on the first package PK1. A plurality of initial connection terminals PCT attached to the bottom surface of the second package PK2 can be aligned with the first pad PD1 of the first package PK1 and attached to the first pad PD1 of the first package PK1. The initial connection terminals PCT can form connection terminals CT attached to the first pad PD1 through a reflow process. The mounting process of the second package PK2 may include a compression process PR. Figure 1B As shown in FIG, even when the second package PK2 is mounted on the first package PK1, the top surface 104T of the warpage preventing member 104 may be spaced apart from the bottom surface PK2L of the second package PK2. In some embodiments, during the reflow process, a portion of the top surface 104T of the warpage preventing member 104 may be in physical contact with the bottom surface PK2L of the second package PK2.

[0058] Figure 4A is a plan view illustrating a semiconductor package device 2000 according to some embodiments of the inventive concept. Figure 4B yes Figure 4A In order to reduce the complexity of the drawings, Figure 4A Omit Figure 4B For simplicity of description, the same reference numerals will be used to identify the previously referenced components. Figure 1A and Figure 1B elements described herein without repeating their description.

[0059] Reference Figure 4A and Figure 4B The first molding member 105 may at least partially cover the top surface of the interposer 103. At least a portion of the top surface of the first molding member 105 may be spaced apart from the bottom surface of the second package substrate 201. The first molding member 105 may be formed to have a groove gv defined on the interposer 103.

[0060] The warping prevention member 104 may be disposed in the groove gv. For example, a portion of the first molding member 105 may be interposed between the warping prevention member 104 and the insert 103. The warping prevention member 104 may be spaced apart from the insert 103, with a portion of the first molding member 105 interposed between the warping prevention member 104 and the insert 103. The bottom surface of the warping prevention member 104 may be in physical contact with a portion of the first molding member 105. At least a portion of the side surface of the warping prevention member 104 may be surrounded by the first molding member 105. A portion of the warping prevention member 104 may extend from the side surface of the groove gv of the first molding member 105 to at least partially cover a portion of the top surface of the first molding member 105.

[0061] The top surface 104T of the warpage preventing member 104 may be in physical contact with the bottom surface PK2L of the second package PK2. The warpage preventing member 104 may not be in physical contact with the connection terminals CT. When viewed in a plan view, the warpage preventing member 104 may be partially or entirely surrounded by the connection terminals CT.

[0062] The warpage prevention member 104 can be formed by solidifying liquid non-conductive adhesive (NCP). The non-conductive adhesive may include, for example, a polymer. The solidified non-conductive adhesive may have a higher thermal expansion coefficient than the insert 103. In some embodiments, the warpage prevention member 104 may also serve as an adhesive layer for attaching the first package PK1 to the second package PK2.

[0063] The width Δ1041 of the warpage prevention member 104 in the first direction D1 may be greater than 0.3 times the width Δ1031 of the insert 103 in the first direction D1. The thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may be greater than the thickness Δ1032 of the insert 103 in the second direction D2. The thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may be in a range of 100 μm to 250 μm. For example, the thickness Δ1042 of the warpage prevention member 104 in the second direction D2 may be approximately 150 μm.

[0064] The groove gv may have a width ΔGV1 in the first direction D1, and the hole HL may have a width ΔHL1 in the first direction D1. The width ΔGV1 of the groove gv in the first direction D1 may be greater than the width ΔHL1 of the hole HL in the first direction D1. The groove gv may have a depth ΔGV2 in the second direction D2, and the hole HL may have a depth ΔHL2 in the second direction D2. The depth ΔGV2 of the groove gv in the second direction D2 may be less than the depth ΔHL2 of the hole HL in the second direction D2.

[0065] Figure 5A and Figure 5BFIG. 2 is a diagram illustrating a semiconductor package device 2001 according to some embodiments of the present inventive concept. Figure 4A and Figure 4B elements described herein without repeating their description.

[0066] Reference Figure 5A and Figure 5B The first molding member 105 may include a plurality of first grooves gv1. A first warpage prevention member 104a may be disposed in each of the first grooves gv1. Each of the first warpage prevention members 104a may have a circular or circular-like shape when viewed in plan. The first warpage prevention members 104a may be arranged two-dimensionally on the first molding member 105 when viewed in plan.

[0067] Figure 6A and Figure 6B FIG. 2 is a diagram illustrating a semiconductor package device 2002 according to some embodiments of the present inventive concept. Figure 4A and Figure 4B elements described herein without repeating their description.

[0068] Reference Figure 6A and Figure 6B The first molding member 105 may include a first groove gv1 and a second groove gv2. When viewed in a plan view, the second warping prevention member 104b may at least partially surround the first warping prevention member 104a. When viewed in a plan view, the second groove gv2 may have a ring, square, or rectangular shape.

[0069] 7A to 7D is a cross-sectional view illustrating a method of manufacturing a semiconductor package device according to some embodiments of the inventive concept.

[0070] Reference Figure 7A , a first package substrate 101 on which a plug-in 103 and a first semiconductor chip 102 are mounted may be prepared. Solder balls SB may be provided on the bottom surface of the first package substrate 101. Bumps BP may be provided between the first semiconductor chip 102 and the first package substrate 101. An underfill layer UF may be provided to at least partially fill the gap between the bumps BP. The plug-in 103 may include a first pad PD1, a second pad PD2, and a redistribution pattern CL. A first initial connection terminal PCT1 may be provided on the first pad PD1. In some embodiments, as Figure 3A As shown in FIG, the first preliminary connection terminals PCT1 may be omitted. A first adhesive layer AF1 may be interposed between the interposer 103 and the first semiconductor chip 102.

[0071] The first molding member 105 may be formed to at least partially cover the first package substrate 101. The first molding member 105 may at least partially cover the top surface and side surfaces of the interposer 103. Formation of the first molding member 105 may include forming a molding material (not shown) to at least partially cover the first package substrate 101 and curing the molding material.

[0072] Reference Figure 7B , a groove gv and a hole HL may be formed in an upper portion of the first molding member 105. The groove gv and the hole HL may be formed through a laser drilling process.

[0073] In some embodiments, the groove gv may be formed by using an additional casting mold (not shown) before curing the molding material (not shown). The hole HL may be formed to expose the first pad PD1 of the interposer 103 .

[0074] Reference Figure 7C Liquid warpage preventing material P104 can be dispensed from a source SC placed on the first molding member 105 toward the groove gv. The liquid warpage preventing material P104 can include, for example, a liquid non-conductive paste (NCP). The liquid warpage preventing material P104 can be formed to selectively at least partially fill the groove gv. The hole HL may not be filled with the liquid warpage preventing material P104 (e.g., may not contain the liquid warpage preventing material P104).

[0075] Combine Figure 7D Reference Figure 4B , the second package PK2 can be mounted on the first package PK1. The plurality of second initial connection terminals PCT2 attached to the bottom surface of the second package PK2 can be aligned with the first initial connection terminals PCT1 of the first package PK1 and then reflowed through a reflow process to form connection terminals CT. The mounting process of the second package PK2 may include a compression process PR. The compression process PR may be performed to bring the liquid warpage preventing material P104 into contact with the bottom surface of the second package PK2. During this process, a portion of the liquid warpage preventing material P104 may overflow to a portion near the groove gv of the top surface of the first molding member 105, but may not enter the hole HL.

[0076] In some embodiments, a curing process may be performed after the compression process and the reflow process. The curing process may be a heat treatment process performed at a lower temperature than that in the reflow process. The curing process may solidify the unsolidified portion of the liquid warpage preventing material P104 to form the warpage preventing member 104.

[0077] According to some embodiments of the present inventive concept, when a silicon interposer is used as the material for an interposer in a semiconductor package device, the heat dissipation characteristics of the semiconductor package device can be improved compared to using a substrate made of an organic material. However, the use of a silicon interposer can lead to warping issues. This warping issue can be alleviated by placing a material with a high coefficient of thermal expansion on the silicon interposer.

[0078] Furthermore, according to some embodiments of the present invention, the space on the silicon insert where no connection terminals are provided can be configured to have an effective structure, and a warpage prevention member can be attached to the space. Thus, warpage can be effectively suppressed. Furthermore, the warpage prevention member can be configured to have a specific material and a specific thickness, which can further effectively suppress warpage.

[0079] According to some embodiments of the inventive concept, it is possible to suppress a warpage problem of a semiconductor package device and improve thermal conductivity properties of the semiconductor package device.

[0080] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor packaging device, comprising: a first packaging substrate; a first semiconductor chip located on the first packaging substrate; an inserter located on the first semiconductor chip; a warping prevention member located on the insert; a molding member located on the interposer and the first packaging substrate; as well as a second packaging substrate located on the molding member, wherein at least a portion of the top surface of the molding member is spaced apart from the bottom surface of the second package substrate, and Here, with respect to the top surface of the first package substrate as a base level, the level of the top surface of the warpage prevention member is equal to or higher than the level of the top surface of the molding member.

2. The semiconductor package device according to claim 1, wherein The warpage prevention member has a higher thermal expansion coefficient than the insert.

3. The semiconductor package device according to claim 1, wherein The warpage prevention member has a thermal conductivity higher than that of the interposer.

4. The semiconductor package device according to claim 1, wherein The warpage prevention member includes a copper or silicon stack.

5. The semiconductor package device according to claim 4, wherein The warpage prevention member has a thickness greater than a thickness of the interposer in a direction perpendicular to a top surface of the first package substrate having the first semiconductor chip thereon.

6. The semiconductor package device according to claim 5, wherein A width of the warpage prevention member is smaller than a width of the interposer in a direction parallel to a top surface of the first package substrate.

7. The semiconductor package device according to claim 6, wherein The warpage prevention member has a thickness in the range of 100 μm to 150 μm.

8. The semiconductor package device according to claim 1 , further comprising a second semiconductor chip located on the second package substrate. in, In a direction perpendicular to a top surface of the first packaging substrate, a thickness of the first packaging substrate is greater than a thickness of the second packaging substrate.

9. The semiconductor package device according to claim 8, wherein The interposer includes a first pad, a second pad, and a redistribution pattern electrically connecting the first pad and the second pad to each other, and The second pad is electrically connected to the first packaging substrate through a bonding wire.

10. The semiconductor package device according to claim 9, further comprising a connection terminal connected to the first pad, in, In a direction perpendicular to the top surface of the first package substrate, a first thickness of the connection terminal is greater than a thickness of the warpage prevention member, and A difference between a first thickness of the connection terminal and a thickness of the warpage preventing member is less than or equal to 30 μm.

11. The semiconductor package device according to claim 1, wherein The molding member does not exist at at least a portion of a side surface of the warpage prevention member.

12. A semiconductor packaging device comprising: a first packaging substrate; a first semiconductor chip located on the first packaging substrate; an inserter located on the first semiconductor chip; a molding member located on the interposer, the first semiconductor chip, and the first package substrate; a warping prevention member and a plurality of connection terminals located on the insert; as well as a second packaging substrate located on the warpage prevention member and electrically contacting the plurality of connection terminals, wherein at least a portion of a top surface of the molding member is spaced apart from the second package substrate, and A first thickness of the connection terminal is greater than a thickness of the warpage prevention member in a direction perpendicular to a top surface of the first package substrate.

13. The semiconductor package device according to claim 12, wherein The connection terminals surround the warpage preventing member when viewed in plan view.

14. The semiconductor package device according to claim 13, wherein The insert has a top surface and a bottom surface opposite to each other, wherein the plug-in further comprises a solder pad on the top surface of the plug-in and an adhesive layer on the bottom surface of the plug-in, and Some of the pads overlap with the connection terminals in a direction perpendicular to the top surface of the first package substrate.

15. The semiconductor package device according to claim 13, wherein The molding member includes a groove and a hole, wherein the warping prevention member is located in the groove, wherein each of the connection terminals is located in the hole, and Wherein, the depth of the hole is greater than the depth of the groove.

16. The semiconductor package device according to claim 15, wherein A portion of the molding member is interposed between the warping prevention member and the inserter.

17. The semiconductor package device according to claim 12, wherein The warping prevention member includes solidified non-conductive glue.

18. The semiconductor package device according to claim 12, wherein The warpage prevention member has a thickness in the range of 100 μm to 150 μm.

19. A semiconductor packaging device comprising: a first package; a second package located on the first package; as well as a plurality of connection terminals electrically connecting the first package to the second package, Wherein, the first package comprises: a first packaging substrate; a first semiconductor chip located on the first packaging substrate; an inserter located on the first semiconductor chip; a first adhesive layer interposed between the first semiconductor chip and the insert; a warping prevention member located on the insert; a second adhesive layer positioned between the warpage preventing member and the insert; and a first molding member located on the interposer and the first package substrate, wherein the second package comprises: a second packaging substrate connected to the plurality of connection terminals; second semiconductor chips located on the second package substrate, and the second semiconductor chips are spaced apart from each other; and a second molding member located in a region between the second semiconductor chips and on side surfaces of the second semiconductor chips, wherein at least a portion of an upper portion of the first molding member is spaced apart from the second packaging substrate, wherein the first molding member does not exist at the top surface of the warpage prevention member, and The warping prevention member has a thickness in a direction perpendicular to a top surface of the first package substrate, and a thermal expansion coefficient of the warping prevention member is greater than a thermal expansion coefficient of the interposer.

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