Signal decoding method and computer storage medium

Abstract

The application discloses a signal decoding method and a computer storage medium. The method comprises the following steps: after 2048-bit data obtained by demodulating a 512-pulse amplitude modulation (PAM16) signal is obtained, log-likelihood ratio (LLR) values of 94 continuous bits of the 2048-bit data starting from the 1627th bit are configured as ideal LLR values in a noise-free state; and low-density parity-check code (LDPC) decoding is performed on the configured 2048-bit data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of information processing, and in particular to a signal decoding method and a computer storage medium. BACKGROUND

[0002] The 2.5G / 5G Ethernet physical layer technology standard is formulated by the IEEE (Institute of Electrical and Electronics Engineers) / 802-3 standardization organization. The technology standard can provide a reliable bidirectional transmission rate of up to more than 1 G through a low-cost 5 twisted pair and a GePHY (Giga bit ethernet physical layer) Ethernet chip in 2.5G / 5G. Figure 1 A transmitting encoding flowchart in the 2.5G / 5G Ethernet physical layer technology standard formulated by the IEEE / 802-3 standardization organization is shown in FIG. 1. As shown in FIG. 1, 1+65*25+97 zeros form 1723 information bits, 1723 bits are encoded by LDPC (Low Density Parity Check Code) (2048, 1723) to output 2048 bits, the positions of the 97 zeros are replaced by random bits, and the 2048 bits are modulated by PAM (Pulse Amplitude Modulation) 16 to obtain 512 PAM16 signals. The processing method of the 97 zeros in the above flowchart is to replace the values of the 97 zeros in the LLR (Log Likelihood Ratio) with a large value before performing LDPC decoding after soft demodulation, which causes a high bit error rate. Figure 1 SUMMARY

[0003] To solve the above technical problems, the present application provides a signal decoding method and a computer storage medium, which can reduce the bit error rate.

[0004] To achieve the purpose of the present application, the present application provides a signal decoding method, which comprises the following steps:

[0005] After demodulating 512 pulse amplitude modulation PAM16 signals to obtain 2048 bit data, the log likelihood ratio LLR values of the continuous 94 bit data starting from the 1627th bit in the 2048 bit data are configured as ideal LLR values in a noiseless state;

[0006] The 2048 real values obtained after the configuration are subjected to low density parity check code LDPC decoding.​

[0007] In one example embodiment, after the 2048 real values after the configuration are subjected to low density parity check code (LDPC) decoding, the method further comprises:

[0008] determining whether all the check results after the decoding are 0;

[0009] if all the check results after the decoding are not 0, configuring the values of the bits adjacent to the 94 consecutive bits as ideal LLR values in the noiseless state, and performing LDPC decoding on the 2048 real values after the configuration of the adjacent bits as ideal LLR values in the noiseless state, until all the check results of the 2048 real values are 0 or the number of iterations performed reaches a threshold of the number of iterations preset, and the decoding operation ends.

[0010] In one example embodiment, the bits adjacent to the 94 consecutive bits are 2 bits before the 1627th bit and 4 consecutive bits after the 94 consecutive bits.

[0011] In one example embodiment, the configuration of the values of the bits adjacent to the 94 consecutive bits as ideal LLR values in the noiseless state comprises:

[0012] regarding 2 bits before the 1627th bit, the 1627th bit and the 1628th bit as a whole, and regarding 4 consecutive bits after the 94 consecutive bits as another whole, processing the real values of the two wholes respectively with the respective corresponding value determination rules stored in advance to obtain respective processing results;

[0013] determining the ideal LLR values in the noiseless state corresponding to the 1625th to 1628th bits and the 4 consecutive bits after the 94 consecutive bits according to the respective processing results.

[0014] In one example embodiment, when 2 bits before the 1627th bit, the 1627th bit and the 1628th bit are regarded as a whole, the ideal LLR value in the noiseless state is obtained by the following method, comprising:

[0015] if the real value of the whole is greater than or equal to 10, the ideal LLR value in the noiseless state corresponding to the whole is sequence AB0;

[0016] if the real value of the whole is less than 10 and greater than 6, the ideal LLR value in the noiseless state corresponding to the whole is sequence AB0 or sequence AB1;

[0017] if the real value of the one whole is less than or equal to 6 and greater than or equal to 2, then the ideal LLR value corresponding to the one whole in the noiseless time is sequence AB1;

[0018] if the real value of the one whole is less than or equal to 2 and greater than -2, then the ideal LLR value corresponding to the one whole in the noiseless time is sequence AB1 or sequence AB2;

[0019] if the real value of the one whole is less than or equal to -2 and greater than or equal to -6, then the ideal LLR value corresponding to the one whole in the noiseless time is sequence AB2;

[0020] if the real value of the one whole is less than or equal to -6 and greater than -10, then the ideal LLR value corresponding to the one whole in the noiseless time is sequence AB2 or sequence AB3;

[0021] if the real value of the one whole is less than or equal to -10, then the ideal LLR value corresponding to the one whole in the noiseless time is sequence AB3;

[0022] wherein the values of the sequence AB0, the sequence AB1, the sequence AB2 and the sequence AB3 correspond to the values of the ideal LLR values in the noiseless time of the 1625th to 1628th bits in sequence;

[0023] the value of the sequence AB0 is 15, -7, 3, 1;

[0024] the value of the sequence AB1 is 1, 7, 3, 1;

[0025] the value of the sequence AB2 is -1, 7, 3, 1;

[0026] the value of the sequence AB3 is -15, -7, 3, 1.

[0027] In one exemplary embodiment, when the real value of the one whole is less than 10 and greater than 6, if the real value of the one whole is less than 10 and greater than or equal to 8, the decoding priority of the sequence AB0 is higher than the decoding priority of the sequence AB1; if the real value of the one whole is less than 8 and greater than 6, the decoding priority of the sequence AB1 is higher than the decoding priority of the sequence AB0;

[0028] when the real value of the one whole is less than or equal to 2 and greater than -2, if the real value of the one whole is less than 2 and greater than or equal to 0, the decoding priority of the sequence AB1 is higher than the decoding priority of the sequence AB2; if the real value of the one whole is less than 0 and greater than -2, the decoding priority of the sequence AB2 is higher than the decoding priority of the sequence AB1;

[0029] When the real value of the one whole is less than or equal to -6 and greater than -10, then if the real value of the one whole is less than -6 and greater than or equal to -8, the decoding priority of sequence AB2 is higher than that of sequence AB3; if the real value of the one whole is less than -8 and greater than -10, the decoding priority of sequence AB3 is higher than that of sequence AB2.

[0030] In one exemplary embodiment, when the continuous 4 bits after the continuous 94 bits are taken as another whole, the ideal LLR value in the noiseless time is obtained by the following way, comprising:

[0031] If the absolute value of the real value of the one whole is greater than or equal to 16, the ideal LLR value corresponding to the one whole in the noiseless time is sequence DE1;

[0032] If the absolute value of the real value of the one whole is less than 16, the ideal LLR value corresponding to the one whole in the noiseless time is sequence DE0 or sequence DE1;

[0033] Wherein, the values of sequence DE0 and sequence DE1 correspond to the values of the ideal LLR value in the noiseless time of the continuous 4 bits after the continuous 94 bits in turn;

[0034] The value of sequence DE0 is 3, 5, 1, -1;

[0035] The value of sequence DE1 is 1, 7, 3, 1.

[0036] In one exemplary embodiment, when the absolute value of the real value of the another whole is less than 16, when one of the following first group of conditions is met, the decoding priority of sequence DE1 is higher than that of sequence DE0; when one of the following second group of conditions is met, the decoding priority of sequence DE0 is higher than that of sequence DE1; wherein:

[0037] The first group of conditions includes: the absolute value of the real value of the another whole is less than 16 and greater than 14; or, the absolute value of the real value of the another whole is less than 10 and greater than 6; or, the absolute value of the real value of the another whole is less than 2;

[0038] The second group of conditions includes: the absolute value of the real value of the another whole is less than or equal to 14 and greater than or equal to 10; or, the absolute value of the real value of the another whole is less than or equal to 6 and greater than or equal to 2.

[0039] In one exemplary embodiment, the LDPC decoding on the 2048 bits after the ideal LLR value of the adjacent bits in the noiseless time is configured, comprising:

[0040] The value of the ideal LLR value of at least one of the one whole and the other whole is two sequences, and the decoding priority of the two sequences is obtained;

[0041] The LDPC decoding operation is performed according to the decoding priority of the two sequences from high to low, and the combination of the sequence values of the one whole and the other whole includes at least one of the following:

[0042] The value of the first sequence of the one whole and the value of the first sequence of the other whole;

[0043] The value of the first sequence of the one whole and the value of the second sequence of the other whole;

[0044] The value of the second sequence of the one whole and the value of the first sequence of the other whole;

[0045] The value of the second sequence of the one whole and the value of the second sequence of the other whole.

[0046] A computer storage medium includes a processor and a memory, wherein the memory stores a computer program, and the processor invokes the computer program in the memory to implement the method of any one of the above.

[0047] In the embodiment provided by the application, after 2048-bit data obtained by demodulating 512 PAM16 signals, the LLR values of 94 continuous bits of data starting from the 1627th bit in the 2048-bit data are configured as ideal LLR values in the case of no noise, and the 2048 real values obtained after the configuration are subjected to LDPC decoding, and the LLR values of the 94 continuous bits are ideal LLR values in the case of no noise, so that the BER performance in the decoding process is improved.

[0048] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0049] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0050] Figure 1 The flowchart of the encoding process in the 2.5G / 5G Ethernet physical layer technical standard formulated by the IEEE / 802-3 standardization organization;

[0051] Figure 2 a flowchart of a signal decoding method provided by the present application;

[0052] Figure 3 a diagram of a result of dividing the 2048 bits after demodulation provided by the present application;

[0053] Figure 4 a diagram of a processing flow of a coding and decoding operation provided by the present application;

[0054] FIG. 5(a) is a flowchart of a signal decoding method provided by Embodiment One of the present application;

[0055] FIG. 5(b) is a flowchart of a signal decoding method provided by Embodiment Two of the present application;

[0056] Figure 6 a BER performance comparison diagram provided by the present application; DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the following will describe the embodiments of the present application in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in any manner without conflict.

[0058] The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Moreover, although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown.

[0059] Figure 2 a flowchart of a signal decoding method provided by the present application; Figure 1 The method comprises:

[0060] Step 201, after obtaining 2048 bits of data from demodulating 512 PAM16 signals, configuring the LLR values of the continuous 94 bits of data starting from the 1627th bit in the 2048 bits of data as ideal LLR values in a noiseless state;

[0061] In one exemplary embodiment, Figure 3 a diagram of a result of dividing the 2048 bits after demodulation provided by the present application. As shown, Figure 3 the continuous 94 bits are the bits corresponding to the B and C positions, and the 3 LLR values of the D position can use the configuration result in the related art, and the LLR values of the above positions are replaced with a large value, for example, le10.

[0062] Step 202, performing LDPC decoding on the 2048 real values obtained after the configuration.

[0063] In one example embodiment, in the encoding process, the 94 consecutive bits are randomly filled with 0 or 1, and do not carry the data required for actual user transmission; in the decoding process, by replacing the values of the above-mentioned bits with ideal LLR values, better BER performance is obtained without causing errors in data transmission.

[0064] In the method embodiment provided in the present application, after 2048 bits of data obtained by demodulating 512 PAM16 signals, the LLR values of 94 consecutive bits of data starting from the 1627th bit in the 2048 bits of data are configured as ideal LLR values in the case of no noise, and the 2048 real values obtained after the configuration are subjected to LDPC decoding, and the LLR values of the 94 consecutive bits are ideal LLR values in the case of no noise, so that the BER performance in the decoding process is improved.

[0065] The method provided in the present application is further described below:

[0066] Figure 4 The processing flow diagram of the encoding and decoding operation provided in the present application is shown in FIG. 1. Figure 4 As shown in FIG. 1, in the LDPC decoding flow, a new module "modify LLR" is added. The module replaces the 94 LLR values in the B and C positions in the in the case of no noise with ideal LLR values. The 3 LLR values in the D position are replaced with large values (for example, 1e10), and the LDPC is started. If the check result is all 0, the decoding is ended, otherwise the following process is continued. Figure 2

[0067] According to the hard decision of the real number of 406#, the 4 LLR values in the A and B positions are replaced with ideal LLR values in the case of no noise. According to the hard decision of the real number of 430#, the 4 LLR values in the D and E positions are replaced with ideal LLR values in the case of no noise. There are at most 4 combinations of the hard decision results of the AB position and the DE position, and the at most 4 combinations are tried in the order of probability from large to small, and if all the check bits of a certain combination are all 0, the decoding is ended in advance.

[0068] By the method described in the present application, better BER (Bit Error Ratio) performance can be obtained at a smaller cost.

[0069] Embodiment 1

[0070] For the 2.5G / 5G Ethernet physical layer encoding scheme of PAM16+LDPC, the receiving end generally first performs PAM16 demapping and then performs LDPC decoding. For the 97 0 bits inserted before the LDPC encoding at the sending end and then replaced with random 01 bits, the LLR values after the PAM16 demapping need to be modified.

[0071] ​ [b0 b1 b2 b3] Level 0 1 0 0 15 0 1 0 1 13 0 1 1 1 11 0 1 1 0 9 0 0 1 0 7 0 0 1 1 5 0 0 0 1 3 0 0 0 0 1 1 0 0 0 -1 1 0 0 1 -3 1 0 1 1 -5 1 0 1 0 -7 1 1 1 0 -9 1 1 1 1 -11 1 1 0 1 -13 1 1 0 0 -15

[0072] Table 1 PAM16 mapping rule

[0073] Referring to Table 1, Table 1 is a mapping rule of PAM16 provided by Embodiment One of the present application, every four bits is a group, and is mapped into a PAM16 signal according to the rule shown in Figure 5, the value range of the PAM16 signal is {±1, ±3, ±5, ±7, ±9, ±11, ±13, ±15}. Figure 3 The four bits of 406# in the AB position have four value possibilities {0100, 0000, 1000, 1100}, and the values after PAM16 mapping of the four value possibilities correspond to {15, 1, -1, -15}. The values of 407#-429# in the C position are {0, 0, 0, 0} after PAM16 mapping, and the value is 1. The four bits of 430# in the DE position have two value possibilities {0001, 0000}, and the values after PAM16 mapping of the two value possibilities correspond to {3, 1}.

[0074] Figure 5(a) is a flow chart of a signal decoding method provided by Embodiment One of the present application. As shown in Figure 5(a), the method comprises:

[0075] The process of PAM16 demap is as follows:

[0076]

[0077]

[0078] The demap values in the following three tables are the LLR values after step 1 of PAM16 demap in an ideal noiseless case.

[0079] Table 2 map values and demap values of the AB position

[0080]

[0081] Table 3 map values and demap values of the C position

[0082]

[0083] Table 4 map values and demap values of the DE position

[0084]

[0085] The values of the B and C positions are modified:

[0086] The two LLR values of b2b3 of 406# in the B position are modified to 3 and 1

[0087] Modify the four LLR values ​​(b0b1b2b3) of all addresses 407#-429# in position C by 1 / 7 / 3 / 1.

[0088] At position D, the three LLR values ​​b0b1b2 at 430# are all modified by a large positive value (e.g., 1e10). The iterative process of the SPA decoding algorithm is as follows:

[0089] Step a)

[0090] initialization

[0091] k = 0

[0092] max_iter = 50

[0093]

[0094]

[0095] k is the number of iterations, llr is the 2048 real numbers in the input, and max_iter is the maximum number of iterations.

[0096] Step b)

[0097] The number of update iterations k = k + 1;

[0098] Verify node updates and calculate value;

[0099]

[0100] Step c)

[0101] Variable node update, calculation and the updated LLR value (i.e. )

[0102]

[0103]

[0104] Step d)

[0105] For the latest LLR value (i.e. Make a hard judgment

[0106]

[0107] Step e)

[0108] Hard judgment result Perform verification H is the test matrix.

[0109] If all values ​​of c are 0, then set correct_flag = 1. As the final decoding result output, exit the iteration process;

[0110] Otherwise, set correct_flag = 0, repeat steps b) - e) if k < max_iter

[0111] correct_flag is a check result flag, 1 means correct

[0112] The BER performance curve under the simulation condition of SPA algorithm and max_iter = 50 is shown in the curve of Figure 6

[0113] Embodiment 2

[0114] Fig. 5(b) is a flow chart of a signal decoding method provided by Embodiment 2 of the present application. As shown in Fig. 5(b), the method includes:

[0115] On the basis of Embodiment 1, the x value of the LLR module 406# and 430# is modified to be hard judged, and the LLR is set to be the possible noiseless ideal value. The PAM16 demap process and the iteration process of the SPA decoding algorithm are the same as Embodiment 1. Only the different places are described below.

[0116] When SNR = 23 dB, the probability of the absolute value of the noise amplitude being greater than 1 is 1.3e-1, the probability of the absolute value of the noise amplitude being greater than 2 is 2.2e-3, and the probability of the absolute value of the noise amplitude being greater than 3 is 4.6e-6. Therefore, the protection interval of the threshold in the following hard judgment is set to be 2.

[0117] The hard judgment algorithm of 406# is shown in Table 4.

[0118] Table 4 Hard judgment result of 406#

[0119] 406# max_try1 1st selection 2nd selection x>＝10 1 AB0 None 10>x>＝8 2 AB0 AB1 8>x>6 2 AB1 AB0 6>＝x>＝2 1 AB1 None 2>x>＝0 2 AB1 AB2 0>x>-2 2 AB2 AB1 -2>＝x>＝-6 1 AB2 None -6>x>＝-8 2 AB2 AB3 -8>x>-10 2 AB3 AB2 x<＝-10 1 AB3 None

[0120] The values of AB0-AB3 are shown in the demap values in Table 1.

[0121] The hard judgment algorithm of 430# is shown in Table 5.

[0122] Table 5 Hard judgment result of 430#

[0123] 430# max_try2 1st selection 2nd selection |x|>＝16 1 DE1 None 16 > |x| > 14 or 10 > |x| > 6 or 2 > |x| 2 DE1 DE0 14 >= |x| >= 10 or 6 >= |x| >= 2 2 DE0 DE1

[0124] The values of DE0-DE1 are shown in the demap values in Table 3.

[0125] ​The decoding times is initialized as 0, and max_try = max_tryl * max_try2. max_try represents the maximum decoding times caused by the hard decision of 406# and 430#, and the possible values are 1 / 2 / 4.

[0126] First, decoding is performed according to the flow of Example 1, and if correct_flag = 0, then max_try times of decoding are performed. Before each decoding, the four LLR values of 406# and 430# are set according to Table 4 and Table 5, respectively.

[0127] The combination order of 406# and 430# is as follows:

[0128] The first selection of 406# + the first selection of 430#,

[0129] The first selection of 406# + the second selection of 430#,

[0130] The second selection of 406# + the first selection of 430#,

[0131] The second selection of 406# + the second selection of 430#

[0132] Under the simulation condition of SPA algorithm and max_iter = 50, the BER performance curve is shown in Figure 6 Curve b.

[0133] At BER = 1e-8, curve b can be improved by about 0.1 dB than the traditional method, and curve a can be improved by about 0.02 dB than the traditional method. It can be seen that the method described in the application can obtain lower bit error rate and higher throughput than the traditional method under the same conditions. The performance of curve b is better than that of curve a, but the implementation complexity of b is also higher than that of a. In the Ethernet physical layer environment, the signal-to-noise ratio is generally high, and the BLER is low. The method of Example 1 is not solved, and the hard decision and the additional maximum 4 times of decoding of 406# and 430# are started, which ensures that the average iteration times of Example 2 are almost the same as those of Example 1, thereby ensuring that the power consumption of the hardware almost does not increase.

[0134] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common and well understood by those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

Claims

1. A signal decoding method, comprising: configuring log-likelihood ratio (LLR) values of 94 consecutive bits starting from the 1627th bit in 2048 bits of data obtained by demodulating a 512 pulse amplitude modulation (PAM16) signal as ideal LLR values in a noiseless state after the 2048 bits of data are obtained by demodulating the 512 pulse amplitude modulation (PAM16) signal; performing low-density parity-check (LDPC) decoding on the 2048 real values obtained after the configuration.

2. The method of claim 1, wherein, After the low-density parity-check (LDPC) decoding on the 2048 real values obtained after the configuration, the method further comprises: determining whether all check results obtained by the decoding are 0; if all check results obtained by the decoding are not all 0, configuring values of bits adjacent to the 94 consecutive bits as ideal LLR values in a noiseless state, and performing LDPC decoding on the 2048 real values after the configuration of the adjacent bits as ideal LLR values in a noiseless state until check results of the 2048 real values are all 0 or the number of iterations performed reaches a threshold of a preset number of iterations, and the decoding operation ends.

3. The method of claim 2, wherein, The bits adjacent to the 94 consecutive bits are 2 bits before the 1627th bit and 4 consecutive bits after the 94 consecutive bits.

4. The method of claim 3, wherein, The configuration of the values of the bits adjacent to the 94 consecutive bits as ideal LLR values in a noiseless state comprises: treating 2 bits before the 1627th bit, the 1627th bit and the 1628th bit as a whole, and treating 4 consecutive bits after the 94 consecutive bits as another whole, respectively processing real numbers of the two wholes with respective corresponding value determination rules to obtain respective processing results; determining ideal LLR values in a noiseless state corresponding to the 1625th to 1628th bits and the 4 consecutive bits after the 94 consecutive bits according to the respective processing results.

5. The method of claim 4, wherein, When the 2 bits before the 1627th bit, the 1627th bit and the 1628th bit are treated as a whole, the ideal LLR values in a noiseless state are obtained by the following way, comprising: if the real number value of the whole is greater than or equal to 10, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB0; if the real number value of the whole is less than 10 and greater than 6, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB0 or sequence AB1; if the real number value of the whole is less than or equal to 6 and greater than or equal to 2, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB1; if the real number value of the whole is less than or equal to 2 and greater than -2, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB1 or sequence AB2; if the real number value of the whole is less than or equal to -2 and greater than or equal to -6, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB2; if the real number value of the whole is less than or equal to -6 and greater than -10, the ideal LLR value in a noiseless state corresponding to the whole is sequence AB2 or sequence AB3; If the real value of the one whole is less than or equal to -10, the ideal LLR value of the one whole in the noiseless time is sequence AB3; Wherein, the values of the sequence AB0, the sequence AB1, the sequence AB2 and the sequence AB3 correspond to the values of the ideal LLR values of the 1625th to 1628th bits in the noiseless time in turn; The value of the sequence AB0 is 15, -7, 3, 1; The value of the sequence AB1 is 1, 7, 3, 1; The value of the sequence AB2 is -1, 7, 3, 1; The value of the sequence AB3 is -15, -7, 3, 1.

6. The method of claim 5, wherein: If the real value of the one whole is less than 10 and greater than 6, if the real value of the one whole is less than 10 and greater than or equal to 8, the decoding priority of the sequence AB0 is higher than that of the sequence AB1; if the real value of the one whole is less than 8 and greater than 6, the decoding priority of the sequence AB1 is higher than that of the sequence AB0; If the real value of the one whole is less than or equal to 2 and greater than -2, if the real value of the one whole is less than 2 and greater than or equal to 0, the decoding priority of the sequence AB1 is higher than that of the sequence AB2; if the real value of the one whole is less than 0 and greater than -2, the decoding priority of the sequence AB2 is higher than that of the sequence AB1; If the real value of the one whole is less than or equal to -6 and greater than -10, if the real value of the one whole is less than -6 and greater than or equal to -8, the decoding priority of the sequence AB2 is higher than that of the sequence AB3; if the real value of the one whole is less than -8 and greater than -10, the decoding priority of the sequence AB3 is higher than that of the sequence AB2.

7. The method of claim 4, wherein, When the continuous 4 bits after the continuous 94 bits are taken as another whole, the ideal LLR value in the noiseless time is obtained by the following way, comprising: If the absolute value of the real value of the one whole is greater than or equal to 16, the ideal LLR value of the one whole in the noiseless time is sequence DE1; If the absolute value of the real value of the one whole is less than 16, the ideal LLR value of the one whole in the noiseless time is sequence DE0 or sequence DE1; Wherein, the values of the sequence DE0 and the sequence DE1 correspond to the values of the ideal LLR values of the continuous 4 bits after the continuous 94 bits in the noiseless time in turn; The value of the sequence DE0 is 3, 5, 1, -1; The value of the sequence DE1 is 1, 7, 3, 1.

8. The method of claim 7, wherein: If the absolute value of the real value of the one whole is less than 16, when one of the following first group of conditions is met, the decoding priority of the sequence DE1 is higher than that of the sequence DE0; when one of the following second group of conditions is met, the decoding priority of the sequence DE0 is higher than that of the sequence DE1; wherein: The first set of conditions includes: an absolute value of the real number of the other whole is less than 16 and greater than 14; or, an absolute value of the real number of the other whole is less than 10 and greater than 6; or, an absolute value of the real number of the other whole is less than 2; The second set of conditions includes: an absolute value of the real number of the other whole is less than or equal to 14 and greater than or equal to 10; or, an absolute value of the real number of the other whole is less than or equal to 6 and greater than or equal to 2.

9. The method according to any one of claims 4 to 8, characterized in that, The LDPC decoding on the 2048 bits after the ideal LLR values of the adjacent bits being configured as noiseless is performed, including: When the value of the ideal LLR value of at least one of the one whole and the other whole is two sequences, obtaining decoding priorities of the two sequences; According to the order of the decoding priorities of the two sequences from high to low, performing an LDPC decoding operation, wherein the combination of the sequence values of the one whole and the other whole includes at least one of the following: The value of the first sequence of the one whole and the value of the first sequence of the other whole; The value of the first sequence of the one whole and the value of the second sequence of the other whole; The value of the second sequence of the one whole and the value of the first sequence of the other whole; The value of the second sequence of the one whole and the value of the second sequence of the other whole.

10. A computer storage medium comprising a processor and a memory, wherein the memory stores a computer program, and the processor invokes the computer program in the memory to implement the method according to any one of claims 1 to 9.

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