Method, communication system and storage medium for recovering error state of integrated circuit card

Abstract

A method for recovering an error state of an integrated circuit card, a communication system and a storage medium are disclosed. In an embodiment, a method for recovering an error state of an integrated circuit card, wherein the integrated circuit card is coupled to a transmitter device via a serial communication interface, the serial communication interface at least comprising a serial clock signal line, and the serial clock signal can be sent from the transmitter device to the integrated circuit card on the serial clock signal line, wherein the method comprises: when an error state is detected, the transmitter device embeds a reset signal into the serial clock signal; the transmitter device sends the serial clock signal as a reference clock signal on the serial clock signal line to the integrated circuit card, the reset signal indicates a change in a parameter of the serial clock signal; the integrated circuit card checks for the existence of a change in the parameter of the serial clock signal; and when the existence of a change in the parameter is checked, the integrated circuit card performs a transition from the error state to the reset state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102019000014595, filed on August 9, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to solutions related to recovering an error state of an integrated circuit card, in particular an eUICC (embedded universal integrated circuit card). The present disclosure also relates to a technique for performing serial communication between an embedded integrated circuit card (eUICC) and a card reader, for example in a mobile communication device. Background Art

[0004] The technical field of the present solution is serial communication between an embedded universal integrated circuit card (eUICC) and a corresponding reader device capable of transmitting data\information (with an accompanying clock) using a serial interface. Examples of such an interface may be a serial peripheral interface (SPI), an interface bus commonly used to send data between devices\microcontrollers, or an ISO 7816-3 interface for smart card communication. Based on any serial connection, data is transmitted using a serial protocol, which is usually implemented as a state machine in the processing units of the transmitter and receiver (e.g. in the master and slave devices of the SPI).

[0005] like Figure 1 As shown, it schematically represents the protocol state machine, starting from a first state S1, which represents an operating state in which, for example, transmission of data occurs, the serial interface between a transmitter (reader) and a receiver (card) may enter an error state E, which then requires a transition to a reset state R in order to then restore the first operating state S1. Summary of the invention

[0006] exist Figure 2 A possible architecture of a communication system 10 including an eUICC is shown in . The communication system 10 may be included in a hosting device such as a mobile communication device or an industrial communication device, ie a hosting device including an eUICC industrial card or an eUICC consumer card.

[0007] A first transmitter device, indicated at 11, is connected to a second receiver device 12, which is an eUICC, via a serial interface 12a, in particular an SPI interface. The first transmitter device 11 may be a reader of an eUICC card, for example an LPA (Local Configuration Assistant) module, or a module generally comprising a processing unit, which functions as a modem, for communicating to and from a communication device comprising the second receiver device 12. The first transmitter device 11 receives a voltage supply VCC via a voltage supply line AL, to which such a second receiver device 12 and also a third device 13 and a fourth device 14 are also coupled to receive a power supply. Such a third device 13 and a fourth device 14 may represent a memory for storing an operating system of a mobile communication device or an application executed by the operating system or other modules in the communication device. A reset line RL is shown, which carries a reset signal RS suitable for resetting one of the first transmitter device 11, the second receiver device 12, the third device 13, the fourth device 14 from an error state E. However, in Figure 2 1 shows a situation where only the first transmitter device 11, the third device 13 and the fourth device 14 are coupled to the reset line RL, while the second receiver device 12 is not coupled to the reset line RL, because, for example, the second receiver device 12 has no reset pin. The third device 13 and the fourth device 14 are coupled to each other via a serial interface 13a, which may be the same SPI interface.

[0008] The first transmitter device 11 may be coupled to a mobile communication interface for communicating with a base station, which base station may comprise a GSM (Global System for Mobile Communications), a CDMA (Code Division Multiple Access) transceiver, a W-CDMA (Wideband Code Division Multiple Access), a UMTS (Universal Mobile Telecommunications System), an HSPA (High Speed ​​Packet Access) and / or an LTE (Long Term Evolution) transceiver.

[0009] The serial interface 12a for exchanging data between the processing unit of the embedded system in the first transmitter device 11 and the second receiver device 12 may be a digital communication interface such as a UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface) and / or USB (Universal Serial Bus) communication interface.

[0010] based on Figure 2 In the system 10 shown, it can be seen that some systems are designed so that all components including the eUICC share only one power line Vcc, but in some systems the reset pin may not be coupled to one or more devices including the eUICC. Similarly, such a system may alternately use the same serial interface between several components including the eUICC. Systems developed subject to the above restrictions may therefore become part of the eUICC ecosystem.

[0011] In particular, the presence of a shared power line and / or the absence of a physical reset pin may be a strong limitation in solutions for interconnecting the eUICC and other systems\devices via serial interface communications.

[0012] There are several application scenarios for the eUICC where the presence of a recovery procedure using alternative signaling may be useful. In case of any type of error, the eUICC may lose the ability to correctly obtain protocol commands from the transmitter device and therefore need to be reset Figure 1 The protocol state machine is shown.

[0013] Failure to recover the data from the serial input stream may make it difficult to reset the state machine of the protocol between the transmitter and the eUICC. This may lead to a situation known as deadlock, in which the receiving device and the transmitting device are no longer able to understand and communicate with each other. As shown in the figure, sometimes not all devices have enough pins to guarantee an electrical\physical reset of the protocol state machine built on top of the (serial) communication.

[0014] Since sometimes the same serial interface can be shared between the eUICC and other devices, such as Figure 2 As shown, the serial interface is therefore blocked by the eUICC due to an unrecoverable error, which also causes serious inconvenience to other devices.

[0015] A device such as an eUICC may have only one physical reset pin, but may need to communicate with two different devices via different serial interfaces (e.g. SPI and ISO\UART). Sometimes it may happen that a physical reset from one serial interface interferes with the activity on another serial interface. Therefore, another inconvenience may be that the device may not be able to reset only one of the communication interfaces.

[0016] exist Figure 3, which shows a signal diagram showing a situation where a first transmitter device 11 communicates with a second receiver device 12 via a serial interface 12a and a third device 13 communicates with the second receiver device 12 via an ISO interface 12b. The power supply VCC and ground GNS shared by the power line AL are shown, and then the serial interface 12a provides pin connections SMI (i.e. SPI MISO), SMO (i.e. SPI MOSI), SCK (i.e. SPI clock input), and SSS (i.e. NSS slave select signal) between the first transmitter device 11 and the second receiver device 12. The ISO interface 12b includes a reset signal input IRI, an ISO clock signal input ICKI, and an ISO data input / output IIO. A deadlock DL is also shown on the serial interface 12a, which cannot be recovered by a physical reset performed by the third device 13 on the reset signal input IRI in the absence of a reset pin, because the deadlock is independent and unknown or because the reset will interfere with its activity. A deadlock DL on the second receiver device 12 on the serial interface 12a may also echo on the second interface, making it impossible to reset or attempt to recover by the other third device 13. In this case, only the transmitter device 11 can reset the second receiver device 12 activity on the serial interface 12a and then recover from the error, but there is no physical reset pin in the second receiver device 12 that can be used for this purpose.

[0017] Some solutions to the problem of recovering from a deadlock could be to physically reset the blocked eUICC or to switch the system voltage supply Vcc on and off. Figure 2 As shown, in some devices a specific reset pin is not available, or it is not possible to disconnect and reconnect the common power supply, as this would damage other components / subsystems other than the eUICC. This inconvenience is increased by the fact that the eUICC is usually soldered in the hosting device (or in any case barely accessible), which makes it further difficult to intervene in order to provide a physical reset solution.

[0018] Embodiments provide solutions that overcome one or more of the above disadvantages.

[0019] Further embodiments provide a method for recovering from an error condition in serial communications with an integrated circuit card. Other embodiments provide related systems, methods, and computer program products.

[0020] In an embodiment, the present disclosure relates to a method for recovering from an error state in serial communication with an integrated circuit card, in particular an eUICC, wherein a serial communication protocol includes a transition from the error state to a reset state upon receipt of a reset signal by the integrated circuit card, the serial communication includes operating on a serial communication interface, the serial communication interface includes at least a serial clock signal line coupling a transmitter device and the integrated circuit card, and a clock signal is sent from the transmitter device to the integrated circuit card on the serial clock signal line, the method comprising: upon detecting the error state, embedding the reset signal at the transmitter device into the serial clock signal sent to the integrated circuit card as a reference clock signal on the serial clock signal line, the reset signal being represented by a change in a parameter of the clock signal; checking for the presence of the change in the parameter of the clock signal at the integrated circuit card, and performing the transition from the error state to the reset state upon checking for the presence of the change in the parameter of the clock signal at the integrated circuit card.

[0021] In a variant embodiment, said variation of a parameter of the clock signal at the integrated circuit card consists of changing the frequency of the clock signal.

[0022] In a variant embodiment, the changing comprises performing a voltage-to-frequency conversion.

[0023] In a variant embodiment, said variation of a parameter of a clock signal at the integrated circuit card comprises changing a clock duty cycle.

[0024] In a variant embodiment, said variation of a parameter of the clock signal at the integrated circuit card comprises changing the duty cycle by pulse width modulation.

[0025] In a variant embodiment, said change in a parameter of the clock signal encodes a further command or instruction to the integrated circuit card other than said reset signal.

[0026] In a variant embodiment, when an error state is detected, the transmitter device and the integrated circuit card enter a clock processing state, during which they respectively perform such a change in the parameters of the clock signal and check the existence of the said change in the parameters of the clock signal, and then the transmitter and the integrated circuit card enter a reset state in a time-aligned manner.

[0027] Other embodiments relate to a communication system including a serial communication interface including at least a data line and a serial clock signal line that couple a transmitter device configured to operate according to the method of any of the above embodiments and an integrated circuit card.

[0028] In a variant embodiment, the transmitter device includes a clock modifier circuit, which is configured to perform the change of the parameters of the clock signal, and the integrated circuit card includes a clock sampler circuit, which is configured to detect the change of the determined parameters of the serial clock signal on the clock signal line of the serial interface.

[0029] In a variant implementation, the integrated circuit card is an eUICC.

[0030] In a variant embodiment, the id communication system is included in a hosting device, in particular a mobile communication device, and the transmitter is a module including a processing unit operating as a modem for communicating to and from a communication device containing an integrated circuit card.

[0031] The present disclosure also relates to a computer program product directly loadable into the internal memory of a digital computer, comprising software code portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting examples only, and in which:

[0033] As described above Figure 1-3 ; is a schematic circuit diagram of an implementation scheme of the technical solution described in this article.

[0034] Figure 4 shows a diagram representing communication protocol states assumed by a transmitter and a receiver according to the methods described herein;

[0035] Figure 5 A schematic block diagram of a system for implementing the method described herein is shown;

[0036] Figure 6 shows a flow chart representing an embodiment of the method described herein; and

[0037] Figure 7 A state diagram is shown that represents an example of an error state occurring in a serial interface. DETAILED DESCRIPTION

[0038] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or several of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0039] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily all refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0040] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0041] As mentioned above, since there is a situation where a specific reset pin in the serial interface is not available when the eUICC is coupled via a serial interface, or the power line cannot be disconnected and connected, the method described herein provides a reset signal (i.e., an error recovery sequence) using a serial clock signal of the serial interface, which performs the reset signal from Figure 1 The transition from the error state E to the reset state R in the eUICC is to issue a "reset" command sequence to the eUICC if the eUICC has lost the ability to receive logical commands on the data line in the event of an error or deadlock.

[0042] exist Figure 4 , the evolution of the states of a first transmitter device 11 and a second receiver device 12 (i.e., receiving device) over time t is shown. At time t=0, the system is in an error state E, and then the first transmitter device 11 enters a clock processing state CP, in which a change VC in the clock parameter is applied to the clock signal of the serial interface 12a (e.g., the clock signal on the SPI clock line SCK). The second receiver device 12 also enters the clock processing state CP, and performs an operation CC of checking the clock signal on the SPI clock line SCK to detect a change in the clock parameter relative to the clock signal. The transmitter device 11 then transitions to a reset state R, and the second receiver device 12 is configured to interpret this change in the clock parameter relative to the clock signal as a reset signal during the checking operation CC, and also transitions to the reset state R. It can therefore be recovered Figure 1 The state machine operates, and then according to the normal protocol provisions, the protocol transitions to the working state S1, for example, at the idle interval IL.

[0043] Therefore, recovery of the protocol reset state R by the second receiver device 12 is performed by sampling the changes of some parameters of the clock signal supplied on the serial interface by the transmitter device 11 in the clock processing state CP.

[0044] As shown, the process requires operating a change VP of some parameter of the clock signal supplied to the second receiver device 12, so that when a change in the clock parameter is detected, the receiving device can return to the protocol state machine "reset". Such clock parameters generally include any parameters that define the evolution of the clock signal over time, and preferably include the clock signal frequency and / or duty cycle. However, a change in amplitude or a change in jitter or phase noise or a change in waveform (e.g., a rise time change) can also be used to represent a reset signal.

[0045] Typically, since the management of the serial protocol interface state is performed by the corresponding processing units of the first transmitter device 11 and the second receiver device 12, these processing units are preferably configured to also respectively command changes in clock parameters VC and operations CC to check the clock signal on the SPI clock line SCK (especially through commands and control of specific circuits or modules configured to perform such operations VC, CC) to detect changes in clock parameters relative to the clock signal.

[0046] refer to Figure 5 , there is shown a partial representation of a system with a first transmitter device 11 and a second receiver device 12, the first transmitter device 11 comprising a clock modifier circuit 111 configured to change a determined parameter of a serial clock signal CKS on a clock signal line SCK of a serial interface 12a to embed a corresponding reset signal RS into the serial clock signal CKS. The second receiver device 12 comprises a clock sampler circuit 121 configured to detect a change of the determined parameter of the serial clock signal CKS on the clock signal line SCK of the serial interface 12a.

[0047] The first transmitter device 11 is configured such that it commands the clock modifier circuit 111 to generate a change in a parameter of the clock signal CKS, in particular the clock frequency or the clock duty cycle, when it obtains information that the second receiver device 12 is not responding and requires a "protocol" reset R. The first transmitter device 11 thus enters a reset state R.

[0048] The clock sampler circuit 121 samples the clock signal CKS measuring the corresponding clock parameter (i.e., the clock frequency or the clock duty cycle), and is configured to interpret the determined change of such parameter as a command for the second receiver device 12 to enter the reset state R, thereby aligning both the first transmitter device 11 and the second receiver device 12 with the protocol reset state R so that communication can be resumed. In other words, the first transmitter device 11 performs a change in the clock parameter and enters the reset state R, and the second receiver device 12 samples the change and enters the reset state R consistent with the first transmitter device 11.

[0049] In order to implement such a solution, a decomposition of the device serial protocol and the definition of related states are performed, such as reset state R, received frame, sent response, etc. .... Error state E can be associated with specific conditions regarding confirmation, or received frame or sent response or others, which for example define the condition that the second receiver device 12 does not respond or responds with erroneous data.

[0050] For example, in Figure 7 In the example of the state diagram, a serial interface is a serial interface and an APDU is sent through the interface. The sending of APDU (application protocol data unit) is a typical activity of the transmitter and the integrated card. The figure shows the state at the first transmitter device 11. In particular, SS represents the start state, from which the idle state AS1 is entered. From the idle state AS1, the send APDU state AS2 is reached by using the action TA1 of requesting to send the application APDU. If the send APDU action AS2 is performed, the transmitter enters the waiting ACK state AS3, and if the NACK (unconfirmed character or message) received action TA4 is detected, the state AS3 can return to the state AS2, or if the ACK reception action TA3 is detected, the state AS3 can return to the ACK (confirmed character or message) received state AS4. If other messages (action TA5) other than ACK or NACK are received in the waiting ACK state AS3, the error state E is reached, which remains unchanged when other messages other than ACK or NACK TA5 are still received. A power-off action TA6 or sending an abort command and receiving an ATR TA7 may perform a transition to the reset state R. From the reset R or ACK received state AS5, an application action TA8 is awaited to return to the idle state AS1.

[0051] If during the processing of a command or APDU the first sender device 11 reaches the Error State E and is unable to disconnect and restart the eUICC (e.g. power off "transition" TA6), or the second receiver device 12 is no longer able to process any "apply" commands (e.g. sending an Abort command and receiving a positive transition of ATR TA7), it will remain permanently in the Error State E state and therefore requires the solution described herein to reset the communication.

[0052] Thus, in this case, the error state E is associated with a specific condition regarding acknowledgement, ie no data is received but no ACK or NACK is received. For example, this defines the condition that the second receiver device 12 does not respond or responds with erroneous data.

[0053] The clock modifier circuit (or logic module) 111 designed to modify the parameters of the clock signal on the sending device in the event of an unrecoverable error can be, for example, a PWM modulation circuit that applies a duty cycle modification. The clock modifier circuit (or logic module) 111 can also be a voltage to frequency converter to apply clock frequency modification to the clock signal CKS.

[0054] The clock sampler circuit (or logic module) 121 designed to detect the modified parameters of the clock signal on the receiving device can be, for example, a low pass filter to detect duty cycle changes, which essentially cuts out the changes in the clock and leaves only the average value of the clock signal to pass for analysis. The clock sampler circuit (or logic module) 121 can also be a frequency-to-voltage converter circuit module for detecting frequency changes, which converts the clock frequency into a voltage value proportional to the frequency change. A pulse counting circuit can also be used instead.

[0055] The first transmitter device 11 is configured to detect a protocol error, for example, when the second receiver device 12 does not respond or responds with erroneous data during transmission. The first transmitter device 11 may decide to modify the serial clock signal CKS by means of the clock modifier circuit 111 to reset the protocol state machine PSM and restart the communication with the receiving module (i.e. the second receiver device 12).

[0056] The second receiver device 12 as a receiver device is configured by the clock sampler circuit 121 to generate a reset signal for the transmitter-receiver protocol state machine PSM, i.e. to perform the transition from the error state to the reset state, if any change exceeding a threshold or tolerance established a priori is detected in the parameters of the detected serial clock signal CKS provided by the first transmitter device 11.

[0057] The serial clock variation may also be used to send simple commands or instructions to the eUICC, ie commands not related to the need to reset the device, which may also be sent over a different serial interface (eg ISO) to which it is coupled with an accompanying clock.

[0058] Thus, generally, a method for recovering an error state E in a serial communication with an integrated circuit card, in particular a second receiver device 12, wherein the serial communication protocol includes a transition from the error state E to the reset state R when the integrated circuit card receives a reset command, may include operating on a serial interface 12a, the serial communication interface comprising at least a data line coupling the first transmitter device 11 and the integrated circuit card, i.e., the clock signal line may not be present. Thus, the method generally comprises: upon detection of the error state E, at the first transmitter device 11, embedding a reset signal in a signal sent to the integrated circuit card via the clock signal interface, which signal may preferably be a clock signal, but may also be a data signal. The reset signal may be a direct change of the clock signal on the interface, which becomes a reference internal clock signal at the second receiver device 12. Thus, checking the presence of the reset signal at the integrated card may be achieved by directly checking a parameter change in the received clock signal CKS or a parameter change in the clock signal of the integrated circuit card derived from the input clock signal CKS, and then performing the transition from the error state E to the reset state R when the presence of the reset signal is checked at the integrated circuit card.

[0059] exist Figure 6 In the figure, a flowchart of a possible implementation of a method for recovering an error state in serial communication with an integrated circuit card, in particular an eUICC, indicated by reference numeral 200 is shown, wherein the serial communication protocol is such as Figure 1 The transition from error state E to reset state R when the integrated circuit card receives a reset command is shown, and the serial communication includes operating on a serial communication interface, such as Figure 2 or Figure 5 As shown, the serial communication interface comprises at least a data line (e.g., Figure 3 SMI or SMO in the SPI shown) and a serial clock signal line (e.g., SCK).

[0060] The operation of detecting the error state E by running the serial interface protocol by means of its processing unit is indicated by 210 , in particular at the first transmitter device 11 .

[0061] 220 indicates an operation in which, if an error state E is detected in operation 210, a reset signal RS is embedded into the serial clock signal CKS at the first transmitter device 11, and the serial clock signal CKS is sent to the integrated circuit card on the serial clock signal line CKS, wherein the reset signal RS is represented by a change VC of a parameter of the clock signal SCK, i.e., preferably a duty cycle change or a frequency clock change.

[0062] Then in step 225 the first transmitter device 11 enters a reset state.

[0063] The operation of checking the presence of the change VC in the parameters of the clock signal SCK at the integrated circuit card by CC is indicated by 230. When the presence of the change VC is checked, the second receiver device 12 also enters the reset state R in step 235, so that the serial interface protocol represented by the first transmitter device 11 and the second receiver device 12 performs the transition from the error state E to the reset state R.

[0064] Therefore, the solution disclosed herein has significant advantages over known solutions.

[0065] It is emphasized that although in the flowchart, operations 225 and 235 regarding the first transmitter device 11 and the second receiver device 12 entering the reset state R are shown as subsequent operations, they are aligned in time, such as Figure 4 As shown, this is because they all enter the clock processing state CP, during which they perform changes VC and checks CC, and then enter the reset state R in a time-aligned manner.

[0066] The solution just described allows transport protocol state machine error recovery for eUICC subsystems where a specific reset pin is not available or too expensive, or where power cycling is not possible.

[0067] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined by the appended claims.

Claims

1. A method for recovering an error state of an integrated circuit card, wherein the integrated circuit card is coupled to a transmitter device via a serial communication interface, the serial communication interface comprising at least a serial clock signal line, a serial clock signal being able to be sent from the transmitter device to the integrated circuit card on the serial clock signal line, the method comprising: When the error state is detected, embedding a reset signal into the serial clock signal by the transmitter device; The transmitter device transmits the serial clock signal as a reference clock signal on the serial clock signal line to the integrated circuit card, the reset signal indicating a change in a parameter of the serial clock signal; checking, by the integrated circuit card, for the presence of a change in the parameter of the serial clock signal; as well as Upon detecting the presence of a change in the parameter, the integrated circuit card performs a transition from the error state to a reset state; Wherein, when the error state is detected, the transmitter device and the integrated circuit card enter a clock processing state, during which the transmitter device and the integrated circuit card perform changes in the parameters of the serial clock signal, and when the presence of the parameter change is detected, the transmitter device and the integrated circuit card enter the reset state in a time-aligned manner. 2 . The method of claim 1 , wherein the change in the parameter of the serial clock signal at the integrated circuit card comprises a change in clock signal frequency. The method of claim 2 , wherein the change in the parameter comprises a voltage-to-frequency conversion. The method of claim 1 , wherein the change in the parameter comprises a change in a clock duty cycle. The method of claim 4 , wherein the variation of the parameter comprises a variation of a clock duty cycle by changing the clock duty cycle through pulse width modulation.

6. The method of claim 1, wherein the change in the parameter comprises an additional instruction to the integrated circuit card that is different from the reset signal.

7. The method of claim 1, wherein the integrated circuit card is an embedded universal integrated circuit card (eUICC), and wherein the transmitter device is a card reader.

8. The method of claim 1, wherein the integrated circuit card does not have a reset pin.

9. A communication system comprising: Transmitter equipment; Integrated circuit card; as well as a serial communication interface, comprising at least a serial clock signal line coupling the transmitter device and the integrated circuit card, The transmitter device is configured as follows: When an error condition is detected, a reset signal is embedded into the serial clock signal, and The serial clock signal is sent to the integrated circuit card as a reference clock signal on the serial clock signal line, the reset signal indicates a change in a parameter of the serial clock signal, and The integrated circuit card is configured as follows: checking for the presence of a change in said parameter of said serial clock signal, and When there is a change in the parameter, performing a transition from the error state to a reset state; Wherein, when the error state is detected, the transmitter device and the integrated circuit card enter a clock processing state, during which the transmitter device and the integrated circuit card perform changes in the parameters of the serial clock signal, and when the presence of the parameter change is detected, the transmitter device and the integrated circuit card enter the reset state in a time-aligned manner.

10. The communication system of claim 9, wherein the transmitter device comprises a clock modifier circuit configured to perform a change in a parameter of the serial clock signal.

11. The communication system of claim 10, wherein the integrated circuit card comprises a clock sampler circuit configured to detect a change in the parameter of the serial clock signal on the serial clock signal line of a serial communication interface.

12. The communication system of claim 9, wherein the integrated circuit card is an embedded universal integrated circuit card (eUICC), and wherein the transmitter device is a card reader.

13. The communication system of claim 9, wherein the communication system is a mobile communication device.

14. The communication system of claim 9, wherein the change in the parameter of the serial clock signal comprises a change in a clock signal frequency.

15. The communication system of claim 9, wherein the change in the parameter of the serial clock signal comprises a clock duty cycle change.

16. The communication system of claim 9, wherein the integrated circuit card does not have a reset pin.

17. A non-transitory machine-readable storage medium storing instructions that, when executed by an apparatus, cause the apparatus to: When an error condition is detected, a reset signal is embedded into the serial clock signal by the transmitter device; The transmitter device transmits the serial clock signal as a reference clock signal on a serial clock signal line to an integrated circuit card, wherein the reset signal indicates a change in a parameter of the serial clock signal; checking, by the integrated circuit card, for the presence of a change in the parameter of the serial clock signal; as well as When there is a change in the parameter, the integrated circuit card performs a transition from the error state to a reset state; Wherein, when the error state is detected, the transmitter device and the integrated circuit card enter a clock processing state, during which the transmitter device and the integrated circuit card perform changes in the parameters of the serial clock signal, and when the presence of the parameter change is detected, the transmitter device and the integrated circuit card enter the reset state in a time-aligned manner.

18. The non-transitory machine-readable storage medium of claim 17, wherein the change in the parameter of the serial clock signal comprises a change in a clock signal frequency.

19. The non-transitory machine-readable storage medium of claim 17, wherein the change in the parameter of the serial clock signal comprises a clock duty cycle change.

Images