System and control method for implementing DSP reset process based on FPGA

Abstract

The application provides a system and a control method for implementing a DSP reset process based on FPGA, and relates to the technical field of DSP reset. A first IO pin of the FPGA is connected with a reset pin of the DSP through a DSP reset line to control the reset process of the DSP. A second IO pin of the FPGA is connected with a GPIO pin of the DSP through a DSP state flag line to represent the reset state of the DSP, so that initial reset control and midway crash reset control are completed. The reset signal of the DSP is controlled by the FPGA, and the application has the characteristics of flexibility, time controllability, state controllability, field maintainability and the like, and effectively solves the two technical problems of power-on non-starting and midway crash of the DSP.

Description

Technical Field

[0001] This invention relates to the field of DSP reset technology, and in particular to a system and control method for implementing the DSP reset process based on FPGA. Background Technology

[0002] With the development of digital signal processors (DSPs) and field-programmable gate arrays (FPGAs), digital hardware systems employing DSP+FPGA have demonstrated their superiority, combining the advantages of both while balancing speed and flexibility. Therefore, this architecture is gaining increasing attention and its applications are becoming more widespread.

[0003] Digital signal processors (DSPs) often experience initial reset failures and program crashes during operation. The DSP product user manual from the National University of Defense Technology offers four suggestions regarding reset signals and the startup system: (1) Reset signals and startup mode setting signals must be stable and reliable; (2) Reset signals should meet the timing requirements of the chip datasheet; (3) Reset operations are generally performed in conjunction with the power supply system's startup process, and their coordinated operation should be carefully considered; (4) Reset signals and startup mode signals are crucial for ensuring normal system startup and operation, but no design can guarantee 100% successful startup. Therefore, reset signals and startup modes should ideally be designed in conjunction with the power supply system to significantly reduce the probability of startup failure through multiple automatic retries. However, currently, there is no effective method to solve the two technical problems of DSPs failing to start upon power-on and crashing mid-program.

[0004] Therefore, there is an urgent need for a technology that can effectively solve the two technical problems of DSP failing to start upon power-up and crashing midway through operation. Summary of the Invention

[0005] The purpose of this invention is to provide a system and control method for implementing the DSP reset process based on FPGA. Using FPGA to control the DSP reset process has the characteristics of flexibility, time controllability, state controllability, and field maintainability, effectively solving the two technical problems of DSP power-on failure and mid-process crash.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A system for implementing a DSP reset process based on an FPGA, the system comprising: an FPGA and a DSP; a first I / O pin of the FPGA connected to the reset pin of the DSP via a DSP reset line; and a second I / O pin of the FPGA connected to the GPIO pin of the DSP via a DSP status flag line.

[0008] The FPGA is used to control the reset process of the DSP through the DSP reset line, and the DSP status flag line represents the reset status of the DSP; the reset status includes the initial reset status and the mid-process crash reset status.

[0009] A control method for implementing DSP reset process based on FPGA, which works based on the above-mentioned system, the control method includes an initial reset control process and a mid-process crash reset control process;

[0010] The initial reset control process includes:

[0011] The FPGA sets the DSP's reset pin to a low level via the DSP reset line;

[0012] The FPGA detects whether the DSP has been successfully reset within a first preset time. If the reset is unsuccessful, it returns to the step of "the FPGA sets the DSP's reset pin to a low level through the DSP reset line" until the DSP is successfully reset. When the DSP is successfully reset, the FPGA sets the DSP's GPIO pin to a low level through the DSP status flag line.

[0013] The mid-process crash reset control process includes:

[0014] The FPGA receives a first signal sent by the DSP every second preset time interval during normal operation;

[0015] If the first signal is not received, the FPGA considers the DSP to have crashed midway, sets the DSP's reset pin to a low level through the DSP reset line, and sends the global variables and intermediate data of the DSP before the crash to the DSP, so that the DSP can resume its working state before the crash after a successful reset.

[0016] A control method for implementing DSP reset process based on FPGA, which works based on the above-mentioned system, the control method includes an initial reset control process and a mid-process crash reset control process;

[0017] The initial reset control process includes:

[0018] The DSP detects whether the reset pin is at a low level.

[0019] If so, the DSP starts resetting and sends a second signal to the FPGA when the reset is successful; if the reset is unsuccessful, it returns to the step of "DSP checks whether the reset pin is low" until the reset is successful.

[0020] The mid-process crash reset control process includes:

[0021] The DSP detects whether the reset pin is at a low level.

[0022] If so, the DSP begins to reset and reads the global variables and intermediate data of the DSP before the crash from the FPGA, so as to restore the working state before the crash when the reset is successful.

[0023] Compared with existing technologies, this invention provides a system and control method for implementing the DSP reset process based on FPGA. The first IO pin of the FPGA is connected to the reset pin of the DSP through the DSP reset line to control the DSP reset process. The second IO pin of the FPGA is connected to the GPIO pin of the DSP through the DSP status flag line to characterize the DSP reset status, thereby completing the initial reset control and the mid-process crash reset control. Using FPGA to control the DSP reset signal has the characteristics of flexibility, time controllability, status controllability, and field maintainability, effectively solving the two technical problems of DSP power-on failure and mid-process crash. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0025] Figure 1 This is a schematic diagram of the system provided in Embodiment 1 of the present invention;

[0026] Figure 2 This is a timing diagram of the first successful DSP initial reset provided in Embodiment 1 of the present invention;

[0027] Figure 3 This is a timing diagram of the second successful initial reset of the DSP provided in Embodiment 1 of the present invention;

[0028] Figure 4 This is a timing diagram of DSP mid-process reset provided in Embodiment 1 of the present invention;

[0029] Figure 5 This is a flowchart of the reset module provided in Embodiment 2 of the present invention;

[0030] Figure 6 This is a flowchart of the detection module provided in Embodiment 2 of the present invention;

[0031] Figure 7 This is a flowchart of the Bootloader assembly program and main() program provided in Embodiment 3 of the present invention;

[0032] Figure 8 This is a flowchart of the interrupt handling function provided in Embodiment 3 of the present invention. Detailed Implementation

[0033] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0034] Example 1:

[0035] The DSP's power-on process is as follows: The DSP is configured in 16-bit boot mode. After power-on reset, the DSP's firmware boot program copies 1KB of program from the address space selected by / CE1 (i.e., 0x90000000) to the internal SRAM address space starting from address 0. This 1KB program, the bootloader program, is executed from address 0. This 1KB program is typically used to move the DSP's running program from Flash to its designated SRAM space and to jump the instruction pointer to the DSP's running program entry point, the main{} function, to execute the DSP's running program. The DSP then continuously runs the DSP's running program.

[0036] During DSP operation, due to external interference or other unknown reasons, the program may crash, resulting in a system freeze. Although the causes and mechanisms of program crashes are not yet fully understood, a mid-process reset can be considered to allow the DSP to continue operating. However, current mid-process resets for DSPs face two main problems: First, the DSP needs to reload its runtime program, which takes approximately 600ms, while the overall communication cycle is required to be 20ms. Such a long restart time is unacceptable. Second, after a reset, the state of the system just before the crash, including some global variables and intermediate data, is corrupted. Entering the main() function requires re-initializing these variables, which is even more unacceptable. To address these two issues, we need to consider whether the program and data segments in the DSP's memory still exist after a program crash. If the program segment exists, a mid-process reset can avoid reloading the DSP runtime program; if the data segment exists, a mid-process reset can restore the state of the system just before the crash without re-initializing global variables. In this embodiment, during DSP online simulation, the CCS Debug mode includes a DSP reset command, `reset cpu`. When `reset cpu` is executed, it is observed that the program segment in memory remains unchanged, while the data segment content changes. Based on the above understanding of the DSP's power-on process and memory state during mid-process crash reset, this embodiment proposes a system based on FPGA to implement the DSP reset process, which can utilize FPGA to implement the DSP watchdog mechanism.

[0037] like Figure 1 As shown, this embodiment provides a system for implementing the DSP reset process based on an FPGA. The system includes an FPGA and a DSP. The first I / O pin of the FPGA is connected to the reset pin / RESET of the DSP via a DSP reset line, and the second I / O pin of the FPGA is connected to the GPIO pin of the DSP via a DSP status flag line. Figure 1 The FPGA is used to control the DSP reset process by operating the DSP reset line. The DSP status flag line is used to represent the DSP reset state. The reset state includes the initial reset state and the mid-term crash reset state. Thus, by operating the DSP status flag line, the FPGA tells the DSP whether the DSP is in the initial reset state or the mid-term crash reset state when it is reset.

[0038] The system in this embodiment can be a long-endurance, high-precision integrated navigation system based on a DSP+FPGA structure. The DSP can be the TMS320C6713B from TI, and the FPGA can be the A3P1000 from ACTEL.

[0039] During the initial power-on reset phase of the above system, the cooperation relationship between the FPGA and the DSP is as follows:

[0040] After the system is initially powered on, the FPGA is reset first, which lasts for approximately 150ms. During this period, the corresponding I / O port of the FPGA (i.e., the first I / O pin) keeps the DSP's reset pin / RESET high. After the FPGA reset is complete, it pulls the DSP's reset pin / RESET low for 500ms to initiate the DSP reset. If the DSP reset is successful, the DSP will automatically load a 1KByte bootloader program, which takes approximately 3ms. After that, the bootloader program will start running, loading the DSP's executable program from Flash into the DSP's SRAM. The loading time depends on the length of the executable program, which is approximately 600ms. Then, the instruction pointer will jump to the main() function entry point of the DSP's executable program to begin execution. After entering the main() function, the DSP immediately sends a "handshake" signal to the FPGA through the EMIF interface to indicate that the DSP is working normally. Based on this, the FPGA continuously monitors the "handshake" signal (including address lines, data lines, the DSP's chip select signal / CE2, and write signal / AWE) for 800ms after the DSP begins its reset. If the FPGA detects that all signals are normal within 800ms (i.e., it receives the "handshake" signal), it considers the DSP reset successful and is operating normally. At this time, the DSP's reset pin remains at a high level. If the FPGA cannot detect the "handshake" signal from the DSP within 800ms, it considers the DSP reset unsuccessful. The FPGA will then re-reset the DSP for 20ms and repeat the previous 800ms detection process. This reset cycle continues until the DSP resets successfully and operates normally. Before the DSP successfully resets, the FPGA sets the corresponding GPIO pin of the DSP to a high level. When it detects the "handshake" signal indicating normal DSP operation, the FPGA sets this GPIO pin to a low level, indicating that the DSP has entered a normal operating state. This method ensures that even if the DSP fails to reset initially, it can still be reset successfully through subsequent detection, thus solving the problem of unsuccessful DSP power-on reset.

[0041] During the DSP crash and reset phase in the above system, the cooperation relationship between the FPGA and the DSP is as follows:

[0042] During DSP operation, external interference or other unknown reasons may cause the program to crash or stop working, resulting in a system freeze. To resolve this issue, system requirements stipulate that the DSP must be able to resume normal operation within 20ms after a freeze. This means completing a reset, loading and executing the bootloader program, and finally jumping to the main() function entry point of the DSP's running program within 20ms. Furthermore, global variables and intermediate data needed for the next computation cycle must be protected. During this period, the system must also be able to receive data and commands from other systems without interrupting the normal workflow.

[0043] To meet the above requirements, close cooperation between the FPGA and DSP is necessary, making reasonable use of the FPGA's timing control capabilities and the DSP's operating mechanism. This embodiment designs the following scheme: After the DSP is working normally, it sends a "feed the watchdog" signal to the FPGA every 5ms via the EMIF interface in its interrupt service routine. The FPGA continuously monitors this "feed the watchdog" signal. If it detects the "feed the watchdog" signal (within 7ms), it considers the DSP to be working normally; otherwise, it considers the DSP to have crashed and sends a 10ms reset signal to the DSP. After the DSP resets, it spends 3ms loading and executing the Bootloader program. The Bootloader program includes a jump branch that checks the GPIO pin level. If the GPIO pin is high, it indicates the DSP is in the initial power-on reset phase, and the Bootloader program will spend approximately 600ms loading the DSP's running program. If the GPIO pin is low, it indicates the DSP is in the mid-process crash reset phase, and the Bootloader program will not load the DSP's running program but will directly jump to the main() function entry point to begin execution. To maintain context, during normal operation, the DSP sends necessary global variables and intermediate data to the FPGA every 5ms during its interrupt service routine. This ensures that when the main() function begins execution, these global variables and intermediate data are immediately read from the corresponding registers on the FPGA, guaranteeing context restoration. During a DSP crash, any data and commands sent to this system from other systems are stored in a FIFO built into the FPGA and will not be lost. These measures ensure that in the event of a DSP crash, the system can seamlessly resume its previous operating state in less than 20ms.

[0044] In order to improve the reliability of the DSP, this embodiment uses an FPGA to control the DSP's reset signal and to save the DSP's global variables in real time. This method is equivalent to using an FPGA to implement the DSP's "watchdog" mechanism, which has the characteristics of flexibility, time controllability, state controllability, and field maintainability. It effectively solves the two technical problems of DSP not starting up after power-on and crashing midway.

[0045] Here, this embodiment verifies the reset result of the system provided above:

[0046] (1) Verification of initial reset results

[0047] Using the above implementation scheme, in approximately one thousand experiments over the past three months, the DSP initial reset success rate was over 95%, and its timing waveform is as follows: Figure 2 As shown, the FPGA reset time is approximately 150ms, and then a 500ms reset signal is sent to the DSP. After the DSP is successfully reset, Flash_cs is first pulled high and then pulled low for 3ms. During these 3ms, the 1KB Bootloader is loaded. Then, it is pulled high and low again for approximately 600ms to complete the transfer of the DSP's running program.

[0048] If the initial DSP reset fails on the first attempt, the second reset will almost certainly succeed. The timing waveform is as follows: Figure 3 As shown, the FPGA reset time is approximately 150ms, and then a 500ms reset signal is sent to the DSP. If the FPGA does not receive a handshake signal from the DSP within 800ms, it assumes that the DSP has not reset successfully, and then sends a 20ms reset signal to the DSP. When the DSP resets successfully for the second time, Flash_cs is first pulled low for 3ms. During these 3ms, the 1KB Bootloader is loaded, and then it is pulled high and low for approximately 600ms to complete the migration of the DSP's running program.

[0049] (2) Verification of the results of mid-process crash and reset

[0050] During normal DSP operation, in the interrupt service routine (every 5ms), a "feed the watchdog" signal is first sent to the FPGA (the DSP writes a value to a fixed address on the FPGA). After completing the interrupt service routine, the current global variable value is written to the FPGA. The FPGA checks for the "feed the watchdog" signal within 7ms (the FPGA checks the corresponding address and data lines). If it does not receive the "feed the watchdog" signal, it assumes the DSP has crashed and sends a 10ms reset signal to the DSP. Figure 4 As shown, after the DSP is successfully reset, Flash_cs is pulled low for 3ms. During this 3ms time, the 1KB Bootloader is loaded. There is no need to load the DSP running program again. The program jumps directly to the main() function entry point, reads global variables from the FPGA, and continues to run. The whole process takes no more than 20ms, which meets the overall communication requirements.

[0051] After repeated verification, the solution in this embodiment has been proven to be effective.

[0052] Example 2:

[0053] This embodiment provides a control method for implementing the DSP reset process based on FPGA, which works based on the system described in Embodiment 1. The control method includes an initial reset control process and a mid-process crash reset control process.

[0054] (1) The initial reset control process includes:

[0055] The FPGA sets the DSP's reset pin to a low level via the DSP reset line;

[0056] The FPGA detects whether the DSP has been successfully reset within a first preset time. If the reset is unsuccessful, it returns to the step of "the FPGA sets the DSP's reset pin to a low level through the DSP reset line" until the DSP is successfully reset. When the DSP is successfully reset, the FPGA sets the DSP's GPIO pin to a low level through the DSP status flag line.

[0057] The FPGA's detection of whether the DSP has successfully reset within a first preset time period can include: the FPGA determining whether it receives a second signal sent after the DSP has successfully reset within the first preset time period; if the second signal is received, the DSP reset is successful; otherwise, the DSP has not reset successfully. The first preset time period can be 800ms, and the second signal is the "handshake" signal.

[0058] During the initial reset control process, when the FPGA first sets the DSP's reset pin to low level through the DSP reset line, it holds the low level for a third preset time. After the third preset time, it sets the DSP's reset pin to high level through the DSP reset line. The third preset time can be 500ms. When the FPGA sets the DSP's reset pin to low level through the DSP reset line for the nth time, it holds the low level for a fourth preset time. After the fourth preset time, it sets the DSP's reset pin to high level through the DSP reset line. n = 2, 3, ..., N, where N is the number of cycles required for a successful DSP reset. The fourth preset time can be 20ms.

[0059] It should be noted that both the third and fourth preset times must be less than the first preset time.

[0060] Before the DSP successfully initializes, the FPGA sets the DSP's GPIO pins to a high level. When the FPGA detects the "handshake" signal indicating normal operation of the DSP, it sets the GPIO pins to a low level. Thus, the DSP can determine its reset state by detecting the level of the GPIO pins.

[0061] (2) The mid-process crash reset control process includes:

[0062] The FPGA receives a first signal sent by the DSP every second preset time during normal operation; the second preset time can be 5ms, and the first signal can be a "feed the dog" signal.

[0063] If the first signal is not received, the FPGA assumes that the DSP has crashed midway. It sets the DSP's reset pin to a low level through the DSP reset line and sends the global variables and intermediate data of the DSP before the crash to the DSP so that the DSP can resume its working state before the crash after a successful reset.

[0064] As an alternative implementation, if the DSP crashes midway, the FPGA receives data and commands sent to the system by external devices.

[0065] To complete the above control process, this embodiment requires the design of an FPGA program. The implementation of the FPGA program requires three modules: a reset module, a detection module, and a global variable access module. For example... Figure 5 As shown, the reset module implements the initial reset and mid-process reset of the DSP. Figure 6 As shown, the detection module is used to detect whether the DSP crashes midway. The global variable access module works with the DSP to read and write global variables.

[0066] To improve DSP reliability, this embodiment uses an FPGA to control the DSP's reset signal and to store the DSP's global variables in real time. This method is equivalent to using an FPGA to implement the DSP's "watchdog" mechanism, offering flexibility, time controllability, state controllability, and field maintainability. It effectively solves the two technical problems of DSP failing to start upon power-on and crashing mid-process. Repeated verification has proven the effectiveness of the solution.

[0067] Example 3:

[0068] This embodiment provides a control method for implementing the DSP reset process based on FPGA, which works based on the system described in Embodiment 1. The control method includes an initial reset control process and a mid-process crash reset control process.

[0069] (1) The initial reset control process includes:

[0070] The DSP detects whether the reset pin is at a low level.

[0071] If so, the DSP starts resetting and sends a second signal to the FPGA when the reset is successful; if the reset is unsuccessful, it returns to the step of "DSP checks whether the reset pin is low" until the reset is successful; the second signal is the "handshake" signal.

[0072] During the initial reset control process, after the DSP starts resetting, it automatically loads and runs the secondary loading program to obtain the DSP running program and automatically executes the DSP running program.

[0073] After a successful initial reset of the DSP, the DSP will send a first signal and the global variables and intermediate data that need to be saved to the FPGA every second preset time interval. The first signal is the "feed the dog" signal.

[0074] (2) The mid-process crash reset control process includes:

[0075] The DSP detects whether the reset pin is at a low level.

[0076] If so, the DSP will begin to reset and read the global variables and intermediate data from the FPGA before the DSP crashed, so as to restore the working state before the crash when the reset is successful.

[0077] When the DSP starts resetting, it automatically loads and runs the secondary loading program. While running the secondary loading program, the DSP detects the level of the GPIO pin. If the GPIO pin is high, the DSP is in the initial reset state, loads the DSP running program, and automatically executes the DSP running program. If the GPIO pin is low, the DSP is in the mid-process crash reset state and directly executes the DSP running program.

[0078] When executing the DSP program, the DSP detects the level of the GPIO pin. If the GPIO pin is high, the DSP is in an initial reset state and initializes global variables. If the GPIO pin is low, the DSP is in a mid-crash reset state and reads the global variables and intermediate data from the FPGA before the mid-crash.

[0079] To implement the above control method, this embodiment requires the design of a DSP program. The DSP program implementation requires three parts: a bootloader assembler, a Main() program, and an interrupt handling function. For example... Figure 7As shown, the first is the Bootloader assembly program: it reads the value of GPIO[5] and determines whether the DSP is in an initial reset state or a mid-process crash reset state. If it is an initial reset, the DSP running program needs to be moved; if it is a mid-process crash reset, the DSP running program does not need to be moved and it directly jumps to the main() function entry point. The second is the Main() program: it reads the value of GPIO[5] and determines whether the DSP is in an initial reset state or a mid-process crash reset state. If it is an initial reset, the global variables need to be initialized; if it is a mid-process crash reset, the global variables do not need to be initialized and are instead read from the FPGA. In addition, the DSP also needs to send a handshake signal to the FPGA to indicate that it has successfully completed the initial reset. Finally, there is the interrupt handling function, such as Figure 8 As shown, the DSP sends a "feed the dog" signal to the FPGA and saves the current global variables.

[0080] This embodiment utilizes an FPGA to implement the "watchdog" mechanism for a DSP. This method offers high flexibility, controllable timing and status, and on-site maintainability. Extensive testing has verified that this method effectively solves the problems of DSPs failing to start upon power-on and crashing mid-process, improving DSP reliability and demonstrating significant application and promotion value.

[0081] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0082] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A control method for implementing a DSP reset procedure based on FPGA, which works based on a system for implementing a DSP reset procedure based on FPGA, the system comprising: FPGA and DSP; the first IO pin of the FPGA is connected with the reset pin of the DSP through a DSP reset line; the second IO pin of the FPGA is connected with the GPIO pin of the DSP through a DSP state flag line; the FPGA is used to control the reset process of the DSP through the DSP reset line and to represent the reset state of the DSP through the DSP state flag line; the reset state includes an initial reset state and an in-process crash reset state; characterized in that the control method includes an initial reset control process and an in-process crash reset control process; the initial reset control process includes: the FPGA sets the reset pin of the DSP to low through the DSP reset line; the FPGA detects whether the DSP is reset successfully within a first preset time; if not, it returns to the step of "the FPGA sets the reset pin of the DSP to low through the DSP reset line" until the DSP is reset successfully; and when the DSP is reset successfully, the FPGA sets the GPIO pin of the DSP to low through the DSP state flag line; the in-process crash reset control process includes: the FPGA receives a first signal sent by the DSP every second preset time during normal operation; if the first signal is not received, the FPGA considers that the DSP crashes in the process, sets the reset pin of the DSP to low through the DSP reset line, and sends the global variables and intermediate data before the DSP crashes to the DSP, so that the DSP can restore the working state before the crash after being reset successfully.

2. The control method according to claim 1, characterized by, the FPGA detecting whether the DSP is reset successfully within a first preset time specifically includes: the FPGA judges whether a second signal sent by the DSP after being reset successfully is received within a first preset time; if the second signal is received, the DSP is reset successfully; otherwise, the DSP is not reset successfully.

3. The control method according to claim 1, characterized by, in the initial reset control process, when the FPGA sets the reset pin of the DSP to low through the DSP reset line for the first time, it maintains for a third preset time, and after the third preset time, it sets the reset pin of the DSP to high through the DSP reset line; when the FPGA sets the reset pin of the DSP to low through the DSP reset line for the nth time, it maintains for a fourth preset time, and after the fourth preset time, it sets the reset pin of the DSP to high through the DSP reset line; n = 2, 3,..., N; N is the number of cycles required for the DSP to be reset successfully.

4. The control method according to claim 1, characterized by, after the DSP crashes in the process, the FPGA receives data and commands sent by an external device to the system.

5. A control method for implementing a DSP reset procedure based on FPGA, which works based on a system for implementing a DSP reset procedure based on FPGA, the system comprising: FPGA and DSP; The first IO pin of the FPGA is connected with the reset pin of the DSP through a DSP reset line; the second IO pin of the FPGA is connected with the GPIO pin of the DSP through a DSP state flag line; the FPGA is used to control the reset process of the DSP through the DSP reset line and to represent the reset state of the DSP through the DSP state flag line; the reset state includes an initial reset state and an in-process crash reset state; The control method includes an initial reset control process and an in-process crash reset control process; The initial reset control process includes: The DSP detects whether the reset pin is low; If yes, the DSP starts to reset, and sends a second signal to the FPGA when the reset is successful; if the reset is not successful, returns to the step of "the DSP detects whether the reset pin is low" until the reset is successful; The in-process crash reset control process includes: The DSP detects whether the reset pin is low; If yes, the DSP starts to reset, and reads the global variables and intermediate data before the in-process crash of the DSP from the FPGA to restore the working state before the crash when the reset is successful.

6. The control method according to claim 5, characterized by In the initial reset control process, after the DSP starts to reset, a secondary loading program is automatically loaded and run to obtain a DSP running program and automatically execute the DSP running program.

7. The control method according to claim 5, characterized by, After the initial reset of the DSP is successful, the DSP sends a first signal and the global variables and intermediate data to be saved to the FPGA every second preset time.

8. The control method according to claim 5, characterized by, After the DSP starts to reset, a secondary loading program is automatically loaded and run; when the secondary loading program is run, the DSP detects the level of the GPIO pin; if the GPIO pin is high, the DSP is in the initial reset state, loads a DSP running program, and automatically executes the DSP running program; if the GPIO pin is low, the DSP is in the in-process crash reset state, and directly executes the DSP running program.

9. The control method according to claim 8, characterized by, When the DSP running program is executed, the DSP detects the level of the GPIO pin; if the GPIO pin is high, the DSP is in the initial reset state, and initializes the global variables; if the GPIO pin is low, the DSP is in the in-process crash reset state, and reads the global variables and intermediate data before the in-process crash of the DSP from the FPGA.

Images