System and control method for implementing DSP reset process based on FPGA

By controlling the DSP reset process with FPGA, the problems of DSP failing to start upon power-on and crashing midway are solved, realizing flexible reset control and state recovery, and improving the reliability and maintainability of the system.

CN115599187BActive Publication Date: 2026-01-06贵州航天控制技术有限公司
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Patent Information

Application Number
CN202211217468.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-04
Publication Date
2026-01-06
Estimated Expiration
2042-10-04

AI Technical Summary

Technical Problem

Existing technologies cannot effectively solve the problems of digital signal processors (DSPs) failing to start upon power-up and crashing mid-process, especially due to instability and unreliability in the design of reset signals and startup modes.

Method used

The reset process of the DSP is controlled by a field-programmable gate array (FPGA). The DSP's reset and status flag lines are connected through the FPGA's I/O pins to achieve flexible initial reset and mid-process crash reset control. Combining the timing control capability of the FPGA and the working mechanism of the DSP, the stability of the reset signal and the controllability of the status are ensured.

Benefits of technology

It effectively solves the problems of DSP failing to start upon power-up and crashing midway, improves the reliability and maintainability of DSP, and ensures that the system's time is controllable and its state is recoverable during the reset process.

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Abstract

The application provides a system and a control method for implementing a DSP reset process based on FPGA, and relates to the technical field of DSP reset. A first IO pin of the FPGA is connected with a reset pin of the DSP through a DSP reset line to control the reset process of the DSP. A second IO pin of the FPGA is connected with a GPIO pin of the DSP through a DSP state flag line to represent the reset state of the DSP, so that initial reset control and midway crash reset control are completed. The reset signal of the DSP is controlled by the FPGA, and the application has the characteristics of flexibility, time controllability, state controllability, field maintainability and the like, and effectively solves the two technical problems of power-on non-starting and midway crash of the DSP.
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