Semi-dynamic trigger and method for designing integrated circuit

Abstract

The present disclosure provides a semi-dynamic trigger and a method for designing an integrated circuit. A semi-dynamic trigger includes: a semiconductor substrate, first to fourth power rails, and at least one clock gate line. The first to fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are sequentially arranged in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate and extends in a second direction to pass through at least two regions of a first region between the first and second power rails, a second region between the second and third power rails, and a third region between the third and fourth power rails. The at least one clock gate line receives an input clock signal.

Description

Technical Field

[0001] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a semi-dynamic flip-flop implemented as a multi-height standard cell and a method of designing an integrated circuit including the semi-dynamic flip-flop. Background Art

[0002] Standard cells with corresponding functions can be used in the design of integrated circuits. Standard cells with predetermined architectures are stored in a cell library. When designing an integrated circuit, standard cells are retrieved from the cell library and placed in the desired locations on the integrated circuit layout. Routing is then performed to connect the standard cells to each other and / or to other cells. Standard cells have predetermined (or set) architectures, such as cell width, cell height, cell length, etc. The design efficiency of the integrated circuit can be determined based on the configuration and layout of the standard cells. Summary of the Invention

[0003] Example embodiments provide a semi-dynamic flip-flop having an efficient signal wiring structure and a method of designing the semi-dynamic flip-flop.

[0004] According to an exemplary embodiment, a semi-dynamic flip-flop includes a semiconductor substrate, a first power rail, a second power rail, a third power rail, a fourth power rail, and at least one clock gate line. The first to fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are sequentially arranged in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate and extends in a second direction to pass through at least two regions of a first region between the first and second power rails, a second region between the second and third power rails, and a third region between the third and fourth power rails. The at least one clock gate line receives an input clock signal.

[0005] According to an exemplary embodiment, a semi-dynamic flip-flop includes: a semiconductor substrate; a plurality of power rails disposed on the semiconductor substrate, extending in a first direction and sequentially arranged in a second direction substantially perpendicular to the first direction; and at least one clock gate line disposed on the semiconductor substrate and extending in the second direction to pass through at least two of a plurality of regions between the plurality of power rails. The at least one clock gate line receives an input clock signal.

[0006] According to an exemplary embodiment, a method for designing an integrated circuit includes: receiving input data defining the integrated circuit; providing at least one multi-height standard cell corresponding to a semi-dynamic flip-flop in a standard cell library; performing placement and routing based on the input data and the standard cell library; and generating output data defining the integrated circuit based on the results of the placement and routing. The multi-height standard cell includes: a semiconductor substrate; a plurality of power rails disposed on the semiconductor substrate, extending in a first direction and sequentially arranged in a second direction substantially perpendicular to the first direction; and at least one clock gate line disposed on the semiconductor substrate and extending in the second direction to pass through at least two of a plurality of regions between the plurality of power rails. The at least one clock gate line receives an input clock signal.

[0007] A semi-dynamic flip-flop and a method for designing the same according to an exemplary embodiment can improve operation and reduce power consumption by implementing the semi-dynamic flip-flop as a multi-height standard cell with efficient arrangement of nodes that significantly affect power consumption. In addition, unnecessary metal wiring can be eliminated by arranging the same nodes or related nodes and connecting the nodes using gate lines, thereby improving design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0009] Figure 1 is a diagram illustrating a layout of a semi-dynamic flip-flop according to an exemplary embodiment.

[0010] Figure 2 is a diagram showing a layout of a semi-dynamic flip-flop according to a comparative example.

[0011] Figure 3 is a block diagram illustrating a semi-dynamic flip-flop according to an exemplary embodiment.

[0012] Figure 4A and Figure 4B is a diagram for describing a negative setup time of a semi-dynamic flip-flop according to an exemplary embodiment.

[0013] Figure 5 It shows Figure 3 A circuit diagram of an exemplary embodiment of a first circuit included in a semi-dynamic trigger.

[0014] Figure 6 It shows Figure 3 A circuit diagram of an exemplary embodiment of a second circuit included in a semi-dynamic trigger.

[0015] Figure 7 It shows Figure 3 A circuit diagram of an exemplary embodiment of an output circuit included in a semi-dynamic trigger.

[0016] Figure 8A 、 Figure 8B and Figure 8C is a timing diagram illustrating a negative setup time of a semi-dynamic flip-flop according to an exemplary embodiment.

[0017] Figure 9 is a diagram showing an example layout of a standard cell.

[0018] Figure 10A 、 Figure 10B and Figure 10C It can have Figure 9 A cross-sectional view of a standard cell having the same layout as the standard cell of FIG.

[0019] Figure 11 is a diagram illustrating an example of a clock transistor and a feedback transistor included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0020] Figure 12A and Figure 12B Is shown in the layout Figure 11 FIG. 1 is a diagram of an exemplary embodiment of a layout of clock transistors and feedback transistors in FIG.

[0021] Figure 13A and Figure 13B Is shown in the layout Figure 11 FIG. 1 is a diagram of an exemplary embodiment of a layout of clock transistors and feedback transistors in FIG.

[0022] Figure 14 is a diagram illustrating an example of a feedback transistor included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0023] Figure 15 Is shown in the layout Figure 14 FIG. 1 is a diagram of an exemplary embodiment of a layout of a feedback transistor in FIG.

[0024] Figure 16 is a diagram illustrating an example of an inverting clock transistor included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0025] Figure 17 Is shown in the layout Figure 16 FIG. 1 is a diagram of an exemplary embodiment of a layout of an inverting clock transistor in FIG.

[0026] Figure 18 is a diagram illustrating an example of an output buffer included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0027] Figure 19 Is shown in the layout Figure 18 FIG. 1 is a diagram of an exemplary embodiment of a layout of transistors included in an output buffer of FIG.

[0028] Figure 20 is a diagram illustrating an example of a scan input transistor included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0029] Figure 21 Is shown in the layout Figure 20 FIG. 1 is a diagram of an exemplary embodiment of a layout of scan input transistors in FIG.

[0030] Figure 22 is a diagram illustrating an example of a scan enable transistor included in a semi-dynamic flip-flop according to an exemplary embodiment.

[0031] Figure 23 Is shown in the layout Figure 22 FIG. 1 is a diagram of an exemplary embodiment of a layout of a scan enable transistor in FIG.

[0032] Figure 24A and Figure 24B is a diagram illustrating a scan test circuit including a semi-dynamic flip-flop according to an exemplary embodiment.

[0033] Figure 25 is a diagram illustrating a method of designing an integrated circuit according to an exemplary embodiment.

[0034] Figure 26 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

[0035] Figure 27 is a block diagram illustrating a mobile device according to an exemplary embodiment. DETAILED DESCRIPTION

[0036] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which like reference numerals may refer to like elements throughout.

[0037] Hereinafter, the structure of an integrated circuit according to an exemplary embodiment is described using a first direction X, a second direction Y, and a third direction Z in a three-dimensional space. The first direction X may be a row direction, the second direction Y may be a column direction, and the third direction Z may be a vertical direction. The first direction X, the second direction Y, and the third direction Z may intersect, for example, may be substantially orthogonal to each other or substantially perpendicular to each other.

[0038] It will be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in one exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0039] It will also be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0040] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] For ease of description, spatially relative terms such as "under," "beneath," "lower," "beneath," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings were turned over, elements described as being "under" or "beneath" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can encompass both above and below orientations.

[0042] It will be understood that when a component, such as a film, region, layer, or element, is referred to as being "on," "connected to," "coupled to," or "adjacent" another component, it can be directly on, directly connected to, coupled to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as "overlying" another component, it can be the only component overlying the other component, or one or more intervening components may also overly the other component. Other words used to describe relationships between elements should be interpreted in a similar manner.

[0043] Furthermore, when two directions are described as being substantially parallel or perpendicular to each other, it will be understood that the two directions are exactly parallel or perpendicular to each other, or approximately parallel or perpendicular to each other within measurement error as would be understood by one of ordinary skill in the art.

[0044] Figure 1 is a diagram illustrating a layout of a semi-dynamic flip-flop according to an exemplary embodiment.

[0045] Reference Figure 1 , the semi-dynamic flip-flop SDFF may include a plurality of power rails PR1-PRn (n is a positive integer) and at least one clock gate line CGL.

[0046] The plurality of power rails PR1 -PRn are formed over the semiconductor substrate, extend in a first direction X, and are sequentially arranged in a second direction Y substantially perpendicular to the first direction X.

[0047] Here, when an element such as, for example, the plurality of power rails PR1 -PRn is described as extending in a specific direction such as, for example, the first direction X, the element may extend longitudinally in the specific direction.

[0048] The clock gate line CGL is formed over the semiconductor substrate and extends in the second direction Y to pass through at least two regions among the plurality of regions RG1 -RGn- 1 between the plurality of power rails PR1 -PRn. The clock gate line CGL receives an input clock signal. Figure 1 An example is shown in which one clock gate line CGL passes through a first region RG1 between a first power rail PR1 and a second power rail PR2, and a second region RG2 between the second power rail PR2 and a third power rail PR3. However, exemplary embodiments are not limited thereto. For example, according to exemplary embodiments, the clock gate line CGL may extend to pass through three or more of the plurality of regions RG1-RGn-1. In exemplary embodiments, the semi-dynamic flip-flop SDFF may include two or more clock gate lines CGL adjacent to each other in the first direction X.

[0049] As a result, the semi-dynamic flip-flop SDFF can be formed in the plurality of regions RG1-RGn-1 between the plurality of power rails PR1-PRn. Each of the plurality of regions RG1-RGn-1 represents a region between two adjacent power rails among the plurality of power rails PR1-PRn. The semi-dynamic flip-flop SDFF can be implemented as a standard cell having a cell height CHP and a cell width CWP. The standard cell corresponding to the semi-dynamic flip-flop SDFF according to the exemplary embodiment has a cell height CH that is a normal standard cell (see Figure 9 ) and can be called a multi-height standard cell.

[0050] Figure 2 is a diagram showing a layout of a semi-dynamic flip-flop according to a comparative example.

[0051] Reference Figure 2The semi-dynamic flip-flop SDFFC in the comparative example is formed in a region between two adjacent power rails PR1 and PR2. The semi-dynamic flip-flop SDFFC can be implemented as a standard cell having a cell height CHC and a cell width CWC.

[0052] When the semi-dynamic flip-flop SDFFC is formed in the one region, due to design limitations, multiple clock gate lines CGL1, CGL2, and CGL3 are distributed in the one region. In such a layout, complex metal wiring may be required and the load of the metal wiring may increase.

[0053] As semiconductor manufacturing processes scale, the area of ​​standard cells also decreases. However, the size of metal wiring cannot be reduced at the same rate as the area of ​​standard cells, which can lead to increased power consumption in the back-end of line (BEOL). Given this, exemplary embodiments are provided herein that reduce the loading (i.e., capacitance) of metal wiring.

[0054] A semi-dynamic flip-flop differs from a master-slave flip-flop in that it has an asymmetric structure and includes many complex nodes. Due to insufficient space for metal wiring, a semi-dynamic flip-flop can essentially use the upper metal rail. Furthermore, reducing the cell height to reduce the area of ​​the standard cell may increase the load on the master node, potentially leading to increased power consumption and reduced operating speed.

[0055] A semi-dynamic flip-flop and a method for designing a semi-dynamic flip-flop according to an exemplary embodiment can improve operation and reduce power consumption by implementing the semi-dynamic flip-flop as a multi-height standard cell with efficient arrangement of nodes that significantly affect power consumption. In addition, unnecessary metal wiring can be eliminated by arranging the same nodes or related nodes and connecting the nodes using gate lines, thereby improving design efficiency.

[0056] Figure 3 is a block diagram illustrating a semi-dynamic flip-flop according to an exemplary embodiment.

[0057] Reference Figure 3 The semi-dynamic trigger 1000 includes a first circuit 1100 , a second circuit 1300 and an output circuit 1500 .

[0058] The first circuit 1100 can generate a first feedback signal FB based on the input data signal D, the input clock signal CK, the scan enable signal SE, the scan input signal SI, and the second feedback signal ZZ1N. The second circuit 1300 can generate a second feedback signal ZZ1N and a latch input signal ZZ2 based on the input data signal D, the input clock signal CK, the scan enable signal SE, and the first feedback signal FB. The output circuit 1500 can generate an output signal QN corresponding to the input data signal D or the scan input signal SI based on the input clock signal CK and the latch input signal ZZ2. The output circuit 1500 may include a latch circuit 1510 and an output buffer 1520. Although Figure 3 The output buffer 1520 is shown as an inverter as an example, but exemplary embodiments are not limited thereto.

[0059] The first circuit 1100 and the second circuit 1300 may control each other through the first feedback signal FB and the second feedback signal ZZ1N in a manner similar to a set-reset (SR) latch.

[0060] In the semi-dynamic flip-flop 1000 according to an exemplary embodiment, the latch input signal ZZ2 may transition even if the input data signal D transitions before the negative setup time elapses from the time point when the input clock signal CK transitions from the first logic level to the second logic level.

[0061] Hereinafter, exemplary embodiments will be described primarily based on a case where a semi-dynamic flip-flop samples an input data signal D at a rising edge of an input clock signal CK. In this case, the first logic level may be a logic low level, and the second logic level may be a logic high level. However, the present invention is not limited thereto. For example, exemplary embodiments may also be applied to a case where a semi-dynamic flip-flop samples an input data signal D at a falling edge of an input clock signal CK. In this case, the first logic level may be a logic high level, and the second logic level may be a logic low level. The exemplary embodiment of rising-edge sampling can be modified to an exemplary embodiment of falling-edge sampling by, for example, signal inversion, switching transistor types between N-type and P-type transistors, or the like.

[0062] Figure 4A and Figure 4B is a diagram for describing a negative setup time of a semi-dynamic flip-flop according to an exemplary embodiment.

[0063] Figure 4A The setup time tSUc, clock-to-output delay time tCQc, and input-to-output delay time tDQc of a general semi-dynamic flip-flop are shown. Figure 4B1 shows the setup time tSUp, clock-to-output delay time tCQp, and input-to-output delay time tDQp of a semi-dynamic flip-flop according to an exemplary embodiment. Figure 4A and Figure 4B In FIG, Tc represents the switching time point of the input clock signal, Tdc and Tdp represent the switching time points of the input signal, and Tqc and Tqp represent the switching time points of the output signal.

[0064] The speed of a flip-flop is generally determined by the input-to-output delay time tDQc. The input-to-output delay time tDQc is defined by the sum of the setup time tSUc and the clock-to-output delay time tCQc. The setup time tSUc is the time required to stably provide data (i.e., the data of the input signal) to the flip-flop. For example, the setup time tSUc represents the time interval during which the input signal transition must be completed before the sampling edge of the clock signal. The clock-to-output delay time tCQc represents the delay time from the sampling of the clock signal to the release of the output data. Reducing the input-to-output delay time tDQc allows the design of high-speed flip-flops.

[0065] like Figure 4A and Figure 4B As shown, the semi-dynamic flip-flop according to an exemplary embodiment has a negative setup time tSUp. The negative setup time indicates that the semi-dynamic flip-flop can still reflect the transition of the input signal even after the transition of the sampling clock signal. The semi-dynamic flip-flop according to an exemplary embodiment can have a reduced input-to-output delay time tDQp due to the increased negative setup time tSUp. Therefore, the operating speed of the semi-dynamic flip-flop and the integrated circuit including the semi-dynamic flip-flop can be increased.

[0066] Figure 5 It shows Figure 3 1 is a circuit diagram of an exemplary embodiment of a first circuit 1100 included in a semi-dynamic trigger.

[0067] Reference Figure 3 and Figure 5, the first circuit 1100 may include a pulse generating circuit 1110 and a scan input circuit 1120. The first circuit 1100 may include: clock transistors PC11 and NC11 receiving an input clock signal CK; inverted clock transistors PC12, PC13, and NC12 receiving an inverted clock signal CKN; a data input transistor PD11 receiving an input data signal D; scan input transistors PS12, PS13, PS14, PS15, NS11, NS12, and NS13 receiving a scan input signal SI, an inverted scan input signal SIN, or a delayed scan input signal SEN; scan enable transistors PS11, PS15, and NS14 receiving a scan enable signal SE; and feedback transistors PZ11, PZ12, PZ13, and NZ11 receiving a first feedback signal FB or a second feedback signal ZZ1N. The transistors may be as follows Figure 5 As shown, it is arranged between the power supply voltage VDD, the ground voltage VSS, the node N11 to which the inverted clock signal CKN is applied, the node N12 to which the intermediate data signal DN is applied, the node N13 to which the first feedback signal FB is applied, the node N14 to which the inverted scan input signal SIN is applied, and the node N15 to which the delayed scan input signal SEN is applied.

[0068] Figure 6 It shows Figure 3 1 is a circuit diagram of an exemplary embodiment of a second circuit 1300 included in a semi-dynamic trigger.

[0069] Reference Figure 3 and Figure 6 , the second circuit 1300 may include a first stage circuit 1310 and a second stage circuit 1320. The second circuit 1300 may include: feedback transistors PZ21, PZ22, PZ23, NZ21, NZ22, and NZ23 receiving a first feedback signal FB or a second feedback signal ZZ1N; clock transistors PC21, NC21, and NC22 receiving an input clock signal CK; a data input transistor ND21 receiving an input data signal D; and a scan enable transistor NS21 receiving a scan enable signal SE. The transistors may be as follows. Figure 6 It is shown disposed between the power supply voltage VDD, the ground voltage VSS, a node N21 to which the intermediate feedback signal ZZ1 is applied, a node N22 to which the latch input signal ZZ2 is applied, a node N23 to which the second feedback signal ZZ1N is applied, and a node N24.

[0070] Figure 7 It shows Figure 3 1 is a circuit diagram of an exemplary embodiment of an output circuit 1500 included in a semi-dynamic trigger.

[0071] Reference Figure 3 and Figure 7 , the output circuit 1500 may include a latch circuit 1510 and an output buffer 1520. The latch circuit 1510 may be as follows Figure 7 The output buffer 1520 includes feedback transistors PZ31, PZ32, NZ31, and NZ32, and a clock transistor PC31, which are arranged between the power supply voltage VDD, the ground voltage VSS, and nodes N31 and N32 to latch the latch input signal ZZ2. The output buffer 1520 may include a plurality of inverters connected in parallel between the node N31 to which the latch input signal ZZ2 is applied and the output node N33 from which the output signal QN is output.

[0072] Figure 8A 、 Figure 8B and Figure 8C is a timing diagram illustrating a negative setup time of a semi-dynamic flip-flop according to an exemplary embodiment.

[0073] Reference Figure 8A , as referenced Figure 5 、 Figure 6 and Figure 7 The described semi-dynamic flip-flop can reflect the transition of the input data signal D between the rising edge of the input clock signal CK and the falling edge of the first feedback signal FB. For example, the negative setup time tSU corresponds to the time interval between the rising edge of the input clock signal CK and the falling edge of the first feedback signal FB.

[0074] Figure 8B 1 shows a negative setup time tSU1 when the input data signal D is converted from a first logic level (logic low level L) to a second logic level (logic high level H), Figure 8C 1 shows the negative setup time tSU2 when the input data signal D changes from a logic high level H to a logic low level L. Tc represents the transition time point of the input clock signal CK, Td1 represents the transition time point of the first feedback signal FB, and Td2 represents the transition time point of the second feedback signal ZZ1N.

[0075] When the input data signal D changes from a logic low level L to a logic high level H, Figure 8B In the case of the negative setup time, the negative setup time corresponds to the first delay time tSU1 from the transition time point Tc of the input clock signal CK to the transition time point Td1 of the first feedback signal FB. On the contrary, when the input data signal D transitions from the logic high level H to the logic low level L, as shown in FIG. Figure 8C In the case of FIG, the negative setup time corresponds to a second delay time tSU2 from a transition time point Tc of the input clock signal CK to a transition time point Td2 of the second feedback signal ZZ1N.

[0076] Reference Figure 8BIn the first case CS1, the input data signal D transitions upward (from a logic low level L to a logic high level H) after the transition time point Td1 of the first feedback signal FB, and in the second case CS2, the input data signal D transitions upward (from a logic low level L to a logic high level H) before or at the transition time point Td1 of the first feedback signal FB. Figure 8C In the third case CS3, the input data signal D transitions downward (from a logic high level H to a logic low level L) after the transition time point Td2 of the second feedback signal ZZ1N, and in the fourth case CS4, the input data signal D transitions downward (from a logic high level H to a logic low level L) before the transition time point Td2 of the second feedback signal ZZ1N or at the transition time point Td2.

[0077] Referring to the second case CS2 and the fourth case CS4, if the input data signal D transitions before the negative setup time tSU1 or tSU2 elapses from the time point Tc when the input clock signal CK transitions from a logic low level L to a logic high level H, one of the first feedback signal FB and the second feedback signal ZZ1N may transition.

[0078] In contrast, referring to the first and third cases CS1 and CS3 , if the input data signal D transitions after the negative setup time tSU1 or tSU2 elapses from the time point Tc (ie, the sampling time point), both the first and second feedback signals FB and ZZ1N do not transition.

[0079] As a result, the semi-dynamic flip-flop according to the exemplary embodiment may have an increased negative setup time reflecting a transition of an input signal after a transition of an input clock signal, and thus, an operating speed of the semi-dynamic flip-flop and an integrated circuit including the same may be increased.

[0080] To help understand the layout of integrated circuits, here is a reference Figure 9 、 Figure 10A 、 Figure 10B and Figure 10C Describe the structure of a standard cell.

[0081] Figure 9 is a diagram showing an example layout of a standard cell. Figure 10A 、 Figure 10B and Figure 10C It can have Figure 9 A cross-sectional view of a standard cell having the same layout as the standard cell of FIG.

[0082] Figure 10A 、 Figure 10B and Figure 10C A portion of a standard cell SCL including a fin field effect transistor (FinFET) is shown. Figure 10AAccording to an exemplary embodiment Figure 9 A cross-sectional view of the standard cell SCL taken along line AA′. Figure 10B According to an exemplary embodiment Figure 9 A cross-sectional view of the standard cell SCL taken along line BB'. Figure 10C According to an exemplary embodiment Figure 9 A cross-sectional view of a standard cell SCL taken along line CC'.

[0083] Reference Figure 9 、 Figure 10A 、 Figure 10B and Figure 10C , a standard cell SCL may be formed on a substrate 110 having an upper surface 110A extending in a horizontal direction (e.g., a first direction X and a second direction Y). The standard cell SCL may include a first device region RX1, a second device region RX2, and an active cutting region ACR separating the first device region RX1 and the second device region RX2 along the second direction Y. Each of the first device region RX1 and the second device region RX2 may include a plurality of fin-type active regions AC protruding from the substrate 110 along a third direction Z, such as Figure 10C As shown. In an exemplary embodiment, the fin structure may be omitted in the case of a bulk metal oxide semiconductor (MOS) process. The active regions AC may extend substantially parallel to each other in a first direction X. A device isolation layer 112 may be formed on the substrate 110 along a second direction Y between the active regions AC. The active regions AC protrude from the device isolation layer 112 along a third direction Z in the form of fins.

[0084] A plurality of gate insulating layers 118 and a plurality of gate lines PC 11-16 may be formed on the substrate 110. The gate lines PC 11-16 may extend in a direction Y intersecting the active area AC. The gate insulating layer 118 and the gate lines PC 11-16 may cover the upper surface and sidewalls of each active area AC and the upper surface of the device isolation layer 112. A plurality of MOS transistors may be formed along the gate lines PC 11-16. The MOS transistors may have a three-dimensional structure in which a channel is formed in the upper surface and both sidewalls of the active area AC.

[0085] The gate insulating layer 118 may be formed of, for example, a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The gate insulating layer 118 may be formed, for example, by using atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0086] Gate lines PC 11-16 may extend on gate insulation layer 118 across active area AC, while covering the upper surface and both sidewalls of each active area AC. A gate mask 122 may be formed on each gate line PC. Gate insulation layer 118, gate lines PC 11-16, and the sidewalls of gate mask 122 may be covered by spacers 124. In an exemplary embodiment, gate mask 122 may be omitted and removed from at least one of gate lines PC 11-16 at a portion where a conductive contact for an upper structure is formed.

[0087] The gate lines PC 11 - 16 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are sequentially stacked.

[0088] A plurality of conductive contacts CA and CB may be formed in the first layer LY1 on the active region AC. The conductive contacts CA and CB may include a plurality of first contacts CA 21-25 and 31-35 (eg, Figure 10B ) and a plurality of second contacts CB 41-43 connected to the gate lines PC 11-16 (as shown Figure 10A and Figure 10C shown).

[0089] The conductive contacts CA and CB may be insulated from each other by a first interlayer insulating layer 132 covering the active region AC and the gate lines PC 11-16. The conductive contacts CA and CB may have upper surfaces substantially at the same level as an upper surface of the first interlayer insulating layer 132. The first interlayer insulating layer 132 may be, for example, a silicon oxide layer.

[0090] A second interlayer insulating layer 134 and a plurality of lower via contacts V0 51-62 passing through the second interlayer insulating layer 134 are formed on the first interlayer insulating layer 132. The second interlayer insulating layer 134 may be, for example, a silicon oxide layer.

[0091] A plurality of wirings M1 71-78 extending in the first direction X or the second direction Y in the second layer LY2, which is higher than the first layer LY1 (e.g., farther from the substrate 110 along the third direction Z), may be formed on the second interlayer insulating layer 134. Each of the wirings M1 71-78 may be connected to one of the conductive contacts CA and CB via one of the lower via contacts V0 51-62 formed between the first layer LY1 and the second layer LY2. Each of the lower via contacts V0 51-62 may be connected to one of the conductive contacts CA and CB, for example, by passing through the second interlayer insulating layer 134. The lower via contacts V0 51-62 may be insulated from each other by the second interlayer insulating layer 134. The wirings M1 71-78 may include internal connection wirings that electrically connect multiple regions in the standard cell SCL. For example, the internal connection wiring 78 may electrically connect the active region AC in the first device region RX1 and the active region AC in the second device region RX2 through the lower via contacts 55 and 58 and the first contacts CA24 and 33 .

[0092] Wirings M1 71 and 72 may correspond to a first power rail PR1 and a second power rail PR2, respectively. The first power rail 71 may be connected to the active region AC in the first device region RX1. The second power rail 72 may be connected to the active region AC in the second device region RX2. One of the first power rail 71 and the second power rail 72 may be a wiring for supplying a power supply voltage (e.g., a first power supply voltage VDD), and the other of the first power rail 71 and the second power rail 72 may be a wiring for supplying a ground voltage (e.g., a second power supply voltage VSS). The first power rail 71 and the second power rail 72 may extend substantially parallel to each other in the first direction X in the second layer LY2. In an exemplary embodiment, the power rails 71 and 72 may be formed substantially simultaneously with the other wirings M1 73-78. The wirings M1 71-78 may pass through a third interlayer insulating layer 136. The third interlayer insulating layer 136 may insulate the wirings M1 71-78 from each other.

[0093] A cell height CH of the standard cell SCL may be defined by a distance between the first power rail 71 and the second power rail 72 along the second direction Y. A cell width CW of the standard cell SCL may be defined along a first direction X substantially parallel to the first power rail 71 and the second power rail 72 .

[0094] The integrated circuit according to the exemplary embodiment may correspond to a combination of various standard cells. Hereinafter, the same reference sign or reference numeral may be used to represent a signal and a node of the signal. For example, "CK" may be used to represent a clock signal or a node to which the clock signal is applied.

[0095] Figure 11is a diagram illustrating an example of a clock transistor and a feedback transistor included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 12A and Figure 12B Is shown in the layout Figure 11 FIG. 1 is a diagram of an exemplary embodiment of a layout of clock transistors and feedback transistors in FIG. Figure 12B According to an exemplary embodiment Figure 12A Cross-sectional view along line DD'.

[0096] Figure 11 Show Figure 5 、 Figure 6 and Figure 7 part of the transistor. Figure 12A Shown by Figure 11 An exemplary embodiment of the layout of the clock transistors PC11, PC21, PC31, NC11, NC21, NC22 and the feedback transistors PZ21, NZ21 is indicated by the dotted circles in FIG.

[0097] The first region RG1 may include a first device region RX11, a second device region RX12, and a first active cutting region ACR1. The second region RG2 may include a third device region RX21, a fourth device region RX22, and a second active cutting region ACR2. The third region RG3 may include a fifth device region RX31, a sixth device region RX32, and a third active cutting region ACR3. The region corresponding to the second power rail 272 between the first region RG1 and the second region RG2 and the region corresponding to the third power rail 273 between the second region RG2 and the third region RG3 may be referred to as a boundary region.

[0098] Reference Figure 11 、 Figure 12A and Figure 12B A multi-height standard cell corresponding to a semi-dynamic flip-flop may be formed using a semiconductor substrate 110 and include a first power rail 271 , a second power rail 272 , a third power rail 273 , a fourth power rail 274 and a plurality of gate lines 211 - 223 .

[0099] exist Figure 12A , nodes with the same reference number can be electrically connected to each other through the upper wiring. The conductive contacts CA and CB and the wiring in the first metal layer M1 can be connected through the lower via contact V0, and the wiring in the first metal layer M1 and the wiring in the second metal layer can be connected through the upper via contact. The first metal layer M1 can be the lowest metal layer, or at least one metal layer can be provided below the first metal layer M1. Figure 12A As shown, power rails 271 , 272 , 273 , and 274 and metal wiring 281 may be formed in the first metal layer M1 . However, exemplary embodiments are not limited thereto.

[0100] At least one of the gate lines 211-223 may be cut or separated by the gate cutting region GLC, so that the at least one gate line may include multiple gate segments. For example, gate line 215 includes three gate segments 215a, 215b, and 215c, gate line 216 includes two gate segments 216a and 216b, and gate line 217 includes two gate segments 217a and 217b.

[0101] The gate segment 216a corresponds to the first clock gate line, the gate segment 215b corresponds to the second clock gate line, and the gate segment 217b corresponds to the feedback gate line.

[0102] The first clock gate line 216a extends in the second direction Y to pass through the first region RG1 and the second region RG2 and receives the input clock signal CK. The second clock gate line 215b extends in the second direction Y to pass through the second region RG2 and receives the input clock signal CK. The second clock gate line 215b is adjacent to the first clock gate line 216a in the first direction X. The first clock gate line 216a is not cut by the gate cutting region GLC in the first region RG1, the second region RG2, and the boundary region between the first region RG1 and the second region RG2.

[0103] The first clock gate line 216a forms the gate electrode of the clock transistor PC31 included in the output circuit 1500 and formed in the first region RG1, the gate electrode of the clock transistor NC22 included in the second circuit 1300 and formed in the first region RG1, and the gate electrodes of the clock transistors NC21 and PC21 included in the second circuit 1300 and formed in the second region RG2. The second clock gate line 215b forms the gate electrodes of the clock transistors NC11 and PC11 included in the first circuit 1100 and formed in the second region RG2.

[0104] Reference Figure 12A and Figure 12B , the first clock gate line 216a and the second clock gate line 215b may be electrically connected to each other through a gate connection path 311. The gate connection path 311 may be formed in the second region RG2 below the lowermost metal layer M1 and extend in the first direction X to electrically connect the first clock gate line 216a and the second clock gate line 215b. The gate connection path 311 may be formed of the same material as the conductive contact CB.

[0105] The feedback gate line 217b extends in the second direction Y to pass through the second region RG2 and the third region RG3. The feedback gate line 217b is adjacent to the first clock gate line 216a in the first direction X, such that the first clock gate line 216a is disposed between the second clock gate line 215b and the feedback gate line 217b. The feedback gate line 217b receives the first feedback signal FB applied via the metal wiring 281. The feedback gate line 217b forms the gate electrodes of the feedback transistors PZ21 and NZ21 included in the second circuit 1300 and formed in the third region RG3.

[0106] Figure 13A and Figure 13B Is shown in the layout Figure 11 FIG. 1 is a diagram of an exemplary embodiment of a layout of clock transistors and feedback transistors in FIG. Figure 13B yes Figure 13A For ease of explanation, the previous reference is omitted. Figure 11 and Figure 12A Further description of the described elements and aspects.

[0107] Reference Figure 11 、 Figure 13A and Figure 13B The gate line 212 includes two gate segments 212a and 212b, the gate line 213 includes two gate segments 213a and 213b, the gate line 214 includes two gate segments 214a and 214b, and the gate line 215 includes two gate segments 215a and 215b.

[0108] The gate segment 212a corresponds to the first clock gate line, the gate segment 213b corresponds to the second clock gate line, and the gate segment 215b corresponds to the feedback gate line.

[0109] The first clock gate line 212a extends in the second direction Y to pass through the first and second regions RG1 and RG2 and receives the input clock signal CK. The second clock gate line 213b extends in the second direction Y to pass through the second and third regions RG2 and RG3 and receives the input clock signal CK. The second clock gate line 213b is adjacent to the first clock gate line 212a in the first direction X.

[0110] The first clock gate line 212a forms the gate electrode of the clock transistor PC31 included in the output circuit 1500 and formed in the first region RG1, the gate electrode of the clock transistor NC22 included in the second circuit 1300 and formed in the first region RG1, and the gate electrodes of the clock transistors NC21 and PC21 included in the second circuit 1300 and formed in the second region RG2. The second clock gate line 213b forms the gate electrodes of the clock transistors NC11 and PC11 included in the first circuit 1100 and formed in the third region RG3.

[0111] Reference Figure 13A and Figure 13B The first clock gate line 212a and the second clock gate line 213b may be electrically connected to each other through a gate connection wiring 282. The gate connection wiring 282 may be formed in the lowermost metal layer M1 in the second region RG2 and extend in the first direction X.

[0112] In the following, refer to Figures 14 to 23 , the other nodes of the standard cell corresponding to the semi-dynamic trigger will be described. Figure 11 and Figure 12A Further description of described elements and aspects may be omitted.

[0113] Figure 14 is a diagram illustrating an example of a feedback transistor included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 15 Is shown in the layout Figure 14 FIG. 1 is a diagram of an exemplary embodiment of a layout of a feedback transistor in FIG.

[0114] Figure 14 Show Figure 5 and Figure 6 part of the transistor. Figure 15 Shown by Figure 14 An exemplary embodiment of the layout of the feedback transistors PZ11 , PZ13 , NZ11 and NZ23 is indicated by the dashed circles in FIG.

[0115] Reference Figure 14 and Figure 15 , the gate line 222 includes two gate segments 222a and 222b. The gate segment 222b corresponds to the feedback gate line.

[0116] The feedback gate line 222b extends in the second direction Y to pass through the second region RG2 and the third region RG3. The feedback gate line 222b receives the second feedback signal ZZ1N applied through the metal wiring 284. The feedback gate line 222b forms the gate electrodes of the feedback transistors PZ11, PZ13, and NZ11 included in the first circuit 1100, and the gate electrode of the feedback transistor NZ23 included in the second circuit 1300, wherein the feedback transistors PZ13 and NZ23 are formed in the second region RG2, and the feedback transistors PZ11 and NZ11 are formed in the third region RG3.

[0117] Figure 16 is a diagram illustrating an example of an inverting clock transistor included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 17 Is shown in the layout Figure 16 FIG. 1 is a diagram of an exemplary embodiment of a layout of an inverting clock transistor in FIG.

[0118] Figure 16 Show Figure 5 part of the transistor. Figure 17 Shown by Figure 16 An exemplary embodiment of the layout of the inverting clock transistors PC12, PC13 and NC12 indicated by the dotted circles in FIG.

[0119] Reference Figure 16 and Figure 17 , the gate line 218 includes two gate segments 218a and 218b. The gate segment 218b corresponds to the inverted clock gate line.

[0120] The inverted clock gate line 218b extends in the second direction Y to pass through the second region RG2 and the third region RG3. The inverted clock gate line 218b receives the inverted clock signal CKN applied through the metal wiring 285. The inverted clock gate line 218b forms gate electrodes of the inverted clock transistors PC12, PC13, and NC12 included in the first circuit 1100, wherein the inverted clock transistor PC13 is formed in the second region RG2, and the inverted clock transistors PC12 and NC12 are formed in the third region RG3.

[0121] Figure 18 is a diagram illustrating an example of an output buffer included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 19 Is shown in the layout Figure 18 FIG. 1 is a diagram of an exemplary embodiment of a layout of transistors included in an output buffer of FIG.

[0122] Figure 18 Inverter transistors P01 - P04 and N01 - N04 included in output buffer 1520 are shown. Figure 19 Shown by Figure 18 An exemplary embodiment of a layout of inverter transistors P01 - P04 and N01 - N04 is indicated by dashed circles in FIG.

[0123] Reference Figure 18 and Figure 19 , the output buffer 1520 may include a plurality of inverters connected in parallel between a node generating a latch input signal ZZ2 of the latch circuit 1510 and an output node generating an output signal QN. Depending on the required drive strength, the output buffer 1520 may include various numbers of inverters. Although Figure 18 and Figure 19 Four inverters connected in parallel are shown as an example, but exemplary embodiments are not limited thereto.

[0124] The gate line 212 includes two gate segments 212a and 212b, and the gate line 213 includes two gate segments 213a and 213b. The gate segment 212a corresponds to the first inverter gate line, and the gate segment 213a corresponds to the second inverter gate line.

[0125] The first inverter gate line 212a extends in the second direction Y through the first and second regions RG1 and RG2 and receives a latch input signal ZZ2. The second inverter gate line 213a is adjacent to the first inverter gate line 212a in the first direction X. The second inverter gate line 213a extends in the second direction Y through the first and second regions RG1 and RG2 and receives a latch input signal ZZ2. The first and second inverter gate lines 212a and 213a form gate electrodes for the inverter transistors P01-P04 and N01-N04 included in the plurality of inverters.

[0126] The first inverter gate line 212a and the second inverter gate line 213a can be electrically connected through the first gate connection path 312 and the second gate connection path 313. Figure 12B The gate connection path 311 and the first gate connection path 312 can be formed in the first region RG1 under the lowest metal layer M1 and extend in the first direction X, and the second gate connection path 313 can be formed in the second region RG2 under the lowest metal layer M1 and extend in the first direction X.

[0127] Drain regions of p-channel metal oxide semiconductor (PMOS) transistors P01-P04 and drain regions of n-channel metal oxide semiconductor (NMOS) transistors N01-N04 may be electrically connected through drain connection wirings 286 and 287. Drain connection wirings 286 and 287 may be electrically connected to each other through an upper metal wiring.

[0128] Figure 20is a diagram illustrating an example of a scan input transistor included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 21 Is shown in the layout Figure 20 FIG. 1 is a diagram of an exemplary embodiment of a layout of scan input transistors in FIG.

[0129] Figure 20 Show Figure 5 part of the transistor. Figure 21 Shown by Figure 20 An exemplary embodiment of a layout of scan input transistors PS13, PS14, NS12, and NS13 indicated by dashed circles in FIG.

[0130] Reference Figure 20 and Figure 21 The gate line 212 includes three gate segments 212a, 212b, and 212c, and the gate line 213 includes two gate segments 213a and 213b. The gate segment 212b corresponds to the scan input gate line, and the gate segment 213b corresponds to the inverse scan input gate line.

[0131] The scan input gate line 212b extends in the second direction Y to pass through the second region RG2 and receives the scan input signal SI. The scan input gate line 212b forms the gate electrodes of the scan input transistors NS12 and PS13 in the second region RG2, which invert the scan input signal SI to generate an inverted scan input signal SIN.

[0132] The inverted scan input gate line 213b is adjacent to the scan input gate line 212b in the first direction X. The inverted scan input gate line 213b extends in the second direction Y to pass through the second region RG2 and the third region RG3. The inverted scan input gate line 213b forms gate electrodes of scan input transistors PS14 and NS13 in the third region RG3, which invert the inverted scan input signal SIN to generate a delayed scan input signal SEN.

[0133] The inversion scan input gate line 213b and the drain regions of the scan input transistors NS12 and PS13 in the second region RG2 may be electrically connected to each other through the wiring 291. The drain regions of the scan input transistors PS14 and NS13 in the third region RG3 may be electrically connected to each other through the wiring 292.

[0134] Figure 22 is a diagram illustrating an example of a scan enable transistor included in a semi-dynamic flip-flop according to an exemplary embodiment. Figure 23 Is shown in the layout Figure 22 FIG. 1 is a diagram of an exemplary embodiment of a layout of a scan enable transistor in FIG.

[0135] Figure 22 Show Figure 5 and Figure 6 part of the transistor. Figure 23 Shown by Figure 22 An exemplary embodiment of a layout of scan enable transistors PS11, PS15, NS14, and NS21 is indicated by dashed circles in FIG.

[0136] Reference Figure 22 and Figure 23 , the gate line 220 includes two gate segments 220a and 220b. The gate segment 220b corresponds to the scan enable gate line.

[0137] The scan enable gate line 220b extends in the second direction Y to pass through the second region RG2 and the third region RG3, and receives a scan enable signal SE applied through the metal wiring 293. The scan enable gate line 220b forms gate electrodes of scan enable transistors PS11, PS15, and NS14 included in the first circuit 1100, and a gate electrode of a scan enable transistor NS21 included in the second circuit 1300, wherein the scan enable transistors PS11 and NS21 are formed in the second region RG2, and the scan enable transistors PS15 and NS14 are formed in the third region RG3.

[0138] As described above, the semi-dynamic flip-flop and the method for designing the same according to the exemplary embodiment can improve operation and reduce power consumption by implementing the semi-dynamic flip-flop as a multi-height standard cell with efficient arrangement of nodes that significantly affect power consumption. In addition, unnecessary metal wiring can be eliminated by arranging the same nodes or related nodes and connecting the nodes using gate lines, thereby improving design efficiency.

[0139] Figure 24A and Figure 24B is a diagram illustrating a scan test circuit including a semi-dynamic flip-flop according to an exemplary embodiment.

[0140] Design for Testability (DFT) schemes for testing semiconductor chips are widely used. Among DFT schemes, a scan test scheme can be used to efficiently test semiconductor integrated circuits. Flip-flops with scan inputs are designed for convenient testing of logic circuits. According to the scan test scheme, the flip-flops in the logic circuit can form a shift register in a scan test mode, and the scan input can be applied to the shift register to observe the resulting output.

[0141] Figure 24A A scan test circuit using a scan input signal SI is shown. Figure 24B A scan test circuit using an inverted scan input signal SIN is shown.

[0142] Reference Figure 24A , the scan test circuit 800 may include a combinational circuit system 802, a sequential circuit system 804, and inverters 801, 803, 805, and 807. The combinational circuit system 802 may include a plurality of logic circuits 810, 820, and 830. The sequential circuit system 804 may include a plurality of flip-flops, including a first flip-flop 840 and a second flip-flop 850.

[0143] The first logic circuit 810 performs a logical operation on the data DATA IN and provides input data D to the first flip-flop 840. The first flip-flop 840 operates synchronously with the input clock signal CK. The logic level of the scan enable signal SE can indicate a normal mode or a scan test mode. The first flip-flop 840 provides output data Q corresponding to the input data D in the normal mode and provides output data Q corresponding to the scan input signal SI in the scan test mode. The second logic circuit 820 performs a logical operation on the output data Q of the first flip-flop 840 and provides input data D to the second flip-flop 850.

[0144] The second flip-flop 850 receives the output data Q of the first flip-flop 840 as a scan input SI, and receives a scan enable signal SE and an input clock signal CK. The third logic circuit 830 performs a logic operation on the output data Q of the second flip-flop 850 and provides output data DATA OUT. The output data Q of the second flip-flop 850 can be provided as a scan output SO through inverters 805 and 807 in a scan test mode.

[0145] Reference Figure 24B Scan test circuit 900 may include combinational circuitry 802, sequential circuitry 904, and inverters 901 and 903. Combinatorial circuitry 802 may include a plurality of logic circuits 810, 820, and 830. Sequential circuitry 904 may include a plurality of flip-flops, including a first flip-flop 910 and a second flip-flop 920. Figure 24B The scan test circuit 900 is similar to Figure 24A The scan test circuit 800, in addition to Figure 24B The first flip-flop 910 and the second flip-flop 920 in the scan test circuit 900 receive the inverted scan input signal SIN and output the inverted output data QN. Figure 24A Further description of the described elements and aspects.

[0146] Figure 24A and Figure 24B The scan trigger included in the scan test circuit in the embodiment can provide output data corresponding to the scan input data SI in the scan test mode. Figure 24Aand Figure 24B The scan test circuit can perform a logic operation on input data DATA IN in a normal mode to provide output data DATA OUT, and form a scan test path to provide a scan output signal SO corresponding to a scan input signal SI to test the operation of the scan test circuit.

[0147] Figure 25 is a diagram illustrating a method of designing an integrated circuit according to an exemplary embodiment.

[0148] Figure 25 The method may include a method of designing a layout of an integrated circuit performed by a design tool. In an exemplary embodiment, the design tool may include programming software (which includes a plurality of instructions executable by a processor), such as software implemented in some form of hardware (e.g., a processor, ASIC, etc.).

[0149] Reference Figure 25 , input data defining an integrated circuit may be received (S100). For example, the integrated circuit may be defined by a plurality of cells, and the integrated circuit may be designed using a cell library including information about the cells. Hereinafter, the cells may be standard cells, and the cell library may be a standard cell library.

[0150] In an exemplary embodiment, the input data may be data generated from an abstract form regarding the behavior of the integrated circuit. For example, the input data may be defined at the register transfer level (RTL) by synthesis using a standard cell library. For example, the input data may be a bitstream and / or netlist generated by synthesizing an integrated circuit defined in a hardware description language (HDL) such as, for example, VHSIC Hardware Description Language (VHDL) or Verilog.

[0151] In an exemplary embodiment, the input data may be data for defining the layout of an integrated circuit. For example, the input data may include geometric information for defining structures implemented as semiconductor materials, metals, and insulators. The layout of the integrated circuit indicated by the input data may include, for example, a layout of cells and conductive lines for connecting cells to other cells.

[0152] At least one multi-height standard cell is provided in a standard cell library (S200). The term "standard cell" may refer to a cell of an integrated circuit in which the size of the layout satisfies a preset or specified rule. A standard cell may include an input pin and an output pin, and may process a signal received through the input pin to output a signal through the output pin. For example, a standard cell may be a basic cell (such as an AND logic gate, an OR logic gate, an NOR logic gate, or an inverter), a complex cell (such as OR / AND / NOT (OAI) or AND / OR / NOT (AOI)), or a storage element (such as a master-slave flip-flop or a latch).

[0153] According to the reference Figures 1 to 23 The described exemplary embodiments, the multi-height standard cell may correspond to a semi-dynamic flip-flop including an efficient wiring structure using gate lines and a transistor arrangement based on the wiring structure.

[0154] A standard cell library may include information about a plurality of standard cells. For example, the standard cell library may include the name and function of the standard cell as well as timing information, power information, and layout information about the standard cell. The standard cell library may be stored in a memory device, and the standard cell library may be provided by accessing the memory device.

[0155] Placement and routing are performed based on input data and a standard cell library (S300), and output data defining an integrated circuit is provided based on a result of the placement and routing (S400).

[0156] In an exemplary embodiment, when the received input data is data such as a bitstream or a netlist generated by synthesizing an integrated circuit, the output data may be a bitstream or a netlist. In an exemplary embodiment, when the received input data is data defining a layout of an integrated circuit (e.g., data in a Graphic Data System II (GDSII) format), the output data may also be in a format that defines the layout of the integrated circuit.

[0157] Figure 26 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

[0158] Figure 26 The integrated circuit 3000 may be, for example, an application specific integrated circuit (ASIC). The layout of the integrated circuit 3000 may be determined by performing the above-described placement and routing of the standard cells SC1-SC12. Power may be provided to the standard cells SC1-SC12 via power rails 511-516. The power rails 511-516 may include high power rails 511, 513, and 515 that provide a first power supply voltage VDD and low power rails 512, 514, and 516 that provide a second power supply voltage VSS that is lower than the first power supply voltage VDD. For example, the first power supply voltage VDD may be a power supply voltage having a positive voltage level, and the second power supply voltage VSS may be a ground voltage having a ground level (e.g., 0V) or a negative voltage level.

[0159] The high power rails 511, 513 and 515 and the low power rails 512, 514 and 516 extend in the first direction X and are alternately arranged one after another in the second direction Y to form boundaries of a plurality of circuit rows CR1-CR5 corresponding to areas defined by the power rails 511-516 arranged in the second direction Y.

[0160] According to an exemplary embodiment, power can be distributed to the power rails 511-516 via power mesh routes 521-524 extending in the second direction Y. Some power mesh routes 522 and 524 can provide a first power supply voltage VDD, and other power mesh routes 521 and 523 can provide a second power supply voltage VSS. The power mesh routes 521-524 can be connected to the power rails 511-516 via vertical contacts VC (such as, for example, via contacts).

[0161] Generally, each of the circuit rows CR1-CR5 can be connected to two adjacent power rails at its boundary to be powered. For example, the standard cells SC1-SC4 in the first circuit row CR1 can be connected to adjacent and corresponding power rail pairs including a high power rail 511 and a low power rail 512.

[0162] For example, Figure 26 As shown, standard cell SC6 may be a dual-height standard cell formed in two circuit rows CR2 and CR3, and standard cell SC7 may be a triple-height standard cell formed in three circuit rows CR2, CR3, and CR4. As a result, through efficient routing of single-height standard cells SC1-SC5 and SC8-SC12 and multi-height standard cells SC6 and SC7, the area occupied by integrated circuit 3000 may be reduced, and the performance of integrated circuit 3000 may be improved.

[0163] Figure 27 is a block diagram illustrating a mobile device according to an exemplary embodiment.

[0164] Reference Figure 27 , the mobile device 4000 may include at least one application processor 4100 , a communication module 4200 , a display / touch module 4300 , a memory device 4400 , and a buffer RAM 4500 .

[0165] The application processor 4100 can control the operation of the mobile device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through the touch panel. The memory device 4400 is implemented to store user data. The memory device 4400 can be, for example, an embedded multimedia card (eMMC), a solid-state drive (SSD), a universal flash memory (UFS) device, etc. The memory device 4400 can perform high-speed caching of the mapping data and the user data as described above.

[0166] The buffer RAM 4500 may temporarily store data for processing operations of the mobile device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a rambus dynamic random access memory (RDRAM), etc.

[0167] At least one component in the mobile device 4000 may include at least one multi-height standard cell according to the exemplary embodiments described herein. As described above, the design of the multi-height standard cell may be included in a standard cell library, and the integrated circuit included in the mobile device 4000 may be designed by automatic placement and routing using a design tool.

[0168] As is conventional in the field of the present invention, exemplary embodiments are described in terms of functional blocks, units and / or modules and are shown in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0169] As will be appreciated by those skilled in the art, aspects of the present invention may be embodied as systems, methods, or computer program products. Thus, aspects of the present invention may take the form of a complete hardware implementation, a complete software implementation (including firmware, resident software, microcode, etc.), or a combination of software and hardware implementations, all of which may be generally referred to herein as "circuits," "modules," or "systems." Additionally, aspects of the present invention may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0170] The exemplary embodiments may be applied to any electronic device and system. For example, the exemplary embodiments may be applied to the following systems: such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0171] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

[0172] This application claims priority from Korean Patent Application No. 10-2019-0096365 filed on August 7, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semi-dynamic trigger, comprising: semiconductor substrates; a first power rail, a second power rail, a third power rail, and a fourth power rail, provided on the semiconductor substrate, extending in a first direction, and arranged sequentially in a second direction perpendicular to the first direction; as well as at least one clock gate line is provided on the semiconductor substrate and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail, wherein the at least one clock gate line receives an input clock signal, The semi-dynamic trigger comprises: a first circuit configured to generate a first feedback signal based on an input data signal, the input clock signal, and a second feedback signal; a second circuit configured to generate the second feedback signal and a latch input signal based on the input data signal, the input clock signal, and the first feedback signal; and The output circuit is configured to generate an output signal corresponding to the input data signal based on the input clock signal and the latch input signal.

2. The semi-dynamic flip-flop of claim 1, wherein the semi-dynamic flip-flop has a negative setup time to reflect a transition of an input signal after a transition of the input clock signal.

3. The semi-dynamic flip-flop according to claim 1 , wherein the at least one clock gate line comprises: a first clock gate line extending in the second direction to pass through the first region and the second region; and a second clock gate line extending in the second direction to pass through the second region, The second clock gate line is adjacent to the first clock gate line in the first direction.

4. The semi-dynamic flip-flop according to claim 3 , wherein the first clock gate line forms a gate electrode of a clock transistor included in the output circuit and formed in the first region, a gate electrode of a clock transistor included in the second circuit and formed in the first region, and a gate electrode of a clock transistor included in the second circuit and formed in the second region, The second clock gate line forms a gate electrode of a clock transistor included in the first circuit and formed in the second region. 5 . The semi-dynamic flip-flop of claim 3 , wherein the first clock gate line is not cut by a gate cutting region in the first region, the second region, and a boundary region between the first region and the second region.

6. The semi-dynamic trigger according to claim 3, further comprising: A gate connection via is formed in the second region below the lowermost metal layer and extends in the first direction to electrically connect the first clock gate line and the second clock gate line.

7. The semi-dynamic trigger according to claim 3, further comprising: a feedback gate line extending in the second direction to pass through the second region and the third region, wherein the feedback gate line is adjacent to the first clock gate line in the first direction, such that the first clock gate line is disposed between the second clock gate line and the feedback gate line, The feedback gate line receives the first feedback signal.

8. The semi-dynamic flip-flop according to claim 1 , wherein the at least one clock gate line comprises: a first clock gate line extending in the second direction to pass through the first region and the second region; and a second clock gate line extending in the second direction to pass through the second region and the third region, The second clock gate line is adjacent to the first clock gate line in the first direction.

9. The semi-dynamic trigger according to claim 8, further comprising: A gate connection wiring is formed in the lowermost metal layer in the second region and extends in the first direction to electrically connect the first clock gate line and the second clock gate line.

10. The semi-dynamic trigger according to claim 1, further comprising: a feedback gate line extending in the second direction to pass through the second region and the third region, The feedback gate line receives the second feedback signal.

11. The semi-dynamic trigger according to claim 1 , further comprising: an inverted clock gate line extending in the second direction to pass through the second region and the third region, The inverted clock gate line receives an inverted clock signal inverted from the input clock signal.

12. The semi-dynamic flip-flop according to claim 1, wherein the output circuit comprises: a latch circuit configured to latch the latch input signal; and A plurality of inverters are connected in parallel between a node to which the latch input signal of the latch circuit is applied and an output node from which the output signal is output.

13. The semi-dynamic trigger according to claim 12, further comprising: a first inverter gate line extending in the second direction to pass through the first region and the second region, wherein the first inverter gate line receives the latch input signal; and a second inverter gate line adjacent to the first inverter gate line in the first direction and extending in the second direction to pass through the first region and the second region, wherein the second inverter gate line receives the latch input signal, The first inverter gate line and the second inverter gate line form gate electrodes of inverter transistors included in the plurality of inverters.

14. The semi-dynamic trigger according to claim 13, further comprising: a first gate connection path formed in the first region below the lowermost metal layer and extending in the first direction to electrically connect the first inverter gate line and the second inverter gate line; a second gate connection path formed in the second region below the lowermost metal layer and extending in the first direction to electrically connect the first inverter gate line and the second inverter gate line; as well as A plurality of drain connection wirings electrically connects a drain region of a PMOS transistor among the inverter transistors and a drain region of an NMOS transistor among the inverter transistors.

15. A semi-dynamic trigger, comprising: semiconductor substrates; a first power rail, a second power rail, a third power rail, and a fourth power rail, provided on the semiconductor substrate, extending in a first direction, and arranged sequentially in a second direction perpendicular to the first direction; as well as at least one clock gate line is provided on the semiconductor substrate and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail, wherein the at least one clock gate line receives an input clock signal, The semi-dynamic trigger comprises: a first circuit configured to generate a first feedback signal based on an input data signal, the input clock signal, a scan enable signal, a scan input signal, and a second feedback signal; a second circuit configured to generate the second feedback signal and a latch input signal based on the input data signal, the input clock signal, the scan enable signal, and the first feedback signal; and The output circuit is configured to generate an output signal corresponding to the input data signal or the scan input signal based on the input clock signal and the latch input signal.

16. The semi-dynamic trigger according to claim 15, further comprising: a scan input gate line extending in the second direction to pass through the second area, wherein the scan input gate line forms a gate electrode of a scan input transistor in the second region, the scan input transistor in the second region inverts the scan input signal to generate an inverted scan input signal, and the scan input gate line receives the scan input signal; an inverted scan input gate line adjacent to the scan input gate line in the first direction and extending in the second direction to pass through the second area and the third area, wherein the inverted scan input gate line forms a gate electrode of a scan input transistor in the third region, the scan input transistor in the third region inverts the inverted scan input signal to generate a delayed scan input signal; as well as A wiring electrically connects the inverted scan input gate line and the drain region of the scan input transistor in the second region.

17. The semi-dynamic trigger according to claim 15, further comprising: a scan enable gate line extending in the second direction to pass through the second area and the third area, The scan enable gate line receives the scan enable signal.

18. A semi-dynamic trigger, comprising: semiconductor substrates; a first power rail, a second power rail, a third power rail, and a fourth power rail, provided on the semiconductor substrate, extending in a first direction, and arranged sequentially in a second direction perpendicular to the first direction; as well as A first clock gate line and a second clock gate line are provided on the semiconductor substrate. wherein each of the first clock gate line and the second clock gate line receives an input clock signal, the first clock gate line extends in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and the second clock gate line extends in the second direction to pass through the second region and a third region between the third power rail and the fourth power rail, and The second clock signal line is adjacent to the first clock signal line in the first direction.

19. A method for designing an integrated circuit, the method comprising: receiving input data defining the integrated circuit; providing at least one multi-height standard cell corresponding to a semi-dynamic flip-flop in a standard cell library; performing placement and routing based on the input data and the standard cell library; as well as generating output data defining the integrated circuit based on the results of the placing and the routing, The multi-height standard unit comprises: semiconductor substrates; a plurality of power rails provided on the semiconductor substrate, extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction; and at least one clock gate line disposed on the semiconductor substrate and extending in the second direction to pass through at least two regions among a plurality of regions between the plurality of power rails, wherein the at least one clock gate line receives an input clock signal, The semi-dynamic trigger comprises: a first circuit configured to generate a first feedback signal based on an input data signal, the input clock signal, and a second feedback signal; a second circuit configured to generate the second feedback signal and a latch input signal based on the input data signal, the input clock signal, and the first feedback signal; and an output circuit configured to generate an output signal corresponding to the input data signal based on the input clock signal and the latch input signal, or The semi-dynamic trigger comprises: a first circuit configured to generate a first feedback signal based on an input data signal, the input clock signal, a scan enable signal, a scan input signal, and a second feedback signal; a second circuit configured to generate the second feedback signal and a latch input signal based on the input data signal, the input clock signal, the scan enable signal, and the first feedback signal; and The output circuit is configured to generate an output signal corresponding to the input data signal or the scan input signal based on the input clock signal and the latch input signal.

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