Semiconductor device, method for forming the same, and integrated chip

Abstract

Various embodiments of the present invention relate to a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed above the semiconductor substrate. A first source / drain region and a second source / drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed above the gate dielectric. A first anti-dimpling structure is embedded in the gate electrode, wherein the perimeter of the first anti-dimpling structure is disposed within the perimeter of the gate electrode. A method for forming a semiconductor device and an integrated chip including the semiconductor device are also provided.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor device, a method for forming the same, and an integrated chip. Background Art

[0002] A semiconductor device is an electronic component that uses the electronic properties of semiconductor materials to affect electrons or their associated fields. A widely used type of semiconductor device is the field-effect transistor (FET). A FET includes a pair of source / drain regions, a selectively conductive channel, and a gate electrode. A FET is a multifunctional device that can be used for switches, amplifiers, and memories, among other things. Examples of FETs include metal-oxide-semiconductor field-effect transistors (MOSFETs). Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a gate dielectric, a first source / drain region, a second source / drain region, a gate electrode, and a first anti-sag structure. The gate dielectric is disposed above the semiconductor substrate. The first source / drain region and the second source / drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. The gate electrode is disposed above the gate dielectric. The first anti-sag structure is embedded in the gate electrode, wherein the perimeter of the first anti-sag structure is disposed within the perimeter of the gate electrode.

[0004] An embodiment of the present invention provides an integrated chip (IC) including a semiconductor substrate, a first gate dielectric, a first gate electrode, a second gate dielectric, a second gate electrode, and a dielectric structure. The first gate dielectric is disposed above the semiconductor substrate. The first gate electrode is disposed above the first gate dielectric, wherein the first gate electrode has a first length. The second gate dielectric is disposed above the semiconductor substrate and is spaced apart from the first gate dielectric. The second gate electrode is disposed above the semiconductor substrate and is spaced apart from the first gate electrode, wherein the second gate electrode has a second length greater than the first length. The dielectric structure is embedded in the second gate electrode, wherein the outer sidewall of the dielectric structure is disposed within the outer sidewall of the second gate electrode.

[0005] An embodiment of the present invention provides a method for forming a semiconductor device, the steps of which are as follows: forming a first opening above a gate dielectric, wherein the gate dielectric is disposed on a semiconductor substrate; depositing a conductive layer above the gate dielectric and in the first opening; forming a second opening in the conductive layer and the second opening is spaced apart from the gate dielectric, wherein a perimeter of the second opening is disposed within a perimeter of the gate dielectric; depositing an anti-sag layer on the conductive layer and in the second opening; and forming a gate electrode and an anti-sag structure embedded in the gate electrode by performing a chemical mechanical polishing (CMP) process on the anti-sag layer and the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1C Various views of some embodiments of semiconductor devices having a plurality of anti-recessing structures embedded in a gate electrode are shown.

[0008] FIG. 2A to FIG. 2C Show Figures 1A to 1C Various views of some other embodiments of semiconductor devices.

[0009] FIG. 3A to FIG. 3C Show Figures 1A to 1C Various views of some other embodiments of semiconductor devices.

[0010] FIG. 4A to FIG. 4B Show Figures 1A to 1C Various views of some other embodiments of semiconductor devices.

[0011] Figure 5 Shown is no ILD structure Figure 1B Top views of some other embodiments of semiconductor devices.

[0012] Figure 6 Show Figure 5 Top views of some other embodiments of semiconductor devices.

[0013] Figure 7 Show Figure 5 Top views of some other embodiments of semiconductor devices.

[0014] Figure 8 Show Figure 5 Top views of some other embodiments of semiconductor devices.

[0015] Fig. 9 Show FIG. 4A to FIG. 4B Cross-sectional views of some more detailed embodiments of semiconductor devices.

[0016] Fig.10 Shown including Fig. 9 Cross-sectional views of some embodiments of an integrated chip (IC) of some embodiments of a semiconductor device and a second semiconductor device.

[0017] Figures 11 to 18 Shown for forming Fig.10 A series of cross-sectional diagrams of some embodiments of methods of ICs.

[0018] Fig.19 A flow chart illustrating some embodiments of a method for forming an IC having a first semiconductor device and a second semiconductor device, wherein the first semiconductor device includes a plurality of anti-recessing structures embedded in a first gate electrode. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] Some metal oxide semiconductor field effect transistors (MOSFETs) include a metal gate electrode disposed above a gate dielectric (e.g., a high-k dielectric). In some embodiments, a method of forming a MOSFET with a metal gate electrode includes forming an opening in an interlayer dielectric (ILD) structure. The opening corresponds to the metal gate electrode. Subsequently, a conductive material (e.g., a metal) is deposited above the ILD structure and in the opening. A chemical-mechanical polishing (CMP) process is then performed on the conductive material and the ILD structure to form a gate electrode.

[0022] One problem with the above method is that the CMP process causes recessing of the conductive material deposited in the opening. For example, due to the process parameters of the CMP process (e.g., chemical slurry composition, pressure, speed, time, etc.) and the different chemical compositions of the ILD structure and the conductive material, the CMP process may remove the conductive material at a faster rate than the ILD structure is removed, thereby recessing the conductive material deposited in the opening. This recess may be exacerbated as the size of the opening increases (e.g., high voltage devices with large gates). Therefore, the recess will adversely affect the performance of the MOSFET because excessive removal of the conductive material will unduly reduce the size (e.g., height) of the metal gate electrode. In addition, in some severe cases, the recess may cause the MOSFET to operate improperly due to complete (or nearly complete) removal of the conductive material in the opening.

[0023] Various embodiments of the present application are directed to a method for forming a semiconductor device. The method includes forming a first opening above a gate dielectric. Depositing a conductive material above the gate dielectric and in the first opening. Forming a second opening in the conductive material and the second opening is spaced apart from the gate dielectric, wherein the perimeter of the second opening is disposed within the perimeter of the gate dielectric. Depositing an anti-depression material on the conductive material and in the second opening. Performing a planarization process (e.g., chemical mechanical polishing (CMP)) on the anti-depression material and the conductive material to form an anti-depression structure embedded in the gate electrode. Because the anti-depression material is deposited in the second opening, the anti-depression material provides structural support during the formation of the semiconductor device to reduce the amount of depression of the conductive material. Therefore, the performance of the semiconductor device can be improved and / or the cost of manufacturing the semiconductor device can be reduced.

[0024] Figures 1A to 1C Various views of some embodiments of a semiconductor device 100 having a plurality of anti-recession structures 112 embedded in a gate electrode 108 are shown. Figure 1A Shows the line A-A' Figure 1B FIG. 1 is a cross-sectional view of a semiconductor device 100 . Figure 1BA top view of the semiconductor device 100 is shown without an inter-layer dielectric (ILD) structure 110 . Figure 1C Shows the line B-B' Figure 1B FIG. 1 is a cross-sectional view of a semiconductor device 100 .

[0025] like Figures 1A to 1C As shown in , the semiconductor device 100 is disposed on / in a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.). The semiconductor device 100 includes a pair of source / drain regions 104a and 104b, such as a first source / drain region 104a and a second source / drain region 104b. The source / drain region 104a and the source / drain region 104b are regions of the semiconductor substrate 102 having a first doping type (e.g., n-type or p-type).

[0026] The gate dielectric 106 is disposed over the semiconductor substrate 102 and between the source / drain region 104a and the source / drain region 104b. In some embodiments, the gate dielectric 106 may include, for example, an oxide (e.g., silicon dioxide (SiO2)), a high dielectric constant dielectric material (e.g., hafnium oxide (HfO2), zirconium oxide (ZrO2), or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing. The gate electrode 108 is disposed over the gate dielectric 106 and between the source / drain region 104a and the source / drain region 104b. In some embodiments, the gate electrode 108 may include, for example, doped polysilicon (e.g., n-type / p-type polysilicon), a metal (e.g., tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), etc.), or the like. An interlayer dielectric (ILD) structure 110 is disposed over the semiconductor substrate 102 and surrounds the gate electrode 108 and the gate dielectric 106. In some embodiments, the ILD structure 110 includes one or more stacked ILD layers, which may respectively include a low-k dielectric (eg, a dielectric material having a dielectric constant less than about 3.9), an oxide (eg, SiO 2 ), and the like.

[0027] A plurality of anti-recessing structures 112 are embedded in the gate electrode 108. For a given CMP process, the plurality of anti-recessing structures 112 have a different chemical mechanical polishing (CMP) removal rate than the gate electrode 108. For example, by performing a given CMP process with predefined process parameters on the anti-recessing structures 112 and the gate electrode 108, the CMP process may remove a portion of the anti-recessing structures 112 at a first CMP removal rate and remove a portion of the gate electrode 108 at a second CMP removal rate greater than the first CMP removal rate. Because the anti-recessing structures 112 are embedded in the gate electrode 108 and because the second CMP removal rate is greater than the first CMP removal rate, the anti-recessing structures 112 may reduce an amount of recessing of the gate electrode 108 caused by the given CMP process. Therefore, the performance of the semiconductor device 100 may be improved and / or the cost of manufacturing the semiconductor device 100 may be reduced.

[0028] For the sake of clarity, some features of the first anti-recession structure 112a among the plurality of anti-recession structures 112 will be described, and it should be understood that each of the anti-recession structures 112 may also have such structural features. For example, the first anti-recession structure 112a may have a sidewall extending vertically along a substantially straight line. Therefore, it should be understood that each anti-recession structure 112 may have a sidewall extending vertically along a substantially straight line.

[0029] In some embodiments, the bottom surface of the first anti-recession structure 112a may be circular and may be connected to a first pair of opposing side walls of the first anti-recession structure 112a. The first pair of opposing side walls are spaced apart in a first direction (e.g., a direction extending along line A-A'). In other embodiments, the first anti-recession structure 112a has a second pair of opposing side walls spaced apart in a second direction perpendicular to the first direction (e.g., a direction extending along line B-B'). The circular bottom surface may extend laterally in the second direction along a substantially straight line.

[0030] FIG. 2A to FIG. 2C Show Figures 1A to 1C Various views of some other embodiments of the semiconductor device 100 are shown. Figure 2A Shows the line A-A' Figure 2B FIG. 1 is a cross-sectional view of a semiconductor device 100 . Figure 2B The ILD structure 110 is shown without Figure 1B Top views of some other embodiments of the semiconductor device 100 are shown. Figure 2C Shows the line B-B' Figure 2B FIG. 1 is a cross-sectional view of a semiconductor device 100 .

[0031] like FIG. 2A to FIG. 2CAs shown in , the bottom surface of the first anti-recession structure 112a is disposed between the upper surface of the gate electrode 108 and the bottom surface of the gate electrode 108. The outer perimeter of the first anti-recession structure 112a is disposed within the outer perimeter of the gate electrode 108. In some embodiments, the bottom surface of the first anti-recession structure 112a is substantially planar. In some embodiments, the first pair of opposing sidewalls may extend vertically along a substantially straight line and may be connected to the substantially planar bottom surface of the first anti-recession structure 112a at an angle (e.g., 90 degrees). In other embodiments, the first pair of opposing sidewalls may extend vertically along a substantially straight line and may be connected to the substantially planar bottom surface of the first anti-recession structure 112a by a rounded corner.

[0032] The gate electrode 108 has a first length L1, a first width W1, and a first height H1. The first anti-recession structure 112a has a second length L2, a second width W2, and a second height H2. The first anti-recession structure 112a may be spaced apart from the second anti-recession structure 112b by a distance D. In some embodiments, the ratio between the first height H1 and the second height H2 may be between about 2:1 and about 5:1. In other embodiments, the second length L2 may be less than or equal to about 33% of the first length L1. In other embodiments, the second width W2 may be between about 99.9% and about 0.1% of the first width W1.

[0033] In some embodiments, the first length L1 may be greater than or equal to about 1.5 micrometers (μm). In other embodiments, the first width W1 may be greater than or equal to about 1 micrometer. In other embodiments, the second length L2 may be between about 0.15 micrometers and about 0.5 micrometers. In still other embodiments, the second width W2 may be greater than or equal to about 0.13 micrometers.

[0034] In some embodiments, the distance D may be greater than or equal to about 0.13 microns. In other embodiments, each anti-recession structure 112 may be spaced the same distance from the nearest adjacent anti-recession structure. In other embodiments, some anti-recession structures 112 may be spaced a different distance from the nearest adjacent anti-recession structure than some other anti-recession structures 112. In still other embodiments, the distance D and the second width W2 may be substantially the same. In other embodiments, the distance D and the second width W2 may be different.

[0035] The first area is defined by the first length L1 multiplied by the first width W1. The first anti-recession structure 112a has a second area (e.g., the second length L2 multiplied by the second width W2). In some embodiments, the sum of the areas of each of the anti-recession structures 112 is between about 5% and about 25% of the first area. In other embodiments, the area of ​​the gate electrode 108 is between about 75% and about 95% of the first area.

[0036] In some embodiments, the anti-recessing structure 112 includes a material having a CMP removal rate that is lower than a CMP removal rate of a material of the gate electrode 108. In other embodiments, the anti-recessing structure 112 may include, for example, an oxide (e.g., SiO2), a nitride (e.g., silicon nitride (SiN)), an oxynitride (e.g., silicon oxynitride (SiO X N Y )), some other material capable of filling the trench gap and having a CMP removal rate different from (eg, less than) that of the gate electrode 108, or a combination thereof. In embodiments where the anti-recessing structure 112 includes a dielectric, the anti-recessing structure 112 may be referred to as a dielectric structure.

[0037] FIG. 3A to FIG. 3C Show Figures 1A to 1C Various views of some other embodiments of the semiconductor device 100 are shown. Figure 3A Shown is a view taken along line A-A' Figure 3B FIG. 1 is a cross-sectional view of a semiconductor device 100 . Figure 3B The ILD structure 110 is shown without Figure 1B Top views of some other embodiments of the semiconductor device 100 are shown. Figure 3C Shows the area taken along line B-B' Figure 3B FIG. 1 is a cross-sectional view of a semiconductor device 100 .

[0038] like FIG. 3A to FIG. 3C As shown in , the first pair of opposing side walls may be beveled. For example, the first pair of opposing side walls may extend vertically from the bottom surface of the first anti-recession structure 112a at opposite angles. In some embodiments, the first pair of opposing side walls may be beveled and may be connected to the substantially planar bottom surface of the first anti-recession structure 112a at a certain angle (e.g., an obtuse angle / acute angle). In other embodiments, the first pair of opposing side walls may be beveled and may be connected to the substantially planar bottom surface of the first anti-recession structure 112a via a rounded corner.

[0039] FIG. 3A to FIG. 3C104a and 104b are at least partially disposed above the semiconductor substrate 102. In such embodiments, the source / drain region 104a and the source / drain region 104b may be epitaxial source / drain regions including epitaxial materials (e.g., formed by an epitaxial process). In other such embodiments, the source / drain region 104a and the source / drain region 104b and the semiconductor substrate 102 may include the same material (e.g., Si). In other such embodiments, the source / drain region 104a and the source / drain region 104b and the semiconductor substrate may include different materials (e.g., Si and SiGe). In still other such embodiments, the source / drain region 104a and the source / drain region 104b may have a substantially diamond-shaped cross-section. In other embodiments, the source / drain region 104a and the source / drain region 104b may be spaced approximately 10 microns apart. In other embodiments, the source / drain regions 104a and the source / drain regions 104b may be spaced apart by less than or greater than about 10 microns.

[0040] FIG. 4A to FIG. 4B Show Figures 1A to 1C Various views of some other embodiments of the semiconductor device 100 are shown. Figure 4A Shown is a view taken along line A-A' Figure 4B FIG. 1 is a cross-sectional view of a semiconductor device 100 . Figure 4B The ILD structure 110 is shown without Figure 1B Top views of some other embodiments of the semiconductor device 100 are shown.

[0041] like FIG. 4A to FIG. 4B As shown in FIG. 1 , in some embodiments, the ILD structure 110 includes a lower ILD structure 110 a and an upper ILD structure 110 b. The lower ILD structure 110 a is disposed above the semiconductor substrate 102 and around the gate electrode 108 and the gate dielectric 106. In some embodiments, the lower ILD structure 110 a includes one or more ILD layers, which may include a low-k dielectric (e.g., a dielectric material having a dielectric constant of less than about 3.9), an oxide (e.g., SiO 2 ), etc. In other embodiments, the lower ILD structure 110 a has an upper surface coplanar with an upper surface of the gate electrode 108 and / or the anti-recess structure 112.

[0042] The upper ILD structure 110b is disposed over the lower ILD structure 110a, the gate electrode 108, and the anti-recess structure 112. In some embodiments, the upper ILD structure 110b contacts the lower ILD structure 110a, the gate electrode 108, and the anti-recess structure 112. In some embodiments, the upper ILD structure 110b includes one or more ILD layers, which may include a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO2), etc.

[0043] A plurality of conductive gate contacts 402 are electrically coupled to the gate electrode 108 and are disposed in the upper ILD structure 110 b. In some embodiments, each of the conductive gate contacts 402 is spaced apart from each of the anti-recessing structures 112. In other embodiments, one or more conductive gate contacts 402 may overlap and / or contact a portion of one or more anti-recessing structures 112. In other embodiments, the conductive gate contacts 402 extend vertically from the gate electrode 108 and completely pass through the upper ILD structure 110 b. In yet other embodiments, the conductive gate contacts 402 may include, for example, W, Ti, Al, and the like.

[0044] In some embodiments, a plurality of conductive gate contact windows 402 are disposed in a peripheral region (e.g., an end cap region) of the gate electrode 108. The peripheral region of the gate electrode 108 is adjacent to a central region of the gate electrode 108. In other embodiments, each of the anti-recess structures 112 is disposed in a central region of the gate electrode 108, and each of the conductive gate contact windows 402 is disposed in a peripheral region of the gate electrode 108. In other embodiments, the source / drain region 104a and the opposite sides of the source / drain region 104b may be disposed within opposite sides of the central region of the gate electrode 108. In yet other embodiments, the peripheral region may be disposed directly above an underlying isolation structure (e.g., a shallow trench isolation (STI) structure), that is, disposed in the semiconductor substrate 102.

[0045] In some embodiments, the conductive gate contact window 402 may be disposed between adjacent anti-recessing structures 112. For example, the first conductive gate contact window 402a and / or the second conductive gate contact window 402b may be disposed between two adjacent anti-recessing structures 112. In some embodiments, the first conductive gate contact window 402a and the second conductive gate contact window 402b are substantially aligned in the lateral direction (e.g., in a row). In other embodiments, the first conductive gate contact window 402a may be substantially aligned with the other conductive gate contact windows 402 in the lateral direction (e.g., in a row).

[0046] In some embodiments, the first conductive gate contact window 402a and / or the second conductive gate contact window 402b may be disposed closer to the first sidewall of the gate electrode 108 than each of the recess prevention structures 112. In other embodiments, the first sidewall of the gate electrode 108 is opposite to the second sidewall of the gate electrode 108. In still other embodiments, the first sidewall and the second sidewall of the gate electrode 108 are spaced apart in a lateral direction perpendicular to the lateral direction in which the source / drain region 104a and the source / drain region 104b are spaced apart.

[0047] Figure 5 The ILD structure 110 is shown without Figure 1B For ease of description, the top view of some other embodiments of the semiconductor device 100 is shown in FIG. Figure 5 Only some conductive gate contact windows 402 and some anti-recessing structures 112 are marked.

[0048] like Figure 5 As shown in , the anti-recession structure 112 can be embedded in the gate electrode 108 at a certain angle (e.g., 15 degrees, 30 degrees, 60 degrees, etc.). In some embodiments, some of the anti-recession structures 112 arranged in the first row are inclined at the same first angle (e.g., positive 10 degrees). In other embodiments, some other anti-recession structures 112 arranged in the second row are inclined at the same second angle. In other embodiments, the first angle and the second angle are substantially the same. In other embodiments, the first angle and the second angle are different. In yet other embodiments, the first angle and the second angle are opposite to each other (e.g., positive 10 degrees and negative 10 degrees).

[0049] Figure 6 Show Figure 5 Top views of some other embodiments of the semiconductor device 100 are shown.

[0050] like Figure 6 As shown in , some anti-recession structures 112 may have different lengths than some other anti-recession structures 112. For example, the length of the third anti-recession structure 112c is greater than the length of the fourth anti-recession structure 112d. In other embodiments, the third anti-recession structure 112c may have a different width and / or geometry than the fourth anti-recession structure 112d. The area (e.g., length multiplied by width) of the third anti-recession structure 112c may be different from the area of ​​the fourth anti-recession structure 112d.

[0051] In some embodiments, the conductive gate contact windows 402 may be respectively disposed between opposite sidewalls of the anti-recessing structures 112. For example, the third conductive gate contact window 402c may be disposed between opposite sidewalls of the third anti-recessing structure 112c, and the fourth conductive gate contact window 402d may be disposed between opposite sidewalls of the fourth anti-recessing structure 112d. In other embodiments, the width and / or length of one or more conductive gate contact windows 402 may be different from (e.g., greater than) the width and / or length of one or more anti-recessing structures 112.

[0052] Figure 7 Show Figure 5 Top views of some other embodiments of the semiconductor device 100 are shown.

[0053] like Figure 7 As shown in , in some embodiments, only a single anti-recess structure may be embedded in the gate electrode 108. For example, only the fifth anti-recess structure 112e may be embedded in the gate electrode 108. In some embodiments, the fifth anti-recess structure 112e may have a spiral layout. In other embodiments, only a single conductive gate contact window may be electrically coupled to the gate electrode 108. For example, only the fifth conductive gate contact window 402e may be electrically coupled to the gate electrode 108.

[0054] Figure 8 Show Figure 5 Top views of some other embodiments of the semiconductor device 100 are shown.

[0055] like Figure 8 As shown in , the conductive gate contact window 402 may be disposed in the central region of the gate electrode 108. In some embodiments, some of the conductive gate contact windows 402 may be disposed in the central region of the gate electrode 108, while some other conductive gate contact windows 402 may be disposed in the peripheral region of the gate electrode 108. In other embodiments, one or more conductive gate contact windows 402 may be disposed between opposing sidewalls of the source / drain region 104a to the source / drain region 104b.

[0056] In some embodiments, each of the anti-recession structures 112 may have the same area. For example, the area (e.g., length multiplied by width) of the sixth anti-recession structure 112f may be substantially the same as the area of ​​the seventh anti-recession structure 112g. In other embodiments, the sidewalls of the anti-recession structures 112 may be aligned in the lateral direction. For example, the opposite sidewalls of the sixth anti-recession structure 112f may be substantially aligned with the opposite sidewalls of the seventh anti-recession structure 112g in the lateral direction, respectively.

[0057] Fig. 9 Show FIG. 4A to FIG. 4B FIG. 1 is a cross-sectional view of some more detailed embodiments of the semiconductor device 100 .

[0058] like Fig. 9 As shown in FIG. 1 , a first doped region 902 is disposed in the semiconductor substrate 102. The first doped region 902 is a region of the semiconductor substrate 102 having a second doping type opposite to the first doping type (e.g., opposite to the doping type of the source / drain region 104a and the source / drain region 104b). An isolation structure 904 is disposed in the semiconductor substrate 102. In some embodiments, the isolation structure 904 may be a shallow trench isolation (STI) structure, etc.

[0059] In some embodiments, the gate dielectric 106 includes a first dielectric structure 906 and a second dielectric structure 908 disposed on the first dielectric structure 906. The first dielectric structure 906 may include an oxide (e.g., SiO2), and the second dielectric structure may include a high-k dielectric (HfO2, ZrO2, etc.). In other embodiments, the height of the first dielectric structure 906 may be greater than the height of the second dielectric structure 908.

[0060] In some embodiments, the gate electrode 108 may include a first conductive structure 910, a second conductive structure 912, a third conductive structure 914, a fourth conductive structure 916, and a fifth conductive structure 918. The fourth conductive structure 916 may line the bottom surface and sidewalls of the fifth conductive structure 918. The third conductive structure 914 may line the bottom surface and sidewalls of the fourth conductive structure 916. The second conductive structure 912 may be disposed along the bottom surface of the third conductive structure 914. The first conductive structure 910 may be disposed along the bottom surface of the second conductive structure 912. In some embodiments, the first conductive structure 910 contacts the second conductive structure 912 and the gate dielectric 106. In some embodiments, the anti-recess structure 112 may be vertically spaced apart from the first conductive structure 910, the second conductive structure 912, the third conductive structure 914, and / or the fourth conductive structure 916.

[0061] In some embodiments, the first conductive structure 910 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), etc. The second conductive structure 912 may include, for example, TaN, TiN, TiAl, etc. In some embodiments, the second conductive structure 912 has a different chemical composition than the first conductive structure 910 (for example, TaN and TiN, respectively). The third conductive structure 914 may include, for example, TiN, TaN, TiAl, etc. In some embodiments, the third conductive structure 914 has the same chemical composition as the first conductive structure 910 (for example, TiN). The fourth conductive structure 916 may include, for example, TiAl, TaN, TiN, etc. In some embodiments, the fourth conductive structure 916 has a different chemical composition than the first conductive structure 910 and the second conductive structure 912. The fifth conductive structure 918 may include, for example, W, Al, Ti, Mo, some other metal, or a combination of the foregoing. In other embodiments, the fifth conductive structure 918 has a CMP removal rate greater than the anti-recessing structure 112. In yet other embodiments, the CMP removal rate of the fourth conductive structure 916 and / or the third conductive structure 914 may be different from (eg, less than) the CMP removal rate of the fifth conductive structure 918 .

[0062] The sidewall spacer 920 may be disposed above the semiconductor substrate 102 and along the sidewalls of the gate electrode 108 and the sidewalls of the gate dielectric 106. In some embodiments, a portion of the outer sidewall of the sidewall spacer 920 is inclined toward the gate electrode 108. The sidewall spacer 920 may have an upper surface that is substantially coplanar with an upper surface of the lower ILD structure 110a. In other embodiments, the sidewall spacer 920 is spaced apart from the anti-recess structure 112. In yet other embodiments, the sidewall spacer 920 may include, for example, a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y ), some other dielectric material, or a combination of the foregoing.

[0063] A contact etch stop layer (CESL) 922 may be disposed over the semiconductor substrate 102, over the source / drain regions 104a and 104b, and along the outer sidewalls of the sidewall spacers 920. In some embodiments, a portion of the outer sidewalls of the CESL 922 extending along the outer sidewalls of the sidewall spacers 920 may be inclined toward the gate electrode 108. The CESL 922 may contact the sidewall spacers 920, the source / drain regions 104a and 104b, and the isolation structure 904. An upper surface of the CESL 922 may be substantially coplanar with an upper surface of the lower ILD structure 110a. In other embodiments, the CESL 922 may include, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y )etc.

[0064] A plurality of conductive source / drain contacts 924 are electrically coupled to the source / drain regions 104a and the source / drain regions 104b and are disposed in the lower ILD structure 110a and the upper ILD structure 110b. In some embodiments, the conductive source / drain contacts 924 are disposed in a different plane than the conductive gate contact 402. In other embodiments, the conductive source / drain contacts 924 may be disposed in the same plane as the conductive gate contact 402. In other embodiments, the conductive source / drain contacts 924 may include, for example, W, Ti, Al, etc.

[0065] Fig. 9 , the upper surface of the fifth conductive structure 918 and the upper surface of the anti-recession structure 112 form a concave surface. In some embodiments, the height of the anti-recession structure 112 increases as the anti-recession structure is disposed closer to the sidewall of the gate electrode 108. For example, the height of the eighth anti-recession structure 112h may be less than the height of the ninth anti-recession structure 112i, and the height of the ninth anti-recession structure 112i may be less than the height of the tenth anti-recession structure 112j. In other embodiments, a portion of the tenth anti-recession structure 112j may be disposed above the uppermost surface of the ninth anti-recession structure 112i, and a portion of the ninth anti-recession structure 112i may be disposed above the uppermost surface of the eighth anti-recession structure 112h. In yet other embodiments, the center point of the upper surface of the fifth conductive structure 918 is disposed below a different point of the upper surface of the fifth conductive structure 918 that is closer to the outer sidewall of the fifth conductive structure 918.

[0066] Fig.10 Shown including Fig. 9 A cross-sectional view of some embodiments of an integrated chip (IC) 1000 of some embodiments of a semiconductor device 100 and a second semiconductor device 1002 .

[0067] like Fig.10 As shown in , the second semiconductor device 1002 includes a second gate dielectric 1004 and a second gate electrode 1006 disposed on the second gate dielectric 1004. In some embodiments, the second semiconductor device 1002 (e.g., a logic MOSFET) has an operating voltage different from that of the semiconductor device 100 (e.g., a high voltage MOSFET). A second pair of source / drain regions 1008a and a source / drain region 1008b are disposed in the semiconductor substrate 102 and on opposite sides of the second gate dielectric 1004. In other embodiments, the length of the second gate electrode 1006 and / or the second gate dielectric 1004 is different from (e.g., smaller than) the length of the gate electrode 108 and / or the gate dielectric 106, respectively. In yet other embodiments, the width of the second gate electrode 1006 and / or the second gate dielectric 1004 is different from (e.g., smaller than) the width of the gate electrode 108 and / or the gate dielectric 106, respectively.

[0068] The second doped region 1010 is disposed in the semiconductor substrate 102. In some embodiments, the second doped region 1010 has the same doping type as the first doped region 902. In such embodiments, the second pair of source / drain regions 1008a and source / drain regions 1008b has the same doping type as the pair of source / drain regions 104a and source / drain regions 104b. In other embodiments, the second doped region 1010 and the first doped region 902 have opposite doping types. In such embodiments, the second pair of source / drain regions 1008a and source / drain regions 1008b and the pair of source / drain regions 104a and source / drain regions 104b have opposite doping types.

[0069] In some embodiments, the second gate dielectric 1004 includes a third dielectric structure 1012 and a fourth dielectric structure 1014 disposed on the third dielectric structure 1012. The third dielectric structure 1012 and the fourth dielectric structure 1014 may have the same chemical composition as the first dielectric structure 906 and the second dielectric structure 908, respectively. In other embodiments, the second gate electrode 1006 includes a sixth conductive structure 1016, a seventh conductive structure 1018, an eighth conductive structure 1020, a ninth conductive structure 1022, and a tenth conductive structure 1024. In still other embodiments, the chemical composition of the sixth conductive structure 1016, the seventh conductive structure 1018, the eighth conductive structure 1020, the ninth conductive structure 1022, and the tenth conductive structure 1024 may be the same as the chemical composition of the first conductive structure 910, the second conductive structure 912, the third conductive structure 914, the fourth conductive structure 916, and the fifth conductive structure 918, respectively.

[0070] In some embodiments, the second sidewall spacer 1026 is disposed over the semiconductor substrate 102 and along the sidewalls of the second gate electrode 1006 and the sidewalls of the second gate dielectric 1004. The chemical composition of the second sidewall spacer 1026 may be the same as the chemical composition of the sidewall spacer 920. In other embodiments, the upper surface of the second sidewall spacer 1026 may be substantially coplanar with the upper surface of the tenth conductive structure 1024.

[0071] In some embodiments, the CESL 922 is disposed along the sidewalls of the second sidewall spacers 1026 and along the second pair of source / drain regions 1008a and the source / drain regions 1008b. In other embodiments, one or more conductive gate contacts 402 are electrically coupled to the second gate electrode 1006. In other embodiments, the one or more conductive gate contacts 402 electrically coupled to the second gate electrode 1006 may be disposed in a different plane of the IC 1000 than the conductive gate contacts 402 electrically coupled to the gate electrode 108. In still other embodiments, some of the conductive source / drain contacts 924 are electrically coupled to the second pair of source / drain regions 1008a and the source / drain regions 1008b, respectively.

[0072] Fig.10 1024. It is also shown that the upper surface of the second gate electrode 1006 may be substantially coplanar with the upper surface of the lower ILD structure 110a. In other embodiments, the upper surface of the second gate electrode 1006 may be concave. In such embodiments, the radius of curvature of the concave surface of the second gate electrode 1006 may be smaller than the radius of curvature of the concave surface formed by the upper surface of the fifth conductive structure 918 and the upper surface of the anti-recess structure 112. In other embodiments, the uppermost portion of the tenth conductive structure 1024 extends continuously between the opposite sidewalls of the tenth conductive structure 1024. In other words, in some embodiments, the anti-recess structure 112 is not disposed in the tenth conductive structure 1024. In yet other embodiments, a portion of the tenth conductive structure 1024 may be disposed above the uppermost surface of each anti-recess structure 112.

[0073] Because the semiconductor device 100 and the second semiconductor device 1002 are integrated on the IC 1000 and because the gate electrode 108 may be larger (e.g., larger in length / width) than the second gate electrode 1006, the CMP process may cause the gate electrode 108 to be more severely recessed than the second gate electrode 1006. Because the anti-recessing structure 112 is embedded in the gate electrode 108 and because the second CMP removal rate is greater than the first CMP removal rate, the anti-recessing structure 112 may reduce the amount of recessing of the gate electrode 108 relative to the amount of recessing of the second gate electrode 1006. Therefore, the performance of the IC 1000 may be improved (e.g., by improving the integration of the semiconductor device 100 and the second semiconductor device 1002) and / or the cost of manufacturing the IC 1000 may be reduced.

[0074] Figures 11 to 19 Shown for forming Fig.10 A series of cross-sectional diagrams of some embodiments of methods of IC 1000 are shown.

[0075] like Fig.11 As shown in FIG. 1 , the first opening 1102 and the second opening 1104 are disposed in the lower ILD structure 110a and above the semiconductor substrate 102. In some embodiments, the Fig.11 A method of forming a structure of a semiconductor substrate 102 may include forming an isolation structure 904 in a semiconductor substrate 102 (e.g., by etching and deposition / growth processes). Subsequently, a first doped region 902 and a second doped region 1010 are formed in the semiconductor substrate 102 (e.g., by ion implantation). A gate dielectric 106 and a second gate dielectric 1004 are formed over the semiconductor substrate 102. Subsequently, a first dummy gate electrode (e.g., a polysilicon gate) and a second dummy gate electrode are formed on the gate dielectric 106 and the second gate dielectric 1004, respectively. Sidewall spacers 920 are formed over the semiconductor substrate 102 and laterally around the gate dielectric 106 and the first dummy gate electrode, and second sidewall spacers 1026 are formed over the semiconductor substrate 102 and laterally around the second gate dielectric 1004 and the second dummy gate electrode. A pair of source / drain regions 104a and 104b and a second pair of source / drain regions 1008a and 1008b are formed in / on the semiconductor substrate (e.g., by an epitaxial process). A CESL 922 is formed on the semiconductor substrate 102, the isolation structure 904, the pair of source / drain regions 104a and 104b, the second pair of source / drain regions 1008a and 1008b, the sidewall spacers 920, the second sidewall spacers 1026, the first dummy gate electrode, and the second dummy gate electrode.

[0076] The ILD layer is formed to cover the CESL 922, the isolation structure 904, the pair of source / drain regions 104a and 104b, the second pair of source / drain regions 1008a and 1008b, the sidewall spacers 920, the second sidewall spacers 1026, the first dummy gate electrode, and the second dummy gate electrode. A planarization process (e.g., CMP) is performed on the ILD layer and the CESL 922 to form a lower ILD structure 110a. Subsequently, the first dummy gate electrode and the second dummy gate electrode are removed (e.g., by an etching process).

[0077] A first conductive layer (not shown) is then deposited over the lower ILD structure 110a, on the gate dielectric 106, and on the second gate dielectric 1004, and is then etched to form a first conductive structure 910 on the gate dielectric 106 and a sixth conductive structure 1016 on the second gate dielectric 1004. A second conductive layer (not shown) is then deposited over the lower ILD structure 110a, on the first conductive structure 910, and on the sixth conductive structure 1016, and is then etched to form a second conductive structure 912 on the first conductive structure 910 and a seventh conductive structure 1018 on the sixth conductive structure 1016. A third conductive layer (not shown) is then deposited over the lower ILD structure 110a, on the second conductive structure 912, and on the seventh conductive structure 1018. The third conductive layer is then etched to form a third conductive structure 914 on the second conductive structure 912 and along the inner sidewalls of the sidewall spacers 920 , and an eighth conductive structure 1020 on the seventh conductive structure 1018 and along the inner sidewalls of the second sidewall spacers 1026 .

[0078] A fourth conductive layer (not shown) is then deposited on the third conductive structure 914 and on the eighth conductive structure 1020, and then etched to form a fourth conductive structure 916 lining the third conductive structure 914 and a ninth conductive structure 1022 lining the eighth conductive structure 1020. It should be understood that in some embodiments, the fourth conductive layer may be deposited on the third conductive layer, and a planarization process may be performed on the third and fourth conductive layers to form the fourth conductive structure 916, the third conductive structure 914, the ninth conductive structure 1022, and the eighth conductive structure 1020. In some embodiments, the above layers and / or structures may be formed using a deposition or growth process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, electrochemical plating, electroless plating, some other deposition or growth process, or a combination of the foregoing).

[0079] like Fig.12 As shown in FIG. 1 , above the lower ILD structure 110 a and the first opening 1102 and the second opening 1104 (see, for example, Fig.11 ) is formed in the conductive layer 1202. In some embodiments, the process for forming the conductive layer 1202 includes depositing a conductive layer on the lower ILD structure 110a, the CESL 922, the sidewall spacers 920, the third conductive structure 914, the fourth conductive structure 916, the second sidewall spacers 1026, the eighth conductive structure 1020, and the ninth conductive structure 1022. In some embodiments, the conductive layer 1202 may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In other embodiments, the conductive layer 1202 may include or be a metal (e.g., W, Al, Ti, Mo, etc.).

[0080] like Fig.13 As shown in FIG. 1 , a plurality of openings 1302 are formed in the conductive layer 1202. In some embodiments, the openings 1302 are formed within the perimeter of the gate dielectric 106. In other embodiments, the openings 1302 are formed to be vertically spaced apart from the gate dielectric 106.

[0081] In some embodiments, the process for forming the opening 1302 includes forming a patterned mask layer 1304 on the conductive layer 1202. In other embodiments, the patterned mask layer 1304 may be formed by a spin coating process (e.g., depositing a mask layer) and patterned using photolithography (e.g., patterning the mask layer into the patterned mask layer 1304). In still other embodiments, the process includes appropriately etching the conductive layer 1202 with the patterned mask layer 1304 (e.g., by a dry / wet etching process), thereby forming the opening 1302. Subsequently, the patterned mask layer 1304 may be removed.

[0082] like Fig.14 As shown in FIG. 1 , above the conductive layer 1202 and the opening 1302 (see, for example, Fig.13 ) is formed in the opening 1302. The anti-depression layer 1402 has a different CMP removal rate than the conductive layer 1202. In some embodiments, the process for forming the anti-depression layer 1402 includes depositing or growing the anti-depression layer 1402 on the conductive layer 1202 and in the opening 1302. In some embodiments, the anti-depression layer 1402 may be deposited by, for example, CVD, PVD, ALD, thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In other embodiments, the anti-depression layer 1402 may include, for example, an oxide (e.g., SiO2), a nitride (e.g., silicon nitride (SiN)), an oxynitride (e.g., silicon oxynitride (SiO X N Y)), some other material capable of filling the opening 1302 and having a CMP removal rate different from (eg, less than) that of the conductive layer 1202, or a combination of the foregoing.

[0083] like Fig.15 As shown in FIG. 1 , the anti-recession layer 1402 (see, for example, Fig.14 ) performs a first planarization process 1502 (e.g., CMP) to form a plurality of anti-recessing structures 112 embedded in conductive layer 1202. In some embodiments, first planarization process 1502 may also be performed in conductive layer 1202. In other embodiments, first planarization process 1502 is a CMP process. In other embodiments, after first planarization process 1502, a portion of anti-recessing layer 1402 (not shown) may be disposed on conductive layer 1202 and coupled to anti-recessing structures 112. In yet other embodiments, this portion of anti-recessing layer 1402 may have an upper surface coplanar with an upper surface of conductive layer 1202.

[0084] like Fig.16 , a gate electrode 108 is formed over the gate dielectric 106, and a second gate electrode 1006 is formed over the second gate dielectric 1004. In some embodiments, the process for forming the gate electrode 108 and the second gate electrode 1006 includes performing a second planarization process 1602 (e.g., CMP) on the anti-recess structure 112 and the conductive layer 1202, thereby forming a fifth conductive structure 918 on the gate dielectric 106 and a tenth conductive structure 1024 on the second gate dielectric 1004. In other embodiments, the second planarization process 1602 may also be performed on the lower ILD structure 110a, the CESL 922, the sidewall spacer 920, the third conductive structure 914, the fourth conductive structure 916, the second sidewall spacer 1026, the eighth conductive structure 1020, and / or the ninth conductive structure 1022.

[0085] In some embodiments, the second planarization process 1602 may have different process parameters (e.g., chemical slurry composition, pressure, speed, time, etc.) than the first planarization process 1502. In other embodiments, the first planarization process 1502 may not be performed. In such embodiments, the second planarization process 1602 may be performed on the anti-sag layer 1402 forming the anti-sag structure 112 and then on the conductive layer 1202 to form the gate electrode 108 and the second gate electrode 1006. In other such embodiments, the second planarization process 1602 may be performed continuously such that a single planarization process is performed on the anti-sag layer 1402 and the conductive layer 1202 until the gate electrode 108 and the second gate electrode 1006 are formed. In still other embodiments, after the gate electrode 108 and the second gate electrode 1006 are formed, the formation of the semiconductor device 100 and the second semiconductor device 1002 is completed.

[0086] like Fig.17 As shown in , an upper ILD structure 110b is formed over the lower ILD structure 110a, the gate electrode 108, the anti-recess structure 112, and the second gate electrode 1006. In some embodiments, the upper ILD structure 110b may be formed with a substantially planar upper surface. In other embodiments, the process for forming the upper ILD structure 110b includes depositing an ILD layer on the lower ILD structure 110a, the gate electrode 108, the anti-recess structure 112, and the second gate electrode 1006. The ILD layer may be deposited by, for example, CVD, PVD, sputtering, or some other deposition process. Subsequently, a planarization process (e.g., CMP) may be performed on the ILD layer.

[0087] like Fig.18 As shown in FIG, a plurality of conductive gate contacts 402 are formed over the gate electrode 108 and the second gate electrode 1006. The conductive gate contacts 402 are formed to extend through the upper ILD structure 110b to the gate electrode 108 and the second gate electrode 1006. In addition, a plurality of conductive source / drain contacts 924 are formed over the semiconductor substrate 102 and extend through the upper ILD structure 110b and the lower ILD structure 110a to the pair of source / drain regions 104a and 104b and the second pair of source / drain regions 1008a and 1008b.

[0088] In some embodiments, the process for forming the conductive gate contact window 402 and the conductive source / drain contact window 924 includes performing a first etching on the upper ILD structure 110b to form a first contact window opening (not shown) corresponding to the conductive gate contact window 402. The first etching may be performed using a first patterned mask layer (not shown) disposed on the upper ILD structure 110b. Subsequently, a conductive material (e.g., W) is deposited on the upper ILD structure 110b and fills the first contact window opening. Subsequently, a planarization process (e.g., CMP) may be performed on the conductive material and the first patterned mask layer, thereby forming the conductive gate contact window 402. In other embodiments, a second etching is performed on the upper ILD structure 110b and the lower ILD structure 110a to form a second contact window opening (not shown) corresponding to the conductive source / drain contact window 924. The second etching may be performed using a second patterned mask layer (not shown) disposed on the upper ILD structure 110b. Subsequently, a conductive material (e.g., W) is deposited on the upper ILD structure 110b and fills the second contact window opening. Subsequently, a planarization process (e.g., CMP) may be performed on the conductive material and the second patterned mask layer, thereby forming a conductive source / drain contact window 924. Although not shown, additional dielectric layers (e.g., ILD layers) and / or conductive features (e.g., metal lines, metal vias, etc.) may be subsequently formed over the upper ILD structure 110b, the conductive gate contact window 402, and the conductive source / drain contact window 924.

[0089] Fig.19 Flowchart 1900 illustrates some embodiments of a method for forming an integrated chip (IC) having a first semiconductor device and a second semiconductor device, wherein the first semiconductor device includes a plurality of anti-recession structures embedded in a first gate electrode. Fig.19 Flowchart 1900 is shown and described herein as a series of actions or events, but it should be understood that the order of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described herein, some actions may occur in a different order and / or at the same time as other actions or events. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or stages.

[0090] At act 1902, a semiconductor substrate having a lower interlayer dielectric (ILD) structure disposed on the semiconductor substrate is provided, wherein a first opening is disposed in the lower ILD structure and over a first gate dielectric, and wherein a second opening is disposed in the lower ILD structure and over a second gate dielectric. Fig.11 A cross-sectional view corresponding to some embodiments of act 1902 is shown.

[0091] At act 1904 , a conductive layer is formed over the lower ILD structure and in the first opening and the second opening. Fig.12 A cross-sectional view corresponding to some embodiments of act 1904 is shown.

[0092] At act 1906, a plurality of anti-recessing structures are formed in the conductive layer, wherein the anti-recessing structures are formed within an outer perimeter of the first gate dielectric. Figures 13 to 15 A series of cross-sectional views corresponding to some embodiments of act 1906 are shown.

[0093] At act 1908, a planarization process is performed on the conductive layer and the anti-recession structure to form a first gate electrode over the first gate dielectric and a second gate electrode over the second gate dielectric, wherein the anti-recession structure is embedded in the first gate electrode. Fig.16 A cross-sectional view corresponding to some embodiments of act 1908 is shown.

[0094] At activity 1910 , an upper ILD structure is formed over the lower ILD structure, the anti-recess structure, the first gate electrode, and the second gate electrode. Fig.17 A cross-sectional view corresponding to some embodiments of act 1910 is shown.

[0095] At act 1912, a plurality of conductive contacts are formed over the semiconductor substrate. Fig.18 A cross-sectional view corresponding to some embodiments of act 1912 is shown.

[0096] In some embodiments, the present application provides a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed above the semiconductor substrate. A first source / drain region and a second source / drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed above the gate dielectric. A first anti-recession structure is embedded in the gate electrode, wherein a perimeter of the first anti-recession structure is disposed within a perimeter of the gate electrode. In some embodiments, a bottom surface of the first anti-recession structure is disposed between an upper surface of the gate electrode and a bottom surface of the gate electrode. In some embodiments, the semiconductor device further includes a sidewall spacer disposed along an outer sidewall of the gate electrode, wherein the first anti-recession structure is spaced apart from the sidewall spacer. In some embodiments, the first anti-recession structure has a circular bottom surface. In some embodiments, the first anti-recession structure includes a dielectric material; and the gate electrode includes a metal. In some embodiments, the first anti-recession structure is one of a plurality of anti-recession structures embedded in the gate electrode. In some embodiments, the semiconductor device further comprises a second anti-recession structure among a plurality of anti-recession structures, wherein the second anti-recession structure is embedded in the gate electrode and spaced apart from the first anti-recession structure, and wherein the perimeter of the second anti-recession structure is disposed within the perimeter of the gate electrode. In some embodiments, the first anti-recession structure comprises a first sidewall and a second sidewall opposite to the first sidewall; the second anti-recession structure comprises a third sidewall and a fourth sidewall opposite to the third sidewall; the first sidewall and the third sidewall are substantially aligned in the lateral direction; and the second sidewall and the fourth sidewall are substantially aligned in the lateral direction. In some embodiments, the first anti-recession structure is disposed between the second anti-recession structure and the outer sidewall of the gate electrode; and a portion of the first anti-recession structure is disposed above the uppermost surface of the second anti-recession structure. In some embodiments, the area of ​​the first anti-recession structure is substantially the same as the area of ​​the second anti-recession structure. In some embodiments, the area of ​​the first anti-recession structure is different from the area of ​​the second anti-recession structure. In some embodiments, the semiconductor device further comprises a conductive contact window electrically coupled to the gate electrode, wherein the conductive contact window is spaced apart from each of the plurality of anti-recession structures. In some embodiments, the gate electrode includes a fifth sidewall; and the conductive contact window is disposed closer to the fifth sidewall than each of the plurality of anti-recess structures. In some embodiments, the gate electrode includes a sixth sidewall opposite to the fifth sidewall; the sixth sidewall is spaced apart from the fifth sidewall in a first lateral direction; and the first source / drain region and the second source / drain region are spaced apart in a second lateral direction perpendicular to the first lateral direction.

[0097] In some embodiments, the present application provides an integrated chip (IC). The IC includes a semiconductor substrate. A first gate dielectric is disposed above the semiconductor substrate. A first gate electrode is disposed above the first gate dielectric, wherein the first gate electrode has a first length. A second gate dielectric is disposed above the semiconductor substrate and spaced apart from the first gate dielectric. The second gate electrode is disposed above the semiconductor substrate and spaced apart from the first gate electrode, wherein the second gate electrode has a second length greater than the first length. A dielectric structure is embedded in the second gate electrode, wherein an outer sidewall of the dielectric structure is disposed within an outer sidewall of the second gate electrode. In some embodiments, the second gate electrode includes a first conductive structure and a second conductive structure. The first conductive structure has a first conductive material. The second conductive structure has a second conductive material different from the first conductive material, wherein the second conductive structure is lined with a bottom surface of the first conductive structure and a sidewall of the first conductive structure, and wherein the dielectric structure is spaced apart from the second conductive structure by a portion of the first conductive structure. In some embodiments, the dielectric structure has a first chemical mechanical polishing removal rate for a chemical mechanical polishing process; the second gate electrode has a second chemical mechanical polishing removal rate for a chemical mechanical polishing process; and the second chemical mechanical polishing removal rate is greater than the first chemical mechanical polishing removal rate. In some embodiments, the first gate electrode comprises a first conductive structure, the first conductive structure comprises a metal; and the metal extends continuously between opposite sidewalls of the first conductive structure in an uppermost portion of the first conductive structure. In some embodiments, the chemical composition of the first gate dielectric is substantially the same as the chemical composition of the second gate dielectric; and the chemical composition of the first gate electrode is substantially the same as the chemical composition of the second gate electrode.

[0098] In some embodiments, the present application provides a method. The method includes forming a first opening above a gate dielectric, wherein the gate dielectric is disposed on a semiconductor substrate. Depositing a conductive layer above the gate dielectric and in the first opening. Forming a second opening in the conductive layer and the second opening is spaced apart from the gate dielectric, wherein a perimeter of the second opening is disposed within a perimeter of the gate dielectric. Depositing an anti-sag layer on the conductive layer and in the second opening. Forming a gate electrode and an anti-sag structure embedded in the gate electrode by performing a chemical mechanical polishing (CMP) process on the anti-sag layer and the conductive layer.

[0099] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a gate dielectric disposed above the semiconductor substrate; a first source / drain region and a second source / drain region disposed in the semiconductor substrate and on opposite sides of the gate dielectric; a gate electrode disposed above the gate dielectric; as well as A plurality of anti-recessing structures are embedded in the gate electrode, wherein a polishing rate of the plurality of anti-recessing structures is lower than a polishing rate of the gate electrode, and the plurality of anti-recessing structures include: a first anti-sag structure, wherein a perimeter of the first anti-sag structure is disposed within a perimeter of the gate electrode; as well as A second anti-recession structure is spaced apart from the first anti-recession structure, and a perimeter of the second anti-recession structure is arranged within the perimeter of the gate electrode, wherein the first anti-recession structure is arranged between the second anti-recession structure and the outer side wall of the gate electrode, and a portion of the first anti-recession structure is arranged above the uppermost surface of the second anti-recession structure. 2 . The semiconductor device according to claim 1 , wherein a bottom surface of the first recess prevention structure is disposed between an upper surface of the gate electrode and a bottom surface of the gate electrode.

3. The semiconductor device according to claim 1, further comprising: A sidewall spacer is disposed along an outer sidewall of the gate electrode, wherein the first anti-recess structure is spaced apart from the sidewall spacer. The semiconductor device according to claim 1 , wherein the first anti-recess structure has a rounded bottom surface.

5. The semiconductor device according to claim 1, wherein: The first anti-sag structure comprises a dielectric material; and The gate electrode includes metal.

6. The semiconductor device according to claim 1, wherein: The first anti-sag structure includes a first side wall and a second side wall opposite to the first side wall; The second anti-sag structure includes a third side wall and a fourth side wall opposite to the third side wall; The first sidewall and the third sidewall are substantially aligned in a lateral direction; as well as The second sidewall and the fourth sidewall are substantially aligned in the lateral direction. 7 . The semiconductor device according to claim 1 , wherein an area of ​​the first anti-recess structure is substantially the same as an area of ​​the second anti-recess structure. 8 . The semiconductor device according to claim 1 , wherein an area of ​​the first anti-recess structure is different from an area of ​​the second anti-recess structure.

9. The semiconductor device according to claim 1, further comprising: A conductive contact window is electrically coupled to the gate electrode, wherein the conductive contact window is spaced apart from each of the plurality of anti-recess structures.

10. The semiconductor device according to claim 9, wherein: The gate electrode includes a fifth sidewall; and The conductive contact window is disposed closer to the fifth sidewall than each of the plurality of anti-recess structures.

11. The semiconductor device according to claim 10, wherein: The gate electrode comprises a sixth side wall opposite to the fifth side wall; The sixth side wall is spaced apart from the fifth side wall in the first lateral direction; as well as The first source / drain region and the second source / drain region are laterally spaced apart in a second lateral direction perpendicular to the first lateral direction.

12. An integrated chip, comprising: Semiconductor substrate; A first gate dielectric is disposed above the semiconductor substrate; a first gate electrode disposed above the first gate dielectric, wherein the first gate electrode has a first length; a second gate dielectric disposed above the semiconductor substrate and spaced apart from the first gate dielectric; a second gate electrode disposed above the semiconductor substrate and spaced apart from the first gate electrode, wherein the second gate electrode has a second length greater than the first length; as well as a dielectric structure embedded in the second gate electrode, wherein a polishing rate of the dielectric structure is less than a polishing rate of the second gate electrode, an outer sidewall of the dielectric structure is disposed within an outer sidewall of the second gate electrode, and the dielectric structure comprises: a first anti-sag structure, wherein a perimeter of the first anti-sag structure is disposed within a perimeter of the second gate electrode; as well as A second anti-recession structure is spaced apart from the first anti-recession structure, and a perimeter of the second anti-recession structure is arranged within the perimeter of the second gate electrode, wherein the first anti-recession structure is arranged between the second anti-recession structure and the outer side wall of the second gate electrode, and a portion of the first anti-recession structure is arranged above the uppermost surface of the second anti-recession structure.

13. The integrated chip according to claim 12, wherein the second gate electrode comprises: A first conductive structure having a first conductive material; as well as A second conductive structure has a second conductive material different from the first conductive material, wherein the second conductive structure lines a bottom surface of the first conductive structure and sidewalls of the first conductive structure, and wherein the dielectric structure is separated from the second conductive structure by a portion of the first conductive structure.

14. The integrated chip according to claim 12, wherein: The first gate electrode comprises a first conductive structure, the first conductive structure comprising metal; and The metal extends continuously between opposing sidewalls of the first conductive structure in an uppermost portion of the first conductive structure.

15. The integrated chip according to claim 12, wherein: The chemical composition of the first gate dielectric is substantially the same as the chemical composition of the second gate dielectric; and A chemical composition of the first gate electrode is substantially the same as a chemical composition of the second gate electrode.

16. A method for forming a semiconductor device, the method comprising: forming a first opening over a gate dielectric, wherein the gate dielectric is disposed on a semiconductor substrate; depositing a conductive layer over the gate dielectric and in the first opening; forming a plurality of second openings in the conductive layer and spaced apart from the gate dielectric, wherein perimeters of the plurality of second openings are disposed within a perimeter of the gate dielectric; depositing an anti-sag layer on the conductive layer and in the plurality of second openings; as well as A gate electrode and a plurality of anti-recession structures embedded in the gate electrode are formed by performing a chemical mechanical polishing process on the anti-recession layer and the conductive layer, wherein a polishing rate of the plurality of anti-recession structures is lower than a polishing rate of the gate electrode, and the plurality of anti-recession structures include: a first anti-sag structure, wherein a perimeter of the first anti-sag structure is disposed within a perimeter of the gate electrode; as well as A second anti-recession structure is spaced apart from the first anti-recession structure, and a perimeter of the second anti-recession structure is arranged within the perimeter of the gate electrode, wherein the first anti-recession structure is arranged between the second anti-recession structure and the outer side wall of the gate electrode, and a portion of the first anti-recession structure is arranged above the uppermost surface of the second anti-recession structure.

17. A semiconductor device comprising: Semiconductor substrate; a gate dielectric disposed above the semiconductor substrate; a pair of source / drain regions disposed in the semiconductor substrate, wherein the source / drain regions are disposed on opposite sides of the gate dielectric; a gate electrode disposed over the gate dielectric, wherein the gate electrode comprises a metal; and a plurality of anti-recession structures embedded in the gate electrode, wherein a polishing rate of the plurality of anti-recession structures is less than a polishing rate of the gate electrode, the plurality of anti-recession structures are laterally spaced apart from each other, and wherein each anti-recession structure is vertically spaced apart from the gate dielectric, and the plurality of anti-recession structures include: a first anti-sag structure, wherein a perimeter of the first anti-sag structure is disposed within a perimeter of the gate electrode; as well as A second anti-recession structure is spaced apart from the first anti-recession structure, and a perimeter of the second anti-recession structure is arranged within the perimeter of the gate electrode, wherein the first anti-recession structure is arranged between the second anti-recession structure and the outer side wall of the gate electrode, and a portion of the first anti-recession structure is arranged above the uppermost surface of the second anti-recession structure.

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