Method and circuit for controlling power supply

Abstract

The present application relates to methods and circuits for controlling a power supply. In the described example, the power supply has a transformer and a switch, the switch being coupled to the primary side of the transformer for controlling current flowing through the primary side of the transformer. The method (700) includes determining an output voltage of the power supply (702). In response to the output voltage being greater than a nominal output voltage and less than a predetermined voltage, a first minimum switching frequency (704) for driving the switch is generated. In response to the output voltage being equal to or greater than the predetermined voltage, a second minimum switching frequency for driving the switch is generated, wherein the first minimum switching frequency is greater than the second minimum switching frequency (706).

Description

[0001] This application is a divisional application of Chinese patent application No. 201780009551.6, entitled “Method and circuit for controlling power supply”, filed on February 6, 2017. Technical Field

[0002] The present application generally relates to methods and circuits for operating a switching power supply. Background Art

[0003] A flyback power supply includes a transformer having a primary side coupled to an input voltage source. The output of the flyback power supply is coupled to the secondary side of the transformer. Output voltage regulation is achieved by controlling the current flowing through the primary side of the transformer. Summary of the invention

[0004] In the described example, a power supply has a transformer and a switch, the switch coupled to the primary side of the transformer for controlling current flowing through the primary side of the transformer. A method includes determining an output voltage of the power supply. In response to the output voltage being greater than a nominal output voltage and less than a predetermined voltage, a first minimum switching frequency for driving the switch is generated. In response to the output voltage being equal to or greater than the predetermined voltage, a second minimum switching frequency for driving the switch is generated, wherein the first minimum switching frequency is greater than the second minimum switching frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of an example of a flyback power supply.

[0006] Figure 2 yes Figure 1 Example waveform of a sample voltage in the power supply.

[0007] Figure 3 It is shown by Figure 1 Timing diagram of the problem caused by the switching frequency in the power supply.

[0008] Figure 4 is a schematic diagram of an example power supply controller.

[0009] Figure 5 It is shown Figure 4 Multiple timing diagrams of example operations of the controller.

[0010] Figure 6 Is a description Figure 4 A flow chart of an example of the operation of a controller.

[0011] Figure 7 Is a description Figure 4 A flow chart of another example of the operation of a controller. DETAILED DESCRIPTION

[0012] Some flyback power supplies use magnetic feedback or primary side regulation (PSR) to avoid the cost and parts count of other feedback methods. The use of PSR is often accompanied by the use of switching frequency foldback, which is used to maintain high operating efficiency at light loads and reduce power consumption in "no-load" or standby conditions. Meeting standby power consumption targets requires a very low standby switching frequency fSW(ST), such as 1kHz to 3kHz for a typical 10W power supply. In standby mode, the external load of the power supply is zero. Although in order to maintain the output voltage level, the power supply operates at a limited load level, which is the sum of the small internal preload and the load applied by the power supply itself. The power supply must be able to reduce its output power delivery to this low level, otherwise it will lose regulation as the output voltage begins to rise.

[0013] In the case of PSR, the power supply control loop has an inherent delay in its response to load changes equal to 1 / fSW, where fSW is the switching frequency of the power supply. During this delay, the output voltage of the power supply drops based on the level of the output current and the size of the output capacitor. If a large change in output current occurs at the beginning of this delay, the drop may be unacceptably large. In the case of repeated load changes, this problem is exacerbated. Increasing the size of the output capacitor is undesirable for cost and size reasons.

[0014] Figure 1 1 is a schematic diagram of an example of a flyback power supply 100. The power supply 100 is a switching power supply that converts an AC input voltage VIN into a DC output voltage VOUT. The power supply 100 includes a bridge rectifier 102 that converts an AC input voltage VAC into a rectified voltage. The output of the bridge rectifier 102 is coupled to a filter 104. The output of the filter 104 is coupled to a primary side 110 of a transformer T11 having an NP winding. The primary side 110 of the transformer T11 also includes an auxiliary winding 112 that has a NAUX winding and is used by the power supply 100 to generate an operating voltage VDD of the power supply 100. The auxiliary winding 112 generates a voltage VAUX during operation of the power supply 100.

[0015] The primary side 110 of the transformer T11 is coupled in series to a switch Q11, a resistor R11, and a ground node. The ground node may be a potential other than the voltage VDD. Figure 1In the example of , switch Q11 is a transistor, such as a field effect transistor (FET). The state of transistor Q11 is set by the gate voltage on transistor Q11. The current flowing through switch Q11 is the current flowing through the primary side 110 of transformer T11 and is referred to herein as current IP. The current IP flowing through resistor R11 generates a current sense voltage VCS, which is measured to determine current IP as described herein.

[0016] The auxiliary winding 112 is coupled to a converter composed of a capacitor C11 and a diode D11, which converts the auxiliary voltage VAUX into an operating voltage VDD. The auxiliary voltage VAUX is sampled by a sampling voltage VS. Figure 1 In the example of FIG. 4 , a voltage divider composed of resistors R12 and R13 reduces the auxiliary voltage VAUX to generate a sampling voltage VS.

[0017] Transformer T11 has a secondary side 120 with NS turns of winding. The output voltage of secondary side 120 is output voltage VOUT. Secondary side 120 generates current IS. Output voltage VOUT is coupled to resistor R14, capacitor C12 and Schottky rectifier D12. Rectifier D12 has a forward voltage VZ21 that can be approximately 0.35V. Resistor R14 is used as a preload. Secondary side 120 generates current IOUT flowing through load 122. As described herein, load 122 has an impedance that can be varied. Changes in the impedance of load 122 change the current IOUT flowing through load 122, which changes the power output of power supply 100.

[0018] The controller 130 monitors the output voltage VOUT of the power supply 100 and controls the switching of the gate of the transistor Q11 to maintain the output voltage VOUT constant. The output voltage VOUT is maintained constant across the varying output load by the controller 130, thereby matching its power delivery to the load 122 at the output voltage VOUT. Then, the specific switching mode of the transistor Q11 can be referred to as generating a specific output power level for the regulated output voltage VOUT entering the load 122. Moreover, by forcing a specific switch control on the transistor Q11, a specific power delivery level independent of the output voltage VOUT can be forced. The controller 130 has inputs coupled to the sampling voltage VS, the operating voltage VDD, and the current sensing voltage VCS. The controller 130 has an output DRV, which drives the gate of the transistor Q11 with a drive voltage VDRV in response to the input to the controller 130.

[0019] Power supply 100 is referred to as a primary side regulated (PSR) power supply because the voltage and / or current on primary side 110 of transformer T11 is sampled and / or regulated to control output voltage VOUT. PSR power supplies do not include the cost and complexity of feedback from secondary side 120 of transformer T11.

[0020] Figure 2 2 is a graph 200 showing an example of auxiliary voltage VAUX as a function of time. During operation of power supply 100, auxiliary voltage VAUX is sampled once per switching cycle at the VS input to controller 130. Figure 2 In the cycle, the auxiliary voltage VAUX is sampled at time t21 and is equal to (VOUT+VZ21)NA / NS. Figure 1 , the sampled voltage VS and / or current IP are measured and used to adjust the output voltage VOUT. For example, the controller 130 switches the transistor Q11 on and off for a certain period of time at a switching frequency fSW in response to the sampled voltage VS and / or current IP. The switching frequency fSW is high when the load 122 draws a high load, and the switching frequency fSW is reduced when a light load is drawn, such as when the power supply 100 is in standby mode. The high switching frequency FSW is a switching frequency generated to drive the load under normal operating conditions other than standby or light load conditions. In some examples, in addition to modulating the on-time of the transistor Q11, the switching frequency of the transistor Q11 can also be modulated to control the power and thus adjust the output voltage VOUT under varying load or input voltage conditions. This output regulation is referred to as the control loop of the power supply 100.

[0021] The switching frequency fSW of transistor Q11 and / or the period during which transistor Q11 is turned on determines the output voltage VOUT for a given load. The switching frequency fSW and / or the period during which transistor Q11 is turned on changes as the impedance in the load 122 changes. For example, under heavy load conditions, the load 122 draws more current than under light load conditions, which causes the output voltage VOUT to drop, so the switching frequency fSW of transistor Q11 increases. When the power supply 100 is operating in a no-load state, the load 122 draws little or no current or power. In this state, transistor Q11 is turned on at a low switching frequency fSW to keep the voltage VDD high enough to operate the power supply 100. During the transition between heavy load and light load, the switching frequency fSW must be monitored to avoid overvoltage conditions or to avoid causing the power supply 100 to draw excessive current, both of which are inefficient.

[0022] Power supplies using primary side regulation (PSR) avoid the cost and parts count of other power supplies that use secondary feedback methods. The use of PSR is often accompanied by the use of switching frequency foldback, which is used to maintain high operating efficiency at light loads and reduce power consumption in no-load or standby conditions. Meeting standby power consumption targets requires very low switching frequencies fSW, such as 1kHz to 3kHz for a typical 10W AC / DC power supply. In standby mode, the current drawn by the load 122 is zero or close to zero, but the power supply 100 operates at a limited load level to maintain the controller 130, which is the sum of the small internal preload (resistor R14) and the load applied by the controller 130 itself. The power supply 100 must be able to reduce its output power delivery to this low level, otherwise it will lose regulation of power due to the rise in the output voltage VOUT. Alternatively, the current drawn during standby can be increased by increasing the preload, which results in an increase in standby power consumption.

[0023] In the case of PSR, the power supply control loop has an inherent potential delay 1 / fSW in its response to changes in the impedance of the load 122. During this delay, the output voltage VOUT of the power supply 100 undergoes a drop that is based on the level of the output current IOUT and the capacitance value of the output capacitor C12. If a large change in the output current IOUT occurs at the beginning of this delay, the drop may be unacceptably large. Increasing the size of the output capacitor C12 is undesirable because it increases the size and cost of the power supply 100.

[0024] In the absence of any additional feedback signal, the initial transient response from the static standby mode is essentially limited by the delay period l / (fSW(ST)) of the standby switching frequency in the standby mode. Typically, the standby switching frequency fSW(ST) varies during the standby mode in proportion to the total load on the secondary side 120. Therefore, optimizing the transient response for this case must be done by adjusting the preload while still keeping the standby power below the maximum specification, which requires increasing the switching frequency fSW to a point where a delay of 1 / fSW results in an acceptable transient response.

[0025] Increasing the standby switching frequency fSW(ST) does not address the situation of repetitive load transients, where the loop response of the power supply 100 causes the output voltage VOUT to overshoot during the negative (load reduction or load dump) transitions of the repetitive transients. These voltage overshoots cause the controller 130 to generate an absolute minimum switching frequency fSW(MIN). This minimum switching frequency fSW(MIN) is typically lower than the standby switching frequency fSW(ST). If a subsequent positive transient edge occurs during this condition, the output voltage drop can be quite large.

[0026] Figure 3308 is a timing diagram illustrating the problems caused by the switching frequency described above. Graph 302 illustrates an example of an auxiliary voltage VAUX with a low to high frequency transition, which corresponds to a high to low period 1 / fSW. During the low frequency period, the switching frequency fSW has reached the minimum switching frequency fSW(MIN), as shown in graph 302. During the minimum switching frequency fSW(MIN) period, the impedance of the load 122 increases rapidly, which causes the output current IOUT to experience a step increase, as shown at time t31 on graph 308. The change in the impedance of the load 122 causes the output voltage VOUT to begin to decrease at time t31, as shown in graph 316, which is an example of the output voltage VOUT as a function of time. Due to the long period of the minimum switching frequency l / fSW(MIN), the output voltage VOUT experiences a significant drop to the minimum drop voltage VDMIN. The difference between the output voltage VOUT and the minimum drop voltage VDMIN is the voltage difference ΔVOUT. The output voltage VOUT continues to decrease until reaching time t32, which is the time when the auxiliary voltage VAUX is reset or the switching frequency fSW is increased. Figure 2 As shown, the output voltage VOUT is sampled during the end of the positive excursion of the voltage VAUX. When the control loop responds to the now known low output voltage VOUT, it stops decreasing some time after the first positive excursion (narrow pulse). The pulse width in the auxiliary voltage VAUX is proportional to the peak primary current IP. In these examples, the controller 130 is used to modulate both the current IP and the switching frequency fSW. Figure 3 The drop described in is the worst case, which occurs when the transient occurs at the beginning of the 1 / fSW delay. The voltage difference ΔV OUT It is given by the following equation (1):

[0027]

[0028] like Figure 3 As shown in the graph 316 of , the output voltage VOUT has experienced a significant drop for a significant period of time, which results in a significant voltage difference ΔVOUT. If the minimum switching frequency fSW(MIN) occurs repeatedly, the output voltage VOUT will experience a series of drops and will be very unstable. For example, if the impedance of the load 122 changes continuously, the output voltage VOUT will continue to experience the undesirable drops shown in the graph 316.

[0029] Power supply controllers and methods of operating the controllers are described herein, which provide for adaptively maintaining a high minimum switching frequency when repeated load steps are applied to the output. The high minimum switching frequency is fixed and improves load transient response, such as reducing the minimum drop voltage level. The methods described herein use an increased minimum switching frequency, which is referred to as a first minimum switching frequency fSW(MIN), which is maintained unless the output voltage VOUT rises to a predetermined overshoot level VOUT(HI). When the output voltage rises to a predetermined level VOUT(HI), a second minimum switching frequency fSW(MIN2) is generated, which reduces the output voltage VOUT. The second minimum switching frequency fSW(MIN2) is also fixed. For the operating current level defined in transistor Q11, the converter 130 can be shown as delivering two defined power levels PRW(min1) and PWR(min2) at the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2).

[0030] Figure 4 is a schematic diagram of an example power supply controller 400 implementing the improvements described herein. The controller 400 may be implemented as Figure 1 The controller 130 may have Figure 4 4. The controller 400 receives the voltage VDD and distributes it to the power and fault management circuit 402 and the driver circuit 406. The circuit 402 determines whether there is a fault in the power supply coupled to the controller 400 or in the controller 400 itself. In response to this determination, the bias voltage VBIAS is output. The bias voltage VBIAS powers devices and / or components within the controller 400 and can terminate the bias voltage VBIAS if the circuit 402 detects a fault.

[0031] The driving circuit 406 drives the switch by outputting a driving voltage VDRV at a driving node DRV, such as Figure 1 The transistor Q11, which switches the Figure 1 The driving circuit 406 includes a current source I41 powered by the voltage VDD, and the current source I41 is coupled to a node N41, which is also coupled to the Figure 1 The driver node DRV. Figure 4 In the example of , node N41 is coupled to a Zener diode D41, which conceptually regulates or limits the drive voltage VDRV. A switch (such as a transistor Q41) is coupled between node N41 and ground. Transistor Q41 receives a control signal to its gate from latch 410. Figure 4In the example of FIG. 4 , a driver or inverter 412 is coupled between the latch 410 and the gate of the transistor Q41. A resistor R41 is coupled in parallel with the transistor Q41. During operation of the controller 400, when the state of the transistor Q41 is on or conducting, the current generated by the current source I41 flows through the transistor Q41. In this state, the drive voltage VDRV is zero or low. When the state of the transistor Q41 is off or non-conducting, the current generated by the current source I41 conducts through the resistor R41 to generate the drive voltage VDRV to drive the transistor Q41. Figure 1 The gate of transistor Q11.

[0032] The voltage VS is input to three devices: a sampler 418, a zero crossing detector 420, and a secondary timing detector 422. The sampler 418 samples the voltage VS and generates a sampled voltage VSS. The zero crossing detector 420 detects a zero crossing in the voltage VS and generates a signal when a zero crossing is detected. The secondary timing detector 422 generates a signal that is input to a current regulation and cable compensation circuit 430. The circuit 430 generates a compensation voltage VCVS and a compensation signal that is coupled to the input of an AND gate 432.

[0033] The error amplifier 436 amplifies the sample voltage VSS using the constant voltage VC and the offset of the compensation voltage VCVS. The constant voltage VC is a voltage related to the ideal or nominal output voltage VOUT(NOM). Figure 4 In the example shown, the constant voltage VC is 4.05V, but it is a design choice and other values ​​may be used. The output of amplifier 436 is a signal indicative of the power output by the power supply operated by controller 400 and is coupled to an input of a control circuit 440 that sets the switching frequency of the power supply. In some examples, the output of amplifier 436 indicates the output voltage of the power supply. The output of amplifier 436 is also coupled to a reset input of latch 442. As described in more detail below, latch 442 determines the minimum switching frequency fSW(MIN) generated by controller 400. Controller 400 generates a first minimum switching frequency fSW(MIN1) and a second minimum switching frequency fSW(MIN2) in response to the output power requirement of the power supply. Figure 4 In the example of FIG. 1 , the first minimum switching frequency fSW(MIN1) is 4 KHz, and the second minimum switching frequency fSW(MIN2) is 1 KHz.

[0034] The comparator 450 compares at least a portion of the sampled voltage VSS with the constant voltage VC described above. Figure 4In the example of , the constant voltage VC is 4.05V and the sample voltage VSS is divided by 1.1. The output of the comparator 450 is coupled to the set input of the latch 442. A high output on the Q output of the latch 442 indicates that the control circuit 440 outputs the second minimum switching frequency fSW(MIN2), and a high output on the Q' output of the latch 442 indicates that the control circuit 440 outputs the first minimum switching frequency fSW(MIN1). Figure 4 In the example of FIG. 1 , the first minimum switching frequency fSW(MIN1) is higher than the second minimum switching frequency fSW(MIN2).

[0035] The current sensing signal CS is coupled to the input of the comparator 451, which compares the current sensing signal CS with the voltage V41. When the current sensing signal CS is greater than the voltage V41, the comparator 451 outputs a high signal to the input of the AND gate 452. The second input of the AND gate 452 is coupled to the leading edge blanking (LEB) signal. Leading edge blanking is a method for preventing the comparator 451 from responding to the leading edge spike on the current sensing signal CS. The spike is the result of the combination of the drive current from the node DRV and the discharge of the switch node to the ground capacitance. The output of the AND gate is coupled to the reset input of the latch 410.

[0036] Figure 5 It is shown Figure 4 502 . The controller 400 maintains the output voltage VOUT as shown in the graph 500 when the output current IOUT is subjected to changes as shown in the graph 502. In some examples, the change in current is a change in the power required to be output by the power supply. Maintaining the output voltage VOUT is achieved by varying the switching frequency fSW as shown in the graph 504. The controller 400 generates multiple switching frequencies, wherein Figure 4 Four of these switching frequencies are shown. The description herein focuses on two of these switching frequencies, namely the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2). The standby switching frequency fSW(ST) operates when the controller 400 is in standby mode, and the high switching frequency fSW(HI) operates when the load 122 draws high current or power and the current can fluctuate. The standby switching frequency fSW(ST) is between the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2). The first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2) are fixed frequencies built into the controller 400. The first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2) correspond to the power levels PWR(min1) and PWR(min2) delivered to the output by the power supply described above.

[0037] During period T51, the power supply operates in the standby mode, so the controller 400 generates the standby switching frequency fSW(ST). In the standby mode, there is no output current IOUT or the output current IOUT is very small, and this situation lasts for a certain period of time. Figure 1 The resistor R14 is used to maintain the operation of the controller 400.

[0038] During period T52, the impedance of load 122 undergoes several changes, which may be periodic and may be a step function. These changes in impedance cause the output current IOUT and / or output power to undergo increasing and decreasing changes. Figure 5 In the example of FIG. 5 , the output current IOUT is shown to experience periodic load steps during period T52. During the period of high output current IOUT, the controller 400 generates a high switching frequency fSW(HI). During the period between high output currents IOUT, the controller 400 generates a first minimum switching frequency fSW(MIN1). Figure 5 As shown, the first minimum switching frequency fSW(MIN1) occurs after the high switching frequency fSW(HI) for driving the high output current IOUT is generated. During these transitions of the impedance of the load 122, since the first minimum switching frequency fSW(MIN1) is higher than the standby switching frequency or the second minimum switching frequency fSW(MIN2), the output voltage VOUT experiences a relatively small transient response. During the period when the controller 400 outputs the first minimum switching frequency fSW(MIN1), the output voltage VOUT continues to rise.

[0039] At the beginning of period T53, the output current IOUT decreases. Figure 5In the example of , the output current IOUT has dropped to zero. During period T53, the controller 400 outputs a first minimum switching frequency fSW(MIN1) so that if the output current IOUT increases, the controller 400 can return to outputting a high switching frequency fSW(HI). During period T53, the output voltage VOUT rises until it reaches the high voltage VOUT(HI). When the output voltage VOUT reaches the high voltage VOUT(HI), the controller 400 enters period T54, which reduces the switching frequency to the second minimum switching frequency fSW(MIN2). During period T54, the output voltage VOUT drops. When the output voltage VOUT reaches the nominal output voltage VOUT(NOM), the switching frequency returns to the standby switching frequency fSW(ST) during period T55. Low standby power can be applied in standby mode by the controller 400, and the output voltage VOUT can be maintained at the nominal voltage VOUT(NOM). During the period when the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2) are effective, a no-load condition may exist at the output of the power supply 100.

[0040] refer to Figure 1 , Figure 4 and Figure 5 The operation of the controller 400 is described below. The output voltage VOUT is measured by the voltage VS, which is Figure 1 The voltage of the auxiliary winding 112 of the transformer T1 in the power supply 100 is measured. In some examples, the output power is measured, which can be related to the output voltage VOUT. The sampler 418 samples the voltage VS and generates a sampled voltage VSS. The sampled voltage VSS is amplified by the amplifier 436 with the offset of the constant voltage VC and the compensation voltage VCVS. In some examples, the output of the amplifier 436 is proportional to the operating power level of the power supply 100. The constant voltage VC corresponds to the nominal output voltage VOUT (NOM) as the preferred output voltage. In some examples, the compensation voltage VCVS is not included in the amplification of the sampled voltage VSS. The output of the amplifier 436 is a linear voltage related to the sampled voltage VSS. In some examples, the low level output by the amplifier 436 means that the level has reached its lowest linear control level, which can be less than approximately 1.3V. This low level is sometimes referred to as a logic 0 with respect to the reset input of the latch 442.

[0041] If the sampled voltage VSS is less than the sum of the nominal output voltage VOUT(NOM) and the compensation voltage VCVS, the amplifier 436 outputs a logic 1 to the control circuit 440. The logic 1 indicates that the output voltage VOUT has dropped below the nominal output voltage VOUT(NOM), so the control circuit 440 generates a high switching frequency fSW(HI). This is shown during the T52 period in the graph 502, when the output current IOUT increases and the output voltage VOUT drops below the nominal output voltage VOUT(NOM). The amplifier 436 outputs a linear voltage decoded by the control circuit 440 to generate a high switching frequency fSW(HI) that is higher than the first minimum switching frequency fSW(MIN1).

[0042] During the period when the output voltage VOUT exceeds the nominal output voltage VOUT(NOM), the amplifier 436 outputs a low voltage or logic 0, as described above. When the control circuit 440 receives the low voltage from the amplifier 436, the control circuit 440 follows the output of the latch 442 in outputting the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2). A logic 0 is also input to the reset input of the latch 442, so the Q output and Q' output of the latch 442 depend on the logic level of the set input. The set input of the latch 442 is coupled to the output of the comparator 450, which determines whether the output voltage VOUT is higher or lower than the high output voltage VOUT(HI). The comparator 450 compares the constant voltage VC, which represents the nominal output voltage VOUT(NOM), with the sampled voltage VSS / 1.10, which is related to the high output voltage VOUT(HI). The sample voltage VSS may be divided by other values, and 1.10 is an example of design choice. When the voltage VSS / 1.10 is less than the constant voltage VC, the comparator 450 outputs a logic 0, meaning that the output voltage VOUT has not yet reached the high output voltage VOUT(HI), as shown in FIG. Figure 5As shown in the period T53 in . In this state, the comparator 450 outputs a logic 0, so the set input and reset input of the latch 442 are logic 0. In this state, the Q output is a logic 0, and the Q' output is a logic 1, which causes the control circuit 440 to generate a first minimum switching frequency fSW (MIN1). When the voltage VSS / 1.10 exceeds the constant voltage VC or is equal to the constant voltage VC in some cases, the output voltage VOUT has reached the high output voltage VOUT (HI), as shown at the beginning of the period T54. In this state, the comparator 450 outputs a logic 1 to the set input of the latch 442, so the Q output transitions to a logic 1, and the Q' output transitions to a logic 0. This state causes the control circuit 440 to generate a second minimum switching frequency fSW (MIN2). After a predetermined period of generating the second minimum switching frequency fSW (MIN2), the control circuit 450 generates a standby switching frequency fSW (ST). The period of time during which the controller 400 generates the second minimum switching frequency fSW (MIN2) can be determined in different ways. In some examples, the period is related to the time it takes for the output voltage VOUT to relax to the nominal output voltage VOUT(NOM). This period is a function of several variables, including Figure 1 The capacitance of the output capacitor C21, the standby load current, the second minimum switching frequency fSW(MIN2), and the voltage difference between VOUT(HI) and VOUT(NOM). In some embodiments, the standby frequency fSW(ST) is generated when the output voltage VOUT reaches the nominal output voltage VOUT(NOM).

[0043] Figure 6 Is a description Figure 4 600 of an example of the operation of a controller of the present invention. The method described in flowchart 600 is based on the output power of power supply 100. In box 602, the output power of power supply 100 is determined. This determination can be done by analyzing the output of amplifier 436, and the output of amplifier 436 can be determined by measuring the output voltage VOUT. Processing proceeds to decision box 610 to determine whether the output power is greater than a first predetermined power. This first predetermined power indicates that the power supply 100 is operated in a manner to output a high current, as shown in graph 502. If the result of decision box 610 is affirmative, processing proceeds to box 614, in which the power supply 100 is capable of outputting high power. The high power may include a peak value of the set current IP. In response to the power setting, the minimum switching frequency is set to a first minimum switching frequency fSW(MIN1).

[0044] If the output of decision block 610 is negative, processing proceeds to decision block 620, where it is determined whether the output power is less than a second predetermined power. If so, processing proceeds to block 622, where the minimum output power is set to a second power less than the first power. This can be achieved by setting a peak value of current IP. In response to this determination, the minimum switching frequency is set to a second minimum switching frequency fSW(MIN2).

[0045] Figure 7 Is a description Figure 4 Flowchart 700 of another example of the operation of a controller of the present invention. In block 702, an output voltage of a power supply is determined. In block 704, in response to the output voltage being greater than a nominal output voltage and less than a predetermined voltage, a first minimum switching frequency for driving a switch is set. The first minimum switching frequency is fixed. In block 704, in response to the output voltage being equal to or greater than a predetermined voltage, a second minimum switching frequency for driving a switch is set. The first minimum switching frequency is greater than the second minimum switching frequency, and the second minimum switching frequency is fixed.

[0046] In other example controllers, different methods may be implemented to control the first minimum switching frequency fSW(MIN1) and the second minimum switching frequency fSW(MIN2). For example, the first minimum switching frequency fSW(MIN1) may be applied for a set period of time. In this example, the output voltage VOUT may be clamped to prevent it from rising too high. The same may apply to the second minimum switching frequency, which may last for a set time, or until a predetermined output voltage is reached.

[0047] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A method of operating a switching power supply, the power supply having a transformer and a switch, the switch being coupled to a primary side of the transformer, the method comprising: determining an output voltage of the power supply; In response to the output voltage being greater than a nominal output voltage and less than a first voltage, setting a switching frequency of the switch to a first switching frequency for driving the switch; as well as In response to the output voltage being equal to or greater than the first voltage, the switching frequency is set to a second switching frequency for driving the switch, wherein the first switching frequency is greater than the second switching frequency. 2 . The method of claim 1 , wherein setting the switching frequency to the second switching frequency comprises maintaining the switching frequency at the second switching frequency until the output voltage reaches the nominal output voltage. 3 . The method of claim 1 , wherein setting the switching frequency to the second switching frequency comprises maintaining the switching frequency at the second switching frequency for a period of time.

4. The method of claim 1 , further comprising setting the switching frequency to a third switching frequency in response to the output voltage being less than the nominal output voltage, wherein the third switching frequency is higher than the first switching frequency, and wherein the third switching frequency varies in response to a change in the output voltage. 5 . The method of claim 1 , further comprising setting the switching frequency to a standby switching frequency in response to the output voltage being equal to the nominal output voltage, the standby switching frequency being higher than the second switching frequency and lower than the first switching frequency. 6 . The method of claim 1 , further comprising setting the switching frequency to a standby switching frequency in response to the power supply entering a standby mode, the standby switching frequency being higher than the second switching frequency and lower than the first switching frequency. 7 . The method of claim 1 , wherein the output voltage increases in response to the switch being driven at the first switching frequency, and wherein the first switching frequency is fixed. 8 . The method of claim 1 , wherein the output voltage decreases in response to the switch being driven at the second switching frequency, and wherein the second switching frequency is fixed.

9. A controller for controlling a switch of a switching power supply, the power supply having a transformer and the switch coupled to a primary side of the transformer, the controller comprising: a voltage measurement circuit configured to determine an output voltage of the power supply; as well as a frequency controller coupled to the voltage measurement circuit and configured to set a switching frequency to a first switching frequency for driving the switch in response to the output voltage being greater than a nominal output voltage and less than a first voltage, and to set the switching frequency to a second switching frequency for driving the switch in response to the output voltage being equal to or greater than the first voltage, and the first switching frequency being higher than the second switching frequency.

10. The controller of claim 9, comprising a latch circuit coupled to the frequency controller, the latch circuit configured to cause the frequency controller to maintain the switching frequency at the second switching frequency until the output voltage reaches the nominal output voltage.

11. The controller of claim 9, wherein the first switching frequency and the second switching frequency are fixed. 12 . The controller of claim 9 , wherein the frequency controller is configured to set the switching frequency to a third switching frequency higher than the first switching frequency in response to the output voltage being less than the nominal output voltage. 13 . The controller of claim 9 , wherein the frequency controller is configured to set the switching frequency to a standby switching frequency in response to the output voltage being equal to the nominal output voltage, the standby switching frequency being higher than the second switching frequency and lower than the first switching frequency.

14. The controller of claim 9, wherein the frequency controller is configured to set the switching frequency to a standby switching frequency in response to the power supply entering a standby mode, wherein the standby switching frequency is higher than the second switching frequency and lower than the first switching frequency.

15. A power supply comprising: a transformer having a primary side and a secondary side, the secondary side coupled to an output of the power supply; a switch coupled to the primary side of the transformer, wherein the switch controls current flowing through the primary side of the transformer; A controller, the controller comprising: an output coupled to the switch for controlling a state of the switch; a voltage measurement circuit configured to determine an output voltage of the power supply; and a frequency controller coupled to the voltage measurement circuit and configured to set a switching frequency of the switch to a first switching frequency for driving the switch in response to the output voltage being greater than a nominal output voltage and less than a first voltage, and to set the switching frequency to a second switching frequency for driving the switch in response to the output voltage being equal to or greater than the first voltage, and the first switching frequency being higher than the second switching frequency.

16. The power supply of claim 15, further comprising a latch circuit coupled to the frequency controller, the latch circuit configured to cause the frequency controller to maintain the switching frequency at the second switching frequency until the output voltage reaches the nominal output voltage.

17. The power supply of claim 15, wherein the first switching frequency and the second switching frequency are fixed.

18. The power supply of claim 15, wherein the frequency controller is configured to set the switching frequency to a third switching frequency greater than the first switching frequency in response to the output voltage being less than the nominal output voltage.

19. The power supply of claim 17, wherein the frequency controller is configured to set the switching frequency to a standby switching frequency in response to the power supply entering a standby mode, wherein the standby switching frequency is higher than the second switching frequency and lower than the first switching frequency.

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