A memory and a neuromorphic chip

Abstract

The embodiments of the present invention disclose a memory and a neuromorphic chip. The memory includes: a connected non-volatile memory unit and a refresh circuit; wherein the refresh circuit is used to read the stored data in the non-volatile memory unit and write the stored data back to the non-volatile memory unit. When the area of ​​the non-volatile memory unit is fixed, the above-mentioned memory increases the storage time of the data stored in the non-volatile memory unit, achieving the technical effect of flexibly adjusting the data storage time.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of chip technology, and in particular to a memory and a neuromorphic chip. Background Art

[0002] According to the data storage time, memory can be divided into volatile memory and non-volatile memory. Among them, the data in volatile memory cannot be retained for a long time after power failure, while the data in non-volatile memory can be retained for a long time after power failure. However, when non-volatile memory is miniaturized to tens of nanometers or even smaller, its non-volatility is greatly challenged, and non-volatile memory often needs to compromise between storage density and data retention time. Summary of the invention

[0003] The embodiments of the present invention provide a memory and a neuromorphic chip, which can flexibly adjust the data storage duration according to actual application conditions and realize long-term data preservation by means of circuit compensation.

[0004] In a first aspect, an embodiment of the present invention further provides a memory, comprising: a connected non-volatile storage unit and a refresh circuit;

[0005] The refresh circuit is used to read the storage data in the non-volatile storage unit and write the storage data back to the non-volatile storage unit.

[0006] Furthermore, the memory mentioned above further includes: a control unit;

[0007] The control unit is connected to the refresh circuit and is used to control the working state of the refresh circuit;

[0008] Wherein, the working status at least includes a refresh frequency.

[0009] Furthermore, the memory further comprises: a timer, wherein the timer is connected to the control unit and the refresh circuit respectively;

[0010] The control unit is further used to control the timing cycle of the timer to trigger the refresh circuit to read the storage data in the non-volatile storage unit at a refresh frequency matching the timing cycle, and write the storage data back to the non-volatile storage unit.

[0011] Furthermore, the control unit is also used to control the refresh circuit to read the storage data in the target storage area in the non-volatile storage unit, and write the storage data back to the target storage area in the non-volatile storage unit.

[0012] Furthermore, the non-volatile storage unit includes a non-volatile memory array and a preset type controller; wherein the preset type controller is used to provide an interface of a preset protocol type.

[0013] Furthermore, the preset protocol type includes at least one of the following: a static random access memory interface protocol and an enhanced dynamic random access memory interface protocol.

[0014] Furthermore, the refresh frequency of the refresh circuit is at the minute level or hour level.

[0015] In a second aspect, an embodiment of the present invention further provides a neuromorphic chip, comprising: at least one memory as described in any embodiment of the present invention.

[0016] Furthermore, when the number of the memories is one, the memory is connected to each neuron computing core in the chip in the form of a bus connection.

[0017] Furthermore, when there are multiple memories, the memories are connected to multiple neuron computing cores in the chip in a distributed manner.

[0018] Furthermore, one of the memories is embedded and distributed in one or more designated neuron computing core areas.

[0019] The memory provided by the embodiment of the present invention includes a connected non-volatile memory unit and a refresh circuit. The refresh circuit reads the storage data in the non-volatile memory unit and writes the storage data back to the non-volatile memory unit. When the area of ​​the non-volatile memory unit is fixed, the storage time of the data stored in the non-volatile memory unit is increased, thereby achieving the technical effect of flexibly adjusting the data storage time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of a memory in the first embodiment of the present invention;

[0021] Figure 2 It is a schematic diagram of the structure of a memory in the first embodiment of the present invention;

[0022] Figure 3 It is a structural schematic diagram of a non-volatile storage unit in a memory in Embodiment 1 of the present invention;

[0023] Figure 4 is a schematic diagram of the structure of a neuromorphic chip in Embodiment 2 of the present invention;

[0024] Figure 5 is a schematic diagram of the structure of a neuromorphic chip in Embodiment 2 of the present invention;

[0025] Figure 6 is a schematic diagram of the structure of a neuromorphic chip in Embodiment 2 of the present invention;

[0026] Figure 7 Schematic diagram of the structure of a neuromorphic chip in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0028] Embodiment 1

[0029] Figure 1 Schematic diagram of a memory structure in the first embodiment of the present invention, which can be applied to any device, such as a neuromorphic chip, a traditional chip, etc. Figure 1 As shown, the memory 10 provided in this embodiment includes: a connected non-volatile memory unit 100 and a refresh circuit 200. The refresh circuit 200 is used to read the storage data in the non-volatile memory unit 100 and write the storage data back to the non-volatile memory unit 100.

[0030] The non-volatile memory unit 100 may include, but is not limited to, one or more of FLASH flash memory, phase change memory, ferroelectric memory FRAM, resistive random access memory RRAM, magnetic memory MRAM, spin random access memory STT-RAM and optical memory.

[0031] The refresh circuit 200 is used to refresh the storage data in the non-volatile storage unit 100, read the storage data in the non-volatile storage unit 100, and write the read storage data back to the non-volatile storage unit 100 to extend the storage time of the non-volatile storage unit 100 storing the storage data.

[0032] The memory of the disclosed embodiment reads the stored data in the non-volatile storage unit through a refresh circuit, and writes the stored data back to the non-volatile storage unit, and realizes long-term data preservation by means of circuit compensation, and can flexibly adjust the data storage duration according to the actual application situation, thereby improving the flexibility of memory use. The memory of the disclosed embodiment can ensure that it still has good non-volatility when it is miniaturized to tens of nanometers or even smaller, and can be applied to any scenario, and the disclosed memory can be used to store any type of data.

[0033] For example, in a neural network computing scenario, the non-volatile storage unit 100 can store relatively stable data of the neuron computing core, such as one or more of the connection weights, network connection methods, neuron activation functions, and initialization information of the neuron computing core, and a refresh circuit can be used to ensure that relatively stable data is stored in the memory for a long time. Optionally, in a neural network computing scenario, the memory of an embodiment of the present disclosure can also be used to store relatively dynamic data, such as input data to be processed. The memory can also store relatively stable data and dynamic data at the same time. For example, part of the storage space can be used to store relatively stable data, and the rest of the storage space can be used to store dynamic data. The refresh circuit is used to read relatively stable stored data and write back the read stored data. The present disclosure does not limit this.

[0034] Optionally, the refresh frequency of the refresh circuit 200 is at the minute level or the hour level, that is, the data stored in the non-volatile storage unit 100 is refreshed once every few minutes or every few hours.

[0035] Taking the non-volatile memory cell 100 as MRAM as an example, the data storage duration of MRAM is related to its material and area. Assuming that the data storage duration of MRAM is 10 minutes, the refresh frequency of the refresh circuit 200 can be set to once every 10 minutes, and the refresh circuit 200 performs the following operations once every 10 minutes: read the storage data in the non-volatile memory cell 100, and write the read storage data back to the non-volatile memory cell 100.

[0036] Optionally, the refresh frequency of the refresh circuit 200 may also be set to a second level or a day level, depending on the data storage duration of the non-volatile storage unit 100 , which is not specifically limited in this embodiment.

[0037] Compared with a DRAM (Dynamic Random Access Memory) with a refresh frequency of milliseconds, the memory provided in this embodiment consumes lower power due to data refresh.

[0038] The memory provided by the embodiment of the present invention includes a connected non-volatile memory unit and a refresh circuit. The refresh circuit reads the storage data in the non-volatile memory unit and writes the storage data back to the non-volatile memory unit. When the area of ​​the non-volatile memory unit is fixed, the storage time of the data stored in the non-volatile memory unit is effectively increased, thereby achieving the technical effect of flexibly adjusting the data storage time.

[0039] In practical applications, when the area of ​​a non-volatile memory cell is fixed, the storage duration of the non-volatile memory cell is also fixed, such as a few minutes or hours. By refreshing the data in the non-volatile memory cell through a refresh circuit, the storage duration of the data stored in the non-volatile memory cell is flexibly adjusted, so that a longer storage effect can be achieved with a smaller storage area, thereby improving the "non-volatile" effect of the memory. At the same time, since the storage data of the non-volatile memory cell is refreshed by a refresh circuit, it is not stored in a fixed and long-term manner, and to a certain extent, it can also be "volatile", that is, the memory provided in this embodiment can achieve a "volatile" effect based on a "non-volatile unit" and a refresh circuit, and can also achieve a "non-volatile" effect, and the memory has a high degree of flexibility in use.

[0040] For example, the non-volatile storage unit 100 of the memory can store data for 10 minutes. If the storage time required by the memory is longer than 10 minutes, a refresh operation of reading the stored data in the non-volatile storage unit 100 and writing the stored data back to the non-volatile storage unit 100 can be performed through the refresh circuit. Optionally, the refresh circuit can perform at least one refresh operation according to the refresh frequency. For example, it can be refreshed every 8 minutes to ensure that the memory does not lose the stored data.

[0041] In some optional embodiments, if the memory needs to store data for a period of less than or equal to 10 minutes, the refresh frequency of the refresh circuit is 0, and the memory can store data for 10 minutes, thereby achieving a "volatile" effect.

[0042] In this way, the memory of the embodiment of the present disclosure can be flexibly applied to various storage scenarios. Among them, the area size and storage duration of the non-volatile storage unit can be flexibly set according to the area constraints of the applicable scenario, customization requirements, cost considerations and other factors, and the present disclosure does not limit this.

[0043] Further, in an optional embodiment, as Figure 2 As shown, the memory 10 further includes: a control unit 300, which is connected to the refresh circuit 200 and is used to control the working state of the refresh circuit 200, wherein the working state at least includes a refresh frequency.

[0044] In this embodiment, the refresh frequency of the refresh circuit 200 can be controlled by the control unit 300. Optionally, the control unit 300 is implemented in the form of software and / or hardware. The refresh frequency can be externally determined and sent to the control unit, or it can be determined by the control unit based on the storage duration of the non-volatile storage unit and the duration to be stored. For example, when the duration to be stored is less than the storage duration of the non-volatile storage unit, the refresh frequency can be determined to be 0. When the duration to be stored is greater than or equal to the storage duration of the non-volatile storage unit, the refresh frequency can be determined based on the storage duration of the non-volatile storage unit. For example, if the storage duration of the non-volatile storage unit is 1 hour, the refresh frequency can be refreshed every 55 minutes to ensure that the data can be stored for a long time. The present disclosure does not limit this.

[0045] When the refresh frequency of the control refresh circuit 200 is zero, the refresh circuit 200 stops working, that is, the storage data in the non-volatile memory cell 100 is not updated. When the refresh frequency of the control refresh circuit 200 is non-zero, the refresh circuit 200 starts working and updates the storage data in the non-volatile memory cell 100 according to the refresh frequency.

[0046] In some optional application scenarios, for example, when the chip where the memory is located is used to process a simple neural network, when the amount of weight data is small or the weight is updated frequently, the refresh frequency of the refresh circuit 200 can be set to zero through the control unit 300, and the refresh circuit stops working. When the weight needs to be updated, the updated weight is read from the off-chip DDRSDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) through the read circuit in the chip and written into the non-volatile storage unit 100.

[0047] Optionally, the working status may further include a refresh count, which may be determined by an external system and sent to the control circuit, or may be determined by the control circuit based on the duration to be stored and the refresh frequency, and the present disclosure does not impose any restrictions on this.

[0048] Further, such as Figure 2 As shown, the memory 100 also includes: a timer 400, which is respectively connected to the control unit 300 and the refresh circuit 200; correspondingly, the control unit 300 is also used to control the timing cycle of the timer 400 to trigger the refresh circuit 200 to read the storage data in the non-volatile storage unit 100 at a refresh frequency matching the timing cycle, and write the storage data back to the non-volatile storage unit 100.

[0049] The control unit 300 can adjust the timing cycle of the timer 400 to adjust the refresh frequency of the refresh circuit 200. For example, when the control unit 300 sets the timing cycle of the timer 400 to 2 minutes, the refresh frequency of the refresh circuit 200 is refreshed every 2 minutes.

[0050] Optionally, each time the timer 400 reaches a set timing cycle, the timer 400 sends a refresh trigger signal to the refresh circuit 200 . After receiving the refresh trigger signal, the refresh circuit 200 executes an operation of updating the storage data in the non-volatile storage unit 100 .

[0051] In an optional implementation, the control unit 300 is further configured to control the refresh circuit 200 to read the storage data in the target storage area in the non-volatile storage unit 100 , and write the storage data back to the target storage area in the non-volatile storage unit 100 .

[0052] The control instruction sent by the control unit 300 to the refresh circuit 200 may include an addressing address, so that the refresh circuit 200 reads the storage data in the non-volatile storage unit 100 according to the addressing address, that is, reads the storage data in the storage area corresponding to the addressing address in the non-volatile storage unit 100, and writes the read storage data back to the corresponding storage area in the non-volatile storage unit 100. The addressing address in the control instruction sent by the control unit 300 to the refresh circuit 200 can be set dynamically.

[0053] In the above embodiment, according to the control of the control unit, the refresh circuit can select part of the stored data in the non-volatile storage unit for updating to increase the storage time of this part of the stored data. For data that does not need to be stored for a long time, no update processing is performed, which has high flexibility and reduces the refresh power consumption to a certain extent.

[0054] In an optional embodiment, if Figure 3 As shown, the non-volatile storage unit 100 includes a non-volatile memory array 101 and a preset type controller 102; wherein the preset type controller 102 is used to provide an interface of a preset protocol type.

[0055] Furthermore, the preset protocol type includes at least one of the following: a static random access memory (SRAM) interface protocol and an enhanced dynamic random access memory (EDRAM) interface protocol.

[0056] In this embodiment, the external interface of the non-volatile memory unit 100 is realized by including a preset type controller 102, which is used to achieve docking with other devices in the chip.

[0057] For example, the preset type controller 102 included in the nonvolatile memory unit 100 is a SRAM-like controller, and the SRAM-like controller provides an external interface of the nonvolatile memory unit 100 , that is, the external interface of the nonvolatile memory unit 100 is a SRAM interface.

[0058] For another example, the preset type controller 102 included in the nonvolatile memory unit 100 is an EDRAM-like controller, and the EDRAM-like controller provides an external interface of the nonvolatile memory unit 100 , that is, the external interface of the nonvolatile memory unit 100 is an EDRAM interface.

[0059] Given that the interface provided by the preset type controller 102 is usually a universal interface, and the protocol of the external interface of the non-volatile storage unit 100 is a universal interface protocol, such as an SRAM interface protocol or an EDRAM interface protocol, developers do not need to perform special processing on the interface of the non-volatile storage unit 100 when developing chips, thereby reducing the complexity of developers' work when developing functional chips.

[0060] Embodiment 2

[0061] Figure 4 Schematic diagram of the structure of a neuromorphic chip in the second embodiment of the present invention, which is suitable for neural network calculation. Figure 4 As shown, the neuromorphic chip 1 provided in this embodiment includes: at least one memory 10 described in any embodiment of the present invention (shown as one memory 10 in the figure).

[0062] It should be noted that Figure 4 The neuromorphic chip shown is only an example of showing that the neuromorphic chip includes a memory 10 and a neuron computing core 50 , and does not specifically limit the structure of the neuromorphic chip.

[0063] Optionally, a neuromorphic chip 1 may include one or more memories 10. When a neuromorphic chip 1 includes only one memory 10 of an embodiment of the present disclosure, the storage data in the memory 10 may be used in common by multiple neuron computing cores; when a neuromorphic chip 1 includes multiple memories 10, the storage data in each memory 10 may be used individually by one neuron computing core, for example, a memory 10 corresponds to a neuron computing core one-to-one, and one memory 10 may also be used in common by multiple neuron computing cores, or the storage data of some memories among multiple memories 10 may be used by one neuron computing core.

[0064] In an optional embodiment, if Figure 5 As shown, when the number of memories 10 included in the neuromorphic chip 1 is one, the memory 10 is connected to each neuron computing core 50 in the neuromorphic chip 1 in the form of a bus connection.

[0065] In the above embodiment, there is only one memory 10, so its stored data is global to the chip and is shared by all neuron computing cores 50 (neuron multi-cores) in the neuromorphic chip 1. Furthermore, the data required by each neuron computing core does not need to be stored repeatedly, thereby reducing the data storage area in the neuromorphic chip and also reducing the size of the neuromorphic chip. In addition, when the storage area of ​​the memory 10 is small, the memory interface will also occupy a considerable proportion of the area. Reducing the number of memories 10 also reduces the number of memory interfaces, relatively increasing the proportion of the data storage area area to the total memory area, thereby increasing the effective use area of ​​the memory in the neuromorphic chip.

[0066] Further, such as Figure 5 As shown, the neuromorphic chip 1 may also include a volatile memory 60, which may also be connected to each neuron computing core 50 in the neuromorphic chip 1 in the form of a bus connection. The volatile memory 60 and the memory 10 are used to store data of different operation stages of the neuron computing core.

[0067] It can be understood that under multiple parallel neural computing cores, the calculation process will generate intermediate data with large data volume and frequent changes but no need to be saved for a long time, as well as key data with infrequent changes, which need to be saved for a long time and saved during power failure.

[0068] Each neuron computing core requires both volatile memory 60 as a memory buffer to calculate intermediate variables, and memory 10 as a hard disk to store data that needs to be preserved for a long time, such as neuron connection patterns and connection weights, to ensure that the chip can save important network model data after power failure, and can quickly load data after power-on.

[0069] Optionally, the memory 10 is used to store relatively stable data of the neuron computing core, and the volatile memory 60 is used to store relatively dynamic data of the neuron computing core. Relatively stable data can be defined as data that needs to be reused, such as one or more of connection weights, network connection methods, neuron activation functions, and initialization information; relatively dynamic data can be defined as data that does not need to be reused, such as data input from an external data source (host computer or external read-only memory) or intermediate values ​​of network calculations.

[0070] In an optional embodiment, the memory 10 included in the neuromorphic chip 1 can also be used to store relatively stable and relatively dynamic data. For example, when there is one memory 10, part of the storage space of the memory can be used to store relatively stable data, and the remaining storage space can be used to store relatively dynamic data. When there are multiple memories 10, part of the memory can be used to store relatively stable data, and the remaining memory can be used to store relatively dynamic data.

[0071] In an optional embodiment, if Figure 6 As shown, when the number of memories 10 included in the neuromorphic chip 1 is multiple, the memories 10 are connected in a distributed corresponding manner to the multiple neuron computing cores 50 in the neuromorphic chip 1. It can be understood that the neuron computing core 50 includes a computing unit 51 for data processing.

[0072] In this embodiment, the memory 10 is introduced into the neuromorphic chip 1 in a distributed manner, and can be used as a functional unit of the neuron computing core 50 to realize the distributed embedded distribution of the memory 10. The embedded distributed memory 10 is connected to the multiple neuron computing cores 50 of the neuromorphic chip architecture in a distributed corresponding manner to form an independent corresponding relationship. That is, it is ensured that each distributed memory 10 is connected to only one or a limited number of neuron computing cores 50.

[0073] Correspondingly, for a neuron computing core with a large amount of computation, data may also be correspondingly stored in one or more distributed memories 10. Accordingly, each neuron computing core is correspondingly connected to one or a limited number of distributed memories 10.

[0074] In the above embodiment, the memory 10 can be of small capacity and built into the neural computing core as an independent non-volatile memory, so that each (or a limited number of) neural computing cores contains both independent volatile memory and independent non-volatile memory, which can effectively alleviate the limitation of data communication bandwidth and improve the stability, reliability and processing efficiency of the system.

[0075] In an optional embodiment, if Figure 7 In the neuromorphic chip shown, a memory 10 is embedded and distributed in one or more designated neuron computing cores 50 areas. Figure 7 , the situations where a memory 10 is embedded and distributed in one, two, three and four designated multiple neuron computing cores 50 areas are shown by way of example.

[0076] In the neuromorphic chip architecture provided in this embodiment, the memory 10 can be embedded and distributed in the chip architecture in the form of multiple neuron computing cores in the chip architecture, with each memory 10 corresponding to one or multiple nearby designated neuron computing cores at the same time. That is, in a system with large-scale parallel computing or functional cores, each embedded and distributed memory 10 is shared by a single or several neuron computing cores.

[0077] There is an independent data channel between each memory 10 and the neuron computing core connected thereto.

[0078] In this embodiment, the memory 10 is introduced into the neuromorphic chip in a distributed manner as a functional unit of the internal neuronal computing core, so that each neuronal computing core has an independent data channel with the corresponding memory 10, thereby solving the data communication bottleneck problem caused by frequent weight updates during online learning.

[0079] Further, such as Figure 7 As shown, the chip architecture further includes a volatile memory 60 corresponding to each of the neuron computing cores, wherein the volatile memory 60 and the memory 10 are used to store data of different operation stages of the neuron computing core.

[0080] Each neuron computing core (or several neuron computing cores) uses a single memory 10 to store different data for the operation of the single neuron computing core (or several neuron computing cores). At the same time, each neuron computing core also needs to include a volatile memory 60, including but not limited to a static random access memory, registers, etc., to cooperate with the memory 10.

[0081] Optionally, the volatile memory 60 is used to store one or more of the computation cache of the neuron computing core and the current neuron state. In order to reasonably distribute data, for the internal volatile memory 60, the neuron computing core will store its computation cache, the current neuron state (membrane potential) and other intermediate variables generated during operation, which are characterized by large data volume, frequent data changes but no need to be stored for a long time.

[0082] The above neuromorphic chip includes one or more memories including a non-volatile storage unit and a refresh circuit provided by any embodiment of the present invention, and has effective effects corresponding to the memory. For technical details not described in detail in this embodiment, please refer to the above embodiments.

[0083] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A memory, characterized in that: include: A connected non-volatile storage unit, a refresh circuit and a control unit; The refresh circuit is used to read the storage data in the non-volatile storage unit and write the storage data back to the non-volatile storage unit to adjust the storage time of the non-volatile storage unit storing the storage data; the storage data is relatively stable data, and the relatively stable data represents data that needs to be reused; The control unit is connected to the refresh circuit and is used to control the working state of the refresh circuit; the working state includes a refresh frequency and a refresh number, the refresh frequency is determined based on the storage time of the non-volatile storage unit and the time to be stored, the storage time is related to the material and area of ​​the non-volatile storage unit, and the refresh number is determined based on the time to be stored and the refresh frequency.

2. The memory according to claim 1, characterized in that: Also includes: A timer, wherein the timer is connected to the control unit and the refresh circuit respectively; The control unit is further used to control the timing cycle of the timer to trigger the refresh circuit to read the storage data in the non-volatile storage unit at a refresh frequency matching the timing cycle, and write the storage data back to the non-volatile storage unit.

3. The memory according to claim 1, characterized in that: The control unit is further used to control the refresh circuit to read the storage data in the target storage area in the non-volatile storage unit, and write the storage data back to the target storage area in the non-volatile storage unit.

4. The memory according to claim 1, characterized in that: The non-volatile storage unit includes a non-volatile memory array and a preset type controller; wherein the preset type controller is used to provide an interface of a preset protocol type.

5. The memory according to claim 4, characterized in that: The preset protocol type includes at least one of the following: a static random access memory interface protocol and an enhanced dynamic random access memory interface protocol.

6. The memory according to any one of claims 1 to 5, characterized in that: The refresh frequency of the refresh circuit is at the minute level or hour level.

7. A neuromorphic chip, characterized in that: include: At least one memory as claimed in any one of claims 1 to 6.

8. The chip according to claim 7, characterized in that: When the number of the memory is one, the memory is connected to each neuron computing core in the chip in the form of a bus connection.

9. The chip according to claim 7, characterized in that: When there are multiple memories, the memories are connected to multiple neuron computing cores in the chip in a distributed corresponding manner.

10. The chip according to claim 9, characterized in that: The memory is embedded and distributed in one or more designated neuron computing core areas.

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