An acceleration card and a server

Abstract

The embodiment of the present invention discloses an acceleration card and a server, which relate to the field of computer technology. It includes a printed circuit board, the edge of the printed circuit board has a gold finger, a deep computing processing chip installation part and a power supply module are provided on the printed circuit board, the deep computing processing chip installation part is connected to the gold finger through a PCIE bus, the power supply module is electrically connected to the deep computing processing chip installation part, and the gold finger supports the PCIE bus and interface standards. It is beneficial to improve the performance of the acceleration card and the device having the acceleration card. The present invention is suitable for the development, OEM processing and hardware acceleration scenarios of electronic devices or equipment such as acceleration cards, computers, industrial computers and servers.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to an acceleration card and a server. Background Art

[0002] An acceleration card is a printed circuit board with integrated circuits (commonly known as a PCB board), which is a processor product specifically used to accelerate the execution of physical simulation algorithms, and is also called a physics processing unit. When it is manufactured, it has a socket (usually a gold finger), which can be inserted into the slot of the main circuit board (motherboard, mainboard) of a computer to accelerate and control the operation of the hardware. After installing the driver program, the corresponding hardware functions can be realized.

[0003] With the high requirements for hardware performance in scenarios, such as in game scenarios, large drawing scenarios, etc., the acceleration cards that have emerged are affected by the signal interface in terms of the signal transmission rate between the motherboard and other circuits or electronic devices, and are also limited by the computing power of the chips currently used in the acceleration cards, which affects the performance of the acceleration cards and the devices with such acceleration cards. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an acceleration card and a server, which at least solve the above-mentioned partial problems and are beneficial to improving the performance of the acceleration card and the devices with such acceleration card.

[0005] To achieve the above invention purpose, the following technical solutions are adopted:

[0006] In a first aspect, the acceleration card provided by an embodiment of the present invention includes a printed circuit board, the edge of the printed circuit board has a gold finger, a deep compute unit installation part and a power supply module are provided on the printed circuit board, the deep compute unit installation part is connected to the gold finger through a PCIE bus, the power supply module is electrically connected to the deep compute unit installation part, and the gold finger supports the PCIE bus and the interface standard.

[0007] Optionally, the gold finger integrates power supply, PCIE signal, CLK signal and SMBUS signal contacts.

[0008] Optionally, the power supply module includes a first power supply unit. The first power supply unit includes a plurality of serial voltage identification power supply domains. The plurality of serial voltage identification power supply domains are divided into two groups, each group having a serial voltage identification interface. The first group of serial voltage identification power supply domains is connected to a first serial voltage identification voltage regulation chip through the serial voltage identification interface, and the second group of serial voltage identification power supply domains is connected to a second serial voltage identification voltage regulation chip through the serial voltage identification interface. The first serial voltage identification voltage regulation chip is used to control the first group of serial voltage identification power supply domains to supply power to the depth calculation processing chip mount, and the second serial voltage identification voltage regulation chip is used to control the second group of serial voltage identification power supply domains to supply power to the depth calculation processing chip mount.

[0009] Optionally, the first group of serial voltage identification power supply domains and the second serial voltage identification power supply domains each include two serial voltage identification power supply sources, and the two serial voltage identification power supply sources share a serial voltage identification interface.

[0010] Optionally, the power supply module further includes a second power supply unit. The second power supply unit includes a plurality of external PCIE power supply connectors provided on a printed circuit board. The external PCIE power supply connectors are electrically connected to the depth calculation processing chip mounting part through a voltage regulation chip set and are used to supply power to the depth calculation processing chip mounting part.

[0011] Optionally, the voltage regulation chip set includes a serial voltage identification voltage regulation chip, a first DC-DC power supply, and a second DC-DC power supply, and the supply current of the first DC-DC power supply is greater than that of the second DC-DC power supply.

[0012] Optionally, an external power supply detection circuit is further provided on the printed circuit board. An alarm is connected to the output end of the external power supply detection circuit. The external power supply detection circuit is connected to the plurality of external PCIE power supply connectors and is used to detect whether there is input power supply to the plurality of external PCIE power supply connectors.

[0013] Optionally, a group of I2C Master interfaces are provided corresponding to the depth calculation processing chip on the depth calculation processing chip mounting part and are used to enable the depth calculation processing chip to control external I2C devices on the printed circuit board. The I2C Master interfaces are connected to the power management bus interfaces of the serial voltage identification voltage regulation chip set.

[0014] Optionally, a CPLD / FPGA chip, a temperature sensor, and an EEPROM are further provided on the printed circuit board. The CPLD / FPGA chip is respectively connected to the gold finger, the temperature sensor, the EEPROM, and the voltage regulation chip set.

[0015] Optionally, the depth calculation processing chip mounting part is respectively connected to a temperature sensor, an EEPROM, and a voltage adjustment chip set. A multiplexing chip is also provided on the printed circuit board. The CPLD / FPGA and the depth calculation processing chip are respectively connected to the multiplexing chip. The multiplexing chip is used to switch signal channels between the CPLD / FPGA and the depth calculation processing chip.

[0016] In a second aspect, an embodiment of the present invention provides a server, including a chassis. A main board is provided inside the chassis. An acceleration card slot is provided on the main board. Any acceleration card of the first aspect is provided in the acceleration card slot. The acceleration card is inserted into the acceleration card slot through the gold finger. A depth calculation processing chip is installed in the depth calculation processing chip mounting part.

[0017] The acceleration card and the server provided by the embodiments of the present invention improve their structures themselves. The depth calculation processing chip mounting part on the printed circuit board is connected to the gold finger through a PCIE bus, and the gold finger supports the PCIE bus and interface standard. Since the bus or interface of the PCIE communication standard can achieve high-speed signal transmission, it is convenient to improve the performance of the acceleration card. In addition, when the acceleration card is inserted into the main board through the gold finger, it is convenient to achieve high-speed signal transmission with the main board and the electronic devices thereon, thereby improving the performance of the device with the acceleration card to a certain extent. Furthermore, since the depth calculation processing chip mounting part provided on the PCB board of the acceleration card is used to install the depth calculation processing chip, the computing power of the acceleration card can be improved, thereby also improving the performance of the device with the acceleration card, such as the main board, server, etc. to a certain extent. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a schematic block diagram of the structure of an embodiment of the acceleration card of the present invention;

[0020] Figure 2 It is a schematic block diagram of the structure of another embodiment of the acceleration card in the present invention;

[0021] Figure 3 It is a schematic block diagram of the structure of an embodiment of the acceleration card with a first power supply unit in the present invention;

[0022] Figure 4Structural schematic block diagram of an acceleration card with a second power supply unit according to an embodiment of the present invention;

[0023] Figure 5 Structural schematic block diagram of another embodiment of the acceleration card according to the present invention;

[0024] Figure 6 Structural schematic block diagram of yet another embodiment of the acceleration card according to the present invention;

[0025] Figure 7 Circuit schematic block diagram of the CPLD / FPGA of the acceleration card according to the present invention for controlling the power-on and power-off of the DCU;

[0026] Figure 8 Structural schematic block diagram of an embodiment of the acceleration card showing the DCU chip according to the present invention. Detailed implementation manners

[0027] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] It should be clear that, in order to more clearly illustrate the present invention, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can still be implemented without some of these details. Additionally, in order to highlight the inventive concept of the present invention, some methods, means, components, and their applications well-known to those skilled in the art are not described in detail. However, this does not affect the implementation of the present invention. The embodiments described herein are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0029] Figure 1 Structural block diagram of an embodiment of the acceleration card according to the present invention; see Figure 1 As shown, the acceleration card provided by the embodiment of the present invention, which is usually also called a physical acceleration card, is a processor product specifically used to accelerate the execution of physical simulation algorithms, and is also called a Physics Processing Unit. It is applicable to personal computers, industrial control computers, and server electronic devices to improve the computing and processing capabilities of hardware, especially CPUs, GPUs, etc.

[0030] The acceleration card includes a printed circuit board (PCB for short). The edge of the printed circuit board has connecting fingers. On the printed circuit board, there are installation parts for deep compute units (customarily abbreviated as DCUs) and a power supply module. The installation parts for deep compute units are connected to the connecting fingers through a PCIE (PCI-Express, a high-speed serial computer expansion bus standard) bus. The power supply module is electrically connected to the installation parts for deep compute units. The connecting fingers support the PCIE bus and interface standards.

[0031] The acceleration card is sometimes also referred to as a board card. It supports the PCIE 4.0 interface and uses standard PCIE connecting fingers as the plug-in cores. Since the installation parts for deep compute units are connected to the connecting fingers through the PCIE bus, when a DCU chip is installed in the installation parts for deep compute units, the SMBUS signal of the DCU's system bus is connected to the connecting fingers of the acceleration card. When the acceleration card is inserted into the main board, it is convenient for the main board system to access and debug the DCU chip through the SMBUS.

[0032] In one embodiment, the DCU chip is a Haiguang DCU chip, which is a high-performance computing chip with rich interfaces. The main interfaces include PCIE, JTAG, SMBUS, I2C, SPI, GPIO, and SVID, etc.

[0033] In this embodiment, the board card, that is, the aforementioned acceleration card, can reserve the installation position for the deep compute unit, that is, the installation part, when leaving the factory. At the specific installation position, there can be slots that cooperate with the connecting fingers, or welding points for installing the deep compute unit can be provided at the installation position, so as to facilitate OEMs, server manufacturers, or users to select and match by themselves.

[0034] Of course, the acceleration card can also be installed with a deep compute unit when leaving the factory.

[0035] In some embodiments, the connecting fingers integrate power supply, PCIE signal, CLK signal, and SMBUS signal contacts. In this way, since the connecting fingers of the acceleration card integrate various types of contacts, or interfaces, it is convenient to improve the ability of the acceleration card to adapt to different devices.

[0036] The acceleration card provided by the embodiment of the present invention improves its own structure, connects the deep computing processing chip mounting part on the printed circuit board to the gold finger through the PCIE bus, and the gold finger supports the PCIE bus and interface standard. Since the bus or interface of the PCIE communication standard can achieve high-speed signal transmission, it is convenient to improve the performance of the acceleration card. In addition, when the acceleration card is inserted into the motherboard through the gold finger, it is convenient to achieve high-speed signal transmission with the motherboard and the electronic devices thereon, thereby improving the performance of the device with the acceleration card to a certain extent. Moreover, since the deep computing processing chip mounting part provided on the PCB board of the acceleration card is used to mount the deep computing processing chip, the computing power of the acceleration card can be improved, thereby also improving the performance of the device with the acceleration card, such as the motherboard, server, etc. to a certain extent.

[0037] Among them, referring to Figure 2 as shown, the power supply module includes a first power supply unit. The first power supply unit includes multiple serial voltage identification power domains (SVID (Serial Voltage Identification) Power Domain). The multiple serial voltage identification power domains are divided into two groups, and each group has a serial voltage identification interface. The first group of serial voltage identification power domains is connected to the first serial voltage identification voltage regulator chip SVID VR (Voltage Regulator) 1 through one of the serial voltage identification interfaces (SVID1 interface). The second group of serial voltage identification power domains is connected to the second serial voltage identification voltage regulator chip SVID VR2 through the serial voltage identification interface, that is Figure 2 the SVID2 interface in, and the first serial voltage identification voltage regulator chip is used to control the first group of serial voltage identification power domains to supply power to the deep computing processing chip mounting base, and the second serial voltage identification voltage regulator chip is used to control the second group of serial voltage identification power domains to supply power to the deep computing processing chip mounting base.

[0038] Continuing to refer to Figure 2 as shown, in some embodiments, the first group of serial voltage identification power domains and the second serial voltage identification power domains each include two serial voltage identification power supplies, and the two serial voltage identification power supplies share a serial voltage identification interface. For example, in Figure 2 the first group of serial voltage identification power domains includes two power supplies, namely SVIDPOWER1 and SVID POWER2, and the second serial voltage identification power domains includes two power supplies, namely SVID POWER3 and SVID POWER4.

[0039] It can be understood that since the power consumption of the DCU is generally high, but the power supply capacity of the PCIE gold finger is low, generally only 75W, in order to ensure the reliable operation of the DCU, in some embodiments, an external power supply unit is additionally provided. Therefore, in some embodiments, the power supply module further includes a second power supply unit. Refer to Figure 3 As shown, the second power supply unit includes a plurality of external PCIE power supply connectors (External Connector) provided on the printed circuit board. The voltage of the power supply connector is 12 volts (V). The external PCIE power supply connector is electrically connected to the depth calculation processing chip mounting portion through a voltage adjustment chipset for supplying power to the depth calculation processing chip mounting portion.

[0040] It can be understood that one of the substantially powered objects of the first power supply unit and the second power supply unit is essentially the chip installed in the depth calculation processing chip mounting portion. When a DCU is installed on the PCB board of the acceleration card, the second power supply unit realizes the purpose of supplying power to the DCU because it is electrically connected to the DCU mounting portion.

[0041] Continue to refer to Figure 3 As shown, the voltage adjustment chipset includes a serial voltage identification voltage adjustment chip, a first DC-DC power supply, and a second DC-DC power supply. The supply current of the first DC-DC power supply is greater than that of the second DC-DC power supply.

[0042] Usually, 1 to 4 ATX (Advanced Technology Extended) standard external PCIE power supply connectors are designed on a single board card, which are used to cooperate with an external power supply device with a gold finger to supply power to the DCU through a voltage regulator (VR). The circuit connection is as Figure 3 shown. Among them, VRx is Figure 2 the SVID VR1 and VR2 in , VRy is a non-SVID high-current DC-DC power supply (i.e., the first DC-DC power supply) to supply power to the DCU, VRm is a non-SVID low-current DC-DC power supply (i.e., the second DC-DC power supply) to supply power to the DCU, and the external power supply voltage is 12V. In some other embodiments, a 3.3V_gold finger slot can also be set to directly supply power to the DCU chip.

[0043] The acceleration card provided by the embodiment of the present invention can, by setting an external power supply connector, connect an external power supply device with the external power supply connector when the DCU chip is working as a supplementary power supply for the DCU chip, which can, to a certain extent, ensure the electric energy required during the operation of the DCU chip, and further improve the reliability of the operation of the DCU chip.

[0044] In order to detect whether an external power supply signal is connected to the external power supply connector, refer toFigure 4 As shown, in some embodiments, an external power supply detection circuit is further provided on the printed circuit board. The output end of the external power supply detection circuit is connected to an alarm. The external power supply detection circuit is connected to the multiple external PCIE power supply connectors for detecting whether there is input power supply for the multiple external PCIE power supply connectors.

[0045] In this embodiment, when it is detected that there is no input power supply at the entrance of the ATX external PCIE power supply connector that should be powered, the speaker Buzzer will give an alarm to prompt the user to insert the external power supply line, so as to avoid abnormal operation of the board card caused by not inserting the external power supply line.

[0046] See Figure 5 As shown, a group of I2C Master interfaces are provided corresponding to the depth calculation processing chip on the depth calculation processing chip installation part for enabling the depth calculation processing chip to control external I2C devices on the printed circuit board. The I2C Master interface is connected to the power management bus PMBUS (Power management bus) interface of the serial voltage identification voltage adjustment chip group.

[0047] In this embodiment, by setting the I2C Master interface and connecting the interface to the power management bus PMBUS interface of the serial voltage identification voltage adjustment chip group, the status information of the voltage adjustment chip VR that cannot be obtained through SVID can be read, so as to ensure that the DCU chip can obtain more comprehensive information about the VR status.

[0048] Continue to see Figure 5 As shown, a CPLD / FPGA chip, a temperature sensor and an EEPROM are further provided on the printed circuit board. The I / O interfaces of the CPLD / FPGA chip are respectively connected to the gold finger temperature sensor, the EEPROM and the voltage adjustment chip group. Among them, the CPLD / FPGA chip is connected to the gold finger through the I / O interface for realizing communication with the CPU and other components on the motherboard.

[0049] When the DCU chip works, it will generate heat. In order to monitor and control the temperature of the DCU chip, the set temperature sensor is provided.

[0050] Among them, the CPLD / FPGA chip is used to control the power-on and power-off timing of the VR, monitor the temperature Sensor, EEPROM, and VR status, and has a gigabit Ethernet interface to provide a management interface externally, which is convenient for monitoring and managing the hardware status of the board card. For example, monitoring the enable of the VR chip, the signal status of the PWRGD (Power Good) pin, the VR health status and the DCU temperature status, etc.

[0051] See Figure 6 As shown, the installation part of the depth calculation processing chip is respectively connected to a temperature sensor, an EEPROM, and a voltage regulation chip group. A multiplexing chip is also provided on the printed circuit board. The CPLD / FPGA and the depth calculation processing chip are respectively connected to the multiplexing chip (i.e., the MUX chip in the figure). The multiplexing chip is used to switch signal channels between the CPLD / FPGA and the depth calculation processing chip.

[0052] In this embodiment, the complex programmable logic device CPLD (Complex Programmable Logic Device) / field programmable gate array FPGA (Field-Programmable Gate Array) and the DCU are switched through the Mux chip to ensure that both the CPLD / FPGA and the DCU can communicate with the temperature Sensor / EEPROM / SVID VR1 / SVID VR2. The working principle is as follows: The Mux chip has an I2C_Sel pin used to select which I2C signal is connected to the temperature Sensor / EEPROM / SVID VR. The signal of the I2C_Sel pin is controlled by the IO of the CPLD / FPGA. The I2C_Sel pin enables the DCU I2C to pass by default. When the CPLD / FPGA needs to obtain information of the I2C device, it sends a Req command to the DCU. After the DCU stops the current I2C access instruction, it gives a Reply signal to the CPLD / FPGA. The CPLD / FPGA controls the I2C_Sel to switch the I2C path of the Mux chip to the CPLD / FPGA. After the reading is completed, the CPLD / FPGA notifies the DCU through Req that the current I2C path permission is handed over to the DCU chip.

[0053] See Figure 7 As shown, a power-on and power-off control circuit for the DCU chip is also provided on the PCB board. The power-on and power-off control circuit uses the CPLD / FPGA to realize the control of the DCU power-on and power-off. The circuit principle of the CPLD / FPGA controlling the DCU power-on and power-off is as follows: The CPLD / FPGA controls the Enable of the VR and receives the PWRGD signal of the VR to control the power-on timing; then the CPLD / FPGA performs a logical operation on the PCIE Reset sent by the motherboard CPU received by the gold finger of the acceleration card and all the PWRGDs of the VRs, and transmits it to the PCIE Reset of the DCU to perform a Reset control on the DCU chip. In this embodiment, the CPLD / FPGA can flexibly control the power-on and power-off timing of the DCU chip.

[0054] As described above, the acceleration card provided by the embodiment of the present invention uses a CPLD to control the power-on and power-off of a voltage regulator chip (VR, also translated as power regulator). Through logic code, the power-on and power-off timings of the power regulator chip VR and the signal input to the CPU can be flexibly adjusted, which can improve the manageability of the overall acceleration card system.

[0055] The present invention is applicable to the development, OEM processing, and hardware acceleration scenarios of electronic devices or equipment such as acceleration cards, computers, industrial control computers, and servers.

[0056] In addition, the embodiment of the present invention further provides a server, including a chassis. A main board is provided in the chassis. An acceleration card slot is provided on the main board. The acceleration card described in any of the foregoing embodiments is provided in the acceleration card slot. The acceleration card is inserted into the acceleration card slot through the gold fingers. A depth calculation processing chip is installed in the depth calculation processing chip installation part.

[0057] Among them, as Figure 8 shown, in some embodiments, the depth calculation processing chip is a high-performance computing chip. The main interfaces include PCIE, JTAG, SMBUS, I2C, SPI, GPIO (General-purpose input / output), and SVID, XTALTN, DPLUS / DMINUS, PROCHOT, FANIN / FANOUT, etc. The DCU chip is plugged into the main board through a 16-lane PCIE gold finger PCIe-Goldenfinger-x16 to communicate with the main board. The main board can also provide a PCIE clock signal to the DCU chip through the PCIE gold finger PCIe-Goldenfinger-x16, specifically connected to the PCIe_REFCLK interface (also called a pin) of the DCU chip; the main board can also supply power to the first power supply unit through the PCIE gold finger PCIe-Goldenfinger-x16. The first power supply unit also includes multiple power supply voltage conversion modules, which convert the 12V power supply voltage transmitted from the gold fingers into the voltage values required by the corresponding pins on the DCU chip and supply power to the corresponding pins on the DCU chip.

[0058] Some GPIO interfaces of the DCU chip are connected to the Complex Programmable Logic Device (CPLD). The CPLD is connected with indicator lights used to indicate various working states of the DCU chip. The CPLD is also connected to the DCU chip through the multiplexed pin Strappin. Among them, the CPLD controls the output selection of some other Strappin through the high and low levels of some Strappin levels, so as to achieve the purpose of internal function selection of the DCU. For example, the aforementioned CPLD can control the power-on and power-off of the DCU chip through the high and low levels of the Strappin.

[0059] The second power supply unit, that is, the voltage provided by the external power supply connector ExternalConnector +12v, is converted into the required voltage and then supplies power to the corresponding pins of the DCU. In addition, it can be understood that the CPLD is connected to the first and second power supply units to achieve power-on and power-off control. Of course, due to the limitation of graphic drawing, the connection between the CPLD and the first power supply unit is not shown.

[0060] The XTALIN interface of the DCU chip is used to connect to an external crystal oscillator with a frequency of 100M. Some GPIO interfaces are connected with signal protocol standard conversion chips, which are used to convert signals with the I2C protocol standard into signals with the UART protocol standard to realize the debugging of the device. The SPI interface of the DCU chip is used to connect to the VBIOS (actually also a kind of BIOS, different from the BIOS naming of the motherboard). Through the pin connector Header connected to this SPI interface, the BIOS firmware information is remotely burned. The I2C interface of the DCU chip is used to connect to the EPROM, and its JTAG interface is used to connect to devices that support the JTAG protocol. The BP pin of the DCU chip is also connected with a pin Debug Header for debugging.

[0061] Of course, Figure 8 It is only a schematic diagram of an embodiment and does not fully show all circuit topologies and details. It can be understood in combination with the relevant prior art in this field and the content of the foregoing embodiments.

[0062] In some embodiments, the DCU chip is a Hygon DCU chip, which can support or be connected with other components according to Figure 8 the circuit topology relationship shown to achieve a predetermined function.

[0063] For the server in this embodiment, since the acceleration card is convenient for realizing the transmission of high-speed signals and the improvement of computing power, the performance of the server can be optimized to a certain extent.

[0064] It should be noted that in this text, terms indicating orientation or positional relationships such as "upper" and "lower" are only used to facilitate the description of the present invention and simplify the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present invention. Unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium. Relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. Those of ordinary skill in the art can understand through specific circumstances.

[0065] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An acceleration card, characterized in that, it includes a printed circuit board, the edge of the printed circuit board has a gold finger, the gold finger is integrated with a power supply signal contact, a depth calculation processing chip mounting part and a power supply module are arranged on the printed circuit board, the depth calculation processing chip mounting part is connected to the gold finger through a PCIE bus, the power supply module is electrically connected to the depth calculation processing chip mounting part, and the gold finger supports the PCIE bus and interface standard; the power supply module includes a first power supply unit, the first power supply unit includes a plurality of serial voltage identification power supply domains, the plurality of serial voltage identification power supply domains are divided into two groups, each group has a serial voltage identification interface, the first group of serial voltage identification power supply domains is connected to a first serial voltage identification voltage adjustment chip through the serial voltage identification interface, the second group of serial voltage identification power supply domains is connected to a second serial voltage identification voltage adjustment chip through the serial voltage identification interface, the first serial voltage identification voltage adjustment chip is used to control the first group of serial voltage identification power supply domains to supply power to the depth calculation processing chip mounting seat, and the second serial voltage identification voltage adjustment chip is used to control the second group of serial voltage identification power supply domains to supply power to the depth calculation processing chip mounting seat.

2. The acceleration card according to claim 1, characterized in that, each group of serial voltage identification power supply domains includes two serial voltage identification power supply sources.

3. The acceleration card according to claim 1, characterized in that, the power supply module further includes a second power supply unit, the second power supply unit includes a plurality of external PCIE power supply connectors arranged on the printed circuit board, and the external PCIE power supply connectors are electrically connected to the depth calculation processing chip mounting part through a voltage adjustment chip group for supplying power to the depth calculation processing chip mounting part.

4. The acceleration card according to claim 3, characterized in that, the voltage adjustment chip group includes a serial voltage identification voltage adjustment chip, a first DC-DC power supply and a second DC-DC power supply, and the supply current of the first DC-DC power supply is greater than that of the second DC-DC power supply.

5. The acceleration card according to claim 3, characterized in that, an external power supply detection circuit is further arranged on the printed circuit board, an alarm is connected to the output end of the external power supply detection circuit, and the external power supply detection circuit is connected to the plurality of external PCIE power supply connectors for detecting whether there is input power supply for the plurality of external PCIE power supply connectors.

6. The acceleration card according to claim 3 or 4, characterized in that, a group of I2C Master interfaces are arranged corresponding to the depth calculation processing chip on the depth calculation processing chip mounting part for enabling the depth calculation processing chip to control external I2C devices on the printed circuit board, and the I2C Master interfaces are connected to the power management bus interfaces of the serial voltage identification voltage adjustment chip group.

7. The acceleration card according to claim 3, characterized in that, The printed circuit board is also provided with a CPLD / FPGA chip, a temperature sensor and an EEPROM, and the CPLD / FPGA chip is respectively connected to the gold finger, the temperature sensor, the EEPROM and the voltage regulation chip set.

8. The acceleration card according to claim 7, wherein, the installation parts of the deep computing processing chips are respectively connected to the temperature sensor, the EEPROM and the voltage regulation chip set, a multiplexing chip is further provided on the printed circuit board, the CPLD / FPGA and the deep computing processing chips are respectively connected to the multiplexing chip, and the multiplexing chip is used for switching signal channels between the CPLD / FPGA and the deep computing processing chips.

9. A server, wherein, it includes a chassis, a main board is provided in the chassis, an acceleration card slot is provided on the main board, any one of the acceleration cards according to claims 1 to 8 is provided in the acceleration card slot, the acceleration card is inserted into the acceleration card slot through the gold finger, and a deep computing processing chip is installed in the installation part of the deep computing processing chip.

Images