Method for manufacturing a semiconductor device comprising a layer of low-k dielectric material

Abstract

A method for fabricating a semiconductor device including a low-k dielectric material layer is provided that includes forming a first pattern structure having a first opening on an understructure including a semiconductor substrate. The first pattern structure includes a stack pattern and a first spacer layer covering at least one side surface of the stack pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer including water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0100384, filed on August 16, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device comprising a layer of low-k (low dielectric constant) dielectric material and said semiconductor device. Background Technology

[0004] Low-k dielectric materials can be used as insulating materials to fill the spaces between interconnects. Low-k dielectric materials reduce parasitic capacitance between interconnects. Summary of the Invention

[0005] Exemplary embodiments of the present invention provide a method for manufacturing a semiconductor device comprising a low-k dielectric material layer and the semiconductor device thereof.

[0006] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a first patterned structure having a first opening on a lower structure (structure) including a semiconductor substrate (base material, substrate). The first patterned structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer is formed on the first spacer layer to fill the first opening and cover an upper portion of the first patterned structure. The first flowable material layer includes a SiOCH material. A first curing process is performed on the first flowable material layer to form a first cured material layer including water (H2O). Performing the first curing process includes supplying a gaseous ammonia (NH3) catalyst into the first flowable material layer. The first curing process is configured to cure the first flowable material layer while generating water (H2O) in the first flowable material layer. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The second curing process is configured to evaporate the water (H2O) in the first cured material layer outward from the first cured material layer. The first low-k dielectric material layer is planarized (planarized) using a first chemical mechanical polishing process to form a planarized first low-k dielectric material layer.

[0007] According to an exemplary embodiment of the inventive concept, a method for fabricating a semiconductor device includes forming a structure having an opening on an underlying structure. A flowable material layer is formed to fill the opening and cover an upper portion of the structure. A first curing process is performed on the flowable material layer to form a cured material layer. A second curing process is performed on the cured material layer to form a low-k dielectric material layer. The low-k dielectric material layer is planarized to form a planarized low-k dielectric material layer in the opening. A volume reduction rate when the flowable material layer is formed to the cured material layer is greater than a volume reduction rate when the cured material layer is formed to the low-k dielectric material layer.

[0008] According to an exemplary embodiment of the inventive concept, a method for fabricating a semiconductor device includes forming a flowable material layer on an underlying structure. A first curing process is performed by supplying an ammonia (NH3) catalyst gas into the flowable material layer at a temperature of about 23 °C or greater to less than 100 °C to form a cured material layer. A second curing process is performed on the cured material layer at a temperature of 100 °C or greater to form a low-k dielectric material layer. The flowable material layer includes a SiOCH material. Water (H2O) is generated during the first curing process. The water (H2O) generated during the first curing process is included in the cured material layer. The water (H2O) in the cured material layer is evaporated and removed during the second curing process. Hydrogen (H) in the cured material layer is removed in the second curing process to form the low-k dielectric material layer of a SiOC material. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a process flow diagram illustrating a method for fabricating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 is a top plan view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 、 4 , 6-8 and 10 are cross-sectional views taken along lines I-I' and II-II' of Figure 2 , which illustrate a method for fabricating a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0013] Figure 5 and 9 are cross-sectional views and enlarged views taken along lines I-I' and II-II' of Figure 2 , which illustrate a method for fabricating a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0014] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0015] Reference Figure 1 A method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention is described. Figure 1 This is a process flow diagram illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to a concept of the present invention.

[0016] refer to Figure 1 In an exemplary embodiment, in block S110, a patterned structure with openings may be formed on the lower structure. In an exemplary embodiment, the lower structure may include a semiconductor substrate, and the patterned structure may be a structure formed for manufacturing a semiconductor device. In one exemplary embodiment, the patterned structure may include a memory cell of a memory device. In another exemplary embodiment, the patterned structure may include a gate structure of a logic device or another structure with openings. However, the exemplary embodiments of the present invention are not limited thereto.

[0017] like Figure 1 As shown in the exemplary embodiment, in block S120, a flowable material layer may be formed to cover the upper portion of the patterned structure while filling the opening. In the exemplary embodiment, the flowable material layer may be formed by a flowable chemical vapor deposition (CVD) process. However, the exemplary embodiments of the present invention are not limited thereto.

[0018] In an exemplary embodiment, the flowable material layer may include a flowable SiOCH material having a composition having chemical formula 1.

[0019] Chemical Formula 1:

[0020]

[0021] For example, in an exemplary embodiment of the present invention, forming a flowable material layer on a lower structure including a semiconductor substrate can be performed using a flowable CVD process that uses octamethylcyclotetrasiloxane (OMCTS) as a precursor and optionally (concurrently) uses at least one compound selected from tetramethyl orthosilicate (TMOS) and tetraethyl orthosilicate (TEOS) as an additive. The TMOS and / or TEOS additives can be added to the OMCTS precursor to provide crosslinking.

[0022] like Figure 1 As shown in the exemplary embodiment, in block S130, a first curing process can be performed to form a flowable material layer as a cured material layer including water.

[0023] A flowable material layer can be formed into a cured material layer having Formula 2 by a reaction of the SiOCH material of Formula 1. Siloxane bonds between silicon-hydroxyl (Si-hydroxyl) groups, e.g., "Si-O-Si linkages," can be formed by the first curing process.

[0024] Formula 2:

[0025]

[0026] In an example embodiment, the first curing process can be performed in an ammonia (NH3) catalyst gas atmosphere. Water (H2O) can be formed in the flowable material layer while the first curing process is performed. For example, water (H2O) can be formed as a byproduct while the siloxane bonds described above are formed. For example, water (H2O) can be formed as a byproduct by reacting a catalyst gas of ammonia (NH3) with one "H" of the "OH" substituent in Formula 1 to form NH4 + and reacting any "OH" of the "OH" substituent in Formula 1 with the NH4 + to convert the NH4 + to NH3 + . As described herein, the H2O formed as a byproduct can remain in the cured material layer even after the first curing process is completed.

[0027] In an example embodiment, performing the first curing process to form the flowable material layer into the cured material layer can include supplying a gaseous ammonia (NH3) catalyst into the flowable material layer to form water (H2O) in the flowable material layer, and curing the flowable material layer to prevent the formed water (H2O) from evaporating outwardly from the flowable material layer. For example, the first curing process can be performed with process conditions in which water is not evaporated, e.g., the first curing process can be performed at a temperature of less than about 100 degrees Celsius (°C). In an example embodiment, the first curing process can be performed at a temperature of about 23 °C or greater to less than about 100 °C. For example, the first curing process can be performed at a temperature of about 40 °C or greater to less than about 80 °C. However, example embodiments of the inventive concept are not limited thereto.

[0028] As Figure 1 shown in an example embodiment of FIG. 1, in block S140, a second curing process can be performed on the cured material layer to form a low-k dielectric material layer while removing water in the cured material layer.

[0029] In the second curing process, water in the layer of cured material can be evaporated out of the layer of cured material to remove the water therefrom. In an exemplary embodiment, the layer of low-k dielectric material can be formed of a SiOC material having a dielectric constant lower than that of silicon dioxide. For example, the layer of low-k dielectric material can be formed of a SiOC material having a backbone represented by Chemical Formula 3.

[0030] Chemical Formula 3:

[0031]

[0032] In an exemplary embodiment, the second curing process can be performed at a temperature of about 100°C or more to remove water remaining in the layer of cured material and / or water generated while converting the layer of cured material into the layer of low-k dielectric material.

[0033] The second curing process can be performed at a temperature at which the lower structure and the pattern structure are not thermally damaged. For example, when the pattern structure is a memory cell of a phase change memory device including a phase change material, the second curing process can be performed at a temperature of about 100°C or more to about 300°C or less. For example, in an exemplary embodiment in which the pattern structure includes a layer of phase change material in an amorphous phase, the second curing process can be performed at a temperature at which the amorphous phase is maintained. For example, in an exemplary embodiment, the second curing process can be performed at a temperature of about 150°C or more to about 250°C or less.

[0034] In an exemplary embodiment, the second curing process can further include using at least one of an ultraviolet (UV) process and an ammonia catalyst process. The UV process can include irradiating UV to a surface of the layer of cured material, and the ammonia catalyst process can include supplying an ammonia catalyst gas to the surface of the layer of cured material.

[0035] In an exemplary embodiment, the second curing process can include irradiating UV to a surface of the layer of cured material at a temperature of about 100°C or more.

[0036] In another exemplary embodiment, the second curing process can include supplying an ammonia catalyst gas to a surface of the layer of cured material at a temperature of about 100°C or more.

[0037] In another exemplary embodiment, the second curing process can include supplying an ammonia catalyst gas to a surface of the layer of cured material at a temperature of about 100°C or more while irradiating UV to the surface of the layer of cured material.

[0038] In an exemplary embodiment, the second curing process may be repeated at least once. For example, in an exemplary embodiment, the second curing process may be performed a total of two or three times. However, the exemplary embodiments conceived in this invention are not limited thereto.

[0039] In an exemplary embodiment, the first and second curing processes can be carried out in a process atmosphere at a pressure lower than atmospheric pressure.

[0040] In an exemplary embodiment, the first curing process can be carried out at a first pressure below atmospheric pressure, and the second curing process can be carried out at a second pressure below atmospheric pressure but above the first pressure. For example, the first curing process can be carried out in a process atmosphere of about 0.1 Torr to about 20 Torr, and the second curing process can be carried out in a process atmosphere of about 300 Torr to about 550 Torr. However, the exemplary embodiments of the present invention are not limited thereto.

[0041] The second curing process may include removing hydrogen (H) from the chemical formula 2 of the curing material layer and water from the curing material layer.

[0042] When the cured material layer is converted into a low-k dielectric material layer through a second curing process, gases such as H2 and C can be generated. x H y The gas can be generated by a second curing process.

[0043] In an exemplary embodiment, the low-k dielectric material layer may have pores.

[0044] The low-k dielectric material layer may have holes of different sizes. For example, the low-k dielectric material layer may have a first hole and a second hole that is larger than the first hole. However, in another exemplary embodiment, the low-k dielectric material layer may have holes of uniform size.

[0045] When a cured material layer having chemical formula 2 is transformed into a low-k dielectric material layer having chemical formula 3 through a second curing process, the aforementioned siloxane bonds, such as "Si-O-Si" bonds, can be maintained.

[0046] In the second curing process, the Si-O-Si bond structure remains essentially intact. Because the Si-O-Si bond structure reacts with the silicon-hydroxy (Si-hydroxy) groups in the cured material layer left after the first curing process, the additional volume reduction caused by the second curing process does not occur.

[0047] In an exemplary embodiment, when the flowable material layer is formed as a low-k dielectric material layer, the volume reduction rate can be about 2% or less (e.g., 2% or less of the total initial volume of the flowable material layer removed by performing a first curing process and a second curing process). For example, the volume reduction rate can be about 1% or less. In contrast, the volume reduction rate when the flowable material layer is formed as a cured material layer by the first curing process can be greater than the volume reduction rate when the cured material layer is formed as a low-k dielectric material layer by the second curing process.

[0048] The low-k dielectric material layer formed by the second curing process can be cured more rigidly than the cured material layer formed by the first curing process without significant volume reduction.

[0049] like Figure 1 As shown in the exemplary embodiment, in block S150, the low-k dielectric material layer can then be planarized to form a planarized low-k dielectric material layer retained in the opening. For example, the low-k dielectric material layer can be planarized by chemical mechanical polishing (CMP) or the like. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0050] When the CMP process is performed after forming the low-k dielectric material layer in the second curing process as described above, the low-k dielectric material layer can be formed in a rigid state and has a low dielectric constant. Because the low-k dielectric material layer is formed in a rigid state, the patterned structure can be prevented from being damaged by the CMP process.

[0051] In the following text, reference will be made to Figures 2 to 10 A method for manufacturing a semiconductor device 1 according to an exemplary embodiment of the present invention is described. Figure 2 This is a top view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 3 , 4 6-8 and 10 are along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 5 and 9 It is along Figure 2 The cross-sectional views and enlarged views taken along lines I-I' and II-II' illustrate a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figures 2 to 10 The description will omit Figure 1 The content has already been provided. Therefore, although the reference... Figures 2 to 10 This describes a method for manufacturing a semiconductor device according to an exemplary embodiment, but from the reference... Figure 1 The description may include omitted or briefly mentioned content.

[0052] refer to Figure 2 and 3 A first patterned structure 57 having a first opening 57o can be formed on a lower structure 12 including a semiconductor substrate 3. For example, as Figure 3 As shown in the exemplary embodiment, the first opening 57o may include a plurality of openings spaced apart in the Y direction. The Y direction may be parallel to the upper surface of the semiconductor substrate 3.

[0053] The lower structure 12 may include a lower insulating layer 5 on the semiconductor substrate 3, lower conductive lines 7 on the lower insulating layer, and an insulating pattern 9 filling the gaps between the lower conductive lines 7 (e.g., in the Y direction). For example, as Figure 3 As shown in the exemplary embodiment, the bottom surface of the lower insulating layer 5 can directly contact the upper surface of the semiconductor substrate 3, and the bottom surface of the lower conductive line 7 and the gap-filling insulating pattern 9 can directly contact the top surface of the lower insulating layer 5. In the exemplary embodiment, the lower conductive line 7 can be a word line of a memory device. However, the exemplary embodiments of the present invention are not limited thereto. In the exemplary embodiment, the lower conductive line 7 can include a conductive material such as tungsten. Figure 2 As shown in the exemplary embodiment, the lower conductor 7 may have a line shape extending in the X direction. The X direction may be a direction parallel to the upper surface of the semiconductor substrate 3 and perpendicular to the Y direction.

[0054] The first pattern structure 57 may include a stacked pattern 45 and a first spacer layer 54. The first spacer layer 54 may cover at least one lateral side surface of the stacked pattern 45 (e.g., in the X direction). For example, as Figure 3 As shown in the exemplary embodiment, the first spacer layer 54 covers each of the lateral side surfaces of the stacked pattern 45.

[0055] The stacked pattern 45 may include multiple material layers. For example, such as Figure 3 As shown in the exemplary embodiment, the stacked pattern 45 may include a lower electrode layer 15, a selector material layer 18, one or more intermediate electrode layers, a data storage material layer 27, one or more upper electrodes, and one or more mask layers. For example, as... Figure 3 As shown in the exemplary embodiment, the lower electrode layer 15, the selector material layer 18, the intermediate electrode layer, the data storage material layer 27, the upper electrode, and the mask layer can be sequentially stacked on the lower structure 12 in the Z direction, which is perpendicular to the upper surface of the semiconductor substrate 3 and perpendicular to the X and Y directions.

[0056] The single or multiple intermediate electrode layers may include a first intermediate electrode material layer 21 and a second intermediate electrode material layer 24 disposed on the first intermediate electrode material layer 21 (e.g., in the Z direction). The single or multiple upper electrode layers may include a first upper electrode material layer 30 and a second upper electrode material layer 33 disposed on the first upper electrode material layer 30 (e.g., in the Z direction). The single or multiple mask layers may include a first mask layer 36 and a second mask layer 39 disposed on the first mask layer 36 (e.g., in the Z direction).

[0057] The first spacer layer 54 may include multiple spacer layers. For example, the first spacer layer 54 may include a first inner spacer layer 48 and a first outer spacer layer 51. The first inner spacer layer 48 and the first outer spacer layer 51 may extend substantially in the Z direction. The first outer spacer layer 51 may be disposed on the first inner spacer layer 48 (e.g., in the Y direction) and may cover the outward-facing longitudinal surface of the first inner spacer layer. The top portion of the first outer spacer layer 51 may extend substantially in the Y direction and may cover the top surface of the second mask layer 39. The bottom portion of the first outer spacer layer 51 may be aligned with the bottom of the opening 57o (e.g., in the Z direction).

[0058] In an exemplary embodiment, forming the first pattern structure 57 may include sequentially forming a lower electrode layer 15, a selector material layer 18, one or more intermediate electrode layers 21 and 24, a data storage material layer 27, one or more upper electrode layers 30 and 33, a first mask layer 36, and a second mask layer 39 on the lower structure 12 (e.g., in the Z direction). The second mask layer 39, the first mask layer 36, the one or more upper electrode layers 30 and 33, and the data storage material layer 27 are then sequentially etched. A first internal spacer layer 48 is formed on the side surfaces of the etched second mask layer 39, the etched first mask layer 36, the etched one or more upper electrode layers 30 and 33, and the etched data storage material layer 27. The second mask layer 39 and the first internal spacer layer 48 are used as etching masks to etch the one or more intermediate electrode layers 21 and 24, the selector material layer 18, and the lower electrode layer 15. Then, the first outer spacer layer 51 is conformally formed over the second mask layer 39, on the outer side surface of the first inner spacer layer 48, the etched single or multiple intermediate electrode layers 24 and 21, the etched selector material layer 18 and the etched lower electrode layer 15, and in the first opening 57o.

[0059] In an exemplary embodiment, the data storage material layer 27 may be formed of a phase change material. For example, the data storage material layer 27 may be formed of a chalcogenide-based phase change material having a phase that can change from a high-resistivity amorphous phase to a low-resistivity crystalline phase, and vice versa, depending on the heating temperature and time by the applied current. For example, the data storage material layer 27 may be formed of a chalcogenide material, such as one comprising at least one element selected from Ge, Sb, and Te. Alternatively, the data storage material layer 27 may be formed of a phase change material comprising at least one element selected from Te and Se, and at least one element selected from Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and In. In another exemplary embodiment, the data storage material layer 27 may be formed of a data storage material that stores data in a manner different from that of a phase change material.

[0060] In an exemplary embodiment, the data storage material layer 27 may be formed as amorphous during the initial formation operation.

[0061] Selector material layer 18 may constitute a switching device. In an exemplary embodiment, selector material layer 18 may constitute a bidirectional threshold switching device. For example, selector material layer 18 may be formed of a chalcogenide-based material different from the chalcogenide-based material of data storage material layer 27. Data storage material layer 27 may be a phase change storage material (e.g., an alloy of Ge, Sb, and / or Te) having a phase that can change from a crystalline phase to an amorphous phase and vice versa during operation of the semiconductor device. Selector material layer 18 may be formed of a chalcogenide-based bidirectional threshold switching material that retains an amorphous phase during operation of the semiconductor device. For example, selector material layer 18 may be formed of an alloy material comprising at least two elements selected from As, S, Se, Te, and Ge, or further comprising additional elements (e.g., Si, N, etc.) added to such an alloy material that can retain an amorphous phase at higher temperatures. Alternatively, the selector material layer 18 may be formed of any of the following: an alloy material comprising Te, As, Ge, and Si; an alloy material comprising Ge, Te, and Pb; an alloy material comprising Ge, Se, and Te; an alloy material comprising Al, As, Te, Se, and As; an alloy material comprising Ge and Si; an alloy material comprising Se, As, Ge, and C; an alloy material comprising Se, Te, Ge, and Si; an alloy material comprising Ge, Sb, Te, Se, and Ge; an alloy material comprising Bi, Te, and Se; an alloy material comprising Ge, As, Sb, and Se; an alloy material comprising Ge, As, Bi, and Te; and an alloy material comprising Ge, As, Bi, and Se. However, exemplary embodiments of the inventive concept are not limited thereto.

[0062] In an exemplary embodiment, the lower electrode layer 15 and the first intermediate electrode material layer 21 may be formed of a carbon layer or a carbon-containing material layer. The carbon-containing material layer may be a material layer comprising carbon and a metal. For example, the carbon-containing material layer may include carbon and at least one metal such as W, Ti, etc. However, the exemplary embodiments of the present invention are not limited thereto.

[0063] In an exemplary embodiment, the second intermediate electrode material layer 24 and the first upper electrode material layer 30 may be formed of metal. For example, the second intermediate electrode material layer 24 and the first upper electrode material layer 30 may be formed of tungsten.

[0064] In an exemplary embodiment, the second upper electrode material layer 33 may be formed of a carbon layer or a carbon-containing material layer.

[0065] The first inner spacer layer 48 and the first outer spacer layer 51 may be formed of insulating material.

[0066] In an exemplary embodiment, the first inner spacer layer 48 and the first outer spacer layer 51 may be formed of insulating materials different from each other. For example, the first inner spacer layer 48 may be formed of at least one compound selected from SiN, SiO2, SiC, SiCN, SiON, SiBN, and SiOCN, and the first outer spacer layer 51 may be formed of a material different from the material of the first inner spacer layer 48 among SiN, SiO2, SiC, SiCN, SiON, SiBN, and SiOCN. However, the exemplary embodiments of the first inner spacer layer 48 and the first outer spacer layer 51 are not limited to such materials, and other materials may be used instead of the materials of the first inner spacer layer 48 and the first outer spacer layer 51.

[0067] In another exemplary embodiment, the first inner spacer layer 48 and the first outer spacer layer 51 may be formed of the same insulating material.

[0068] A first energy-flowable material layer 60 may be formed on the first spacer layer 54 to cover the upper portion of the first patterned structure 57 while filling the first opening 57o. The first energy-flowable material layer 60 may have an upper surface 60S disposed at a level higher than the level (height) of the upper surface of the first patterned structure 57 (e.g., the distance from the top surface of the semiconductor substrate 3 in the Z direction).

[0069] The first flowable material layer 60 can be referenced. Figure 1 The described energy-flowable material layer is the same. Therefore, since the first energy-flowable material layer 60 can be used with the reference layer... Figure 1 The same method described is used, so its detailed description will be omitted.

[0070] refer to Figure 2and 4 The first curing process 70 can be performed to enable the first flowable material layer ( Figure 3 60) is cured to form a first cured material layer 61 including water 63H.

[0071] Performing a first curing process 70 to form a first cured material layer 61 may include supplying a gaseous ammonia (NH3) catalyst to the first flowable material layer 60 to generate water 63H in the first flowable material layer while simultaneously curing the first flowable material layer 60 to prevent water (H2O) 63H from evaporating outward from the first flowable material layer 60. Therefore, the first cured material layer 61 may include water 63H.

[0072] A first cured material layer 61 is formed by performing a first curing process 70 on a first flowable material layer 60. By performing the first curing process 70, the volume of the first cured material layer 61 can be reduced. Therefore, the upper surface 61S of the first cured material layer 61 can (e.g., in the Z direction) be lower than the upper surface 60S of the first flowable material layer 60 before performing the first curing process 70. Figure 4 The dashed line in the figure represents the level of the upper surface 60S of the first flowable material layer before the first curing process 70.

[0073] The first curing process 70 can be combined with Figure 1 The first curing process described herein is the same, and the first cured material layer 61 can be used with... Figure 1 The cured material layer is the same as described in the reference. Therefore, since the first curing process 70 and the first cured material layer 61 are available from the reference... Figure 1 The content described is understood, so its detailed description will be omitted.

[0074] refer to Figure 2 and 5 Then, a second curing process 75 can be performed on the first cured material layer 61 to form a first low-k dielectric material layer 62. During the second curing process 75, water 63H evaporates from the first cured material layer 61 outwards.

[0075] In an exemplary embodiment, the first low-k dielectric material layer 62 may have a first hole 63P.

[0076] like Figure 5 As shown in the enlarged view, the first low-k dielectric material layer 62 may further have a second hole 65 that is larger than the first hole 63P. Therefore, the first low-k dielectric material layer 62 may have first and second holes 63P and 65 with different sizes from each other.

[0077] In the accompanying drawings, for clarity of description, the dimensions of the first hole 63P and the second hole 65 may be enlarged.

[0078] In an exemplary embodiment, when a first curing process 70 is performed on the first flowable material layer 60 and a second curing process 75 is performed on the cured material layer 61 to form a first low-k dielectric material layer 62, the volume reduction rate can be about 2% or less. For example, when the first curing process 70 and the second curing process 75 are performed to form the first low-k dielectric material layer 62 from the first flowable material layer 60, the volume reduction rate can be about 1% or less.

[0079] The volume reduction rate when the first flowable material layer 60 is subjected to a first curing process 70 to form a first cured material layer 61 can be greater than the volume reduction rate when the first cured material layer 61 is subjected to a second curing process 75 to form a first low-k dielectric material layer 62. For example, the height difference between the upper surface of the first flowable material layer 60 and the upper surface 61S of the first cured material layer 61 can be greater than the height difference between the upper surface 61S of the first cured material layer 61 and the upper surface 62S of the first low-k dielectric material layer 62.

[0080] According to an exemplary embodiment, when the first curing process 70 and the second curing process 75 are performed to form the first low-k dielectric material layer 62 from the first flowable material layer 60, the volume reduction rate can be significantly reduced to prevent peeling between the side surfaces of the first spacer layer 54 and the second upper electrode material layer 33 which may contain carbon, and to prevent a reduction in the interfacial bonding force between the side surfaces of the first spacer layer 54 and the second upper electrode material layer 33.

[0081] refer to Figure 2 and 6 The first low-k dielectric material layer 62 can be planarized by a first planarization process to form a planarized first low-k dielectric material layer 62a.

[0082] In an exemplary embodiment, the first planarization process may be a chemical mechanical polishing (CMP) process.

[0083] like Figure 6 As shown in the exemplary embodiment, when the first low-k dielectric material layer 62 is planarized by the first planarization process, the first pattern structure 57 can also be planarized to form a planarized first pattern structure 57a. The second upper electrode material layer 33 of the first pattern structure can be exposed by the first planarization process, and one or more mask layers 36 and 39 disposed on the second upper electrode material layer 33 can be removed by the first planarization process.

[0084] The first planarization process can planarize the first stacked pattern 45 to form a planarized first stacked pattern 45a that exposes the upper surface of the second upper electrode material layer 33. The first spacer layer 54 can be planarized by the first planarization process to form a planarized first spacer layer 54a. Therefore, the planarized first pattern structure 57a may include the planarized first stacked pattern 45a and the planarized first spacer layer 54a.

[0085] (For example, in the Y direction) A portion of the planarized first spacer layer 54a between the planarized first low-k dielectric material layer 62a and the second upper electrode material layer 33 may include a first inner spacer layer 48 and a first outer spacer layer 51.

[0086] Since the first curing process 70 and the second curing process 75 can be performed to significantly reduce the volume reduction that occurs when the first flowable material layer 60 is formed into a rigidly cured first low-k dielectric material layer 62, the first stacking pattern 45 (or 45a) and the first spacer layer 54 (or 54a) can be prevented from being peeled off by the first planarization process.

[0087] refer to Figure 2 and Figure 7 The upper conductor 78 and the upper mask line 80 can be formed by stacking them sequentially. Figure 6 On the planarized first patterned structure 57a and the planarized first low-k dielectric material layer 62a. For example, as Figure 7 As shown in the exemplary embodiment, the bottom surface of the upper conductor 78 can directly contact the top surface of the planarized first patterned structure 57a and the planarized first low-k dielectric material layer 62a.

[0088] like Figure 2 As shown in the exemplary embodiment, the upper conductor 78 may have a line shape extending in the Y direction.

[0089] The second patterned structure 92a having the second opening 92o can be formed by etching the planarized first patterned structure 57a and the planarized first low-k dielectric material layer 62a using an etching process that employs an upper conductor 78 and an upper mask line 80 as an etching mask. For example, as Figure 7 As shown in the exemplary embodiment, the second opening 92o may include a plurality of openings spaced apart in the X direction. A second spacer layer 89 may then be formed to extend on the lateral and top surfaces of the second patterned structure 92a and in the second opening 92o.

[0090] The planarized first patterned structure 57a and the planarized first low-k dielectric material layer 62a can be formed into a patterned first patterned structure and a first low-k dielectric material layer 62b, respectively, by an etching process using an upper conductor 78 and an upper mask line 80 as an etching mask. The patterned first patterned structure may include a second stacked pattern 45b formed by patterning a planarized first stacked pattern 45a and a patterned first spacer layer 54b formed by patterning a planarized first spacer layer 54a. The second spacer layer 89 may cover at least one side surface of the first patterned structure. The second patterned structure 92a may include the patterned first patterned structure, the first low-k dielectric material layer 62b, the upper conductor 78, the upper mask line 80, and the second spacer layer 89.

[0091] The second stacked pattern 45b may be formed to include layers substantially the same as those of the planarized first stacked pattern 45a, such as a lower electrode layer 15, a selector material layer 18, a first intermediate electrode material layer 21, a second intermediate electrode material layer 24, a data storage material layer 27, a first upper electrode material layer 30, and a second upper electrode material layer 33.

[0092] The second spacer layer 89 may include a second inner spacer layer 83 and a second outer spacer layer 86. For example... Figure 7 As shown in the exemplary embodiment, the second outer spacer layer 86 may be disposed on the second inner spacer layer 83 in the X direction.

[0093] In an exemplary embodiment, the second inner spacer layer 83 and the second outer spacer layer 86 may be formed of insulating materials different from each other. For example, the second inner spacer layer 83 may be formed of at least one compound selected from SiN, SiO2, SiC, SiCN, SiON, SiBN, and SiOCN, and the second outer spacer layer 86 may be formed of a material different from the material of the second inner spacer layer 83 among SiN, SiO2, SiC, SiCN, SiON, SiBN, and SiOCN. However, the exemplary embodiments of the present invention are not limited to such materials, and in other exemplary embodiments, the materials of the second inner spacer layer 83 and the second outer spacer layer 86 may be replaced with other materials.

[0094] In another exemplary embodiment, the second inner spacer layer 83 and the second outer spacer layer 86 may be formed of the same insulating material.

[0095] Forming the second spacer layer 89 may include forming a second inner spacer layer 83 to cover the lateral side surfaces of the second upper electrode material layer 33, the first upper electrode material layer 30, and the data storage material layer 27 after etching the planarized first pattern structure 57a using the upper conductor 78 and the upper mask line 80 as an etching mask.

[0096] Forming the second spacer layer 89 may include etching one or more intermediate electrode layers 21 and 24, the selector material layer 18, and the lower electrode layer 15 using the second inner spacer layer 83 and the upper mask line 80 as an etching mask after forming the second inner spacer layer 83, and conformally forming the second outer spacer layer 86. The second outer spacer layer 86 may cover the side surfaces of the one or more intermediate electrode layers 21 and 24, the selector material layer 18, and the lower electrode layer 15, the outer side surface of the second inner spacer layer 83 (e.g., in the X direction), the upper surface of the upper mask line 80, and the upper surface of the lower conductor 7 adjacent to the lower electrode layer 15 (e.g., in the Z direction).

[0097] The second flowable material layer 103 may be formed on the second spacer layer 89 to cover the upper portion of the second patterned structure 92a while filling the second opening 92o. For example, as Figure 7 As shown in the exemplary embodiment, the bottom surface of the second flowable material layer 103 can directly contact the top surface of the second patterned structure 92a. In the exemplary embodiment, the second flowable material layer 103 can be formed by the same method as the first flowable material layer 60 and by the same material as the first flowable material layer 60.

[0098] refer to Figure 2 and 8 A third curing process 110 can be performed on the second flowable material layer 103 to form a second cured material layer 104 including water 106H. In an exemplary embodiment, the third curing process 110 can be combined with... Figure 4 The first curing process 70 described herein is substantially the same, and the second curing material layer 104 can be used with... Figure 4 The first cured material layer 61 described herein is substantially the same. Therefore, since the third cured process 110 and the second cured material layer 104 can be easily understood from the first cured process 70 and the first cured material layer 61, their detailed description will be omitted.

[0099] refer to Figure 2 and 9A fourth curing process 115 can be performed on the second cured material layer 104 to form a second low-k dielectric material layer 105 while evaporating water 106H from the second cured material layer 104 outward.

[0100] In an exemplary embodiment, the second low-k dielectric material layer 105 may have a third hole 106P and a fourth hole 108, the third hole 106P and the fourth hole 108 respectively corresponding to the first hole 63P and the second hole 65 of the first low-k dielectric material layer 62.

[0101] In an exemplary embodiment, when the second flowable material layer 103 is subjected to a third curing process 110 and a fourth curing process 115 to form a second low-k dielectric material layer 105, the volume reduction rate can be about 2% or less. For example, when the second flowable material layer 103 is subjected to a third curing process 110 and a fourth curing process 115 to form a second low-k dielectric material layer 105, the volume reduction rate can be about 1% or less.

[0102] The volume reduction rate when the second flowable material layer 103 is subjected to a third curing process 110 to form a second cured material layer 104 can be greater than the volume reduction rate when the second cured material layer 104 is subjected to a fourth curing process 115 to form a second low-k dielectric material layer 105. For example, the height difference between the upper surface 103S of the second flowable material layer 103 and the upper surface 104S of the second cured material layer 104 can be greater than the height difference between the upper surface 104S of the second cured material layer 104 and the upper surface 105S of the second low-k dielectric material layer 105.

[0103] The fourth curing process 115 can be combined with the second curing process described above. Figure 5 The second low-k dielectric material layer 105 is substantially the same as the first low-k dielectric material layer (75), and the second low-k dielectric material layer 105 may be used with the first low-k dielectric material layer (75). Figure 5 The process is essentially the same as 62) in the previous process. Therefore, due to the fourth curing process 115 and the second low-k dielectric material layer 105, it is possible to obtain... Figure 5 The second curing process described in the text ( Figure 5 75) and the first low-k dielectric material layer ( Figure 5 62) is easily understood, so its detailed description will be omitted.

[0104] refer to Figure 2 and 10 The second low-k dielectric material layer ( Figure 9 105) can be planarized by a second planarization process to form a planarized second low-k dielectric material layer 105a.

[0105] In an exemplary embodiment, the second planarization process may be a chemical mechanical polishing (CMP) process. However, the exemplary embodiments of the present invention are not limited thereto.

[0106] When the second low-k dielectric material layer 105 is planarized by the second planarization process, the second pattern structure 92a can also be planarized to form a planarized second pattern structure 92b. The upper conductor 78 of the second pattern structure 92a can be exposed, and the upper mask line 80 can be removed by the second planarization process.

[0107] Because the third curing process 110 and the fourth curing process 115 can be performed to significantly reduce the volume reduction that occurs when the second flowable material layer 103 is formed into a rigidly cured second low-k dielectric material layer 105, the side surfaces of the second spacer layer 89 and the second stacked pattern 45b can be prevented from being peeled off by the second planarization process. Therefore, the defect rate of the semiconductor device can be reduced and the process productivity can be improved.

[0108] According to exemplary embodiments of the present invention, a method with... Figure 10 The semiconductor device shown has a structure that is referenced Figures 1 to 10 The described method for manufacturing semiconductor devices is formed. For example, having Figure 10 The semiconductor device with the structure shown above may include those described in the reference above. Figures 1 to 10 The described method forms the component (assembly). Therefore, from the reference... Figures 1 to 10 The components formed by the described method allow for easy understanding of the structure of the semiconductor device.

[0109] As described above, exemplary embodiments of the present invention provide a method for manufacturing semiconductor devices, wherein a flowable material layer is transformed into a rigidly cured low-k dielectric material layer by sequentially performing a first curing process using an ammonia (NH3) catalyst gas and a second curing process at a temperature of about 100°C or higher. The volume reduction rate can be 2% or less when the flowable material layer is transformed into the low-k dielectric material layer. Such a low-k dielectric material layer can be formed in openings of a patterned structure. The patterned structure may include an electrode layer comprising carbon and spacer layers covering the side surfaces of the electrode layers. Since the volume reduction that occurs when the flowable material layer is transformed into the low-k dielectric layer can be significantly reduced, defects caused by peeling between the electrode layer and the spacer layers can be prevented. As a result, the productivity of the semiconductor device can be improved.

[0110] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, comprising: forming a first pattern structure having a first opening on an understructure including a semiconductor substrate, the first pattern structure including a stack pattern and a first spacer layer covering at least one lateral side surface of the stack pattern; forming a first flowable material layer on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure, the first flowable material layer including a SiOCH material; performing a first curing process on the first flowable material layer to form a first cured material layer including water (H2O), the performing a first curing process including supplying a gaseous ammonia (NH3) catalyst into the first flowable material layer, the first curing process configured to cause the first flowable material layer to cure while generating water (H2O) in the first flowable material layer; performing a second curing process on the first cured material layer to form a first low-k dielectric material layer having a dielectric constant lower than that of silicon dioxide, the second curing process configured to evaporate water (H2O) in the first cured material layer outwardly from the first cured material layer; and planarizing the first low-k dielectric material layer using a first chemical mechanical polishing process to form a planarized first low-k dielectric material layer.

2. The method of claim 1, wherein: the first curing process is performed at a temperature below 100 °C at which water (H2O) generated in the first flowable material layer is not evaporated; and the second curing process is performed at a temperature of 100 °C or higher at which water (H2O) in the first cured material layer is evaporated outwardly from the first cured material layer.

3. The method of claim 2, wherein: the stack pattern includes an electrode layer, the electrode layer including a carbon-containing material layer; a first portion of the first spacer layer is formed between a lateral side surface of the electrode layer and the first flowable material layer; and the first portion of the first spacer layer includes at least two layers.

4. The method of claim 2, wherein: the stack pattern includes an electrode layer, the electrode layer including a carbon layer; a first portion of the first spacer layer is formed between a lateral side surface of the electrode layer and the first flowable material layer; and the first portion of the first spacer layer includes at least two layers.

5. The method of claim 3 or 4, wherein: the stack pattern further includes an amorphous phase change material layer; and a temperature at which the second curing process is performed is configured to maintain an amorphous phase of the amorphous phase change material layer.

6. The method of claim 1, wherein a volume reduction rate when the first flowable material layer is formed into the first cured material layer by the first curing process is greater than a volume reduction rate when the first cured material layer is formed into the first low-k dielectric material layer by the second curing process.

7. The method of claim 1, wherein: ​ ​ ​ the first flowable material layer includes a SiOCH material formed using octamethylcyclotetrasiloxane as a precursor; and the SiOCH material of the first flowable material layer has a chemical formula 1: 。 <Chemical Formula 1> 8. The method of claim 1, wherein: the first flowable material layer includes a SiOCH material formed using octamethylcyclotetrasiloxane as a precursor and at least one compound selected from tetramethyl orthosilicate and tetraethyl orthosilicate as an additive; and the SiOCH material of the first flowable material layer has a chemical formula 1: 。 <Chemical Formula 1> 9. The method of claim 7 or 8, wherein: the SiOCH material of the first flowable material layer forms siloxane bonds in the first curing process to form the first cured material layer; and the first cured material layer has a chemical formula 2: 。 <Chemical Formula 2> 10. The method of claim 9, wherein: hydrogen (H) of the first cured material layer is removed in the second curing process to form a SiOC material in the first low-k dielectric material layer; and the SiOC material of the first low-k dielectric material layer has a backbone represented by a chemical formula 3: 。 <Chemical Formula 3> 11. The method of claim 1, wherein: a planarized first pattern structure is formed from the first pattern structure by performing the first chemical mechanical polishing process; the method further includes: forming upper wiring lines and upper mask lines on the planarized first pattern structure and the planarized first low-k dielectric material layer, wherein the upper wiring lines and the upper mask lines are sequentially stacked on the planarized first pattern structure and the planarized first low-k dielectric material layer; forming a second pattern structure having second openings, wherein forming a second pattern structure includes: etching the planarized first pattern structure and the planarized first low-k dielectric material layer by an etching process using the upper wiring lines and the upper mask lines as etching masks, the planarized first pattern structure and the planarized first low-k dielectric material layer being etched to form a patterned first pattern structure and a patterned first low-k dielectric material layer, respectively, and forming a second spacer layer covering at least one side surface of the patterned first pattern structure; forming a second flowable material layer to fill the second openings and cover an upper portion of the second pattern structure, the second flowable material layer being formed of a same material as the first flowable material layer; performing a third curing process on the second flowable material layer to form a second cured material layer including water (H2O), the performing a third curing process including supplying a gaseous ammonia (NH3) catalyst into the second flowable material layer, the third curing process being configured to cause the second flowable material layer to cure while generating water (H2O) in the second flowable material layer and preventing water (H2O) from evaporating outward from the second flowable material layer; performing a fourth curing process on the second cured material layer to form a second low-k dielectric material layer having a dielectric constant lower than a dielectric constant of silicon dioxide, the fourth curing process configured to evaporate water (H2O) in the second cured material layer outward from the second cured material layer; and planarizing the second low-k dielectric material layer using a second chemical mechanical polishing process to form a planarized second low-k dielectric material layer.

12. The method of claim 11, wherein the lower structure further comprises a lower insulating layer on the semiconductor substrate, lower conductive lines on the lower insulating layer, and an interstitial insulating pattern between the lower conductive lines, wherein the lower conductive lines extend in a first direction parallel to an upper surface of the semiconductor substrate, and wherein the upper conductive lines extend in a second direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction.

13. The method of claim 1, wherein: the stack pattern comprises a lower electrode layer, a selector material layer, a first intermediate electrode material layer, a second intermediate electrode material layer, a data storage material layer, a first upper electrode material layer, and a second upper electrode material layer sequentially stacked on the lower structure; and the first spacer layer comprises: an inner spacer layer covering lateral side surfaces of each of the data storage material layer, the first upper electrode material layer, and the second upper electrode material layer; and an outer spacer layer covering outer side surfaces of the inner spacer and extending downward to cover side surfaces of each of the second intermediate electrode material layer, the first intermediate electrode material layer, the selector material layer, and the lower electrode layer.

14. The method of claim 13, wherein: the second upper electrode material layer is formed from a carbon-containing material layer; and the inner spacer layer is in direct contact with side surfaces of the second upper electrode material layer.

15. The method of claim 13, wherein: the second upper electrode material layer is formed from a carbon layer; and the inner spacer layer is in direct contact with side surfaces of the second upper electrode material layer.

16. The method of claim 1, wherein the second curing process comprises using at least one of an ultraviolet process and an ammonia catalyst process; wherein the ultraviolet process comprises irradiating ultraviolet light to a surface of the first cured material layer, and wherein the ammonia catalyst process comprises supplying an ammonia catalyst gas to the surface of the first cured material layer.

17. The method of claim 1, wherein: the first curing process is performed at a first pressure lower than atmospheric pressure; and the second curing process is performed at a second pressure lower than atmospheric pressure and higher than the first pressure.

18. A method for fabricating a semiconductor device, comprising: forming a structure having an opening on a lower structure; forming a flowable material layer to fill the opening and cover an upper portion of the structure; performing a first curing process on the flowable material layer to form a cured material layer, wherein water (H2O) is generated in the cured material layer during the first curing process; performing a second curing process on the cured material layer to form a low-k dielectric material layer having a dielectric constant lower than that of silicon dioxide, wherein water (H2O) is evaporated during the second curing process; and planarizing the low-k dielectric material layer to form a planarized low-k dielectric material layer in the opening, wherein a volume reduction rate when the flowable material layer is formed into the cured material layer is greater than a volume reduction rate when the cured material layer is formed into the low-k dielectric material layer.

19. The method according to claim 18, wherein a volume reduction rate when the flowable material layer is formed into the low-k dielectric material layer by the first curing process and the second curing process is 2% or less.

20. The method according to claim 18, wherein the structure having an opening includes a pattern structure and a spacer layer on at least one side surface of the pattern structure, the pattern structure includes an electrode layer including a carbon-containing material layer, an inner side surface of the spacer layer is in contact with a side surface of the electrode layer, and the low-k dielectric material layer is in contact with an outer side surface of the spacer layer.

21. The method according to claim 18, wherein the structure having an opening includes a pattern structure and a spacer layer on at least one side surface of the pattern structure, the pattern structure includes an electrode layer including a carbon layer, an inner side surface of the spacer layer is in contact with a side surface of the electrode layer, and the low-k dielectric material layer is in contact with an outer side surface of the spacer layer.

22. The method according to claim 20, wherein: the spacer layer includes an inner spacer layer and an outer spacer layer; the inner spacer layer covers a side surface of the pattern structure, the outer spacer layer extends to a lower surface of the opening while covering an upper surface of the inner spacer layer and the pattern structure, and a portion of the outer spacer layer disposed on the pattern structure is removed while planarizing the low-k dielectric material layer.

23. The method according to claim 18, wherein the second curing process includes at least one of a UV process and an ammonia catalyst process; wherein the UV process includes irradiating UV light to a surface of the cured material layer, and wherein the ammonia catalyst process includes supplying an ammonia catalyst gas to a surface of the cured material layer.

24. The method according to claim 18, wherein: the first curing process is performed at a first pressure lower than an atmospheric pressure; and the second curing process is performed at a second pressure lower than the atmospheric pressure and higher than the first pressure.

25. A method for manufacturing a semiconductor device, comprising: forming a flowable material layer on a lower structure; performing a first curing process by supplying an ammonia (NH3) catalyst gas into the flowable material layer at a temperature of 23°C or higher and lower than 100°C to form a cured material layer; and performing a second curing process on the cured material layer at a temperature of 100°C or higher to form a low-k dielectric material layer having a dielectric constant lower than that of silicon dioxide, ​ wherein the flowable material layer comprises a SiOCH material, wherein water (H2O) is generated during the first curing process, wherein the water (H2O) generated during the first curing process is included in the cured material layer, wherein the water (H2O) in the cured material layer is evaporated and removed during the second curing process, and wherein the hydrogen (H) in the cured material layer is removed in the second curing process to form a low-k dielectric material layer of SiOC material.

26. The method of claim 25, wherein: the flowable material layer has Chemical Formula 1: <Chemical Formula 1> the cured material layer has Chemical Formula 2: <Chemical Formula 2> , and the low-k dielectric material layer has Chemical Formula 3: <Chemical Formula 3> 。 27. The method of claim 25, wherein the second curing process comprises at least one of a UV process and an ammonia catalyst process; wherein the UV process comprises irradiating UV light to a surface of the cured material layer, and wherein the ammonia catalyst process comprises supplying an ammonia catalyst gas to a surface of the cured material layer.

28. The method of claim 25, wherein: the first curing process is performed at a first pressure that is lower than atmospheric pressure; and the second curing process is performed at a second pressure that is lower than atmospheric pressure and higher than the first pressure.

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