Semiconductor device and method of forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The method for forming the same includes: providing a substrate, on which an interlayer dielectric layer is provided; etching the interlayer dielectric layer to form a contact hole, the contact hole exposing the surface of the substrate; forming a barrier layer on the substrate within the contact hole; forming a metal layer on the barrier layer, and the metal layer filling the contact hole. In the present invention, ions in the barrier layer can preferably adsorb such ions with relatively large electronegativity. Therefore, the barrier layer can effectively prevent the diffusion of ions with relatively large electronegativity, thereby avoiding the diffusion of ions with relatively large electronegativity, reducing damage to the semiconductor device, and improving the performance of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor devices, they are currently widely used. The control ability of traditional planar devices for channel current becomes weak, resulting in short-channel effects and leakage current, ultimately affecting the electrical performance of semiconductor devices.

[0003] During the manufacturing process of semiconductor devices, contact holes need to be formed on the source region, drain region, or gate structure of transistors, etc., and then a metal layer is filled in the contact holes to form metal plugs, so that components such as transistors form electrical connections with the interconnect metal layer through the metal plugs. When filling the metal layer in the contact holes to form metal plugs, however, there is damage to the semiconductor devices under the contact holes caused by diffused ions during the filling of the metal layer, thus affecting the quality of the formed semiconductor devices.

[0004] How to form semiconductor devices with good quality is an urgent problem to be solved currently. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, ensuring that the formed semiconductor device has high quality.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, on which an interlayer dielectric layer is provided; etching the interlayer dielectric layer to form a contact hole, the contact hole exposing the surface of the substrate; forming a barrier layer on the substrate in the contact hole; forming a metal layer on the barrier layer, and the metal layer filling the contact hole.

[0007] Optionally, the material of the barrier layer is cobalt or tantalum.

[0008] Optionally, the method for forming the barrier layer is selective growth method, chemical vapor deposition method or atomic layer deposition method.

[0009] Optionally, the method for forming the contact hole is dry etching or wet etching.

[0010] Optionally, the material of the metal layer is tungsten.

[0011] Optionally, the method for forming the metal layer includes one or more of chemical vapor deposition method, selective growth method or atomic layer vapor deposition method.

[0012] Optionally, the step of forming the metal layer includes: forming a first metal layer in the contact hole by selective growth; forming a second metal layer on the first metal layer and the interlayer dielectric layer by chemical vapor deposition; planarizing the first metal layer and the second metal layer until the surface of the interlayer dielectric layer is exposed.

[0013] Optionally, before forming the barrier layer, it further includes: forming a reactive metal layer on the bottom, sidewalls of the contact hole and the surface of the interlayer dielectric layer; forming a diffusion barrier layer on the surface of the reactive metal layer.

[0014] Optionally, before forming the barrier layer, it further includes: removing the diffusion barrier layer and the unreacted reactive metal layer.

[0015] Correspondingly, the present invention further provides a semiconductor device, including: a substrate; an interlayer dielectric layer located on the substrate; a contact hole located in the interlayer dielectric layer and exposing the surface of the substrate; a barrier layer located on the substrate in the contact hole; a metal layer located on the barrier layer in the contact hole and filling the contact hole.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] Before filling the metal layer in the contact hole, a barrier layer is first formed at the bottom of the contact hole, and then a metal layer is formed on the barrier layer. The barrier layer is used to block the diffusion of ions. This is because during the process of forming the metal layer, ions with a relatively large electronegativity are likely to be generated. The ions in the barrier layer can preferably adsorb such ions with a relatively large electronegativity. Therefore, the barrier layer can effectively block the diffusion of ions with a relatively large electronegativity, thereby avoiding the diffusion of ions with a relatively large electronegativity and reducing damage to the semiconductor device, so as to improve the performance of the formed semiconductor device. Description of the Drawings

[0018] Figures 1 to 4 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment;

[0019] Figures 5 to 10 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0020] During the formation process of a semiconductor device, it is necessary to fill a metal layer in the contact hole to form a metal plug. However, currently, during the process of filling the metal layer, it is easy to cause damage to the semiconductor device under the contact hole, resulting in a poor yield and poor performance stability of the formed semiconductor device. For the specific formation process, refer to Figures 1 to 4 .

[0021] First, refer to Figure 1 , a base 1 is provided, and an interlayer dielectric layer 2 is formed on the base 1.

[0022] Refer to Figure 2 , etch the interlayer dielectric layer 2 to form a contact hole 3 in the dielectric 2.

[0023] Refer to Figure 3 , a reactive metal layer 4 and a diffusion barrier layer 5 are sequentially formed on the bottom, sidewall of the contact hole 3, and the surface of the interlayer dielectric layer 2.

[0024] A silicide layer 41 is formed between the reactive metal layer 4 and the surface of the base 1.

[0025] Refer to Figure 4 , a metal layer 6 is filled in the contact hole 3 to form a metal plug, and the top surface of the metal layer 6 is flush with the top surface of the diffusion barrier layer 5.

[0026] The inventors found that the stability of the performance of semiconductor devices formed by this method is poor, and phenomena such as failure are likely to occur, which limits the use of semiconductor devices. This is because the formed metal layer 6 contains easily diffusible F ions, which damage the silicide layer 41 under the contact hole 3. At the same time, the F ions also damage the unreacted reactive metal layer 4, resulting in poor performance stability of the formed semiconductor devices.

[0027] The inventors' research found that before filling the metal layer in the contact hole, a barrier layer is first formed at the bottom of the contact hole, and the barrier layer is used to block the diffusion of F ions in the metal layer, effectively preventing the diffusion of F ions, thereby reducing the damage to the silicide layer and the like, and improving the quality and performance of the formed semiconductor devices.

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0029] Figures 5 to 10 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention.

[0030] First, refer to Figure 5 , provide the base 100, and the base 100 has an interlayer dielectric layer 200.

[0031] In this embodiment, the base 100 includes a substrate, and storage devices, logic devices, etc. are located on the substrate.

[0032] In this embodiment, the material of the interlayer dielectric layer 200 is silicon oxide.

[0033] In other embodiments, the material of the interlayer dielectric layer 200 may also be silicon nitride, silicon boron nitride, silicon carbon oxynitride, silicon oxynitride, etc.

[0034] In this embodiment, the interlayer dielectric layer 200 is formed on the substrate 100 by chemical vapor deposition. The process parameters of the chemical vapor deposition process include that the gases used include oxygen, ammonia (NH3), and N(SiH3)3 gas. The flow rate of oxygen is 20 sccm to 10000 sccm, the flow rate of ammonia (NH3) gas is 20 sccm to 10000 sccm, the flow rate of N(SiH3)3 gas is 20 sccm to 10000 sccm, the chamber pressure is 0.01 to 10 Torr, and the temperature is 30 °C to 90 °C.

[0035] Reference Figure 6 Then, the interlayer dielectric layer 200 is etched to form a contact hole 210 in the interlayer dielectric layer 200, and the bottom of the contact hole 210 exposes the surface of the substrate 100.

[0036] In this embodiment, the contact hole 210 is formed by a dry etching process; the parameters of the dry etching process include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20 sccm to 200 sccm, the flow rate of CH3F is 20 sccm to 50 sccm, the source radio frequency power is 200 watts to 500 watts, and the chamber pressure is 1 Torr to 10 Torr.

[0037] In other embodiments, the contact hole 210 may also be formed by a wet etching process.

[0038] Reference Figure 7 Then, a diffusion barrier layer 220 is formed on the bottom, sidewalls of the contact hole 210, and the interlayer dielectric layer 200.

[0039] In this embodiment, before forming the diffusion barrier layer 220, a reactive metal layer 240, such as a Ti layer, etc., is further formed on the bottom, sidewalls of the contact hole 210, and the interlayer dielectric layer 200. The reactive metal layer 240 reacts with the substrate 100 to form a silicide layer 230.

[0040] In this embodiment, the silicide layer 230 is formed by a directed self-assembly (DSA) process, and the silicide layer 230 is formed during the heat treatment process.

[0041] In this embodiment, the material of the diffusion barrier layer 220 is TiN; in other embodiments, the material of the diffusion barrier layer 220 may also be TaN, etc.

[0042] In this embodiment, the purpose of forming the diffusion barrier layer 220 on the surface of the reactive metal layer 240 is to prevent the reactive metal layer 240 from being oxidized during the formation of the silicide layer 230, resulting in defects such as holes in the formed silicide layer 230 and affecting the performance of the formed semiconductor device.

[0043] Reference Figure 8 , the diffusion barrier layer 220 and the unreacted reactive metal layer 240 are removed.

[0044] In this embodiment, the purpose of removing the diffusion barrier layer 220 and the unreacted reactive metal layer 240 is to reduce the contact resistance between the subsequently formed barrier layer and the silicide layer 230 and reduce phenomena such as easy heating during the use of the semiconductor device; at the same time, since the diffusion barrier layer 220 and the unreacted reactive metal layer 240 are removed, the volume of the metal layer filled in the contact hole 210 is also increased subsequently.

[0045] In this embodiment, the diffusion barrier layer 220 and the unreacted reactive metal layer 240 are removed by wet etching.

[0046] Reference Figure 9 , the barrier layer 300 is filled in the contact hole 210.

[0047] In this embodiment, the diffusion barrier layer 220 and the unreacted reactive metal layer 240 are removed before forming the barrier layer 300; in other embodiments, the diffusion barrier layer 220 and the unreacted reactive metal layer 240 may not be removed before forming the barrier layer 300.

[0048] In this embodiment, the material of the barrier layer 300 is cobalt (Co); in other embodiments, the material of the barrier layer 300 may also be tantalum or the like.

[0049] In this embodiment, the barrier layer 300 is formed by selective growth; in other embodiments, the barrier layer 300 may also be formed by chemical vapor deposition or atomic layer vapor deposition.

[0050] In this embodiment, the reason for forming the barrier layer 300 by selective growth method is that, on the one hand, the barrier layer 300 formed by selective growth method has good compactness inside, which can play a good blocking role; on the other hand, the barrier layer 300 formed by selective growth method grows from the bottom of the contact hole 210, and has little influence on the size of the formed contact hole 210. In this way, it is convenient to fill more volume of metal layer in the contact hole 210 subsequently, so that the contact resistance of the formed semiconductor device is reduced and the performance of the formed semiconductor device is improved.

[0051] In this embodiment, before forming the barrier layer 300, the diffusion barrier layer 220 and the unreacted reaction metal layer 240 are removed. Since the diffusion barrier layer 220 and the unreacted reaction metal layer 240 have relatively large resistance, removing the diffusion barrier layer 220 and the unreacted reaction metal layer 240 can reduce the contact resistance of the formed semiconductor device.

[0052] In other embodiments, the diffusion barrier layer 220 and the unreacted reaction metal layer 240 may not be removed, and the barrier layer 300 is formed on the bottom and side walls of the diffusion barrier layer 220. The formed barrier layer 300 can not only block the diffusion of F ions and avoid damage to the silicide layer 230 and the unreacted reaction metal layer 240; but also use the selective growth method to make the barrier layer 300 grow from the bottom of the diffusion barrier layer 220 and gradually grow on the side walls, ensuring that the opening size of the contact hole 210 changes little during the formation of the barrier layer 300, so as not to affect the subsequent filling of the metal layer.

[0053] In this embodiment, the process parameters for forming the barrier layer 300 include: the organic source is CODCP, the reaction gases include hydrogen (H2), ammonia (NH3) and argon (Ar), where the flow rate of hydrogen (H2) is 1000 - 8000 sccm, the flow rate of ammonia (NH3) is 1000 - 5000 sccm, and the gas flow rate of argon (Ar) is 10 - 500 sccm; the source radio frequency power is 100 - 2000 watts, the temperature is 100 - 400 °C, and the pressure is 10 - 40 torr.

[0054] In this embodiment, the thickness of the barrier layer 300 is 20 - 100 angstroms; when the thickness of the barrier layer 300 is less than 20 angstroms, the formed barrier layer 300 cannot play a good role in blocking ion diffusion; when the thickness of the barrier layer 300 is greater than 100 angstroms, the thickness of the formed barrier layer 300 is relatively thick, resulting in a reduction in the volume of the subsequently formed metal layer.

[0055] ReferenceFigure 10 , a metal layer 400 is formed on the barrier layer 300, and the metal layer 400 fills the contact hole 210.

[0056] In this embodiment, the material of the metal layer 400 is tungsten (W).

[0057] In this embodiment, the metal layer 400 is formed by a method combining selective growth and chemical vapor deposition.

[0058] In other embodiments, the metal layer 400 can also be formed by chemical vapor deposition and planarized to form metal plugs.

[0059] In this embodiment, after the metal layer 400 is formed, the metal layer 400 is planarized until the surface of the interlayer dielectric layer 200 is exposed.

[0060] Reference Figures 10a to 10b The step of forming the metal layer 400 includes specifically referring to Figure 10a , first, a first metal layer 410 that fills the contact hole 210 is formed by selective growth, and the top of the first metal layer 410 is higher than the surface of the interlayer dielectric layer 200.

[0061] Reference Figure 10b , a second metal layer 420 is formed on the surface of the interlayer dielectric layer 200 by chemical vapor deposition.

[0062] In this embodiment, before the second metal layer 420 is formed, an adhesion layer 250 is formed on the surface of the interlayer dielectric layer 200. The function of the adhesion layer 250 is to facilitate better adhesion of the formed second metal layer 420 to the interlayer dielectric layer 200 and prevent peeling during subsequent planarization.

[0063] After the first metal layer 410 and the second metal layer 420 are formed, the surfaces of the first metal layer 410 and the second metal layer 420 are planarized by chemical mechanical polishing until the surface of the interlayer dielectric layer 200 is exposed (reference Figure 10 ).

[0064] In this embodiment, the reason for forming the metal layer 400 by combining the selective growth method and the chemical vapor deposition method is that the first metal layer 410 is first formed by the selective growth method, so that the formed first metal layer 410 has a high density inside. In addition, the first metal layer 410 is formed by the selective growth method from the bottom of the contact hole 210 upwards, and the first metal layer 410 is formed in the contact hole 210 at one time, reducing the damage to the formed components. In addition, the second metal layer 420 is formed by chemical vapor deposition, aiming to provide an extra part for planarizing the metal layer 400, so as to facilitate the formation of the metal layer 400 with good surface quality.

[0065] Since ions with relatively large electronegativity, such as F ions, are easily generated during the formation of the metal layer 400, these F ions are prone to diffusion, thereby damaging the silicide layer 230 and reducing the performance of the formed semiconductor device.

[0066] In this embodiment, before forming the metal layer 400, the barrier layer 300 is formed at the bottom of the contact hole 210. By using the adsorption effect of the ions inside the barrier layer 300 on F ions, the diffusion of F ions is effectively blocked, reducing the damage of F ions to the silicide layer 230. At the same time, the formed barrier layer 300 is grown from the bottom of the contact hole 210 to the sidewall by the selective growth method, so that the size of the contact hole 210 changes very little during the formation of the barrier layer 300, increasing the volume of the formed metal layer 400 and thus improving the performance of the formed semiconductor device.

[0067] A semiconductor device formed by using the above method includes: a substrate 100; an interlayer dielectric layer 200 located on the substrate 100; a contact hole 210 located in the interlayer dielectric layer 200 and exposing the surface of the substrate 100 at the bottom; a silicide layer 230 located on the substrate 100 at the bottom of the contact hole 210; a barrier layer 300 located on the substrate 100 in the contact hole 210; and a metal layer 400 located on the barrier layer 300 in the contact hole 210 and filling the contact hole 210.

[0068] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate, on which an interlayer dielectric layer is provided; Etching the interlayer dielectric layer to form a contact hole, the contact hole exposing the surface of the substrate, and F being contained in the process of forming the contact hole; Forming a reactive metal layer on the bottom, sidewalls and surface of the interlayer dielectric layer of the contact hole; Forming a diffusion barrier layer on the surface of the reactive metal layer; Removing the diffusion barrier layer and the unreacted reactive metal layer; Forming a barrier layer on the substrate within the contact hole; Forming a metal layer on the barrier layer, and the metal layer filling the contact hole; The material of the barrier layer is cobalt or tantalum, and the barrier layer is located at the bottom of the contact hole.

2. The forming method according to claim 1, characterized in that, The method for forming the barrier layer is selective growth method or chemical vapor deposition method or atomic layer deposition method.

3. The forming method according to claim 1, characterized in that, The method for forming the contact hole is dry etching or wet etching.

4. The forming method according to claim 1, characterized in that, The material of the metal layer is tungsten.

5. The forming method according to claim 1, characterized in that, The method for forming the metal layer includes one or more of chemical vapor deposition method, selective growth method or atomic layer vapor deposition method.

6. The forming method according to claim 5, characterized in that, The steps for forming the metal layer include: Forming a first metal layer in the contact hole by selective growth method; Forming a second metal layer on the first metal layer and the interlayer dielectric layer by chemical vapor deposition method; Planarizing the first metal layer and the second metal layer until the surface of the interlayer dielectric layer is exposed.

7. A semiconductor device formed by the forming method according to any one of claims 1-6, characterized in that, Comprising: Substrate; Interlayer dielectric layer, located on the substrate; Contact hole, located in the interlayer dielectric layer and exposing the surface of the substrate; Barrier layer, located on the substrate within the contact hole, and the material of the barrier layer is cobalt or tantalum; Metal layer, located on the barrier layer within the contact hole and filling the contact hole.

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