Semiconductor packaging including image sensor chips

Abstract

A semiconductor package may include: an image sensor chip; a transparent substrate spaced apart from the image sensor chip; a bonding structure contacting the top surface of the image sensor chip and the bottom surface of the transparent substrate at an edge region of the top surface of the image sensor chip; and a circuit board electrically connected to the image sensor chip. The image sensor chip may include: a through-electrode penetrating at least a portion of the interior of the image sensor chip; and terminal pads located at an edge region of the top surface of the image sensor chip and connected to the through-electrode. The bonding structure may include: a spacer; and an adhesive layer between and attached to the spacer and the image sensor chip. The bonding structure may overlap with the terminal pads.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0099478, filed on August 14, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a semiconductor package, and more specifically, to a semiconductor package including an image sensor chip. Background Technology

[0004] Image sensors (such as charge-coupled device (CCD) sensors or complementary metal-oxide-semiconductor (CIS) image sensors) are used in a variety of electronic products, such as mobile phones, digital cameras, optical mice, security cameras, and / or biometric devices. Due to the growing demand for small and multifunctional electronic products, semiconductor packages, including image sensors, may require improved technical attributes (e.g., small size, high density, low power consumption, multifunctionality, high signal processing speed, high reliability, low cost, and / or clear image quality). Research is underway to achieve these technical attributes in semiconductor packages. Summary of the Invention

[0005] Some embodiments of the present invention provide a small-size semiconductor package.

[0006] Some embodiments of the present invention provide a highly reliable semiconductor package.

[0007] According to some embodiments of the present invention, a semiconductor package may include: an image sensor chip; a transparent substrate spaced apart from the image sensor chip; a bonding structure contacting the top surface of the image sensor chip and the bottom surface of the transparent substrate at an edge region of the top surface of the image sensor chip; and a circuit board electrically connected to the image sensor chip. The image sensor chip may include: a through-electrode penetrating at least a portion of the interior of the image sensor chip; and terminal pads located at an edge region of the top surface of the image sensor chip and connected to the through-electrode. The bonding structure may overlap with the terminal pads.

[0008] According to some embodiments of the present invention, a semiconductor package may include an image sensor chip comprising a pixel region and a peripheral region, the peripheral region surrounding the pixel region in a planar view. Microlenses and color filters may be located on the image sensor chip. The semiconductor package may include: a transparent substrate on the image sensor chip; a bonding structure in the peripheral region, the bonding structure connecting the image sensor chip to the transparent substrate; a circuit board electrically connected to the image sensor chip; an insulating layer between the image sensor chip and the circuit board; and a reinforcing substrate contacting the bottom surface of the circuit board and overlapping at least the pixel region in a direction substantially perpendicular to the image sensor chip. The bonding structure may include: spacers; and an adhesive layer between the spacers and the image sensor chip.

[0009] According to some embodiments of the present invention, a semiconductor package may include: a transparent substrate including an infrared cutoff filter; a circuit board spaced apart from the transparent substrate in a first direction perpendicular to the bottom surface of the transparent substrate; an image sensor chip between the transparent substrate and the circuit board, the image sensor chip including a microlens array and a color filter array on a central region of its top surface; terminal pads on an edge region of the top surface of the image sensor chip; a through electrode penetrating the image sensor chip and connected to the terminal pads; a connection structure electrically connecting the through electrode to the circuit board; and a bonding structure on an edge region of the top surface of the image sensor chip and in contact with the bottom surface of the transparent substrate and the top surface of the image sensor chip. The bonding structure may include: a spacer; and an adhesive layer between the image sensor chip or the transparent substrate and the spacer. The width of the bonding structure in a second direction perpendicular to the first direction may be greater than the width of the terminal pads in the second direction. Attached Figure Description

[0010] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0011] Figure 1 This is a schematic plan view of a semiconductor package according to some embodiments of the present invention.

[0012] Figures 2 to 5 It is along Figure 1 The cross-sectional views are taken along line I-I', and each cross-sectional view illustrates a semiconductor package according to some embodiments of the concept of the present invention.

[0013] Figures 6 to 10 It shows Figures 2 to 5 An enlarged cross-sectional view of part "A" shown in the diagram.

[0014] Figures 11A to 11D It shows the manufacturing process. Figure 6A cross-sectional view of the method for joining structures.

[0015] Figure 12A and Figure 12B It shows the manufacturing process. Figure 7 A cross-sectional view of the method for joining structures.

[0016] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in certain exemplary embodiments and to supplement the written description provided below. However, these figures may not necessarily be drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as defining or limiting the range of values ​​or properties contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0017] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0018] Figure 1 This is a schematic plan view of a semiconductor package according to some embodiments of the present invention. Figure 2 It is along Figure 1 The cross-sectional view taken by line I-I' is used to illustrate a semiconductor package according to some embodiments of the concept of the present invention.

[0019] refer to Figure 1 and Figure 2 According to some embodiments of the present invention, a semiconductor package 10 may include: an image sensor chip SC; a transparent substrate 200 disposed on the image sensor chip SC; and a circuit board 300 electrically connected to the image sensor chip SC. The image sensor chip SC, the transparent substrate 200, and the circuit board 300 may be disposed parallel to a plane perpendicular to a first direction D1. When viewed in cross-sectional view, the image sensor chip SC and the transparent substrate 200 may have substantially the same width in a second direction D2 perpendicular to the first direction D1. When measured in the second direction D2, the width of the circuit board 300 may be greater than the width of the image sensor chip SC and / or the transparent substrate 200.

[0020] The image sensor chip SC may include a first surface SCt and a second surface SCb opposite to each other. The first surface SCt and the second surface SCb may be planes parallel to each other. The first surface SCt and the second surface SCb may be planes perpendicular to a first direction D1. The first surface SCt may include a pixel region PX and a peripheral region PE surrounding the pixel region PX. A microlens array MLA may be disposed on the pixel region PX of the first surface SCt. The microlens array MLA may include multiple hemispherical microlenses. A color filter array CFA may be disposed between the microlens array MLA and the image sensor chip SC. The color filter array CFA may include multiple color filters. For example, the color filter array CFA may have a structure that arranges a red color filter, a blue color filter, and two green color filters in a unit area, a structure that arranges the individual color filters in a 2x2 arrangement, and / or a structure that arranges the individual color filters in a 3x3 arrangement. The microlenses of the microlens array MLA and the color filters of the color filter array CFA may be arranged on a plane perpendicular to the first direction D1.

[0021] In some embodiments, the image sensor chip SC may include a through-silicon via (TSV) or a through-silicon via (TSV). The through-silicon via (TSV) may be configured to overlap with the peripheral region PE. The through-silicon via (TSV) may be configured to be parallel to a first direction D1. The through-silicon via (TSV) may be configured to penetrate at least a portion of the image sensor chip SC. The through-silicon via (TSV) may be formed of or include at least one metallic material (e.g., copper (Cu), aluminum (Al), and / or tungsten (W)). The through-silicon via (TSV) may be electrically connected to a terminal pad TP on a first surface SCt and a top conductive pad TCP on a second surface SCb. Although in Figures 2 to 5 Two through-electrode TSVs are shown, but the number of through-electrode TSVs extending from the top conductive pad TCP to penetrate at least a portion of the image sensor chip SC can be greater than two.

[0022] Although not shown, the image sensor chip SC may also include a logic chip. The logic chip may include circuitry for operating the image sensor chip SC. In some embodiments, the image sensor chip SC may include a structure in which doped semiconductor layers and insulating layers are stacked. Multiple electrodes and multiple plugs may be disposed in the insulating layer. Additionally, the image sensor chip SC may include pixels located directly beneath the first surface SCt and configured to face the color filter. Pixels may be disposed in a pixel region PX. Pixels may be separated from each other by a device isolation layer. The device isolation layer may have a grid shape. Each pixel may include a photoelectric conversion component disposed therein. The photoelectric conversion component may be doped to have a conductivity type different from that of its adjacent semiconductor layers. Furthermore, a protective layer and / or a fixed charge layer may also be disposed on the first surface SCt of the image sensor chip SC.

[0023] A transparent substrate 200 may be configured to be adjacent to a first surface SCt of an image sensor chip SC. A bottom surface 200b of the transparent substrate 200 may be parallel to the first surface SCt of the image sensor chip SC. The transparent substrate 200 may be formed of or comprise a transparent polymer material (e.g., acrylic) or glass. The transparent substrate 200 may include an infrared (IR) cutoff filter. The IR cutoff filter may include multiple alternating deposited materials with different refractive indices. The transparent substrate 200 can block infrared light signals, thus improving image sharpness.

[0024] A bonding structure JS can be disposed between the image sensor chip SC and the transparent substrate 200. The bonding structure JS can be formed of or include an insulating material. The bonding structure JS can be formed of, for example, at least one of epoxy resin, polyimide, and / or photoresist. The bonding structure JS can prevent light reflected or secondary reflected by the peripheral region PE from incident into the pixel region PX. The bonding structure JS can be configured along the edge of the image sensor chip SC and can have a closed-loop shape. In other words, the bonding structure JS can be configured to overlap with the peripheral region PE. Due to the bonding structure JS, a cavity GAP can be formed between the transparent substrate 200 and the image sensor chip SC. The cavity GAP can be blocked from the outside by the bonding structure JS. In other words, the bonding structure JS can prevent external moisture or contaminating materials from entering the cavity GAP. Additionally, the bonding structure JS can suppress or prevent the image sensor chip SC from being affected by temperature changes in the adjacent area.

[0025] The bonding structure JS can contact the first surface SCt of the image sensor chip SC and the bottom surface 200b of the transparent substrate 200. The height of the bonding structure JS in the first direction D1 can be uniform. The bonding structure JS can have a first length L1 in the first direction D1. The bonding structure JS can have a second length L2 in the second direction D2. The first length L1 can be in the range of, for example, about 10 μm to 150 μm. The second length L2 can be in the range of, for example, about 30 μm to 450 μm. The bottom surface 200b of the transparent substrate 200 can be spaced apart from the first surface SCt of the image sensor chip SC by the first length L1. The bottom surface 200b of the transparent substrate 200 can be sufficiently spaced apart from the first surface SCt of the image sensor chip SC, thus suppressing image distortion caused by contaminating materials on the transparent substrate 200. The first length L1 can be greater than the sum of the heights of the microlens array MLA and the color filter array CFA in the first direction D1. Therefore, the transparent substrate 200 can be spaced apart from the microlens array MLA. In addition, cavity GAPs can be formed on pixel regions PX.

[0026] The bonding structure JS can be spaced apart from the microlens array MLA and the color filter array CFA in the second direction D2. When along... Figure 1 When viewed in a cross-section taken along line I-I', the bonding structure JS can be spaced apart from the microlens array MLA and the color filter array CFA by a third length L3 in the second direction D2. In some embodiments, the third length L3 can be in the range of about 20 μm to 300 μm. The smaller the second length L2 and the third length L3, the smaller the area of ​​the peripheral region PE. In other words, the smaller the second length L2 and the third length L3, the smaller the size of the semiconductor package 10. In addition, a portion of the outer surface 202 of the bonding structure JS can be aligned with the side surface 201 of the transparent substrate 200 and the side surface 203 of the image sensor chip SC. Since a portion of the outer surface 202 of the bonding structure JS, the side surface 201 of the transparent substrate 200, and the side surface 203 of the image sensor chip SC are aligned with each other, the area of ​​the peripheral region PE can be reduced.

[0027] The circuit board 300 can be arranged adjacent to the second surface SCb of the image sensor chip SC. The circuit board 300 can be provided in the form of a flexible thin film. The thickness of the circuit board 300 in the first direction D1 can be less than the thickness of the image sensor chip SC in the first direction D1. The circuit board 300 can be, for example, a chip-on-film (COF) substrate or a flexible printed circuit board (FPCB). Top conductive pads TCP, bottom conductive pads BCP, and solder balls SB can be disposed between the circuit board 300 and the image sensor chip SC. The top conductive pads TCP, bottom conductive pads BCP, and solder balls SB can be formed of or include at least one metallic material. The top conductive pads TCP can contact the second surface SCb of the image sensor chip SC, the through electrode TSV, and the solder balls SB. The bottom conductive pads BCP can contact the top surface of the circuit board 300 and the solder balls SB. The solder balls SB can contact the top conductive pads TCP and the bottom conductive pads BCP. The top conductive pads TCP, bottom conductive pads BCP, and solder balls SB can be disposed in the peripheral region PE and / or the pixel region PX. The image sensor chip SC and the circuit board 300 can be electrically connected to each other via the top conductive pad TCP, the bottom conductive pad BCP, and the solder ball SB.

[0028] An insulating layer IL can be disposed between the circuit board 300 and the image sensor chip SC. The insulating layer IL can surround or encapsulate the top conductive pad TCP, the bottom conductive pad BCP, and the solder balls SB. The insulating layer IL can be formed of, for example, epoxy resin or comprise epoxy resin. The insulating layer IL can have a single-layer or multi-layer structure. The width of the insulating layer IL in the second direction D2 can increase in the direction from the image sensor chip SC toward the circuit board 300. In other words, the side surface of the insulating layer IL can be tilted at an angle relative to the second surface SCb of the image sensor chip SC. According to some embodiments, the side surface of the insulating layer IL can be a curved surface.

[0029] A reinforcing substrate 400 can be disposed on the bottom surface of the circuit board 300 to support the circuit board 300. The reinforcing substrate 400 can support the circuit board 300, which has flexible properties, through the bottom surface of the circuit board 300. The reinforcing substrate 400 can be formed of, for example, stainless steel (SUS) or include SUS. The reinforcing substrate 400 can overlap with the pixel region PX and the peripheral region PE in a first direction D1, and can extend in a second direction D2. The reinforcing substrate 400 can protect the pixel region PX of the image sensor chip SC from external impacts. The reinforcing substrate 400 can help increase the overall structural stability of the semiconductor package 10.

[0030] In some embodiments of the semiconductor package 10 conceived according to the present invention, the pads for wire bonding may not be provided on the first surface SCt of the image sensor chip SC. The image sensor chip SC and the circuit board 300 can be connected to each other in a flip-chip bonding manner using through electrodes TSV and solder balls SB instead of the pads for wire bonding. Therefore, the transparent substrate 200 can be attached to the image sensor chip SC, and no additional space for wire bonding is required. More specifically, the transparent substrate 200 can be directly attached to the image sensor chip SC, thus reducing the first length L1. In addition, no additional space for wire bonding is required, thus reducing the second length L2 and the third length L3. This can reduce the overall height and area of ​​the semiconductor package 10.

[0031] Figure 3 It is along Figure 1 The cross-sectional view taken by line I-I' is used to illustrate a semiconductor package according to some embodiments of the concept of the present invention.

[0032] refer to Figure 3 In some embodiments of the present invention, the semiconductor package 20 may include conductive bumps BP, instead of Figure 2 The top conductive pads TCP and solder balls SB. For brevity, refer to the previous section. Figures 1 to 2 The components described herein can be identified by similar or identical reference numerals, and will not be described in detail again.

[0033] The conductive bump BP can contact the second surface SCb of the image sensor chip SC and the bottom conductive pad BCP. In other words, the conductive bump BP can electrically connect the image sensor chip SC to the circuit board 300. The conductive bump BP can have a top surface coplanar with the second surface SCb of the image sensor chip SC. The width of the conductive bump BP in the second direction D2 can be increased in the first direction D1. The conductive bump BP can be formed of or include at least one metallic material. For example, the conductive bump BP can include gold (Au).

[0034] Figure 4 It is along Figure 1 The cross-sectional view taken by line I-I' is used to illustrate a semiconductor package according to some embodiments of the concept of the present invention.

[0035] refer to Figure 4 In some embodiments of the present invention, the semiconductor package 30 may include an anisotropic conductive film ACF, instead of Figure 2 Solder balls SB and insulation layer IL, or replace Figure 3 The conductive bump BP. For the sake of brevity, the previous reference... Figures 1 to 2The components described herein can be identified by similar or identical reference numerals, and will not be described in detail again.

[0036] An anisotropic conductive film (ACF) can be disposed between an image sensor chip (SC) and a circuit board (300). The ACF may include a plurality of conductive particles (CB) and an insulating resin (AL) in which the conductive particles (CB) are disposed. Each of the conductive particles (CB) can be shaped as a sphere, such as a circle or an ellipse. Although not shown, a thin insulating layer may also be disposed to cover or overlap the conductive particles (CB). The conductive particles (CB) may be unevenly dispersed in the insulating resin (AL). The conductive particles (CB) may be formed from, for example, at least one of carbon, nickel (Ni), or a nickel-gold alloy (Ni / Au), or include at least one of carbon, Ni, or Ni / Au. The conductive particles (CB) may be formed from or include lead-free or environmentally friendly materials. The insulating resin (AL) may be formed from, for example, at least one of styrene-butadiene rubber (SBR), polyethylene butene, polyurethane, acrylic resin, or epoxy resin, or include at least one of SBR, polyethylene butene, polyurethane, acrylic resin, or epoxy resin. When heat or pressure is applied to the anisotropic conductive film (ACF), the thin insulating layer of the conductive particles (CB) may break. Therefore, the anisotropic conductive film ACF can electrically connect the top conductive pad TCP to the bottom conductive pad BCP. In other words, the anisotropic conductive film ACF can electrically connect the image sensor chip SC to the circuit board 300.

[0037] In some embodiments, although not shown, a non-conductive film (NCF) may be provided instead of an anisotropic conductive film (ACF). The non-conductive film may not include conductive particles (CB). The non-conductive film may include conductive bumps that contact the top conductive pad (TCP). If heat or pressure is applied to the conductive bumps, the conductive bumps may contact the bottom conductive pad (BCP). Therefore, the non-conductive film can electrically connect the top conductive pad (TCP) to the bottom conductive pad (BCP). In other words, the non-conductive film can electrically connect the image sensor chip (SC) to the circuit board 300.

[0038] Figure 5 It is along Figure 1 The cross-sectional view taken by line I-I' is used to illustrate a semiconductor package according to some embodiments of the concept of the present invention.

[0039] refer to Figure 5 In some embodiments of the present invention, the semiconductor package 40 may include an image sensor chip SC having a stepped structure. For the sake of brevity, reference has been previously made to... Figures 1 to 2 The components described herein can be identified by similar or identical reference numerals, and will not be described in detail again.

[0040] The image sensor chip SC may include a protruding portion protruding in a direction opposite to the first direction D1. The protruding portion may be disposed within the pixel region PX. In other words, the thickness of the image sensor chip SC may be greater in the pixel region PX than in the peripheral region PE. The side surface of the protruding portion of the image sensor chip SC may be inclined at an angle relative to the first surface SCt of the image sensor chip SC. The circuit board 300 may have an opening, and a portion of the protruding portion may be disposed within the opening. The protruding portion may be spaced apart from the circuit board 300. The protruding portion may contact the reinforcing substrate 400.

[0041] More specifically, the image sensor chip SC may include a first surface SCt and a second surface SCb opposite to each other, a third surface SCm located between the first surface SCt and the second surface SCb, and inclined surfaces SCs connecting the second surface SCb to the third surface SCm. The first surface SCt, the second surface SCb, and the third surface SCm may be flat surfaces perpendicular to the first direction D1. Conversely, the inclined surfaces SCs may be flat surfaces inclined at an angle relative to the first direction D1 between the third surface SCm and the second surface SCb. The second surface SCb, the third surface SCm, and the inclined surfaces SCs may be connected to form a stepped structure. The image sensor chip SC with the stepped structure can be formed by an anisotropic etching process. The image sensor chip SC with the stepped structure can be formed relatively thickly between the transparent substrate 200 and the reinforcing substrate 400. Therefore, the structural stability of the image sensor chip SC can be improved.

[0042] The second surface SCb can contact the reinforcing substrate 400. More specifically, the second surface SCb can be coplanar with the top surface of the reinforcing substrate 400 and the bottom surface of the circuit substrate 300. The third surface SCm can be disposed between the circuit substrate 300 and the first surface SCt. More specifically, the third surface SCm can be coplanar with the bottom surface of the through electrode TSV and the top surface of the top conductive pad TCP. The width of the image sensor chip SC in the second direction D2 can increase in the direction from the second surface SCb towards the third surface SCm. The width of the image sensor chip SC in the second direction D2 can be uniform from the third surface SCm to the first surface SCt.

[0043] The circuit board 300 can be configured along the edge region of the image sensor chip SC. The circuit board 300 can be spaced apart from the inclined surfaces SCs of the image sensor chip SC. The circuit board 300 may not be located within the pixel region PX or a portion of the peripheral region PE. Top conductive pads TCP, bottom conductive pads BCP, and solder balls SB can be disposed on the circuit board 300 spaced apart from the inclined surfaces SCs. In other words, the circuit board 300 and the image sensor chip SC can be electrically connected to each other in the region spaced apart from the inclined surfaces SCs. Figures 2 to 4 Compared to the previous structure, the thickness of the image sensor chip SC in the first direction D1 may increase, but the total height of the semiconductor package 40 in the first direction D1 may not increase.

[0044] Figures 6 to 10 They are shown separately. Figures 2 to 5 An enlarged cross-sectional view of part "A" shown in the diagram.

[0045] The bonding structure JS may include an adhesive layer 530 and one or more spacers 510 and 520. Spacers 510 and 520 may be formed of or comprise at least one of polyimide or photoresist, for example. As an example, spacers 510 and 520 may include a dry film photoresist (DFR). Spacers 510 and 520 may be formed of or comprise at least one substantially identical material. The adhesive layer 530 may be formed of or comprise at least one of epoxy resin or other adhesive materials. The epoxy resin may be, for example, a B-stage epoxy resin. When heat or pressure is applied to the adhesive layer 530, the adhesive layer 530 may become fluid.

[0046] refer to Figure 6The bonding structure JS on the first surface SCt of the image sensor chip SC may include a first spacer 510, a second spacer 520, and an adhesive layer 530. The first spacer 510 may contact the bottom surface 200b of the transparent substrate 200. The first spacer 510 may include at least two patterns. The patterns of the first spacer 510 may be spaced apart from each other in a second direction D2. The second spacer 520 may be disposed between the first spacer 510 and the first surface SCt of the image sensor chip SC. The second spacer 520 may fill the gap region between the separated patterns of the first spacer 510. According to some embodiments, a portion of the bottom surface of the second spacer 520 may have a recessed shape. The adhesive layer 530 may be disposed between and attached to the first surface SCt of the image sensor chip SC and the second spacer 520. A portion of the top surface of the adhesive layer 530 may have a protruding shape that suitably engages with the recessed portion of the bottom surface of the second spacer 520. The adhesive layer 530 may cover the terminal pads TP on the first surface SCt of the image sensor chip SC. The width of each of the first spacer 510, the second spacer 520, and the adhesive layer 530 in the second direction D2 may be greater than the width of the terminal pad TP in the second direction D2.

[0047] refer to Figure 7 An adhesive layer 530 may be disposed between and attached to the first spacer 510 and the second spacer 520. The adhesive layer 530 may fill the gap region between the separated patterns of the first spacer 510. The second spacer 520 may be disposed between the adhesive layer 530 and the first surface SCt of the image sensor chip SC. The top surface of the second spacer 520 may be parallel to the first surface SCt of the image sensor chip SC. The second spacer 520 may cover or overlap the terminal pads TP on the first surface SCt of the image sensor chip SC. For brevity, previous references may be omitted. Figure 6 Further details about the components described.

[0048] refer to Figure 8The second spacer 520 and the adhesive layer 530 can be disposed on the first surface SCt of the image sensor chip SC. The adhesive layer 530 can be attached to the outer surface of the second spacer 520. The adhesive layer 530 can support the second spacer 520 through the outer surface of the second spacer 520. The second spacer 520 may not contact the terminal pad TP on the first surface SCt of the image sensor chip SC. The adhesive layer 530 may cover or overlap the terminal pad TP on the first surface SCt of the image sensor chip SC. The width of the adhesive layer 530 in the second direction D2 may be greater than the width of the terminal pad TP in the second direction D2. However, according to some embodiments, unlike those shown in the figures, the adhesive layer 530 may not cover a portion of the terminal pad TP or may not overlap with it. In this case, the second spacer 520 may cover or overlap with the portion of the terminal pad TP that is not covered by the adhesive layer 530 or does not overlap with the adhesive layer.

[0049] refer to Figure 9 The second spacer 520 can contact the bottom surface 200b of the transparent substrate 200. An adhesive layer 530 can be disposed between and attached to the second spacer 520 and the first surface SCt of the image sensor chip SC. The adhesive layer 530 can support the second spacer 520 via the bottom surface of the second spacer 520. The adhesive layer 530 can cover or overlap the terminal pads TP on the first surface SCt of the image sensor chip SC. The width of each of the second spacer 520 and the adhesive layer 530 in the second direction D2 can be greater than the width of the terminal pads TP in the second direction D2. Additionally, the bonding structure JS can also include a hydrophobic coating material 540. The hydrophobic coating material 540 can be configured to contact the side surface of the second spacer 520.

[0050] refer to Figure 10 The second spacer 520 can be attached to the transparent substrate 200 and the image sensor chip SC via a pair of adhesive layers 530 disposed above and below the second spacer 520. The adhesive layers 530 can support the second spacer 520 via its top and bottom surfaces. One of the adhesive layers 530 can cover or overlap with the terminal pad TP on the first surface SCt of the image sensor chip SC. The width of each of the second spacer 520 and the adhesive layer 530 in the second direction D2 can be greater than the width of the terminal pad TP in the second direction D2. However, according to some embodiments, unlike those shown in the figures, the adhesive layer 530 may not cover or overlap with a portion of the terminal pad TP. In this case, the second spacer 520 may cover or overlap with the portion of the terminal pad TP not covered by the adhesive layer 530.

[0051] exist Figures 8 to 10 In some embodiments, the bonding structure JS can be formed on the bottom surface 200b of the transparent substrate 200 and then attached to the first surface SCt of the image sensor chip SC.

[0052] Figures 11A to 11D It shows the manufacturing process. Figure 6 A cross-sectional view of the method for joining the structure. Hereinafter, the surface facing the first direction D1 will be referred to as the top surface, and the surface opposite to the top surface will be referred to as the bottom surface.

[0053] refer to Figure 11A A first spacer 510 can be formed on the bottom surface 200b of the transparent substrate 200. The first spacer 510 may include at least two patterns. The patterns of the first spacer 510 may be spaced apart from each other in the second direction D2. The patterns of the first spacer 510 can be formed by a photolithography process.

[0054] refer to Figure 11B A second spacer 520 can be formed on the bottom surface 200b of the transparent substrate 200 and on the pattern of the first spacer 510. The second spacer 520 can be formed to fill the gap region between the patterns of the first spacer 510. The second spacer 520 can be formed by a photolithography process. Due to its stepped coverage characteristics, the second spacer 520 can be formed such that a portion of its bottom surface has a recessed shape.

[0055] refer to Figure 11C The adhesive layer 530 can be disposed on the recessed bottom surface of the second spacer 520. The adhesive layer 530 can be formed of, for example, epoxy resin or include epoxy resin. The adhesive layer 530 can protrude above the bottom surface of the second spacer 520.

[0056] refer to Figure 11D A transparent substrate 200 can be placed thereon, with the bottom surface 200b of the substrate, on which the first spacer 510, the second spacer 520, and the adhesive layer 530 are formed, facing the first surface SCt of the image sensor chip SC. The adhesive layer 530 can then be attached to the edge region of the image sensor chip SC. When the adhesive layer 530 covers or overlaps with the image sensor chip SC and the terminal pads TP, the protruding bottom surface of the adhesive layer 530 can be deformed.

[0057] Refer again Figure 6The bonding structure JS may include a first spacer 510, a second spacer 520, and an adhesive layer 530. The adhesive layer 530 may cover or overlap the terminal pad TP between the second spacer 520 and the first surface SCt of the image sensor chip SC.

[0058] Figure 12A and Figure 12B It shows the manufacturing process. Figure 7 A cross-sectional view of the method for joining structures.

[0059] refer to Figure 12A It can be compared with the reference Figure 11A The method described is essentially the same as that used to form a first spacer 510 on the bottom surface 200b of the transparent substrate 200. Then, an adhesive layer 530 can be dispersed in the gap regions between the separated patterns of the first spacer 510. The adhesive layer 530 can protrude above the bottom surface of the first spacer 510.

[0060] refer to Figure 12B A second spacer 520 can be formed on the first surface SCt of the image sensor chip SC. The second spacer 520 can be formed on the edge region of the image sensor chip SC. The second spacer 520 can be formed to cover or overlap with the terminal pad TP. A transparent substrate 200 can be placed such that its bottom surface 200b, on which the first spacer 510 and adhesive layer 530 are formed, faces the first surface SCt of the image sensor chip SC. The adhesive layer 530 can then be attached to the second spacer 520. The protruding bottom surface of the adhesive layer 530 can be deformed into a shape parallel to the first surface SCt of the image sensor chip SC.

[0061] Refer again Figure 7 The joining structure JS may include a first spacer 510 and a second spacer 520, and an adhesive layer 530 located between them. The adhesive layer 530 may fasten the first spacer 510 and the second spacer 520.

[0062] According to some embodiments of the present invention, a semiconductor package is provided in which an image sensor chip and a transparent substrate are in contact with each other in a minimized area or an area smaller than that of conventional methods of forming a semiconductor package, thereby reducing the size of the semiconductor package.

[0063] In addition, image sensor chips can be connected to the circuit board via flip-chip bonding or through-silicon vias, which can reduce the resistance and parasitic capacitance of the semiconductor package and improve the reliability of the semiconductor package.

[0064] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Image sensor chip; A transparent substrate, spaced apart from the image sensor chip; A bonding structure is formed on the edge region of the top surface of the image sensor chip, which contacts the top surface of the image sensor chip and the bottom surface of the transparent substrate. The circuit board is electrically connected to the image sensor chip; as well as A reinforcing substrate contacts and supports the bottom surface of the circuit board. The image sensor chip includes: a through electrode penetrating at least a portion of the interior of the image sensor chip; and a terminal pad on the edge region of the top surface of the image sensor chip and connected to the through electrode. The bonding structure covers the terminal pads. The image sensor chip mentioned above includes: The first surface is adjacent to the transparent substrate; The second surface is in contact with the reinforcing substrate; A third surface, located between the first surface and the second surface; and An inclined surface is used to connect the second surface to the third surface, and The circuit board is spaced apart from the inclined surface.

2. The semiconductor package of claim 1, wherein the bonding structure comprises a spacer and an adhesive layer between the spacer and the image sensor chip.

3. The semiconductor package according to claim 2, The spacer has a recessed bottom surface, and The adhesive layer is located between the recessed bottom surface of the spacer and the image sensor chip.

4. The semiconductor package according to claim 2, The spacers include a first spacer that contacts the bottom surface of the transparent substrate and a second spacer that contacts the top surface of the image sensor chip. The first spacer comprises a plurality of patterns spaced apart from each other. The adhesive layer is located between the first spacer and the second spacer and contacts both the first spacer and the second spacer. The adhesive layer at least partially fills the space between the patterns.

5. The semiconductor package according to claim 2, The spacer comprises one of polyimide and photoresist, and The adhesive layer therein comprises epoxy resin.

6. The semiconductor package according to claim 1, further comprising: A microlens array on the top surface of the image sensor chip; as well as A color filter array is positioned between the microlens array and the image sensor chip. The microlens array is spaced apart from the bottom surface of the transparent substrate, and The microlens array and the color filter array are spaced apart from the bonding structure.

7. The semiconductor package according to claim 1, further comprising: Conductive pads and solder balls are located between the third surface and the circuit board. The conductive pads and solder balls are spaced apart from the inclined surface of the image sensor chip.

8. The semiconductor package according to claim 1, further comprising: An insulating layer is located between the image sensor chip and the circuit board. as well as Conductive pads are respectively located on the bottom surface of the image sensor chip and the top surface of the circuit board; The insulating layer is located between and in contact with the conductive pads; and The conductive pad is connected to one of a solder ball, a conductive bump, an anisotropic conductive film, or a non-conductive film.

9. The semiconductor package according to claim 1, The distance between the image sensor chip and the transparent substrate ranges from 10 μm to 150 μm, and The width of the joint structure ranges from 30 μm to 450 μm.

10. A semiconductor package, comprising: An image sensor chip includes a pixel region and a peripheral region surrounding the pixel region in a planar view; Microlenses and color filters are on the image sensor chip; A transparent substrate is placed on the image sensor chip; A bonding structure, in the peripheral region, connects the image sensor chip to the transparent substrate; The circuit board is electrically connected to the image sensor chip; An insulating layer is located between the image sensor chip and the circuit board. as well as The reinforcing substrate is in contact with the bottom surface of the circuit substrate and overlaps at least with the pixel region in a vertical direction substantially perpendicular to the image sensor chip. The bonding structure includes a spacer and an adhesive layer between the spacer and the image sensor chip.

11. The semiconductor package of claim 10, further comprising: Terminal pads, in the peripheral region and on the top surface of the image sensor chip; as well as A penetrating electrode is provided in the peripheral region, which penetrates the image sensor chip and connects to the terminal pad.

12. The semiconductor package of claim 10, wherein the side surface of the image sensor chip, the side surface of the transparent substrate, and the outer surface of the bonding structure are coplanar with each other.

13. The semiconductor package of claim 10, wherein the bonding structure is spaced apart from the pixel region.

14. The semiconductor package according to claim 10, The microlens is spaced apart from the transparent substrate, and The semiconductor package has a cavity between the transparent substrate and the image sensor chip including the microlens.

15. The semiconductor package according to claim 10, The spacer has a recessed bottom surface, and The adhesive layer at least partially fills the gap defined by the recessed bottom surface of the spacer.

16. A semiconductor package, comprising: Transparent substrate, including an infrared light cutoff filter; The circuit board is spaced apart from the transparent substrate in a first direction perpendicular to the bottom surface of the transparent substrate; An image sensor chip is located between the transparent substrate and the circuit substrate, and the image sensor chip includes a microlens array and a color filter array on the central region of its top surface. Terminal pads are located on the edge region of the top surface of the image sensor chip. A penetrating electrode that penetrates the image sensor chip and connects to the terminal pad; A connection structure electrically connects the penetrating electrode to the circuit board. as well as A bonding structure is located on the edge region of the top surface of the image sensor chip and contacts the bottom surface of the transparent substrate and the top surface of the image sensor chip; The bonding structure includes a spacer and an adhesive layer between the image sensor chip or the transparent substrate and the spacer. The width of the bonding structure in the second direction perpendicular to the first direction is greater than the width of the terminal pad in the second direction. The image sensor chip extends partially in the first direction. The image sensor chip has a side portion extending in the first direction that is tilted at an angle relative to the top surface of the image sensor chip. The circuit board is spaced apart from the side portion of the image sensor chip.

17. The semiconductor package of claim 16, wherein the side surface of the image sensor chip, the side surface of the transparent substrate, and the outer surface of the bonding structure are coplanar with each other.

18. The semiconductor package of claim 16, wherein the thickness of the circuit substrate is less than the thickness of the image sensor chip.

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