Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate having a source doping layer in the substrate; a channel column located on the source doping layer; a gate structure located on the sidewall surface of the channel column; a first contact layer located on the surface of the source doping layer, the first contact layer having a first thickness; a second contact layer located on the top surface of the channel column, the second contact layer having a second thickness, and the first thickness is greater than the second thickness. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Fin FET is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the fin, and source and drain doping regions in the fin on both sides of the gate structure. Compared with planar metal-oxide semiconductor field effect transistors, fin field effect transistors have stronger short channel suppression capabilities and higher operating currents.

[0003] With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and traditional fin field effect transistors are limited in further increasing the operating current. Specifically, since only the area close to the top surface and the sidewall of the fin is used as the channel area, the volume of the fin used as the channel area is small, which limits the increase in the operating current of the fin field effect transistor. Therefore, a fin field effect transistor with a channel gate-all-around (GAA) structure is proposed, which increases the volume used as the channel area, further increasing the operating current of the fin field effect transistor with a channel gate-all-around structure.

[0004] However, the performance of the FinFET with a trench gate-around structure in the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, wherein the substrate has a source doping layer; a channel column located on the source doping layer; a gate structure located on the sidewall surface of the channel column; a first contact layer located on the surface of the source doping layer, the first contact layer has a first thickness; a second contact layer located on the top surface of the channel column, the second contact layer has a second thickness, and the first thickness is greater than the second thickness.

[0007] Optionally, the first thickness ranges from 5 nm to 10 nm.

[0008] Optionally, the second thickness ranges from 3 nm to 6 nm.

[0009] Optionally, the material of the first contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon; the material of the second contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon.

[0010] Optionally, it further includes: a first conductive structure located on the surface of the first contact layer; and a second conductive structure located on the surface of the second contact layer.

[0011] Optionally, the material of the first conductive structure includes metal, and the metal includes copper, tungsten or aluminum; the material of the second conductive structure includes metal, and the metal includes copper, tungsten or aluminum.

[0012] Optionally, the gate structure includes a first portion and a second portion, the first portion surrounds the channel column, and the second portion is located on a surface of the substrate on one side of the channel column.

[0013] Optionally, the first part of the gate structure includes: a gate dielectric layer located on the side wall of the channel column, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; the second part of the gate structure includes: a work function layer located on the surface of the substrate, and a gate layer located on the surface of the work function layer.

[0014] Optionally, the material of the gate dielectric layer includes silicon oxide or a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9; the material of the work function layer includes titanium nitride, titanium aluminum or tantalum nitride; the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.

[0015] Optionally, it also includes: a third conductive structure located on the surface of the second portion of the gate structure.

[0016] Optionally, there is a first isolation layer between the gate structure and the substrate surface; there is a second isolation layer on the first isolation layer, and the gate structure is located in the second isolation layer.

[0017] Optionally, it also includes: a third isolation layer located on the gate structure and the second isolation layer.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming any of the above-mentioned semiconductor structures, including: providing a substrate, wherein the substrate has a source doping layer; forming a channel column on the source doping layer; forming a gate structure on the side wall surface of the channel column; forming a first contact layer on the surface of the source doping layer, the first contact layer has a first thickness; forming a second contact layer on the top surface of the channel column, the second contact layer has a second thickness, and the first thickness is greater than the second thickness.

[0019] Optionally, the method for forming the first contact layer includes: forming a first mask layer on the surface of the third isolation layer, the first mask layer exposing a portion of the surface of the third isolation layer; etching the third isolation layer, the second isolation layer, the first isolation layer and the source doping layer using the first mask layer as a mask to form a first groove in the third isolation layer, the second isolation layer, the first isolation layer and the source doping layer; forming a first contact material layer at the bottom of the first groove; and annealing the first contact material layer to form the first contact layer.

[0020] Optionally, it also includes: forming a first conductive structure on the first contact layer; the method for forming the first conductive structure includes: forming a conductive structure material layer on the surface of the first contact layer and the surface of the third isolation layer, and flattening the conductive structure material layer until the surface of the third isolation layer is exposed to form the first conductive structure.

[0021] Optionally, the process of forming the first contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

[0022] Optionally, the method for forming the second contact layer includes: forming a second mask layer on the surface of the third isolation layer, the second mask layer exposing a portion of the surface of the third isolation layer; etching the third isolation layer using the second mask layer as a mask until the top surface of the channel column is exposed, thereby forming a second trench in the third isolation layer; forming a second contact material layer at the bottom of the second trench; and annealing the second contact material layer to form the second contact layer.

[0023] Optionally, after forming the second isolation layer, the method further includes: etching back the second isolation layer and the gate layer and the work function layer on the top of the channel column until the gate dielectric layer on the top of the channel column and the gate dielectric layer on part of the sidewall of the channel column are exposed.

[0024] Optionally, it also includes: forming a second conductive structure on the second contact layer; the method for forming the second conductive structure includes: forming a conductive structure material layer on the surface of the second contact layer and the surface of the third isolation layer, and flattening the conductive structure material layer until the surface of the third isolation layer is exposed to form the second conductive structure.

[0025] Optionally, the process of forming the second contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] In the semiconductor structure of the technical solution of the present invention, the first contact layer has a first thickness, the second contact layer has a second thickness, the first thickness is greater than the second thickness, and the thickness of the first contact layer is larger, then the first contact layer has a smaller contact resistance, so that the current of the circuit is larger, which is beneficial to improving the performance of the semiconductor structure; the thickness of the second contact layer is smaller, then the diffusion of metal ions in the second contact layer into the channel column is reduced, so that the subsequently formed conductive structure leaks electricity at the contact position with the second contact layer. In summary, the performance of the semiconductor structure is improved.

[0028] In the method for forming a semiconductor structure in the technical solution of the present invention, the first contact layer formed on the surface of the source doping layer has a first thickness, and the second contact layer formed on the top surface of the channel column has a second thickness. The first contact layer and the second contact layer have different formation processes, so that first contact layers and second contact layers of different thicknesses can be formed to meet the situation where the semiconductor structure requires contact layers of different thicknesses at different positions, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment;

[0030] Figures 2 to 8 It is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the performance of the prior art FinFET with a gate-around trench structure needs to be improved.

[0032] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor structure in one embodiment.

[0033] Please refer to Figure 1The semiconductor structure includes a substrate 100, a source doping layer 101 located on the substrate 100; a channel pillar 104 located on the source doping layer 101; an isolation layer 102 located on the source doping layer 101, wherein the isolation layer 102 is located on a portion of the sidewall of the channel pillar 102; a gate structure located on the sidewall of the channel pillar 102, wherein the gate structure surrounds the channel pillar 102, and wherein the gate structure includes a gate dielectric layer 105 located on the sidewall surface of the channel pillar, a work function layer 106 located on the gate dielectric layer 105, and a gate layer 107 located on the work function layer 106, wherein a portion of the work function layer 106 and a portion of the gate layer 107 extend to the isolation layer 101. 02 surface; a dielectric layer 103 located on the isolation layer 102, and the gate structure is located in the dielectric layer 103; a source conductive structure located on the surface of the source doping layer 101, in the isolation layer 102 and in the dielectric layer 103, the source conductive structure includes a source contact layer 109 located in the source doping layer 101 and a source plug 108 located on the source contact layer 109; a drain conductive structure located on the top of the channel column 102 and in the dielectric layer 103, the drain conductive structure includes a drain contact layer 110 and a drain plug 111 located on the drain contact layer 110; a gate conductive plug 112 located on the gate layer 107 and in the dielectric layer 103.

[0034] In the semiconductor structure, the source contact layer 109 in the source conductive structure and the drain contact layer 110 in the drain conductive structure are formed by the same process and have the same thickness. However, the source conductive structure and the drain conductive structure have different performance requirements. The source contact layer 109 in the source conductive structure requires a smaller contact resistance so that the current of the source conductive structure is larger, thereby requiring a thicker source contact layer 109; the drain conductive structure is located at the top of the channel column 102. If the thickness of the drain contact layer 110 is too thick, the ions in the drain contact layer 110 are easily diffused into the channel column 102, so that the position where the drain conductive structure contacts the channel column 102 is prone to leakage, thereby affecting the performance of the semiconductor structure.

[0035] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein the source contact layer and the drain contact layer have different thicknesses, wherein if the thickness of the source contact layer is thicker, the source conductive structure and the source doping layer have a smaller contact resistance, thereby making the current of the source conductive structure circuit larger; if the thickness of the drain contact layer is thinner, the diffusion of metal ions in the drain contact layer into the channel column is reduced, resulting in leakage at the contact position between the drain conductive structure and the drain contact layer, thereby improving the performance of the semiconductor structure.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 8 It is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure in an embodiment of the present invention.

[0038] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 has a source doping layer 201 therein.

[0039] The source doping layer 201 is the source of the semiconductor structure.

[0040] The source doping layer 201 has doping ions therein. The doping ions are of N-type or P-type. The N-type ions include phosphorus ions or arsenic ions. The P-type ions include boron ions or indium ions.

[0041] In this embodiment, the process of forming the source doping layer 201 includes an ion implantation process. In other embodiments, the process of forming the source doping layer includes an in-situ doping process.

[0042] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate may also be polycrystalline silicon or amorphous silicon; in other embodiments, the material of the substrate may also be semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

[0043] Please refer to Figure 3 , a channel pillar 202 is formed on the source doping layer 201 .

[0044] The method for forming the channel pillar 202 includes: forming a channel material layer (not shown) on the substrate 200; forming a first mask layer (not shown) on the surface of the channel material layer, wherein the first mask layer exposes a portion of the surface of the channel material layer; etching the channel material layer using the first mask layer as a mask until the surface of the source doping layer 201 is exposed, thereby forming the channel pillar 202 on the source doping layer 201.

[0045] In this embodiment, the process of etching the channel material layer includes a dry etching process.

[0046] In this embodiment, the material of the channel pillar 202 includes silicon. In other embodiments, the material of the channel pillar includes semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

[0047] In this embodiment, the process of forming the channel material layer includes a physical vapor deposition process. In other embodiments, the process of forming the channel material layer includes an epitaxial growth process or an atomic layer deposition process.

[0048] In this embodiment, the material of the first mask layer includes photoresist; in other embodiments, the material of the first mask layer includes a hard mask material, and the hard mask material includes silicon oxide or silicon nitride.

[0049] In this embodiment, the process of forming the first mask layer includes a spin coating process.

[0050] After forming the channel pillar 202, the first mask layer is removed. In this embodiment, the process of removing the first mask layer includes an ashing process.

[0051] Please continue to refer to Figure 3 After removing the first mask layer, a first isolation layer 203 is formed on the surface of the substrate 200 , wherein the first isolation layer 203 is located on a portion of the sidewall of the channel column 202 , and a top surface of the first isolation layer 203 is lower than a top surface of the channel column 202 .

[0052] The first isolation layer 203 provides structural support and electrical isolation for the subsequent formation of a first contact layer in the source doping layer 201 and a first conductive structure located on the first contact layer.

[0053] In this embodiment, the material of the first isolation layer 203 includes silicon oxide; in other embodiments, the material of the first isolation layer includes silicon nitride or silicon carbide.

[0054] In this embodiment, the process of forming the first isolation layer 203 includes a chemical vapor deposition process. In other embodiments, the process of forming the first isolation layer includes an atomic layer deposition process or a thermal oxidation process.

[0055] Please refer to Figure 4 , a gate structure is formed on the sidewall surface of the channel pillar 202 .

[0056] The gate structure includes a first portion and a second portion, the first portion surrounds the channel pillar 202 , and the second portion is located on the surface of the substrate 200 at one side of the channel pillar 202 .

[0057] The first part of the gate structure includes: a gate dielectric layer 204 located on the sidewall of the channel pillar 202 , a work function layer 205 located on the surface of the gate dielectric layer 204 , and a gate layer 206 located on the surface of the work function layer 205 .

[0058] The second portion of the gate structure includes: a work function layer 205 located on the surface of the substrate 200 , and a gate layer 206 located on the surface of the work function layer 205 .

[0059] The method for forming the gate dielectric layer 204 includes: forming a gate dielectric material layer (not shown) on the surface of the substrate 200 and the side wall surface and top surface of the channel pillar 202; forming a second mask layer (not shown) on the surface of the gate dielectric material layer, the second mask layer exposing a portion of the surface of the gate dielectric material layer; etching the gate dielectric material layer using the second mask layer as a mask until the surface of the source doping layer 201 is exposed, and forming the gate dielectric layer 204 on the side wall of the channel pillar 202.

[0060] In this embodiment, the material of the gate dielectric layer 204 includes a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9; the high dielectric constant material includes hafnium oxide or aluminum oxide.

[0061] In other embodiments, the material of the gate dielectric layer includes silicon oxide.

[0062] In this embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process. In other embodiments, the process of forming the gate dielectric material layer includes an atomic layer deposition process.

[0063] In this embodiment, the material of the second mask layer includes photoresist; in other embodiments, the material of the second mask layer includes a hard mask material, and the hard mask material includes silicon oxide or silicon nitride.

[0064] In this embodiment, the process of forming the second mask layer includes a spin coating process.

[0065] After forming the gate dielectric layer 204, the second mask layer is removed. In this embodiment, the process of removing the second mask layer includes an ashing process.

[0066] The method for forming the work function layer 205 and the gate layer 206 includes: forming a work function material layer (not shown) on the surface of the substrate 200 and the surface of the gate dielectric layer 204; forming a gate material layer (not shown) on the surface of the work function material layer; forming a third mask layer (not shown) on the surface of the gate material layer, wherein the third mask layer exposes a portion of the surface of the gate material layer; etching the gate material layer and the work function material layer using the third mask layer as a mask until the surface of the source doping layer 201 is exposed, and forming the work function layer 205 and the gate layer 206 located on the work function layer 205 on the side walls of the channel pillar 202 and the surface of the substrate 200.

[0067] The material of the work function layer 205 includes titanium nitride, titanium aluminum nitride or tantalum nitride.

[0068] The material of the gate layer 206 includes polysilicon or metal. In this embodiment, the material of the gate layer includes metal, and the metal includes tungsten.

[0069] In this embodiment, the process of forming the work function material layer includes a chemical vapor deposition process or a physical vapor deposition process.

[0070] In this embodiment, the process of forming the gate material layer includes a physical vapor deposition process or an electroplating process.

[0071] In this embodiment, the process of etching the gate material layer and the work function material layer includes a dry etching process.

[0072] In this embodiment, the material of the third mask layer includes photoresist; in other embodiments, the material of the third mask layer includes a hard mask material, and the hard mask material includes silicon oxide or silicon nitride.

[0073] In this embodiment, the process of forming the third mask layer includes a spin coating process.

[0074] After forming the work function layer 205 and the gate layer 206, the third mask layer is removed. In this embodiment, the process of removing the third mask layer includes an ashing process.

[0075] Please continue to refer to Figure 4 After forming the gate structure, an initial second isolation layer 207 is formed on the first isolation layer 203 , and the gate structure is located in the initial second isolation layer 207 .

[0076] In this embodiment, the material of the initial second isolation layer 207 includes silicon oxide; in other embodiments, the material of the initial second isolation layer includes silicon nitride or silicon carbide.

[0077] In this embodiment, the process of forming the initial second isolation layer 207 includes a chemical vapor deposition process. In other embodiments, the process of forming the initial second isolation layer includes an atomic layer deposition process or a thermal oxidation process.

[0078] Next, a first contact layer is formed on the surface of the source doping layer 201, and the first contact layer has a first thickness; a second contact layer is formed on the top surface of the channel pillar 202, and the second contact layer has a second thickness. For the specific formation process, please refer to Figures 5 to 7 .

[0079] Please refer to Figure 5, the initial second isolation layer 207 and the gate layer 206 and the work function layer 205 on the top of the channel column 202 are etched back until the gate dielectric layer 204 on the top of the channel column 202 and the gate dielectric layer 204 on a portion of the sidewall of the channel column 202 are exposed to form a second isolation layer 208.

[0080] The initial second isolation layer 207 and the gate layer 206 and the work function layer 205 on the top of the channel column 202 are etched back until the gate dielectric layer 204 on the top of the channel column 202 is exposed, so that after the subsequent formation of the third isolation layer, when a second contact layer and a second conductive structure located on the surface of the second contact layer are formed on the top surface of the channel column 202, the gate dielectric layer 204 on the top of the channel column 202 can be quickly opened, thereby saving the steps of etching the gate layer 206 and the work function layer 205, thereby simplifying the process flow.

[0081] The etching gas used for back-etching the initial second isolation layer 207 and the gate layer 206 and the work function layer 205 on the top of the channel column 202 has a higher etching selectivity for the gate dielectric layer 204, so that when etching the initial second isolation layer 207, the gate layer 206 and the work function layer 205, the etching degree of the gate dielectric layer 204 is small, thereby avoiding damage to the channel column 202.

[0082] The second isolation layer 208 and the first isolation layer 203 together provide structural support and electrical isolation for the subsequent formation of a first contact layer and a first conductive structure on the first contact layer in the source doping layer 201, and a third conductive structure on the second portion of the gate structure.

[0083] Please continue to refer to Figure 5 After forming the second isolation layer 208 , a third isolation layer 209 is formed on the gate structure and the second isolation layer 208 .

[0084] The third isolation layer 209, the second isolation layer 208 and the first isolation layer 203 together provide structural support and electrical isolation for the subsequent formation of a first contact layer and a first conductive structure located on the first contact layer in the source doping layer 201, the formation of a third conductive structure on the surface of the second part of the gate structure, and the formation of a second contact layer on the top surface of the channel column and a second conductive structure located on the surface of the second contact layer.

[0085] A top surface of the third isolation layer 209 is higher than a top surface of the gate structure.

[0086] In this embodiment, the material of the third isolation layer 209 includes silicon oxide; in other embodiments, the material of the third isolation layer includes silicon nitride or silicon carbide.

[0087] In this embodiment, the process of forming the third isolation layer 209 includes a chemical vapor deposition process. In other embodiments, the process of forming the third isolation layer includes an atomic layer deposition process or a thermal oxidation process.

[0088] Please refer to Figure 6 , a first trench (not shown) is formed in the third isolation layer 209, the second isolation layer 208, the first isolation layer 203 and the source doping layer 201; a first contact layer 210 is formed at the bottom of the first trench; and a first conductive structure 211 is formed on the surface of the first contact layer 210.

[0089] The method for forming the first groove includes: forming a fourth mask layer (not shown) on the surface of the third isolation layer 209, the fourth mask layer exposing a portion of the surface of the third isolation layer 209; etching the third isolation layer 209, the second isolation layer 208, the first isolation layer 203 and the source doping layer 201 using the fourth mask layer as a mask to form a first groove in the third isolation layer 209, the second isolation layer 208, the first isolation layer 203 and the source doping layer 201.

[0090] In this embodiment, the process of etching the third isolation layer 209 , the second isolation layer 208 , the first isolation layer 203 and the source doping layer 201 includes a dry etching process.

[0091] The method for forming the first contact layer 210 and the first conductive structure 211 includes: forming a first contact material layer (not shown) at the bottom of the first groove and on the surface of the third isolation layer 209; forming the first conductive material layer (not shown) on the surface of the first contact material layer, and the first conductive material layer fills the first groove; planarizing the first conductive material layer and the first contact material layer until the surface of the third isolation layer 209 is exposed, forming an initial first contact layer (not shown) and an initial first conductive structure (not shown) located on the initial first contact layer in the first groove; performing a first annealing treatment on the initial first contact layer and the initial first conductive structure to form the first contact layer 210 and the first conductive structure 211.

[0092] The material of the first contact material layer includes metal, and the metal includes titanium, nickel or cobalt.

[0093] The material of the first contact layer 210 includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon.

[0094] After the annealing process, the initial first contact layer reacts with the source doping layer 201 to form the first contact layer 210 .

[0095] The process of forming the first contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

[0096] In this embodiment, the process of forming the first contact material layer includes an atomic layer deposition process, which can form a first contact material layer with a dense structure and precise thickness.

[0097] The first thickness of the first contact layer 210 is greater than the second thickness of the second contact layer formed subsequently. If the first contact layer 210 is thicker, the first contact layer 210 has a smaller contact resistance, so that the current of the circuit is larger, which is beneficial to improving the performance of the semiconductor structure.

[0098] In this embodiment, the first thickness ranges from 5 nm to 10 nm.

[0099] If the thickness of the first contact layer 210 is too large, the initial first contact layer forming the first contact layer 210 cannot fully react with the source doping layer 201 to form a metal silicide during annealing, thereby making the contact resistance of the first contact layer 210 relatively large and failing to reduce the contact resistance between the first conductive structure 211 and the source doping layer 201; if the thickness of the first contact layer 210 is too small, the effect of reducing the contact resistance is not obvious.

[0100] The material of the first conductive structure 211 includes metal, and the metal includes copper, tungsten or aluminum.

[0101] The process of forming the first conductive structure 211 includes a physical vapor deposition process or an electroplating process.

[0102] In this embodiment, the temperature range of the first annealing treatment is 400°C to 700°C.

[0103] In this embodiment, the process of planarizing the first conductive material layer and the first contact material layer includes a chemical mechanical polishing process.

[0104] Please refer to Figure 7 , forming a second trench (not shown) in the third isolation layer 209 ; forming a second contact layer 212 at the bottom of the second trench; and forming a second conductive structure 213 on the second contact layer 212 .

[0105] The method for forming the second groove includes: forming a fifth mask layer (not shown) on the surface of the third isolation layer 209, the fifth mask layer exposing a portion of the surface of the third isolation layer 209; etching the third isolation layer 209 and the gate dielectric layer 204 on the top surface of the channel column 202 using the fifth mask layer as a mask until the top surface of the channel column 202 is exposed, thereby forming a second groove in the third isolation layer 209.

[0106] In this embodiment, the process of etching the third isolation layer 209 and the gate dielectric layer 204 on the top surface of the channel pillar 202 includes a dry etching process.

[0107] The method for forming the second contact layer 212 and the second conductive structure 213 includes: forming a second contact material layer (not shown) at the bottom of the second groove and on the surface of the third isolation layer 209; forming the second conductive material layer (not shown) on the surface of the second contact material layer, and the second conductive material layer fills the second groove; planarizing the second conductive material layer and the second contact material layer until the surface of the third isolation layer 209 is exposed, forming an initial second contact layer (not shown) and an initial second conductive structure (not shown) located on the initial second contact layer in the second groove; performing a second annealing treatment on the initial second contact layer and the initial second conductive structure to form the second contact layer 212 and the second conductive structure 213.

[0108] The material of the second contact material layer includes metal, and the metal includes titanium, nickel or cobalt.

[0109] The material of the second contact layer 212 includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon.

[0110] After the second annealing process, the initial second contact layer reacts with the channel pillar 202 to form the second contact layer 212 .

[0111] The process of forming the second contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

[0112] In this embodiment, the process of forming the second contact material layer includes an atomic layer deposition process, which can form a second contact material layer with a dense structure and precise thickness.

[0113] The second thickness of the second contact layer 212 is less than the first thickness of the first contact layer 210. The smaller thickness of the second contact layer 212 reduces the diffusion of metal ions in the second contact layer 212 into the channel pillar 202, so that the formed second conductive structure 213 leaks electricity at the contact position with the second contact layer 212, which is beneficial to improving the performance of the semiconductor structure.

[0114] In this embodiment, the second thickness ranges from 3 nm to 6 nm.

[0115] If the thickness of the second contact layer 212 is too large, during the annealing treatment, the metal ions in the initial second contact layer will easily diffuse into the channel column 202, causing the second conductive structure 213 to leak electricity at the contact position with the second contact layer 212, thereby affecting the performance of the semiconductor structure; if the thickness of the second contact layer 212 is too small, the contact resistance is large, which is not conducive to improving the performance of the semiconductor structure.

[0116] The material of the second conductive structure 213 includes metal, and the metal includes copper, tungsten or aluminum.

[0117] The process of forming the second conductive structure 213 includes a physical vapor deposition process or an electroplating process.

[0118] In this embodiment, the temperature range of the second annealing treatment is 400°C to 700°C.

[0119] In this embodiment, the second annealing process is performed simultaneously with the first annealing process.

[0120] In this embodiment, the process of planarizing the second conductive material layer and the second contact material layer includes a chemical mechanical polishing process.

[0121] Please refer to Figure 8 , forming a third conductive structure 214 on the surface of the second portion of the gate structure.

[0122] The method for forming the third conductive structure 214 includes: forming a sixth mask layer (not shown) on the surface of the third isolation layer 209, wherein the sixth mask layer exposes a portion of the surface of the third isolation layer 209; etching the third isolation layer 209 and the second isolation layer 208 using the sixth mask layer as a mask until the surface of the gate layer 206 of the second part of the gate structure is exposed, and forming a third trench (not shown) in the third isolation layer 209 and the second isolation layer 208; forming a third conductive material layer (not shown) in the third trench and on the surface of the third isolation layer 209; and planarizing the third conductive material layer until the surface of the third isolation layer 209 is exposed to form the third conductive structure 214.

[0123] The material of the third conductive structure 214 includes metal, and the metal includes copper, tungsten or aluminum.

[0124] The process of forming the third conductive structure 214 includes a physical vapor deposition process or an electroplating process.

[0125] In this embodiment, the process of etching the third isolation layer 209 and the second isolation layer 208 includes a dry etching process.

[0126] In this embodiment, the process of planarizing the third conductive material layer includes a chemical mechanical polishing process.

[0127] At this point, a semiconductor structure is formed, in which the first contact layer formed on the surface of the source doping layer has a first thickness, and the second contact layer formed on the top surface of the channel column has a second thickness, and the first thickness is greater than the second thickness, thereby satisfying the situation where the semiconductor structure requires contact layers of different thicknesses at different positions, thereby improving the performance of the semiconductor structure.

[0128] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 8 ,include:

[0129] A substrate 200, wherein the substrate 200 has a source doping layer 201;

[0130] A channel pillar 202 located on the source doping layer 201;

[0131] A gate structure located on the sidewall surface of the channel pillar 202;

[0132] A first contact layer 210 located on the surface of the source doping layer 201, wherein the first contact layer 210 has a first thickness;

[0133] A second contact layer 212 is located on the top surface of the channel pillar 202 , wherein the second contact layer 212 has a second thickness, and the first thickness is greater than the second thickness.

[0134] The first thickness ranges from 5nm to 10nm; the second thickness ranges from 3nm to 6nm;

[0135] The material of the first contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon; the material of the second contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon;

[0136] A first conductive structure 211 located on the surface of the first contact layer 210; a second conductive structure 213 located on the surface of the second contact layer 212;

[0137] The material of the first conductive structure includes metal, and the metal includes copper, tungsten or aluminum. The material of the second conductive structure includes metal, and the metal includes copper, tungsten or aluminum;

[0138] The gate structure includes a first part and a second part, the first part surrounds the channel column, and the second part is located on the substrate surface on one side of the channel column; the first part of the gate structure includes: a gate dielectric layer located on the sidewall of the channel column, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; the second part of the gate structure includes: a work function layer located on the substrate surface, and a gate layer located on the surface of the work function layer;

[0139] A third conductive structure 214 located on a second portion of the surface of the gate structure;

[0140] A first isolation layer 203 is located between the gate structure and the surface of the substrate 200 ; a second isolation layer 208 is provided on the first isolation layer 203 , and the gate structure is located in the second isolation layer 208 ; and a third isolation layer 209 is located on the gate structure and the second isolation layer 208 .

[0141] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a source doping layer therein; A channel column located on the source doping layer, wherein the bottom of the channel column is in contact with the source doping layer; A gate structure located on the sidewall surface of the channel pillar; A first contact layer located on a surface of the source doping layer, wherein the first contact layer has a first thickness; A second contact layer is located on the top surface of the channel column, the second contact layer has a second thickness, the first thickness is greater than the second thickness, and the area of ​​the second contact layer is less than or equal to the area of ​​the top surface of the channel column.

2. The semiconductor structure according to claim 1, wherein: The first thickness ranges from 5 nm to 10 nm.

3. The semiconductor structure according to claim 1, wherein: The second thickness ranges from 3 nm to 6 nm.

4. The semiconductor structure according to claim 1, wherein: The material of the first contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon; the material of the second contact layer includes metal silicide, and the metal silicide includes titanium silicon, nickel silicon or cobalt silicon.

5. The semiconductor structure according to claim 1, wherein: Also includes: a first conductive structure located on a surface of the first contact layer; A second conductive structure is located on the surface of the second contact layer.

6. The semiconductor structure according to claim 5, characterized in that The material of the first conductive structure includes metal, and the metal includes copper, tungsten or aluminum; the material of the second conductive structure includes metal, and the metal includes copper, tungsten or aluminum.

7. The semiconductor structure according to claim 1, wherein: The gate structure includes a first portion and a second portion, wherein the first portion surrounds the channel column, and the second portion is located on a substrate surface at one side of the channel column.

8. The semiconductor structure according to claim 7, wherein: The first part of the gate structure includes: a gate dielectric layer located on the side wall of the channel column, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; the second part of the gate structure includes: a work function layer located on the surface of the substrate, and a gate layer located on the surface of the work function layer.

9. The semiconductor structure according to claim 8, characterized in that The material of the gate dielectric layer includes silicon oxide or a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9; the material of the work function layer includes titanium nitride, titanium aluminum or tantalum nitride; the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.

10. The semiconductor structure according to claim 7, wherein: Also includes: A third conductive structure is located on the surface of the second portion of the gate structure.

11. The semiconductor structure according to claim 1, wherein: A first isolation layer is provided between the gate structure and the substrate surface; a second isolation layer is provided on the first isolation layer, and the gate structure is located in the second isolation layer.

12. The semiconductor structure according to claim 11, wherein: Also includes: A third isolation layer is located on the gate structure and the second isolation layer.

13. A method for forming a semiconductor structure according to any one of claims 1 to 12, characterized in that: include: Providing a substrate, wherein the substrate has a source doping layer; forming a channel column on the source doping layer, wherein the bottom of the channel column contacts the source doping layer; forming a gate structure on the sidewall surface of the channel pillar; forming a first contact layer on the surface of the source doping layer, wherein the first contact layer has a first thickness; A second contact layer is formed on the top surface of the channel column, wherein the second contact layer has a second thickness, and the first thickness is greater than the second thickness, and an area of ​​the second contact layer is less than or equal to an area of ​​the top surface of the channel column.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first contact layer includes: forming a first mask layer on the surface of the third isolation layer, the first mask layer exposing a portion of the surface of the third isolation layer; etching the third isolation layer, the second isolation layer, the first isolation layer and the source doping layer using the first mask layer as a mask, forming a first groove in the third isolation layer, the second isolation layer, the first isolation layer and the source doping layer; forming a first contact material layer at the bottom of the first groove; and annealing the first contact material layer to form the first contact layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: forming a first conductive structure on the first contact layer; The method for forming the first conductive structure includes: forming a conductive structure material layer on the surface of the first contact layer and the surface of the third isolation layer, and planarizing the conductive structure material layer until the surface of the third isolation layer is exposed to form the first conductive structure.

16. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the first contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

17. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the second contact layer includes: forming a second mask layer on the surface of the third isolation layer, the second mask layer exposing a portion of the surface of the third isolation layer; etching the third isolation layer using the second mask layer as a mask until the top surface of the channel column is exposed, thereby forming a second groove in the third isolation layer; forming a second contact material layer at the bottom of the second groove; and annealing the second contact material layer to form the second contact layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: After forming the second isolation layer, the method further includes: etching back the second isolation layer and the gate layer and work function layer at the top of the channel column until the gate dielectric layer at the top of the channel column and the gate dielectric layer on part of the sidewall of the channel column are exposed.

19. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: forming a second conductive structure on the second contact layer; The method for forming the second conductive structure includes: forming a conductive structure material layer on the surface of the second contact layer and the surface of the third isolation layer, and planarizing the conductive structure material layer until the surface of the third isolation layer is exposed to form the second conductive structure.

20. The method for forming a semiconductor structure according to claim 17, wherein: The process of forming the second contact material layer includes a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

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