Compensation of reference transistors and memory cells in analog neuron memories in deep learning artificial neural networks

Abstract

Disclosed are numerous embodiments for compensating for slope differences in current-voltage characteristic curves between a reference transistor (2282), a reference memory cell, and a flash memory cell (2284) during read operations in simulated neural memory in deep learning artificial neural networks. These embodiments are capable of compensating for slope differences during both sub-threshold and linear operation of the reference transistor.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 696718, filed July 11, 2018, entitled “Compensation for Reference Transistors and Memory Cells in Analog Neuro Memory in Deep Learning Artificial Neural Network”, and U.S. Patent Application No. 16 / 150606, filed October 3, 2018, entitled “Compensation for Reference Transistors and Memory Cells in Analog Neuro Memory in Deep Learning Artificial Neural Network”. Technical Field

[0003] This invention discloses numerous embodiments for compensating for slope differences in the current-voltage characteristic curves between a reference transistor, a reference memory cell, and a flash memory cell during read operations in a simulated neural memory within a deep learning artificial neural network. These embodiments are capable of compensating for slope differences during both subthreshold and linear operations of the reference transistor. Background Technology

[0004] Artificial neural networks mimic biological neural networks (e.g., the central nervous system of animals, particularly the brain). These artificial neural networks are used to estimate or approximate functions that may depend on a large number of inputs and are often unknown. Artificial neural networks typically consist of interconnected layers of “neurons” that exchange messages with each other.

[0005] Figure 1 An artificial neural network 100 is illustrated, where circles represent the inputs or layers of neurons. Connections (called synapses) are indicated by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to its inputs and learn. Typically, a neural network comprises layers with multiple inputs. There are usually one or more intermediate layers of neurons, and output layers of neurons that provide the outputs of the neural network. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0006] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. Real-world neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e., very high computational parallelism. In principle, such complexity can be achieved using digital supercomputers or dedicated clusters of graphics processing units. However, compared to biological networks, these methods are generally energy inefficient, in addition to being costly, as biological networks consume less energy primarily due to their ability to perform low-precision analog computations. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, most CMOS-implemented synapses are excessively large.

[0007] The applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594439, which is incorporated herein by reference. The non-volatile memory array operates as a simulated neuromorphic memory. The neural network device includes a plurality of first synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a plurality of first neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each memory cell includes: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store weight values ​​corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0008] Every non-volatile memory cell used in an analog neuromorphic memory system must be erased and programmed to maintain a very specific and precise amount of charge in the floating gate. For example, each floating gate must hold one of N distinct values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, and 64.

[0009] A unique characteristic of analog neuromorphic memory systems is that the system must support two different types of read operations. In a normal read operation, individual memory cells are read, as in a conventional memory system. However, in a neural read operation, the entire array of memory cells is read at once, where each bit line outputs a current that is the sum of all currents from the memory cells connected to that bit line.

[0010] Therefore, analog neuromorphic memory systems are highly sensitive to mismatches between memory cells and transistors. Extremely high accuracy is required, and the system will be inaccurate if the two devices have different current-voltage characteristic curves.

[0011] There is a need for an improved analog neuromorphic memory system that compensates for differences in current-voltage characteristic curves between different memory cells and transistors. Summary of the Invention

[0012] This invention discloses numerous embodiments for compensating for slope differences in the current-voltage characteristic curves between a reference transistor, a reference memory cell, and a flash memory cell during read operations in a simulated neural memory within a deep learning artificial neural network. These embodiments are capable of compensating for slope differences during both subthreshold and linear operations of the reference transistor. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating an existing artificial neural network.

[0014] Figure 2 This is a cross-sectional side view of a conventional 2-gate non-volatile memory cell.

[0015] Figure 3 This is a cross-sectional side view of a conventional 4-gate non-volatile memory cell.

[0016] Figure 4 This is a side cross-sectional view of a conventional 3-gate non-volatile memory cell.

[0017] Figure 5 A cross-sectional side view of another conventional 2-gate nonvolatile memory cell.

[0018] Figure 6 This is a schematic diagram illustrating different stages of an exemplary artificial neural network utilizing an array of non-volatile memory.

[0019] Figure 7 A block diagram illustrating the vector multiplier matrix.

[0020] Figure 8 A block diagram illustrating the various levels of the vector multiplier matrix.

[0021] Figure 9 Another implementation scheme for the vector multiplier matrix is ​​described.

[0022] Figure 10 Another implementation scheme for the vector multiplier matrix is ​​described.

[0023] Figure 11 Describing the Figure 10 The operating voltage for the vector multiplier matrix to perform operations.

[0024] Figure 12 Another implementation scheme for the vector multiplier matrix is ​​described.

[0025] Figure 13 Describing the Figure 12 The operating voltage for the vector multiplier matrix to perform operations.

[0026] Figure 14 Another implementation scheme for the vector multiplier matrix is ​​described.

[0027] Figure 15 Describing the Figure 14 The operating voltage for the vector multiplier matrix to perform operations.

[0028] Figure 16 Another implementation scheme for the vector multiplier matrix is ​​described.

[0029] Figure 17 Describing the Figure 16 The operating voltage for the vector multiplier matrix to perform operations.

[0030] Figure 18A A reference transistor is depicted.

[0031] Figure 18B Depicting Figure 18A The subthreshold current-voltage characteristic curve of the reference transistor.

[0032] Figure 18C Depicting Figure 18A The linear current-voltage characteristic curve of the reference transistor.

[0033] Figure 18D The memory cell is described.

[0034] Figure 18E Depicting Figure 18C The subthreshold current-voltage characteristic curve of the memory cell.

[0035] Figure 18F Depicting Figure 18D The linear current-voltage characteristic curve of the memory cell.

[0036] Figure 19 A reference transistor is depicted.

[0037] Figure 20 The reference memory cell is described.

[0038] Figure 21 Another reference memory cell is described.

[0039] Figure 22 The changes in the characteristic curve based on slope compensation are depicted.

[0040] Figure 23 An implementation scheme for the slope compensation system is described.

[0041] Figure 24 Another implementation scheme of the slope compensation system is described.

[0042] Figure 25 Another implementation scheme of the slope compensation system is described.

[0043] Figure 26 Another implementation scheme of the slope compensation system is described.

[0044] Figure 27 An implementation scheme for a memory cell array is described.

[0045] Figure 28 The current-voltage characteristic curves of various slope compensation systems were depicted.

[0046] Figure 29 The current-voltage characteristic curves of various slope compensation systems were depicted.

[0047] Figure 30 An exemplary reference transistor and its current-voltage characteristic curves are depicted.

[0048] Figure 31 The data stored in the lookup table is depicted to compensate for slope differences.

[0049] Figure 32 It describes existing long short-term memory systems.

[0050] Figure 33 An exemplary cell in a prior art long short-term memory system is depicted.

[0051] Figure 34 Depicting Figure 33 A specific implementation of an exemplary cell in a long short-term memory system.

[0052] Figure 35 A prior art gated loop unit system is described.

[0053] Figure 36 An exemplary cell in a prior art gated loop cell system is depicted.

[0054] Figure 37 Depicting Figure 36 A specific implementation of an exemplary cell in a gated loop unit system. Detailed Implementation

[0055] The artificial neural network of this invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0056] Non-volatile memory cells

[0057] Digital nonvolatile memory is well known. For example, U.S. Patent 5,029,130 ​​(“the '130 patent’) discloses a split-gate nonvolatile memory cell array, which is incorporated herein by reference for all purposes. Such memory cells in Figure 2 As shown in the figure. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 16. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0058] The memory cell 210 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel from the floating gate 20 to the word line terminal 22 through the intermediate insulator via Fowler-Nordheim tunneling.

[0059] Memory cell 210 is programmed by applying a positive voltage to word line terminal 22 and a positive voltage to source terminal 16 (where electrons are placed on the floating gate). Electron current flows from source terminal 16 to drain terminal 14. When electrons reach the gap between word line terminal 22 and floating gate 20, they accelerate and become hot. Due to electrostatic attraction from floating gate 20, some heated electrons are injected into floating gate 20 through gate oxide 26.

[0060] Memory cell 210 is read by applying a positive read voltage to drain 14 and word line terminal 22 (which is connected to the channel region below the word line terminal). If floating gate 20 is positively charged (i.e., electrons are erased and positively coupled to drain 16), the portion of the channel region below floating gate 20 is also connected, and current flows through channel region 18, which is sensed as erased or "1". If floating gate 20 is negatively charged (i.e., programmed electronically), the portion of the channel region below floating gate 20 is mostly or completely turned off, and current does not (or very little) flow through channel region 18, which is sensed as programmed or "0".

[0061] Table 1 shows the typical voltage range that can be applied to the terminals of memory cell 210 to perform read, erase, and program operations:

[0062] Table 1: Figure 2 Operation of flash memory cell 210

[0063] WL BL SL Read 2V-3V 0.6V-2V 0V erase Approximately 11-13V 0V 0V programming 1V-2V 1-3μA 9V-10V

[0064] Other split-gate memory cell configurations are known. For example, Figure 3 A quad-gate memory cell 310 is shown, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 28 (typically coupled to a word line) over a second portion of the channel region 18, a control gate 22 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected to or can be electrically connected to a voltage source. Programming is illustrated by heated electrons from the channel region 18, which inject themselves onto the floating gate 20. Erasing is illustrated by electrons tunneling from the floating gate 20 to the erase gate 30.

[0065] Table 2 depicts the typical voltage range that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations:

[0066] Table 2: Figure 3 Operation of flash memory cell 310

[0067] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0-2.6V 0-2.6V 0V erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 1μA 8V-11V 4.5V-9V 4.5V-5V

[0068] Figure 4 A split-gate tri-gate memory cell 410 is shown. Memory cell 410 and... Figure 3 The memory cell 310 is the same as the memory cell 410, except that the memory cell 410 does not have a separate control gate. Erase operations (erasing via the erase gate) and read operations are the same as... Figure 3 The operation is similar, except that there is no control gate bias. The programming operation is also performed without control gate bias, so the programming voltage on the source line is higher to compensate for the lack of control gate bias.

[0069] Table 3 depicts the typical voltage range that can be applied to the terminals of memory cell 410 to perform read, erase, and program operations:

[0070] Table 3: Figure 4 Operation of flash memory cell 410

[0071]

[0072] Figure 5A stacked gate memory cell 510 is shown. The memory cell 510 is similar to... Figure 2 The memory cell 210 differs in that the floating gate 20 extends over the entire channel region 18, and the control gate 22 extends over the floating gate 20, separated by an insulating layer. Erase, program, and read operations operate in a manner similar to those previously described for memory cell 210.

[0073] Table 4 depicts the typical voltage range that can be applied to the terminals of memory cell 510 to perform read, erase, and program operations:

[0074] Table 4: Figure 5 Operation of flash memory cell 510

[0075] CG BL SL P-sub Read 2V-5V 0.6V–2V 0V 0V erase -8V to -10V / 0V FLT FLT 8V-10V / 15-20V programming 8V-12V 3V-5V 0V 0V

[0076] To utilize memory arrays comprising one of the aforementioned types of non-volatile memory cells in artificial neural networks, two modifications were made. First, the circuitry was configured such that each memory cell could be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, continuous (simulated) programming of the memory cells was provided.

[0077] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state independently and with minimal interference to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state and vice versa, independently and with minimal interference to other memory cells. This means that the cell storage device is analog, or at least can store one discrete value from many discrete values ​​(such as 16 or 64 different values), which allows for very precise and individual tuning of all cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0078] Neural networks using non-volatile memory cell arrays

[0079] Figure 6 A conceptual, non-limiting example of a neural network utilizing a non-volatile memory array is illustrated. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application can also be implemented using a neural network based on a non-volatile memory array.

[0080] In this example, S0 is the input, which is a 32×32 pixel RGB image with 5-bit precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5-bit precision per pixel). The synapse CB1 from S0 to C1 has both different sets of weights and shared weights, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by one pixel (or more than one pixel as indicated by the model). Specifically, the values ​​of nine pixels in a 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, whereby these nine input values ​​are multiplied by the appropriate weights, and after summing the output of this multiplication, a single output value is determined and provided by the first neuron of CB1 to generate the pixels of one layer of feature mapping, C1. The 3×3 filter is then shifted one pixel to the right (i.e., adding a column of three pixels on the right and releasing a column of three pixels on the left), whereby nine pixel values ​​in this newly positioned filter are provided to synapse CB1, whereby they are multiplied by the same weights, and a second single output value is determined by the associated neuron. Continue this process until the 3×3 filter scans all three colors and all bits (precision values) across the entire 32×32 pixel image. Then repeat the process with different sets of weights to generate different feature maps for C1, until all feature maps for layer C1 are computed.

[0081] At C1, in this example, there are 16 feature maps, each with 30×30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array. Therefore, in this example, synapse CB1 consists of a 16-layer two-dimensional array (remember that the neuron layers and arrays referred to in this article are logical relationships, not necessarily physical relationships; that is, the array does not have to be oriented to a physical two-dimensional array). Each of the 16 feature maps is generated by a set of sixteen different groups of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary recognition. For example, the first map (generated using the first weight recombination, shared for all scans used to generate the first map) can recognize circular edges, the second map (generated using the second weight recombination, different from the first weight recombination) can recognize rectangular edges, or the aspect ratio of certain features, and so on.

[0082] Before transitioning from C1 to S1, activation function P1 (pooling) is applied, which pools values ​​from consecutive non-overlapping 2×2 regions in each feature map. The purpose of the pooling phase is to average the neighboring locations (or, alternatively, use a max function) to, for example, reduce dependence on edge locations and decrease the data size before moving to the next stage. At S1, there are 16 15×15 feature maps (i.e., 16 different arrays, each 15×15 pixels). The synapses and associated neurons in CB2 from S1 to C2 scan the maps in S1 using a 4×4 filter, where the filter is shifted by 1 pixel. At C2, there are 22 12×12 feature maps. Before transitioning from C2 to S2, activation function P2 (pooling) is applied, which pools values ​​from consecutive non-overlapping 2×2 regions in each feature map. At S2, there are 22 6×6 feature maps. Activation functions are applied to the synapses CB3 from S2 to C3, where each neuron in C3 is connected to each map in S2. At C3, there are 64 neurons. The synapse CB4, from C3 to output S3, completely connects S3 to C3. The output at S3 consists of 10 neurons, with the highest-output neuron determining the class. For example, this output can indicate the recognition or classification of the content of the original image.

[0083] Each level of synapse is implemented using an array or a portion of an array of non-volatile memory cells. Figure 7 This is a block diagram of a vector-matrix multiplication (VMM) array that includes non-volatile memory cells and serves as a synapse between the input layer and the next layer. Specifically, VMM 32 includes a non-volatile memory cell array 33, erase gate and word line gate decoders 34, control gate decoders 35, bit line decoders 36, and source line decoders 37, which decode the inputs of memory array 33. In this example, source line decoder 37 also decodes the outputs of the memory cell array. Alternatively, bit line decoder 36 can decode the outputs of the memory array. The memory array serves two purposes. First, it stores weights that will be used by the VMM. Second, the memory array efficiently multiplies the inputs with the weights stored in the memory array and adds them together at each output line (source line or bit line) to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits, and in-situ memory computation is also highly efficient.

[0084] The output of the memory array is provided to a differential adder (such as an adder operational amplifier or an adder current mirror) 38, which sums the output of the memory cell array to create a single value for the convolution. The differential adder is used to sum the positive and negative weights with the positive input. The summed output value is then provided to an activation function circuit 39, which modifies the output. The activation function may include a sigmoid, tanh, or ReLU function. The modified output value becomes an element of the feature map for the next layer (e.g., C1 as described above) and is then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the memory array constitutes multiple synapses (which receive their inputs from existing neuron layers or from input layers such as an image database), and the summing operational amplifier 38 and the activation function circuit 39 constitute multiple neurons.

[0085] Figure 8 This is a block diagram of each level of the VMM. For example... Figure 8 As shown, the input is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM 32a. The converted analog input can be voltage or current. The input D / A conversion of the first layer can be accomplished by using a function or LUT (lookup table) that maps the input to the appropriate analog level of the matrix multiplier. Input conversion can also be accomplished by an A / A converter to convert the external analog input to an analog input mapped to the VMM. The output generated by input VMM 32a is provided as the input to the next VMM (hidden level 1) 32b, which in turn generates the output provided as the input to the next VMM (hidden level 2) 32b, and so on. The layers of VMM 32 serve as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM can be an independent non-volatile memory array, or multiple VMMs can utilize different portions of the same non-volatile memory array, or multiple VMMs can utilize overlapping portions of the same non-volatile memory array. Figure 8 The example shown contains five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will recognize that this is merely exemplary, and conversely, a system may include more than two hidden layers and more than two fully connected layers.

[0086] Vector-Matrix Multiplication (VMM) Array

[0087] Figure 9 The neuron VMM 900 is shown, which is particularly suitable for Figure 3The VMM 900 comprises a memory array 901 of non-volatile memory cells and a reference array 902 (at the top of the array). Alternatively, another reference array may be placed at the bottom. In the VMM 900, control gate lines (such as control gate line 903) extend in a vertical direction (therefore the reference array 902 is in a row direction orthogonal to the input control gate lines), and erase gate lines (such as erase gate line 904) extend in a horizontal direction. Here, inputs are provided on the control gate lines, and outputs appear on the source lines. In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on the source lines performs a summation function from all currents from the memory cells connected to the source lines.

[0088] As described herein with respect to neural networks, flash memory cells are preferably configured to operate in the subthreshold region.

[0089] The memory cells described in this article are weakly reverse biased:

[0090] Ids = Io * e (Vg-Vth) / kVt =w*Io*e (Vg) / kVt

[0091] w = e (-Vth) / kVt

[0092] For an I-to-V logarithmic converter that uses a memory cell to convert input current to input voltage:

[0093] Vg = k * Vt * log[Ids / wp * Io]

[0094] For a memory array used as a vector matrix multiplier (VMM), the output current is:

[0095] Iout = wa * Io * e (Vg) / kVt ,Right now

[0096] Iout = (wa / wp) * Iin = W * Iin

[0097] W = e (Vthp-Vtha) / kVt

[0098] Word lines or control gates can be used as inputs to memory cells that accept input voltages.

[0099] Alternatively, the flash memory cell can be configured to operate in a linear region:

[0100] Ids=beta*(Vgs-Vth)*Vds; beta=u*Cox*W / L

[0101] Wα(Vgs-Vth)

[0102] For an I-to-V linear converter, a memory cell operating in the linear region can be used to linearly convert input / output current into input / output voltage.

[0103] Other implementations of the ESF vector matrix multiplier are described in U.S. Patent Application 15 / 826345, which is incorporated herein by reference. Source lines or bit lines can be used as neuron outputs (current summation outputs).

[0104] Figure 10 The neuron VMM 1000 is shown, which is particularly suitable for Figure 2 The VMM 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001, and a reference array 1002. Reference arrays 1001 and 1002, in the column direction of the array, are used to convert the current input flowing into terminal BLR0-3 into a voltage input WL0-3. In practice, the reference memory cells are diodes connected via multiplexers, into which the current input flows. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix. Memory array 1003 serves two purposes. First, it stores weights that will be used by the VMM 1000. Secondly, memory array 1003 efficiently multiplies the input (current input provided in terminal BLR0-3; reference arrays 1001 and 1002 convert these current inputs into input voltages to provide to word lines WL0-3) by weights stored in the memory array and then adds the results (memory cell currents) to produce an output, which will be the input to the next layer or to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, voltage inputs are provided on the word lines, and outputs appear on the bit lines during read (inference) operations. The current placed on the bit lines performs a summation function from all currents from the memory cells connected to the bit lines.

[0105] Figure 11 The operating voltages for the VMM 1000 are shown. The columns in the table indicate the voltages applied to the word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. Rows indicate read, erase, and program operations.

[0106] Figure 12 The neuron VMM 1200 is described, which is particularly suitable for Figure 2The VMM 1200 comprises memory cells of the type shown, and serves as synapses and components for neurons between the input layer and the next layer. The VMM 1200 includes a memory array 1203, a reference array 1201, and a reference array 1202, all of which are non-volatile memory cells. The reference arrays 1201 and 1202, extending in the row direction of the VMM 1200, are similar to those of the VMM 1000, except that in the VMM 1200, word lines extend in the vertical direction. Here, inputs are provided on the word lines, and outputs appear on the source lines during read operations. The current placed on the source lines performs a summation function from all currents from the memory cells connected to the source lines.

[0107] Figure 13 The operating voltages for the VMM 1200 are depicted. The columns in the table indicate the voltages applied to the word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. Rows indicate read, erase, and program operations.

[0108] Figure 14 The neuron VMM 1400 was described, which is particularly suitable for Figure 3 The VMM 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401, and a reference array 1402. Reference arrays 1401 and 1402 are used to convert the current input flowing into terminal BLR0-3 into a voltage input CG0-3. In practice, the reference memory cells are diodes connected via a cascode multiplexer 1414, into which the current input flows. Multiplexer 1414 includes multiplexer 1405 and a cascode transistor 1404 to ensure a constant voltage on the bit line of the reference cell during reading. The reference cell is tuned to a target reference level. Memory array 1403 serves two purposes. First, it stores weights that will be used by the VMM 1400. Secondly, memory array 1403 efficiently multiplies the inputs (current inputs provided to terminal BLR0-3; reference arrays 1401 and 1402 convert these current inputs into input voltages to provide to control gate CG0-3) by weights stored in the memory array and then sums the results (cell currents) to produce an output, which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the inputs are provided on the word lines, and the outputs appear on the bit lines during read operations. The currents placed on the bit lines perform a summation function from all the currents from the memory cells connected to the bit lines.

[0109] The VMM 1400 implements unidirectional tuning for the memory cells in the memory array 1403. That is, each cell is erased and then partially programmed until the required charge is reached on the floating gate. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell must be erased, and the sequence of partial programming operations must start again. As shown, two rows sharing the same erase gate need to be erased together (called page erase), and thereafter, each cell is partially programmed until the required charge is reached on the floating gate.

[0110] Figure 15 The operating voltages for the VMM 1400 are depicted. The columns in the table indicate the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the voltage on the source line for the unselected cell. Rows indicate read, erase, and program operations.

[0111] Figure 16 The VMM 1600 neuron was described, which is particularly suitable for... Figure 3 The VMM 1600 consists of memory cells of the type shown, serving as synapses and components for neurons between the input layer and the next layer. The VMM 1600 includes a memory array 1603, a reference array 1601, and a reference array 1602 of non-volatile memory cells. The EG line extends vertically, while the CG and SL lines extend horizontally. The VMM 1600 is similar to the VMM 1400, except that the VMM 1600 implements bidirectional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to achieve the desired amount of charge on the floating gate. As shown, reference arrays 1601 and 1602 convert the input current in terminal BLR0-3 into a control gate voltage CG0-3 to be applied to the memory cell along the row direction (through the action of the reference cells connected via diodes of the multiplexer). The current output (neuron) is in the bit line, which sums all currents from the memory cells connected to the bit line.

[0112] Figure 17The operating voltages for the VMM 1600 are depicted. The columns in the table indicate the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the voltage on the source line for the unselected cell. Rows indicate read, erase, and program operations.

[0113] Existing technologies include a concept known as Long Short-Term Memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows neural networks to remember information for arbitrary time intervals and use that information in subsequent operations. A typical LSTM cell includes a cell, an input gate, an output gate, and a forget gate. These three gates regulate the flow of information into and out of the cell. Virtual Memory Models (VMMs) are particularly useful in LSTM cells.

[0114] Figure 32 An exemplary LSTM 3200 is depicted. In this example, the LSTM includes cells 3201, 3202, 3203, and 3204. Cell 3201 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 3202 receives the input vector x1, the output vector (hidden state) h0, and the cell state c0 from cell 3201 and generates the output vector h1 and the cell state vector c1. Cell 3203 receives the input vector x2, the output vector (hidden state) h1, and the cell state c1 from cell 3202 and generates the output vector h2 and the cell state vector c2. Cell 3204 receives the input vector x3, the output vector (hidden state) h2, and the cell state c2 from cell 3203 and generates the output vector h3. Additional cells can be used, and the LSTM with four cells is only an example.

[0115] Figure 33 Depicting what can be used Figure 32 An exemplary specific implementation of LSTM cell 3300 in cells 3201, 3202, 3203 and 3204 is shown. LSTM cell 3300 receives input vector x(t) and cell state vector c(t-1) from the previous cell and generates cell state (t) and output vector h(t).

[0116] The LSTM cell 3300 includes sigmoid function devices 3301, 3302, and 3303, each employing a number between 0 and 1 to control how much of each component of the input vector is allowed to reach the output vector. The LSTM cell 3300 also includes hyperbolic tangent devices 3304 and 3305 for applying a hyperbolic tangent function to the input vector, multiplier devices 3306, 3307, and 3308 for multiplying two vectors together, and an adder device 3309 for adding two vectors together.

[0117] Figure 34 The LSTM cell 3400 is depicted, which is an example of a concrete implementation of the LSTM cell 3300. For the reader's convenience, in... Figure 34 And used in LSTM cell 3400 Figure 33 Same numbering as LSTM cell 3300. (For example, in...) Figure 34 As can be seen, the S-shaped function devices 3301, 3302, and 3303, as well as the hyperbolic tangent devices 3304 and 3305, each include multiple VMM arrays 3401. Therefore, it can be seen that VMM arrays are particularly important in LSTM cells used in some neural network systems.

[0118] It is also understood that LSTM systems typically include multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM array itself (such as adders, activation blocks, and high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be inefficient to some extent. Therefore, the implementation described below attempts to minimize the circuitry required outside the VMM arrays themselves.

[0119] Similarly, a simulated VMM implementation can be used in a GRU (Gated Recurrent Unit) system. A GRU is a gating mechanism in recurrent neural networks. A GRU is similar to an LSTM, with one significant difference being that a GRU lacks an output gate.

[0120] Figure 35An exemplary GRU 3500 is depicted. This example GRU includes cells 3501, 3502, 3503, and 3504. Cell 3501 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 3502 receives an input vector x1, an output vector (hidden state) h0, and a cell state c0 from cell 3501, and generates an output vector h1 and a cell state vector c1. Cell 3503 receives an input vector x2, an output vector (hidden state) h1, and a cell state c1 from cell 3502, and generates an output vector h2 and a cell state vector c2. Cell 3504 receives an input vector x3, an output vector (hidden state) h2, and a cell state c2 from cell 3503, and generates an output vector h3. Additional cells may be used, and the GRU with four cells is merely an example.

[0121] Figure 36 Depicting what can be used Figure 35 An exemplary specific implementation of GRU cell 3600, comprising cells 3501, 3502, 3503, and 3504, is shown below. GRU cell 3600 receives an input vector x(t) and a cell state vector h(t-1) from the previous cell and generates a cell state h(t). GRU cell 3600 includes S-shaped function devices 3601 and 3602, each applying a number between 0 and 1 to the components from cell state h(t-1) and input vector x(t). GRU cell 3600 also includes a hyperbolic tangent device 3603 for applying a hyperbolic tangent function to the input vector, multiplier devices 3604, 3605, and 3606 for multiplying two vectors together, an adder device 3607 for adding two vectors together, and a complement device 3608 for subtracting the input from 1 to generate the output.

[0122] Figure 37 The GRU cell 3700 is depicted, which is an example of a concrete implementation of the GRU cell 3600. For the reader's convenience, in... Figure 37 And used in GRU cell 3700 Figure 36 Same number as GRU cell 3600. (For example, in...) Figure 37 As can be seen, the S-shaped function devices 3601 and 3602 and the hyperbolic tangent device 3603 each include multiple VMM arrays 3701. Therefore, it can be seen that VMM arrays are particularly useful in GRU cells used in some neural network systems.

[0123] It is also understood that a GRU system will typically include multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM array itself (such as adder and activation circuit blocks, and high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be inefficient to some extent. Therefore, the implementation described below attempts to minimize the circuitry required outside the VMM arrays themselves.

[0124] Figure 18A An exemplary reference transistor 1801 is depicted, such as for use with Figure 9 The reference transistor in the reference array 902, Figure 10 Reference arrays 1001 / 1002 in Figure 12 Reference arrays 1201 / 1202 in Figure 14 Reference arrays 1401 / 1402 in Figure 16 The reference array 1601 / 1602 is used. When the reference transistor 1801 operates in the subthreshold region, the amount of current drawn, Ids, increases logarithmically linearly (exponentially) with increasing voltage Vgs. Figure 18B An exemplary current-voltage characteristic curve 1802 is shown. It can be seen that the logarithmic curve 1802 has a certain slope.

[0125] When the reference transistor 1801 operates in the linear region, the amount of current drawn, Ids, increases linearly with increasing voltage Vgs. Figure 18C An exemplary current-voltage characteristic curve 1802 is shown. It can be seen that curve 1803 has a certain slope.

[0126] Figure 18D An exemplary memory cell 1804 is depicted. When the memory cell 1804 operates in the subthreshold region, the amount of current drawn, Ids, increases exponentially with the increase of voltage Vwl / Vcg. Figure 18E An exemplary current-voltage characteristic curve 1805 is shown. It can be seen that curve 1805 has a certain slope.

[0127] Figure 18D An exemplary memory cell 1804 is depicted. When the memory cell 1804 operates in the linear region, the amount of current drawn, Ids, increases linearly with the increase of voltage Vwl / Vcg. Figure 18F An exemplary current-voltage characteristic curve 1806 is shown. It can be seen that curve 1804 has a certain slope. As shown, the slopes in the IV curves between the reference transistor and the memory cell can be different, therefore normalization (so that they have similar slopes) is required to match them.

[0128] Figure 19 Depicting having with Figure 18A An exemplary reference transistor 1900 with the same configuration as shown is illustrated. Figure 20 Another exemplary reference memory cell (word line coupled to bit line) with a different configuration is depicted, and Figure 21 Another exemplary reference memory cell (floating gate FG coupled to bit line) with a different configuration is depicted. It should be understood that each of these devices may have different current-voltage characteristic curves.

[0129] The implementation scheme described herein compensates for the slope differences in the current-voltage characteristic curves of the reference transistor, the reference memory cell, and / or selected memory cells.

[0130] In a system of two devices with different subthreshold current-voltage characteristic curves, the drain-source current through the first device will be:

[0131] Ids1=Ids0*exp(Vgs1–Vt) / k1*Ut

[0132] The drain-source current through the second device will be:

[0133] Ids2=Ids0*exp(Vgs2–Vt) / k2*Ut

[0134] It can be seen that in each case, the slope will be proportional to ~1 / k.

[0135] In some embodiments described below, slope normalization is implemented by using the gate-source voltage of the first device under the following conditions:

[0136] Vgs1=k*Vgs2

[0137] This would mean that Ids1 and Ids will have the same slope after slope normalization.

[0138] This is Figure 22 The diagram illustrates that when a voltage of Vgs1 = k * Vgs2 is applied to device 1, the slope of the current-voltage characteristic curve of the first device approximates the slope of the current-voltage characteristic curve of the second device.

[0139] Various implementation schemes for performing slope normalization will now be described.

[0140] Figure 23 A slope normalization system 2280 is depicted, which includes a reference transistor 2282 (such as, for...). Figure 9 Reference array 902 in Figure 10 Reference arrays 1001 / 1002 in Figure 12 Reference arrays 1201 / 1202 in Figure 14 Reference arrays 1401 / 1402 in Figure 16 Reference transistors in reference arrays 1601 / 1602), selected memory cell 2284 (such as...) Figure 9 Array 901 in Figure 10 Array 1003 in Figure 12 Array 1203 in Figure 14 Array 1403 in Figure 16 The array 2282 is a portion of the array 1603, with gate driver 2281 and absolute normalizer circuit 2403. Gate driver 2281 receives an input voltage Vgs and multiplies it by k to generate an output voltage Vgsint, which is applied to the gate of reference transistor 2282. Absolute normalizer circuit 2403 may be a trimmed current mirror (a current mirror circuit for adjusting the ratio between the current from the reference transistor and the current output from the memory cell), wherein the trimming process can adjust for differences caused by the reference transistor or array transistors or by IV slope mismatch. Selected memory cell 2282 is one of the memory cells in the memory cell array.

[0141] Figure 24 A slope normalization system 2400 is depicted, comprising a reference transistor 2401 and input adjustable capacitors 2402 and 2403. Adjustable capacitor 2402 receives an input voltage Vgs. The ratio of adjustable capacitors 2402 and 2403 affects the voltage Vgsint applied to the gate of the reference transistor. Therefore, the slope is changed by adjusting capacitors 2402 and 2403.

[0142] Figure 25 A slope normalization system 2500 is depicted, which includes operational amplifiers 2501 and 2502, resistors 2503, 2504 and 2505, and a variable resistor 2506. The slope normalization system 2500 receives an input voltage Vgs1 and outputs an output voltage Vgs1' regulated by the variable resistor 2506.

[0143] Figure 26 A slope normalization system 2600 is depicted, comprising a reference transistor 2601, a selected memory cell 2603, and a driver 2602. The driver 2602 receives a voltage Vgs and multiplies it by k to obtain an output voltage Vgs'. Therefore, the reference transistor 2601 and the selected memory cell 2603 will receive different voltages, where this difference results in a difference in slope.

[0144] Figure 27An array 2700 is depicted of memory cells (such as exemplary memory cells 2701, 2702, 2703, and 2704). The memory cells are connected in a configuration that allows compensation for the slope of a linear current-voltage reference curve for the memory cells.

[0145] Here, the current flowing through a specifically selected memory cell (such as memory cells 2701, 2702, 2703, or 2704) will be:

[0146] Ids=β*(Vgs-Vt)*Vds

[0147] Therefore, Vgs or Vds can be compensated by multiplying by k.

[0148] Figure 28 An exemplary current-voltage characteristic curve 2800 (Ids vs. Vds) based on the difference k is depicted.

[0149] Figure 29 An exemplary current-voltage characteristic curve 2800 (Ids vs. Vgs) based on the difference k is depicted.

[0150] Figure 30 An exemplary current-voltage characteristic curve 3002 of reference transistor 3001 is depicted. It should be understood that an ideal value for k can be determined such that... Figure 28 Or the slope of curve 29 is approximately equal to Figure 30 The slope of the curve.

[0151] Figure 31 An exemplary current-voltage characteristic curve 3100 is depicted for a transistor, a reference memory cell, or a selected memory cell as the operating temperature of the device changes. In this embodiment, the data for curve 3100 is stored in a lookup table 3101, and k is determined by the lookup table 3101 rather than by a mathematical formula during operation. The lookup table 3101 may contain different desired output currents for each input voltage at various operating temperatures. This data may be populated in the lookup table 3101 during the manufacturing or testing process. The reference memory cell and the selected memory cell are optionally non-volatile flash memory cells.

[0152] It should be noted that, as used herein, the terms “above” and “on” both encompass “directly on” (without intermediate material, elements, or space between) and “indirectly on” (with intermediate material, elements, or space between). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or space between) and “indirectly adjacent” (with intermediate material, elements, or space between), “mounted to” includes “directly mounted to” (without intermediate material, elements, or space between) and “indirectly mounted to” (with intermediate material, elements, or space between), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming an element directly on the substrate without intermediate material / elements between them, and forming an element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A method for adjusting a reference transistor in a flash memory system, the method comprising: Receive an input voltage, wherein the input voltage is connected to the drain of the reference transistor; The input voltage is multiplied by a coefficient to generate the output voltage; The output voltage is applied to the gate of the reference transistor; as well as The reference transistor is used in the sensing operation to determine the value stored in the selected memory cell. The slope difference between the current-voltage characteristic curves of the reference transistor and the selected memory cell is compensated during the read operation so that the slopes of the current-voltage characteristic curves of the reference transistor and the selected memory cell are approximately equal during the sensing operation.

2. The method according to claim 1, further comprising: The input voltage is coupled to the gate of a memory cell in the memory array.

3. The method of claim 1, wherein the reference transistor operates in the subthreshold region.

4. The method of claim 1, wherein the reference transistor operates in a linear region.

5. The method of claim 2, wherein the reference transistor operates in the subthreshold region.

6. The method of claim 2, wherein the reference transistor operates in a linear region.

7. The method of claim 1, wherein the input current is connected to the drain of the reference transistor to generate the input voltage.

8. The method of claim 1, wherein the input voltage is coupled to a normalization circuit.

9. The method of claim 8, wherein the output of the normalization circuit is connected to the selected memory cell.

10. The method of claim 8, wherein the normalization circuit is a current mirror circuit.

11. The method of claim 8, wherein the value from the memory cell is a bit line current or a source line current.

12. The method of claim 1, wherein the memory cell is non-volatile.

13. The method of claim 1, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a driver circuit coupled to the gate of the reference transistor.

14. The method of claim 1, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a pair of input capacitors coupled to the gate of the reference transistor.

15. The method of claim 1, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a pair of operational amplifiers coupled to the gate of the reference transistor.

16. A method for adjusting a reference transistor in a flash memory system, the method comprising: Receive an input voltage, wherein the input voltage is connected to the drain of the reference transistor; The input voltage is multiplied by a coefficient to generate the output voltage; The output voltage is applied to the gate of the memory cell; as well as The reference transistor is used in the sensing operation to determine the value stored in one of the memory cells. The slope difference between the current-voltage characteristic curves of the reference transistor and the memory cell is compensated during the read operation so that the slopes of the current-voltage characteristic curves of the reference transistor and the memory cell are approximately equal during the sensing operation.

17. The method of claim 16, further comprising applying the input voltage to the gate of the reference transistor.

18. The method of claim 16, wherein the reference transistor operates in the subthreshold region.

19. The method of claim 16, wherein the reference transistor operates in a linear region.

20. The method of claim 16, wherein the memory cell operates in the subthreshold region.

21. The method of claim 16, wherein the memory cell operates in a linear region.

22. The method of claim 16, wherein the input current is connected to the drain of the reference transistor to generate the input voltage.

23. The method of claim 16, wherein the value from one of the memory cells is a bit line current or a source line current.

24. The method of claim 16, wherein the memory cell is non-volatile.

25. A method for adjusting the characteristic curve of a reference memory cell in a flash memory system, the method comprising: Receive an input voltage, wherein the input voltage is connected to the drain of a reference transistor; The input voltage is multiplied by a coefficient to generate the output voltage; The output voltage is applied to the gate of the reference memory cell; as well as The reference memory cell is used in the sensing operation to determine the value stored in the selected memory cell. The difference in the slope of the current-voltage characteristic curves of the reference memory cell and the selected memory cell is compensated during the read operation so that the slopes of the current-voltage characteristic curves of the reference memory cell and the selected memory cell are approximately equal during the sensing operation.

26. The method of claim 25, wherein the reference transistor operates in the subthreshold region.

27. The method of claim 25, wherein the reference transistor operates in a linear region.

28. The method of claim 25, wherein the reference memory cell operates in a subthreshold region.

29. The method of claim 25, wherein the reference memory cell operates in a linear region.

30. The method of claim 25, wherein the memory cell is non-volatile.

31. The method of claim 25, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a driver circuit coupled to the gate of the reference memory cell.

32. The method of claim 25, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a pair of input capacitors coupled to the gate of the reference memory cell.

33. The method of claim 25, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a pair of operational amplifiers coupled to the gate of the reference memory cell.

34. A method for adjusting the slope of the current-voltage characteristic curve of a selected memory cell in a flash memory system, the method comprising: Receive an input voltage, wherein the input voltage is connected to the drain of a reference device, the reference device being a transistor or a memory cell; The input voltage is multiplied by a coefficient to generate the output voltage; The output voltage is applied to the gate of the selected memory cell; as well as The selected memory cell and the reference device are used to perform a sensing operation to determine the value stored in the selected memory cell; The slope difference between the current-voltage characteristic curves of the reference device and the selected memory cell is compensated during the read operation so that the slope of the current-voltage characteristic curve of the reference device and the slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sensing operation.

35. The method of claim 34, wherein the step of multiplying the input voltage by a coefficient to generate the output voltage is performed by a driver circuit coupled to the gate of the selected memory cell.

36. A flash memory system with built-in compensation for the slope difference of the current-voltage characteristic curves of a reference transistor and selected memory cells, the flash memory system comprising: Reference transistor; Selected memory unit; and A compensation circuit, coupled to the reference transistor, is configured to compensate for the slope difference of the current-voltage characteristic curves of the reference transistor and the selected memory cell during a read operation, such that the slope of the current-voltage characteristic curve of the reference transistor and the slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during a sensing operation, in order to determine the value stored in the selected memory cell.

37. The system of claim 36, wherein the compensation circuit includes a driver circuit coupled to the gate of the reference transistor.

38. The system of claim 36, wherein the compensation circuit includes a pair of input capacitors coupled to the gate of the reference transistor.

39. The system of claim 36, wherein the compensation circuit includes a pair of operational amplifiers coupled to the gate of the reference transistor.

40. The system of claim 36, wherein the flash memory system is used for a vector multiplication matrix multiplication array in a long short-term memory system.

41. The system of claim 36, wherein the flash memory system is used in a vector multiplication matrix multiplication array in a gated loop unit system.

42. A flash memory system with built-in compensation for the slope difference of the current-voltage characteristic curves of a reference memory cell and a selected memory cell, the flash memory system comprising: Reference memory cell; Selected memory unit; and A compensation circuit, coupled to the reference memory cell, is configured to compensate for the slope difference of the current-voltage characteristic curves of the reference memory cell and the selected memory cell during a read operation, so that the slopes of the current-voltage characteristic curves of the reference memory cell and the selected memory cell are approximately equal during a sensing operation, in order to determine the value stored in the selected memory cell.

43. The system of claim 42, wherein the compensation circuit includes a driver circuit coupled to the gate of the reference memory cell.

44. The system of claim 42, wherein the compensation circuit includes a pair of input capacitors coupled to the gate of the reference memory cell.

45. The system of claim 42, wherein the compensation circuit includes a pair of operational amplifiers coupled to the gate of the reference memory cell.

46. ​​The system of claim 42, wherein the flash memory system is used as a vector multiplication matrix multiplication array in a long short-term memory system.

47. The system of claim 42, wherein the flash memory system is used in a vector multiplication matrix multiplication array in a gated loop unit system.

48. A flash memory system having compensation for the slope difference of the current-voltage characteristic curves of a reference device and selected memory cells, the flash memory system comprising: Reference device, wherein the reference device is a transistor or a memory cell; Selected memory unit; and A compensation circuit, coupled to the selected memory cell, is configured to compensate for the slope difference of the current-voltage characteristic curves of the reference device and the selected memory cell during a read operation, such that the slopes of the current-voltage characteristic curves of the reference device and the selected memory cell are approximately equal during a sensing operation to determine a value stored in the selected memory cell. The compensation circuit includes a driver circuit coupled to the gate of the selected memory cell, the driver circuit being adapted to receive an input voltage, multiply the input voltage by a coefficient to generate an output voltage, and apply the output voltage to the gate of the selected memory cell.

49. The system of claim 48, wherein the flash memory system is used for a vector multiplication matrix multiplication array in a long short-term memory system.

50. The system of claim 48, wherein the flash memory system is used in a vector multiplication matrix multiplication array in a gated loop unit system.

51. A flash memory system having compensation for the slope difference of current-voltage characteristic curves of a reference device and a selected memory cell, said reference device being a transistor or memory cell, said flash memory system comprising: Input current; Reference lookup table, wherein the lookup table includes data derived from current-voltage characteristic curves based on different operating temperatures of the reference transistor; and Selected memory unit; An input voltage is generated based on the input current to be applied to the gate of the selected memory cell and the reference lookup table, wherein the input voltage is connected to the drain of the reference device, and The slope difference of the current-voltage characteristic curves of the reference device and the selected memory cell is compensated during the read operation so that the slope of the current-voltage characteristic curve of the reference device and the slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sensing operation.

52. The system of claim 51, wherein the memory cell is non-volatile.

53. The system of claim 51, wherein the flash memory system is used as a vector multiplication matrix multiplication array in a long short-term memory system.

54. The system of claim 51, wherein the flash memory system is used in a vector multiplication matrix multiplication array in a gated loop unit system.

Images