Photomask structure, method of manufacturing the same and semiconductor manufacturing method using the same

Abstract

Embodiments of the present invention relate to photomask structures, methods of manufacturing the same, and semiconductor manufacturing methods using the same. Embodiments of the present invention provide a method for manufacturing a photomask. The method includes several operations. A photomask substrate having a chip region and a peripheral region adjacent to the chip region is received. A reference pattern is formed in the peripheral region by emitting a first radiation shot and a first beta pattern is formed by emitting a plurality of second radiation shots. The plurality of second radiation shots are emitted along a first direction. A roughness of a boundary of the first beta pattern along the first direction is compared to a roughness of a boundary of the reference pattern along the first direction from a top view perspective. If a result of the comparison exceeds a tolerance, an alignment of the plurality of second radiation shots is adjusted, or the photomask is formed. Embodiments of the present invention also provide a photomask structure and a method for manufacturing a semiconductor.

Description

Technical Field

[0001] The present invention relates to a photomask structure, a method for manufacturing the same, and a semiconductor manufacturing method using the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using fabrication) has decreased. This scaling-down process generally delivers benefits by improving production efficiency and reducing associated costs, while increasing the amount of functionality that can be provided within a reduced chip area. This scaling-down has resulted in increased complexity in processing and manufacturing ICs, and the processes required for effective quality control of the products have become increasingly stringent. Summary of the Invention

[0003] According to an embodiment of the present invention, a method for manufacturing a photomask includes: receiving a photomask substrate having a chip area and a peripheral area adjacent to the chip area; forming a reference pattern by emitting a first radiation exposure in the peripheral area; forming a first β pattern by emitting a plurality of second radiation exposures in the peripheral area, wherein the plurality of second radiation exposures are emitted along a first direction; comparing the roughness of a boundary of the first β pattern along the first direction with the roughness of a boundary of the reference pattern along the first direction from a top-down perspective; adjusting the alignment of the plurality of second radiation exposures if a result of the comparison exceeds a tolerance; and forming the photomask if the result of the comparison is within the tolerance.

[0004] According to an embodiment of the present invention, a method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip area and a peripheral area adjacent to the chip area; forming a design pattern in the chip area; forming a reference pattern by emitting a first radiation exposure and forming a β pattern by emitting a plurality of second radiation exposures in the peripheral area, wherein the pixel size of the first radiation exposure is larger than the pixel size of the second radiation exposure; comparing a reference roughness of a boundary of the reference pattern with a β roughness of a boundary of the β pattern; if the difference between the reference roughness and the β roughness is within a tolerance, transferring the design pattern to the shielding layer; and transferring the design pattern to a semiconductor substrate.

[0005] According to an embodiment of the present invention, a photomask structure includes: a chip region and a peripheral region adjacent to the chip region; a design pattern located in the chip region; and a plurality of test patterns located in the peripheral region and separated from the design pattern, wherein the plurality of test patterns include: a reference pattern having a first boundary; and a β pattern having a second boundary, wherein the roughness of the second boundary is greater than the roughness of the first boundary. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flow chart illustrating various stages of a method for manufacturing a photomask according to some embodiments of the present invention.

[0008] Figure 2 is a flow chart illustrating various stages of a method for fabricating a semiconductor according to some embodiments of the present invention.

[0009] Figures 3 to 7 is a schematic diagram of various stages of a method according to one or more embodiments of the present invention.

[0010] Figures 8 to 10 is a top view of a photomask according to some embodiments of the present invention.

[0011] Figures 11 to 16 are cross-sectional views of a photomask substrate at various stages of a method according to some embodiments of the present invention.

[0012] Figures 17 to 18 are cross-sectional views of a photomask substrate at various stages of a method according to some embodiments of the present invention.

[0013] Figures 19 to 28 are cross-sectional views of a photomask substrate at various stages of a method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be directly contacted. In addition, embodiments of the present invention may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," and the like) may be used herein to describe the relationship of one element or component to another element or component, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, although terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and "third" as used herein do not imply a sequence or order.

[0017] Although the numerical ranges and parameters describing the broad scope of the embodiments of the present invention are approximate, the numerical values ​​described in the specific examples should be reported as precisely as possible. However, any numerical value inherently contains certain errors that are necessarily due to the standard deviation observed in each test measurement. In addition, as used herein, the terms "substantially," "approximately," and "about" generally mean within a value or range that one of ordinary skill in the art would consider. Alternatively, the terms "substantially," "approximately," and "approximately" mean within an acceptable standard deviation of the mean value that one of ordinary skill in the art would consider. One of ordinary skill in the art will understand that acceptable standard deviations can vary depending on the technology. Except in the operating / working examples or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein (e.g., numerical ranges, quantities, values, and percentages of material quantities, durations, temperatures, operating conditions, quantitative ratios, and the like) should be understood as being modified in all instances by the terms "substantially," "approximately," or "approximately." Therefore, unless otherwise indicated, the numerical parameters described in the embodiments of the present invention and the appended claims are approximate values ​​that can vary as desired. Finally, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other or between two endpoints. Unless otherwise indicated, all ranges disclosed herein include endpoints.

[0018] Photolithography is commonly used in the manufacture of semiconductor devices, in which the pattern of a photomask is transferred to a target substrate (typically a semiconductor substrate having a photosensitive layer disposed thereon). If the photomask has defects, the defects or changes in the pattern of the photomask are also transferred to the target substrate as defects in the pattern developed onto the semiconductor substrate. There are many reasons for defects. For example, defects may be caused by degradation of components of a mask writer during the manufacture of the photomask. If the defects are caused by the mask writer, the pattern of the photosensitive layer used in the exposure (or writing) operation of the photomask is deformed. However, small changes in the pattern of the photosensitive layer are difficult to detect, and after performing multiple pattern transfer operations on multiple layers via the photosensitive layer, the changes in the pattern eventually become defects.

[0019] Defects (which can be caused by slight variations in the boundaries or roughness of the pattern of the photosensitive layer) can be detected on the finished photomask. Post-strip inspection (ASI) of the finished photomask is provided to ensure the quality of the photomask before it is used in the patterning process of a semiconductor substrate, thereby improving the production yield of the semiconductor substrate. ASI can be performed to compare the general shape of the photomask pattern from a top-down perspective, eliminating the need for detailed inspection, as it cannot identify specific issues that cause defects. Furthermore, while the ASI is searching for defects, the next batch or even the next two batches of photomask substrates have already entered the mask writer, and similar defects are detected in the next batch or two batches of photomasks, reducing the production yield of the photomask.

[0020] Embodiments of the present invention provide a method for manufacturing photomasks, which includes providing post-etch inspection (AEI) or post-development inspection (ADI). The method of an embodiment of the present invention includes performing inspection of a pattern of a photomask having detailed variations to provide accurate and online or real-time inspection during the manufacture of the photomask. The inspection of an embodiment of the present invention can provide an analysis of defects in the photomask and can prepare solutions based on the inspection results. If the photomask fails the inspection, the process can be stopped and the problem can be corrected in real time. Similar defects and scrapping of the next batch or two of photomasks can be prevented, and thus the product yield of the photomask can be improved.

[0021] Figure 1 1 is a flowchart illustrating a method M10 for manufacturing a photomask according to some embodiments of the present invention. Method M10 includes several operations: (O101) receiving a photomask substrate having a chip region and a peripheral region adjacent to the chip region; (O102) forming a reference pattern by emitting a first radiation shot in the peripheral region; (O103) forming a first beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein the plurality of second radiation shots are emitted along a first direction; (O104) comparing, from a top view perspective, a roughness of a boundary of the first beta pattern along the first direction with a roughness of a boundary of the reference pattern along the first direction; (O105) adjusting the alignment of the plurality of second radiation shots if the result of the comparison exceeds a tolerance; and (O106) forming a photomask if the result of the comparison is within the tolerance. In some embodiments, after adjusting the alignment of the plurality of second radiation shots (O105), method M10 may return to operations O102 and O103. In some embodiments, operations O105 , O102 , O103 , and O104 may be repeatedly performed until the result of the comparison is within the tolerance and method M10 proceeds to operation O106 .

[0022] If the photomask passes one or more inspections according to embodiments of the present invention, then the photomask is used in a patterning operation of a semiconductor substrate.Thus, applying concepts similar to those applied in method M10, a method M20 for fabricating a semiconductor is provided. Figure 21 is a flowchart illustrating a method M20 for manufacturing a photomask according to some embodiments of the present invention. The method M20 includes several operations: (O201) receiving a photomask substrate including a shielding layer; (O202) defining a chip region and a peripheral region adjacent to the chip region; (O203) forming a design pattern in the chip region; (O204) forming a reference pattern by emitting a first radiation shot in the peripheral region, and forming a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is larger than a pixel size of the second radiation shot; (O205) comparing a reference roughness of a boundary of the reference pattern with a beta roughness of a boundary of the beta pattern; (O206) transferring the design pattern to the shielding layer if the difference between the reference roughness and the beta roughness is within a tolerance; and (O207) transferring the design pattern to a semiconductor substrate.

[0023] To illustrate the concepts and methods M10 and M20 of the present invention, various embodiments are provided below. However, it is not intended to limit the present invention to any particular embodiment. In addition, the elements, conditions, or parameters described in different embodiments may be combined or modified to form different combinations of embodiments, as long as the elements, parameters, or conditions used do not conflict. For ease of description, reference numerals for elements with similar or identical functions and properties are reused in different embodiments and figures.

[0024] Figures 3 to 4 is a schematic diagram illustrating operation O101 of method M10 and / or operations O201 through O202 of method M20 according to some embodiments of the present invention. A photomask substrate PS1 or PS2 is received and includes a chip area A1 and a peripheral area A2. In some embodiments, photomask substrate PS1 or PS2 includes a carrier layer, a shielding layer on the carrier layer, a hard layer on the shielding layer, and an optional shielding layer on the hard layer. A detailed description of the structure of photomask substrate PS1 or PS2 will be provided later in this specification.

[0025] In some embodiments, the peripheral region A2 surrounds the chip region A1. In some embodiments, the chip region A1 is located at the center of the photomask substrate PS1, and the peripheral region A2 is along the boundary of the photomask substrate PS1. Figure 3 In some embodiments, the pattern formed in the chip area A1 will be transferred to the semiconductor substrate, and the pattern formed in the peripheral area A2 will not be transferred to the semiconductor substrate. In some embodiments, the chip area A1 is the irradiation area during the exposure process. In some embodiments, the photomask substrate PS2 includes Figure 4, and peripheral area A2 surrounds and separates each of the chip areas A1. In some embodiments, portions of peripheral area A2 between adjacent chip areas A1 serve as spaces for scribe lines. In some embodiments, the patterns formed in peripheral area A2 are used for comparison operations in embodiments of the present invention. In some embodiments, the patterns formed in peripheral area A2 between chip areas A1 are transferred to scribe lines between chips on the semiconductor substrate.

[0026] Figures 5 to 7 1 is a schematic diagram illustrating operations O102 to O103 of method M10 and / or operations O204 to O205 of method M20 according to some embodiments of the present invention. Figures 5 to 7 Only the peripheral area A2 is shown.

[0027] Figure 5 Operation O102 of method M10 and / or operation O204 of method M20 are described according to some embodiments. Reference pattern R1 is formed by emitting radiation exposure P1 in peripheral area A2. The size of reference pattern R1 is the same as the pixel size of radiation exposure P1, and the pixel shape of reference pattern R1 is the same as the pixel shape of radiation exposure P1. In some embodiments, method M10 and / or method M20 further includes forming reference pattern R2 by emitting radiation exposure P2, wherein the orientation of reference pattern R2 is different from the orientation of reference pattern R1 so that critical dimensions along different directions can be measured. The size of reference pattern R2 is the same as the pixel size of radiation exposure P2, and the pixel shape of reference pattern R2 is the same as the pixel shape of radiation exposure P2. In some embodiments, radiation exposure P1 and / or radiation exposure P2 include an electron beam or a laser beam, depending on the mask writer or application.

[0028] In the following description, the length of a pattern is measured along its longitudinal direction, and the width of a pattern is measured along its transverse direction, where the transverse direction is generally perpendicular to the longitudinal direction. Furthermore, the roughness is focused on the boundary along the longitudinal direction of the pattern. Multiple widths are measured at different locations on the pattern. For example, the top width at one end of the pattern, the center width at the waist of the pattern, and the bottom width at the other end of the pattern are measured.

[0029] In addition, various reference patterns and β patterns are provided according to different embodiments. For ease of description and understanding, if similar parameters, conditions, characteristics, properties, functions, sub-operations, or optional operations have been described in other paragraphs or sections of this specification, the repeated description will be omitted. However, the embodiments of the present invention are not intended to be limited thereto.

[0030] In some embodiments, reference pattern R1 is polygonal. In some embodiments, reference pattern R1 is rectangular with a longitudinal dimension along the Y direction and a transverse dimension along the X direction. In some embodiments, the width W1 of reference pattern R1, measured along the X direction, is in the range of 90 nm (nanometers) to 150 nm. In some embodiments, the length L1 of pattern R1, measured along the Y direction, is in the range of 200 nm to 300 nm. In some embodiments, a boundary B1 of reference pattern R1 is measured along the Y direction, and a reference roughness can be obtained by measuring or comparing the boundary B1 of reference pattern R1. In some embodiments, the width W1 and length L1 of the formed reference pattern R1 closely match the desired width and length of reference pattern R1.

[0031] In some embodiments, reference pattern R2 is polygonal. In some embodiments, reference pattern R2 is rectangular. In some embodiments, reference pattern R1 and reference pattern R2 are substantially perpendicular. In some embodiments, reference pattern R2 has a longitudinal dimension along the X direction and a transverse dimension along the Y direction. In some embodiments, reference pattern R2 is separated from reference pattern R1 in peripheral area A2. In some embodiments, reference pattern R2 contacts reference pattern R1 in peripheral area A2. In some embodiments, a boundary B2 of reference pattern R2 is measured along the X direction, and a reference roughness can be obtained by measuring or comparing boundary B2 of reference pattern R2. In some embodiments, the width W2 and length L2 of the formed reference pattern R2 closely match the desired width and length of reference pattern R2.

[0032] In some embodiments, to facilitate measurement and detection, reference patterns R1 and R2 are formed in the peripheral area A2 with the same configuration (including size and shape) and different orientations, such as Figure 5 . However, embodiments of the present invention are not limited thereto. In some embodiments, reference patterns R1 and R2 have different configurations and different orientations. In some embodiments, the pixel size of radiation irradiation P1 is different from the pixel size of radiation irradiation P2. In some embodiments, the shape of reference pattern R1 is different from the shape of reference pattern R2.

[0033] Figure 6Operations O103-O104 of method M10 and / or operations O204-O205 of method M20 are described according to some embodiments. At least a beta pattern is formed by emitting a plurality of radiation shots in peripheral area A2. The pixel size of each of the plurality of radiation shots used to form the beta pattern is smaller than the pixel size of a corresponding reference pattern (e.g., reference pattern R1 or R2). In some embodiments, emitting the plurality of radiation shots includes repeatedly emitting the radiation shots along a direction, and the radiation shots are thus connected to form a beta pattern corresponding to the reference pattern. In some embodiments, the plurality of radiation shots are emitted to form the beta pattern. In some embodiments, each of the plurality of radiation shots has the same exposure time and the same energy intensity.

[0034] In some embodiments, a beta pattern T1a configured according to reference pattern R1 is formed by emitting a plurality of radiation shots P1a. In some embodiments, a dimension D1a of radiation shots P1a along the longitudinal direction of beta pattern T1a is in the range of 5 nm to 30 nm, depending on the application. In some embodiments, dimension D1a of radiation shots P1a is the same as the minimum dimension of radiation shots used to fabricate the design pattern in chip area A1 of photomask substrate PS1.

[0035] In some embodiments, the formed beta pattern T1a has a configuration and orientation substantially identical to that of the reference pattern R1, as viewed from above the photomask substrate PS1. In some embodiments, radiation shots P1a are emitted and connected along the longitudinal direction of the beta pattern T1a. In some embodiments, the longitudinal direction of the beta pattern T1a is the Y direction. In some embodiments, the roughness of the boundary B1a of the beta pattern T1a along the Y direction is obtained and compared with the roughness of the boundary B1 of the reference pattern R1. In some embodiments, due to the single radiation shot P1, the roughness of the boundary B1 of the reference pattern R1 is relatively lower than the roughness of the boundary B1a resulting from the connection of multiple radiation shots P1a. In some embodiments, due to the precise alignment of the radiation shots P1a along the Y direction of the beta pattern T1a, the roughness of the boundary B1a is similar to or substantially identical to the roughness of the boundary B1.

[0036] In some embodiments, method M10 or method M20 further includes comparing one or more widths W1a with the width W1 of reference pattern R1. In some embodiments, the width comparison operation is performed after operation 104 or operation 205, or before operation 104 or operation 205. In some embodiments, due to effective control of the exposure time and energy of the radiation irradiation, the width W1a of the β pattern T1a is substantially equal to the width W1 of the reference pattern R1. In some embodiments, the length L1a and slope of the β pattern T1a are also substantially the same as the length and slope of the reference pattern R1.

[0037] In some embodiments, a beta pattern T1b is further formed according to the configuration of reference pattern R1 by emitting a plurality of radiation shots P1b. In some embodiments, beta pattern T1b has a configuration and orientation substantially identical to that of reference pattern R1, as viewed from above photomask substrate PS1. In some embodiments, radiation shots P1b are emitted and connected along a lateral direction (i.e., the X direction) of beta pattern T1b. In some embodiments, dimension D1b of radiation shots P1b is measured along the X direction (which is the lateral direction of beta pattern T1b). In some embodiments, due to effective control of the exposure time and energy of radiation shots P1b, the width W1b of beta pattern T1b along the X direction is substantially equal to the width W1 of reference pattern R1. In some embodiments, the length L1b and slope of beta pattern T1b are also substantially identical to those of reference pattern R1.

[0038] In some embodiments, a beta pattern T2a is formed by emitting a plurality of radiation shots P2a according to the configuration of the reference pattern R2. In some embodiments, the formed beta pattern T2a has a configuration and orientation substantially identical to the reference pattern R2 in the peripheral area A2, as viewed from above the photomask substrate PS1. In some embodiments, the radiation shots P2a are emitted and connected along a lateral direction (e.g., the Y direction) of the beta pattern T2a. In some embodiments, a dimension D2a of the radiation shots P2a is measured along the Y direction (which is the lateral direction of the beta pattern T2a). In some embodiments, due to effective control of the exposure time and energy of the radiation shots P2a, the width W2a of the beta pattern T2a along the Y direction is substantially equal to the width W2 of the reference pattern R2. In some embodiments, the length L2a and slope of the beta pattern T2a are also substantially identical to those of the reference pattern R2.

[0039] In some embodiments, a beta pattern T2b is formed from multiple radiation shots P2b according to the configuration of a reference pattern R2. In some embodiments, the formed beta pattern T2b has substantially the same configuration and orientation as the reference pattern R2 in the peripheral area A2, as viewed from above the photomask substrate PS1. In some embodiments, radiation shots P2b are emitted and connected along a longitudinal direction (e.g., the X direction) of the beta pattern T2b. In some embodiments, the roughness of a boundary B2b of the beta pattern T2b along the longitudinal direction is measured and compared with the roughness of a boundary B2. In some embodiments, due to the single radiation shot P1, the roughness of the boundary B2 of the reference pattern R2 is relatively lower than the roughness of the boundary B2b resulting from the connection of multiple radiation shots P2b. In some embodiments, due to the precise alignment of the radiation shots P2b along the X direction of the beta pattern T2b, the roughness of the boundary B2b is similar to or substantially the same as the roughness of the boundary B2. In some embodiments, a dimension D2b of the radiation shots P2b is measured along the X direction, which is the longitudinal direction of the beta pattern T2b. In some embodiments, due to effective control of radiation exposure time and energy, the width W2b of the β pattern T2b is substantially equal to the width W2 of the reference pattern R2. In some embodiments, the length L2b and slope of the β pattern T2b are also substantially the same as those of the reference pattern R2.

[0040] Therefore, one or more reference patterns R1 and R2 and one or more β patterns T1a, T1b, T2a, and T2b are formed in peripheral area A2, depending on the factors to be tested. In some embodiments, reference patterns R1 and R2 and all β patterns T1a, T1b, T2a, and T2b are formed to test the functionality of the mask writer under various conditions, so that the causes of different defects can be identified.

[0041] In some embodiments, too much or too little radiation energy in the exposure or writing operations of manufacturing a photomask or degradation of the shaping deflector of the mask writer can lead to different types of defects on the photomask. Figure 7 Operations O103 to O104 of method M10 and / or operations O204 to O205 of method M20 according to other embodiments are described.

[0042] In some embodiments, the β patterns T1a' and T1b' and the β patterns T2a' and T2b' are formed on Figure 7β patterns T1a', T1b', T2a', and T2b' are similar to β patterns T1a, T1b, T2a, and T2b, and for ease of explanation, single quotes indicate different embodiments, but are not intended to limit the present invention. In some embodiments, the widths W1a', W1a", and W1a'' at different positions in the Y direction of β pattern T1a' are measured and compared. In some embodiments, the roughness of boundary B1a' of β pattern T1a' is obtained and compared with the roughness of boundary B1. In some embodiments, the roughness of boundary B1a' is greater than Figure 5 The roughness of the boundary B1 of the reference pattern R1 shown in FIG. In some embodiments, if this comparison yields a difference exceeding a tolerance, the photomask substrate PS1 is determined to have failed the inspection and a roughness defect has been detected. In some embodiments, the tolerance is within ±3 nm, defined by the maximum difference in edge profile on a single edge side. In some embodiments, the tolerance can be adjusted depending on the application and is not limited thereto.

[0043] In some embodiments, misalignment of radiation shot P1a' along the Y direction indicates radiation drift in the X direction. In some embodiments, roughness of boundary B1a' indicates degradation or contamination of a mask writer's shaping deflector. In some embodiments, if a roughness defect is detected, the shaping deflector is replaced or cleaned. This allows the alignment of radiation shot P1a' along the Y direction to be adjusted or improved.

[0044] According to the above description and operations O105 and O106, if the comparison result exceeds the tolerance, the alignment of radiation shot P1a' is adjusted; however, if the comparison result is within the tolerance, the photomask is subsequently formed. The formation and comparison of the β and reference patterns can be repeated until the photomask substrate PS1 passes inspection (i.e., the roughness difference between the reference pattern and the β pattern is within the tolerance). By performing inspection at one or more early stages of photomask manufacturing (detailed instructions for manufacturing the photomask will be provided later in this specification), defects in the photomask can be prevented.

[0045] In some embodiments, Figure 7 The width Wlb' of the β pattern Tlb' shown in FIG. Figure 5, which is the width W1 of reference pattern R1 shown in FIG. In some embodiments, multiple widths W1b' are measured at different locations of β pattern T1b', and the roughness of boundary B1b' is low. In some embodiments, the roughness of boundary B1b' of β pattern T1b' is similar to or substantially equal to the roughness of boundary B1 of reference pattern R1. That is, the radiation exposure P1b' emitted to form β pattern T1b' is homogeneously or substantially too weak to form a pattern having a width substantially equal to width W1 of reference pattern R1. In some embodiments, if the difference between width W1b' and width W1 exceeds the tolerance, photomask substrate PS1 is determined to have failed inspection and a homo-small defect has been detected.

[0046] In some embodiments, the tolerance is equal to 1% of the width W1 of the reference pattern R1. In some embodiments, the tolerance is equal to 5% of the width W1 of the reference pattern R1. In some embodiments, the tolerance is equal to 0.05% of the width W1 of the reference pattern R1. In some embodiments, the tolerance is an absolute value rather than a percentage of the width W1. In some embodiments, the tolerance is 2 nm, and the acceptable range for the width W1b' of the β pattern is within ±2 nm of the width W1 of the reference pattern R1. In some embodiments, the tolerance is equal to 5 nm, and the acceptable range for the width W1b' of the β pattern is within ±5 nm of the width W1 of the reference pattern R1. The tolerance can be adjusted depending on the application and is not limited thereto.

[0047] In some embodiments, the homogeneous small width W1b' indicates that the radiation shot P1b' emitted onto the photomask substrate PS1 has insufficient radiation energy. In some embodiments, if a defect of the homogeneous small width W1b' of the β pattern T1b' is detected, the exposure time of the radiation shot P1b' is increased. In some embodiments, if a defect of the homogeneous small width W1b' of the β pattern T1b' is detected, the beam energy of the radiation shot P1b' is increased. Similarly, after adjusting the beam energy, the formation of another β pattern and the comparison of the widths can be repeated until the photomask substrate PS1 passes inspection (i.e., the width difference is within tolerance). Thus, photomask defects can be prevented.

[0048] In some embodiments, Figure 7 The width W2a' of the β pattern T2a' shown in FIG is greater than Figure 5β pattern T2a' is measured at different locations of the reference pattern R2. In some embodiments, multiple widths W2a' are measured at different locations of the β pattern T2a', and the roughness of the boundary B2a' is determined. In some embodiments, the roughness of the boundary B2a' of the β pattern T2a' is similar to or substantially equal to the roughness of the boundary B2 of the reference pattern R2. That is, the radiation exposure P2a' emitted to form the β pattern T2a' is homogeneously or substantially too strong to form a pattern having a width substantially equal to the width W2 of the reference pattern R2. In some embodiments, if the difference between width W2a' and width W2 exceeds the tolerance, the photomask substrate PS1 is determined to have failed inspection and a homogeneous large defect has been detected.

[0049] In some embodiments, a uniformly large width W2a' indicates that the radiation shot P2a' emitted onto the photomask substrate PS1 has excessive radiation energy. In some embodiments, if a defect of uniformly large width W2a' is detected in the β pattern T2a', the exposure time of the radiation shot P2a' is reduced. In some embodiments, if a defect of uniformly large width W2a' is detected in the β pattern T2a', the beam energy of the radiation shot P2a' is reduced. Similarly, after adjusting the beam energy, the formation of another β pattern and the comparison of the widths can be repeated until the photomask substrate PS1 passes inspection (i.e., the width difference is within tolerance). Thus, photomask defects can be prevented.

[0050] In the above-described embodiments, Figure 7 The β patterns T1a', T1b' and T2a' show different types of defects, respectively. In some embodiments, a combination of different types of defects may occur.

[0051] In some embodiments, as Figure 7 As shown in the β pattern T2b' in FIG, the widths W2b', W2b" and W2b"' measured at different positions of the β pattern T2b' are substantially much smaller than the width W2 of the reference pattern R2. In addition, the roughness of the boundary B2b' of the β pattern T2b' is greater than Figure 5 The roughness of the boundary B2 of the reference pattern R2 shown in FIG.

[0052] In some embodiments, misalignment of the radiation exposure P2b' occurring along the X direction indicates the presence of radiation drift in the Y direction. In some embodiments, the roughness of the boundary B2b' indicates degradation or contamination of the forming deflector of the mask writer, and the homogeneous small widths W2b', W2b", and W2b'" indicate that the radiation energy of the radiation exposure P2b' emitted onto the photomask substrate PS1 is generally too weak. In some embodiments, if a defect in roughness is detected, the forming deflector is replaced or cleaned, and if a homogeneous small defect in the β pattern T2b' is detected, the exposure time of the radiation exposure P2b' is increased. Similarly, the formation of another β pattern and the comparison of width and roughness and the adjustment of beam energy and the alignment of the radiation exposure P2b' can be repeated until the photomask substrate PS1 passes the inspection (i.e., both the difference in width and the difference in roughness are within the corresponding tolerances). Therefore, defects in the photomask can be prevented.

[0053] The positions and numbers of the reference patterns and β patterns are not limited as long as the reference patterns and β patterns are located in the peripheral area A2 of the photomask substrate. Figure 8 In some of the embodiments shown, only each of the reference patterns R1 and R2 and each of the beta patterns T1a, T1b, T2a, and T2b are formed in the peripheral area A2 of the photomask PM1. In some embodiments, defects in the mask writer tend to repeat across the photomask substrate, and several identical beta patterns and / or reference patterns may not necessarily be formed. Figure 9 In some embodiments shown, multiple beta patterns T1a / T1b / T2a / T2b are formed across the photomask PM2. In some embodiments, if the performance of the mask writer is not stable across the photomask substrate, different defects can be detected. Figure 10 In some embodiments shown, the β patterns T1a / T1b / T2a / / T2b are formed between the design patterns A1a and the chip area A1 of the photomask PM3. Figure 10 Only some chip areas A1 including design patterns are shown in FIG. In some embodiments, each of the chip areas A1 includes the same or different design patterns A1a.

[0054] exist Figures 8 to 10In some of the illustrated embodiments, method M10 further includes forming a design pattern A1a in chip area A1. In some embodiments, operations O102 and O103 are performed simultaneously. In some embodiments, operation O102 is performed after operation O103 or before operation O103. In some embodiments, operations O102 and O103 are performed simultaneously with, before, or after forming design pattern A1a. In some embodiments, design pattern A1a is formed after the photomask substrate passes inspection, and the pattern (including the reference pattern, the qualified beta pattern, and the design pattern) is then transferred to one or more layers below the photoresist layer of the photomask substrate. The order of operations may depend on the manufacturing process and the mask writer and is not limited thereto. Furthermore, in some embodiments, the additional exposure time for forming the reference pattern and the beta pattern may be limited to less than 10 minutes. Due to the simple configuration and large scale of the reference pattern and the beta pattern relative to design pattern A1a, the additional exposure time should be shorter than the exposure time for forming design pattern A1a.

[0055] Similarly, in some embodiments, operation O203 of method M20 is performed simultaneously with operation O204. In some embodiments, operation O203 of method M20 is performed after operation O204, before operation O204, or simultaneously with operation O204. In some embodiments, forming the reference pattern and forming the β pattern are performed simultaneously during the writing process. In some embodiments, forming the reference pattern is performed before forming the β pattern or after forming the β pattern.

[0056] Therefore, the different longitudinal orientations of reference patterns R1 and R2 and β patterns T1a / T1a' and T2b / T2b' can provide inspection results corresponding to different shaped deflectors (e.g., X-direction deflectors or Y-direction deflectors). Furthermore, the different alignment directions of the radiation used to form the respective β patterns can facilitate the detection of different types of defects. The method for manufacturing a photomask provided by embodiments of the present invention provides detailed inspection under various conditions and can improve product yield.

[0057] To detect defects in a photomask at an early stage of manufacturing, a comparison operation or inspection may be performed after forming a patterned photoresist layer.

[0058] Figures 11 to 16 1 is a cross-sectional view illustrating different stages of fabrication of a super binary mask (SBIM) according to some embodiments of the present invention. Figures 11 to 16 A portion of a photomask substrate and the formation of the β patterns T2 a and T2 b are shown, but it is not intended that the following process of the embodiment of the present invention be limited to the β patterns T2 a and T2 b .

[0059] refer to Figure 11, receiving a photomask substrate PS3. The photomask substrate PS3 includes a carrier layer 10, a shielding layer 11 on the carrier layer 10, and a hard layer 13 on the shielding layer 11. In some embodiments, a photoresist layer 15 is formed on the hard layer 13 of the photomask substrate PS3. In some embodiments, the photoresist layer 15 comprises a positive photoresist. In some embodiments, the carrier layer 10 is transparent. In some embodiments, the carrier layer 10 comprises at least one of quartz and glass. In some embodiments, the shielding layer 11 comprises molybdenum silicide (MoSi). In some embodiments, the hard layer 13 comprises chromium (Cr).

[0060] refer to Figure 12 , patterning the photoresist layer 15, thereby forming a patterned photoresist layer 15'. In some embodiments, a photolithography operation (or write operation) comprising emitting radiation irradiation P1, P2, P1a, P1b, P2a, and P2b is performed to form the patterned photoresist layer 15'. In some embodiments, the patterned photoresist layer 15' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, a comparison operation (operation O104 or O205) is performed after forming the patterned photoresist layer 15' and before patterning the hard layer 13 or proceeding to the next operation. In some embodiments, manufacturing is suspended if the photomask substrate PS3 fails inspection and continues if the photomask substrate PS3 passes inspection. In some embodiments having a positive photoresist layer 15, the reference pattern and the β pattern include spaces between portions of the patterned photoresist layer 15'. Positive photoresist is a type of photoresist in which portions of the photoresist exposed to light become soluble in the photoresist developer, and therefore, the spaces formed after development of the photolithography operation are critical. In some embodiments, the roughness and width of the boundary between the reference pattern and the β pattern are determined by measuring the width of the space between portions of the patterned photoresist layer 15'. If Figure 12 If the test fails in the stage shown, the patterned photoresist layer 15' is removed and the process is repeated. Figures 11 to 12 The operations shown in .

[0061] refer to Figure 13 , the reference pattern, the β pattern (e.g., T2a and T2b), and the design pattern are transferred to the hard layer 13. In some embodiments, a portion of the hard layer 13 is removed via the patterned photoresist layer 15' to form the patterned hard layer 13'. In some embodiments, a comparison operation (operation O104 or O205) is performed after the patterned hard layer 13' is formed and before the patterned photoresist layer 15' is removed or the next operation is performed. In some embodiments, manufacturing is suspended if the photomask substrate PS3 fails inspection and continues if the photomask substrate PS3 passes inspection.

[0062] refer to Figure 14, patterned photoresist layer 15' is removed. In some embodiments, patterned hard layer 13' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, a comparison operation (operation O104 or O205) is performed after removing patterned photoresist layer 15' and before patterning mask layer 11 or proceeding to the next operation. In some embodiments using a positive photoresist layer 15, the roughness and width of the boundary between the reference pattern and the β pattern are determined by measuring the width of the space between portions of patterned hard layer 13'. In some embodiments, manufacturing is suspended if photomask substrate PS3 fails inspection and continues if photomask substrate PS3 passes inspection.

[0063] refer to Figure 15 , the reference pattern, β pattern, and design pattern are transferred to the shielding layer 11. In some embodiments, if the photomask substrate PS3 passes inspection, the design pattern A1a is transferred to the shielding layer 11 simultaneously with the reference pattern and β pattern. That is, in some embodiments, if the difference between the roughness and / or width of the β pattern and the roughness and / or width of the reference pattern is within tolerance, the design pattern is transferred to the shielding layer 11. In some embodiments, a portion of the shielding layer 11 is removed via the patterned hard layer 13' to form the patterned shielding layer 11'. In some embodiments, the patterned shielding layer 11' includes the reference pattern, the β pattern, and the design pattern. In some embodiments, the accuracy and quality of the design pattern of the patterned shielding layer 11' are ensured by performing a comparison operation before forming the patterned shielding layer 11'.

[0064] refer to Figure 16 , the patterned hard layer 13' is removed to form a photomask PM4. In some embodiments, the pattern of the patterned shielding layer 11' is the pattern of the photomask PM4.

[0065] Method M10 can be applied to various types of photomasks. Figures 17 to 18 are cross-sectional views illustrating different stages of fabricating an alternating phase-shift mask (APSM) using positive photoresist according to some embodiments of the present invention. Figures 17 to 18 Only a portion of the photomask substrate and the formation of the β patterns T2 a and T2 b are shown, but it is not intended that the following process of the embodiment of the present invention be limited to the β patterns T2 a and T2 b .

[0066] refer to Figure 17 , receiving the photomask substrate PS4. Execution similar to Figures 11 to 15 The operations described in the above are performed to form a patterned hard layer 13' and a patterned shielding layer 11'. Another patterned photoresist layer 16' is formed on the patterned hard layer 13'. In some embodiments, the comparison operation can be performed before patterning the patterned hard layer 13'. Figure 18, a portion of the patterned hard layer 13 ′ is removed through the patterned photoresist layer 16 ′ to form a patterned hard layer 13 ″. Next, the patterned photoresist layer 16 ′ is removed to form a photomask PM5 .

[0067] In some embodiments, the photoresist layer 15 comprises a negative photoresist. Figures 19 to 28 are cross-sectional views illustrating different stages of fabricating an APSM using a negative photoresist according to some embodiments of the present invention. Figures 19 to 28 Only a portion of the photomask substrate and the formation of the β patterns T2 a and T2 b are shown, but it is not intended that the following process of the embodiment of the present invention be limited to the β patterns T2 a and T2 b .

[0068] refer to Figure 19 , receiving a photomask substrate PS5. Photomask substrate PS5 includes a carrier layer 10, a shielding layer 11 on carrier layer 10, a hard layer 13 on shielding layer 11, a shielding layer 14 on hard layer 13, and a photoresist layer 15 on shielding layer 14. In some embodiments, photoresist layer 15 comprises a negative photoresist. In some embodiments, carrier layer 10 is transparent. In some embodiments, carrier layer 10 comprises at least one of quartz and glass.

[0069] refer to Figure 20 , patterning the photoresist layer 15, thereby forming a patterned photoresist layer 15'. In some embodiments, a photolithography operation (or write operation) including emitting radiation irradiation P1, P2, P1a, P1b, P2a, and P2b is performed to form the patterned photoresist layer 15'. In some embodiments, the patterned photoresist layer 15' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, a comparison operation (operation O104 or O205) is performed after forming the patterned photoresist layer 15' and before patterning the shield layer 14 or performing the next operation. In some embodiments, manufacturing is suspended when the photomask substrate PS5 fails the inspection and continues when the photomask substrate PS5 passes the inspection. In some embodiments having a negative photoresist, the reference pattern and the β pattern include portions of the patterned photoresist layer 15'. Negative photoresist is a type of photoresist in which portions of the photoresist exposed to light become insoluble in the photoresist developer, and the unexposed portions of the photoresist are dissolved by the photoresist developer. In some embodiments, the roughness and width of the boundaries of the reference pattern and the β pattern are determined by measuring the width of a portion of the patterned photoresist layer 15'.

[0070] refer to Figure 21, the reference pattern, the β pattern (e.g., T2a and T2b), and the design pattern are transferred to the shield layer 14. In some embodiments, a portion of the shield layer 14 is removed via the patterned photoresist layer 15' to form the patterned shield layer 14'. In some embodiments, a comparison operation (operation O104 or O205) is performed after the patterned shield layer 14' is formed and before the patterned photoresist layer 15' is removed or the next operation is performed. In some embodiments, manufacturing is suspended when the photomask substrate PS5 fails inspection and continues when the photomask substrate PS5 passes inspection.

[0071] refer to Figure 22 , remove the patterned photoresist layer 15'. In some embodiments, the patterned shield layer 14' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, a comparison operation (operation O104 or O205) is performed after removing the patterned photoresist layer 15' and before patterning the hard layer 13 or performing the next operation. In some embodiments, the comparison operation is performed before removing the patterned shield layer 14'. In some embodiments using a negative photoresist layer 15, the roughness and width of the boundaries of the reference pattern and the β pattern are determined by measuring the width of a portion of the patterned shield layer 14'. In some embodiments, manufacturing is suspended when the photomask substrate PS5 fails the inspection and continues when the photomask substrate PS5 passes the inspection.

[0072] refer to Figure 23 , the reference pattern, the β pattern (e.g., T2a and T2b), and the design pattern are transferred to the hard layer 13. In some embodiments, a portion of the hard layer 13 is removed via the patterned mask layer 14' to form the patterned hard layer 13'. In some embodiments, a comparison operation (operation O104 or O205) is performed after the patterned hard layer 13' is formed and before the patterned mask layer 14' is removed or the next operation is performed. In some embodiments, manufacturing is suspended if the photomask substrate PS5 fails inspection and continues if the photomask substrate PS5 passes inspection.

[0073] refer to Figure 24 , the patterned shield layer 14' is removed. In some embodiments, the patterned shield layer 14' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, a comparison operation (operation O104 or O205) is performed after removing the patterned shield layer 14' and before patterning the shield layer 11 or proceeding to the next operation. In some embodiments using a negative photoresist layer 15, the roughness and width of the boundary between the reference pattern and the β pattern are determined by measuring a portion of the patterned hard layer 13'. In some embodiments, manufacturing is suspended when the photomask substrate PS5 fails inspection and continues when the photomask substrate PS5 passes inspection.

[0074] refer to Figure 25, the reference pattern, the β pattern, and the design pattern are transferred to the shielding layer 11. In some embodiments, if the photomask substrate PS5 passes the inspection, the design pattern is transferred to the shielding layer 11 simultaneously with the reference pattern and the β pattern. That is, in some embodiments, if the difference between the roughness and / or width of the β pattern and the roughness and / or width of the reference pattern is within the tolerance, the design pattern is transferred to the shielding layer 11. In some embodiments, a portion of the shielding layer 11 is removed via the patterned hard layer 13' to form the patterned shielding layer 11'. In some embodiments, the patterned shielding layer 11' includes a reference pattern, a β pattern, and a design pattern. In some embodiments, the correctness and quality of the design pattern of the patterned shielding layer 11' are ensured by performing a comparison operation before forming the patterned shielding layer 11'.

[0075] refer to Figure 26 , forming a patterned photoresist layer 16' covering a portion of the patterned hard layer 13'. Figure 27 , removing the portion of the patterned hard layer 13' exposed through the patterned photoresist layer 16' to form a patterned hard layer 13". Figure 28 , and then the patterned photoresist layer 16 ′ is removed to form a photomask PM6 .

[0076] The photomask formed according to the method described above is used in a photolithography / patterning operation of a semiconductor substrate. The photomask may include one or more reference patterns and one or more β patterns in a peripheral area. In some embodiments, the photomask includes a chip area A1 and a peripheral area A2 adjacent to the chip area A1. In some embodiments, the photomask includes a design pattern A1a in the chip area A1 and a plurality of test patterns in the peripheral area A2 including at least one of the reference patterns and at least one of the β patterns. The test pattern is separated from the design pattern. In some embodiments, the reference pattern has a first boundary (B1 or B2) and the β pattern has a second boundary (B1a, B1b, B2a, or B2b), wherein the roughness of the second boundary is greater than the roughness of the first boundary. In some embodiments, the roughness of the second boundary is greater than the roughness of the first boundary, and the difference between the width of the β pattern and the width of the reference pattern is within a tolerance.

[0077] In some embodiments, the photomask may include a Figure 7One or more β patterns T1a, T1b, T2a, and T2b formed in the manner of the β patterns shown in FIG (for example, having slightly greater roughness, slightly smaller width, slightly larger width, or a combination thereof relative to the corresponding reference patterns R1 and / or R2), but the photomask can still pass inspection when the detected variations are within the corresponding tolerances. In some embodiments, if the photomask passes one or more inspections during manufacturing, the design pattern of the photomask is transferred to the semiconductor substrate. In some embodiments, if the photomask fails the inspection, the patterned layer (for example, the patterned photoresist layer 15', the patterned hard layer 13', or the patterned shielding layer 14') is removed and modified on the shielding layer 11. The quality of the patterned semiconductor substrate is ensured and defects in the semiconductor substrate caused by low-quality photomasks are prevented. Therefore, the product yield of the semiconductor substrate or device is improved.

[0078] Some embodiments of the present invention provide a method for manufacturing a photomask. The method includes receiving a photomask substrate having a chip region and a peripheral region adjacent to the chip region; forming a reference pattern by emitting a first radiation shot in the peripheral region; forming a first beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein the emitting of the plurality of second radiation shots is performed along a first direction; and comparing, from a top view perspective, a roughness of a boundary of the first beta pattern along the first direction with a roughness of a boundary of the reference pattern along the first direction.

[0079] Some embodiments of the present invention provide a method for manufacturing a semiconductor. The method includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting a first radiation shot and forming a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is larger than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern with a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.

[0080] Some embodiments of the present invention provide a photomask structure. The photomask structure includes: a chip region and a peripheral region adjacent to the chip region; a design pattern located in the chip region; and a plurality of test patterns located in the peripheral region and separated from the design pattern. The plurality of test patterns include: a reference pattern having a first boundary; and a β pattern having a second boundary, wherein the second boundary has a roughness greater than that of the first boundary.

[0081] The advanced lithography processes, methods, and materials described in the embodiments of the present invention can be used in many applications, including fin field-effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between components, for which the above disclosure is well suited. Furthermore, spacers used to form the fins of FinFETs can be processed according to the above disclosure.

[0082] The above summarizes the structures of several embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions should not depart from the spirit and scope of the embodiments of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

[0083] Explanation of symbols

[0084] 10 Carrier layer

[0085] 11 Shielding layer

[0086] 11' patterned shield

[0087] 13 Hard layer

[0088] 13' patterned hard layer

[0089] 13” patterned hard layer

[0090] 14 shielding layer

[0091] 14' patterned shield

[0092] 15 Photoresist layer

[0093] 15' Patterned photoresist layer

[0094] 16' Patterned photoresist layer

[0095] A1 chip area

[0096] A1a Design

[0097] A2 Outer Area

[0098] B1 Boundary

[0099] B1a Boundary

[0100] B1a' border

[0101] B1b' border

[0102] B2 Boundary

[0103] B2a' border

[0104] B2B Boundary

[0105] B2b' border

[0106] D1a size

[0107] D1b size

[0108] D2a size

[0109] L1 length

[0110] L1a length

[0111] L1b length

[0112] L2 length

[0113] L2a length

[0114] L2b length

[0115] M10 method

[0116] M20 method

[0117] O101 Operation

[0118] O102 Operation

[0119] O103 Operation

[0120] O104 Operation

[0121] O105 Operation

[0122] O106 Operation

[0123] O201 Operation

[0124] O202 Operation

[0125] O203 Operation

[0126] O204 Operation

[0127] O205 Operation

[0128] O206 Operation

[0129] O207 Operation

[0130] P1 Radiation Exposure

[0131] P1a Radiation exposure

[0132] P1a' radiation exposure

[0133] P1b radiation exposure

[0134] P1b' radiation exposure

[0135] P2 Radiation Exposure

[0136] P2a Radiation Exposure

[0137] P2a' radiation exposure

[0138] P2b radiation exposure

[0139] P2b' radiation exposure

[0140] PM1 Photomask

[0141] PM2 Photomask

[0142] PM3 Photomask

[0143] PM4 Photomask

[0144] PM5 Photomask

[0145] PM6 photomask

[0146] PS1 Photomask Substrate

[0147] PS2 photomask substrate

[0148] PS3 photomask substrate

[0149] PS4 photomask substrate

[0150] PS5 photomask substrate

[0151] R1 reference pattern

[0152] R2 reference pattern

[0153] T1a beta pattern

[0154] T1a' β pattern

[0155] T1b beta pattern

[0156] T1b' β pattern

[0157] T2a beta pattern

[0158] T2a' β pattern

[0159] T2b beta pattern

[0160] T2b' β pattern

[0161] W1 width

[0162] W1a width

[0163] W1a' width

[0164] W1a” width

[0165] W1a”' width

[0166] W1b width

[0167] W1b' width

[0168] W2 width

[0169] W2a width

[0170] W2a' width

[0171] W2b width

[0172] W2b' width

[0173] W2b” width

[0174] W2b"' width

Claims

1. A method for manufacturing a photomask, comprising: receiving a photomask substrate having a chip region and a peripheral region adjacent to the chip region; forming a reference pattern by emitting a first radiation illumination in the peripheral region; forming a first beta pattern by emitting a plurality of second radiant shots in the peripheral region, wherein the plurality of second radiant shots are emitted along a first direction; comparing, from a top view, the roughness of a boundary of the first β pattern along the first direction with the roughness of a boundary of the reference pattern along the first direction; adjusting the alignment of the plurality of second radiation shots if a result of the comparing exceeds a tolerance; and If the result of the comparison is within the tolerance, then the photomask is formed. 2 . The method of claim 1 , wherein the first radiant exposure has a pixel size that is larger than a pixel size of each of the plurality of second radiant exposures.

3. The method according to claim 1, further comprising: comparing a width of the first β pattern and a width of the reference pattern from the top view, wherein the width of the first β pattern and the width of the reference pattern are measured along a second direction; and If a result of the comparison of the widths exceeds a tolerance, then the beam energy of the second plurality of radiation shots is adjusted. The method according to claim 3 , wherein the first direction and the second direction are parallel or perpendicular. The method of claim 3 , wherein if the result of the comparison of the widths is within the tolerance, then forming the photomask. 6 . The method according to claim 1 , wherein the photomask substrate comprises a shielding layer, a hard layer on the shielding layer, and a photoresist layer on the hard layer, and the reference pattern and the first β pattern are formed in the photoresist layer.

7. The method according to claim 6, further comprising: forming a design pattern in the chip region of the substrate; and If a difference between the roughness of the boundary of the first beta pattern and the roughness of the boundary of the reference pattern is within the tolerance, the design pattern is transferred to the shielding layer.

8. The method of claim 1, wherein a photoresist layer of the photomask substrate comprises a positive photoresist, and the reference pattern and the first beta pattern comprise spaces between portions of the photoresist layer.

9. The method of claim 1, wherein the photoresist layer of the photomask substrate comprises a negative photoresist.

10. The method of claim 1, wherein the first direction is a longitudinal direction of the reference pattern.

11. The method according to claim 1 , further comprising: forming a second beta pattern by emitting a plurality of third radiant shots in the peripheral region, wherein the emitting of the plurality of third radiant shots is performed along a second direction perpendicular to the first direction; comparing the width of the second β pattern with the width of the reference pattern from the top view; and If a result of the comparison of the widths exceeds a tolerance, then the beam energy of the third plurality of radiation shots is adjusted.

12. A photomask structure comprising: a chip region and a peripheral region adjacent to the chip region; a design pattern located in the chip area; and a plurality of test patterns located in the peripheral area and separated from the design pattern, wherein the plurality of test patterns include: a reference pattern having a first boundary; and A β pattern has a second boundary, wherein the roughness of the second boundary is greater than the roughness of the first boundary. 13 . The photomask structure according to claim 12 , wherein the reference pattern and the β pattern are rectangular, and the first boundary and the second boundary extend along longitudinal directions of the reference pattern and the β pattern, respectively.

14. A method for manufacturing a photomask, comprising: receiving a photomask substrate having a chip region and a peripheral region; forming a reference pattern by emitting a first radiation shot in the peripheral region; forming a first beta pattern by emitting a plurality of second radiant shots in the peripheral region, wherein the plurality of second radiant shots are emitted in a first direction and the first radiant shot has a pixel size that is greater than a pixel size of each of the plurality of second radiant shots; comparing, from a top view, the roughness of a boundary of the first β pattern along the first direction with the roughness of a boundary of the reference pattern along the first direction; adjusting the alignment of the plurality of second radiation shots when a result of the comparing exceeds a tolerance; When the result of the comparison is within the tolerance, a design pattern is formed in the chip region, wherein the size of the first radiation shot is the same as a minimum size of radiation shots used to form the design pattern.

15. The method according to claim 14, further comprising: comparing a width of the first β pattern and a width of the reference pattern from the top view, wherein the width of the first β pattern and the width of the reference pattern are measured along a second direction; and adjusting the beam energy of the plurality of second radiation shots if a result of the comparison of the widths exceeds a tolerance, The first direction and the second direction are parallel or perpendicular. 16 . The method of claim 14 , wherein the photomask substrate comprises a shielding layer, a hard layer on the shielding layer, and a photoresist layer on the hard layer, and the reference pattern and the first β pattern are formed in the photoresist layer. 17 . The method of claim 16 , further comprising transferring the design pattern to the shielding layer when the result of the comparing is within the tolerance. The method of claim 14 , wherein the first direction is a longitudinal direction of the reference pattern.

19. The method of claim 18, further comprising: forming a second beta pattern by emitting a plurality of third radiant shots in the peripheral region, wherein the emitting of the plurality of third radiant shots is performed along a second direction perpendicular to the first direction; comparing the width of the second β pattern with the width of the reference pattern from the top view; and If a result of the comparison of the widths exceeds a tolerance, then the beam energy of the third plurality of radiation shots is adjusted.

20. The method of claim 19, wherein the second beta pattern and the first beta pattern comprise similar configurations and orientations.

21. A method for manufacturing a semiconductor, comprising: receiving a photomask substrate including a first shield layer; defining a chip area and a peripheral area adjacent to the chip area; forming a design pattern in the chip region; forming a reference pattern by emitting a first radiation shot and forming a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is larger than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern with a beta roughness of a boundary of the beta pattern; transferring the design pattern to the first shielding layer if the difference between the reference roughness and the beta roughness is within a tolerance; and The design pattern is transferred to a semiconductor substrate.

22. The method of claim 21 , wherein the photomask substrate comprises a carrier layer below the first shielding layer and a hard layer on the first shielding layer, and the method further comprises: forming a patterned photoresist layer on the hard layer, wherein the patterned photoresist layer comprises the reference pattern and the β pattern; removing portions of the hard layer through the patterned photoresist layer to form a patterned hard layer; and The patterned photoresist layer is removed.

23. The method of claim 22, wherein the comparing operation is performed on the patterned photoresist layer after the removing of the portion of the hard layer.

24. The method of claim 22, wherein the comparing operation is performed on the patterned photoresist layer prior to the removing of the portion of the hard layer.

25. The method of claim 21, wherein the photomask substrate comprises a carrier layer below the first shielding layer, a hard layer on the first shielding layer, and a second shielding layer on the hard layer, and the method further comprises: forming a patterned photoresist layer on the hard layer; removing a portion of the second shielding layer through the patterned photoresist layer to form a patterned second shielding layer; removing the patterned photoresist layer; removing portions of the hard layer through the patterned second shielding layer to form a patterned hard layer; and The patterned second shielding layer is removed.

26. The method of claim 25, wherein the patterned photoresist layer includes the reference pattern and the beta pattern, and the comparing operation is performed before the removing of the patterned photoresist layer.

27. The method of claim 25, wherein the patterned second mask layer comprises the reference pattern and the beta pattern, and the comparing operation is performed before the removing of the patterned second mask layer.

28. A method for manufacturing a semiconductor, comprising: receiving a photomask substrate; forming a reference pattern on the photomask substrate by emitting a first radiation exposure; forming a beta pattern on the photomask substrate by emitting a plurality of second radiant shots in a direction, wherein a pixel size of the first radiant shots is larger than a pixel size of the second radiant shots; comparing the roughness of the boundary of the reference pattern with the roughness of the boundary of the β pattern along the direction as viewed from above; forming a design pattern on the photomask substrate when a result of the comparison is within a tolerance; and The design pattern is transferred to a semiconductor substrate.

29. The method of claim 28, wherein the photomask substrate comprises a carrier layer, a shielding layer on the carrier layer, and a hard layer on the shielding layer.

30. The method of claim 29, further comprising: forming a patterned photoresist layer on the hard layer, wherein the patterned photoresist layer comprises the reference pattern and the β pattern; transferring the reference pattern and the beta pattern from the patterned photoresist layer to the hard layer to form a patterned hard layer; and The patterned photoresist layer is removed.

31. The method of claim 30, wherein the comparing operation is performed on the patterned photoresist layer after the transferring of the reference pattern and the beta pattern.

32. The method of claim 30, wherein the comparing operation is performed on the patterned photoresist layer prior to the transferring of the reference pattern and the beta pattern.

33. The method of claim 28, wherein the photomask substrate comprises a carrier layer, a first shield layer on the carrier layer, a hard layer on the first shield layer, and a second shield layer on the hard layer.

34. The method of claim 33, further comprising: forming a patterned photoresist layer on the hard layer, wherein the patterned photoresist layer comprises the reference pattern and the β pattern; transferring the reference pattern and the beta pattern from the patterned photoresist layer to the second shielding layer to form a patterned second shielding layer; removing the patterned photoresist layer; transferring the reference pattern and the beta pattern from the patterned second shield layer to the hard layer to form a patterned hard layer; and The patterned second shielding layer is removed.

35. The method of claim 34, wherein the comparing operation is performed before the removing of the patterned photoresist layer.

36. The method of claim 34, wherein the comparing operation is performed before the removing of the patterned second shielding layer. 37 . The method of claim 28 , wherein the photomask substrate further comprises a chip region and a peripheral region, the design pattern is formed in the chip region, and the reference pattern and the β pattern are formed in the peripheral region.

38. A method for manufacturing a semiconductor, comprising: receiving a photomask substrate; forming a reference pattern on the photomask substrate by emitting a first radiation exposure; forming a beta pattern on the photomask substrate by emitting a plurality of second radiant shots, wherein a pixel size of the first radiant shots is larger than a pixel size of the second radiant shots; comparing the roughness of the boundary of the reference pattern with the roughness of the boundary of the β pattern; adjusting the alignment of the plurality of second radiation shots when a result of the comparing exceeds a tolerance; forming a design pattern on the photomask substrate when a result of the comparison is within the tolerance; and The design pattern is transferred to a semiconductor substrate.

39. The method of claim 38, wherein the photomask substrate comprises a carrier layer, a shielding layer on the carrier layer, and a hard layer on the shielding layer, and the method further comprises: forming a patterned photoresist layer on the hard layer, wherein the patterned photoresist layer comprises the reference pattern and the β pattern; removing portions of the hard layer through the patterned photoresist layer to form a patterned hard layer; and The patterned photoresist layer is removed.

40. The method of claim 38, wherein the photomask substrate comprises a carrier layer, a first shield layer on the carrier layer, a hard layer on the first shield layer, and a second shield layer on the hard layer, and the method further comprises: forming a patterned photoresist layer on the hard layer; removing a portion of the second shielding layer through the patterned photoresist layer to form a patterned second shielding layer; removing the patterned photoresist layer; removing portions of the hard layer through the patterned second shielding layer to form a patterned hard layer; and The patterned second shielding layer is removed.

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