Communication system based on MIPS architecture processor

Abstract

The present invention discloses a communication system based on a MIPS architecture processor. The system comprises: a first microsystem, the first microsystem comprises a first UART0 interface module and a first SPI interface module, the first UART0 interface module is used to interact with a first peripheral terminal device; a second microsystem, the second microsystem comprises a second SPI interface module, the second SPI interface module is connected to the first SPI interface module, and is used to receive data sent by the first SPI interface module to realize data transmission between the first microsystem and the second microsystem. According to the present invention, communication and data storage between two independent microsystems can be realized, and the terminal device transmits data to the second microsystem through the connected first microsystem to realize the function of the microsystem (such as collecting data or storing data), thereby improving the efficiency of the entire system.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a communication system based on a MIPS architecture processor. Background Art

[0002] With the advancement of integrated circuit manufacturing, the integration level on the same chip has been greatly improved. The development of embedded flash memory manufacturing process allows the storage system to be fully implemented on the same chip without the need for PCB board-level storage support. These conditions allow the 32-bit microprocessor system to run on a single chip, forming an independent microcomputer system, and with the necessary peripheral modules, a microcontroller system is formed.

[0003] At present, most of the microprocessors in China use ARM architecture. The PC controls the CPU to execute some commands, such as collecting or storing data, and then the CPU uses the corresponding program to control the corresponding functional modules (such as sensors) to implement the functions of these commands. Such a system is not efficient enough and cannot realize more complex functions to improve the efficiency of the entire system.

[0004] In order to solve the problems in the prior art, the present invention provides a communication system based on a MIPS architecture processor. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In order to solve the problems in the prior art, the present invention provides a communication system based on a MIPS architecture processor, comprising:

[0007] A first microsystem, the first microsystem comprising a first UART0 interface module and a first SPI interface module, the first UART0 interface module being used to interact with a first peripheral terminal device;

[0008] The second microsystem includes a second SPI interface module, and the second SPI interface module is connected to the first SPI interface module to receive data sent by the first SPI interface module to realize data transmission between the first microsystem and the second microsystem.

[0009] Exemplarily, at least two second microsystems are included, wherein the second SPI interface modules of at least two of the at least two microsystems are connected to the first SPI interface module of the same first microsystem.

[0010] Exemplarily, the first microsystem further includes a first processor module, the first processor module is used to detect the working state of the first UART0 interface module and control the data transmission between the first UART0 interface module and the first peripheral terminal device according to the working state, the working state including the data transmission state and the idle state;

[0011] When the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data from the first peripheral terminal device;

[0012] When the first UART0 interface module is in the idle state, the first UART0 interface module is controlled to receive data of the first peripheral terminal device.

[0013] Exemplarily, the first processor module further detects a working state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the working state, wherein the working state includes a data transmission state and an idle state;

[0014] When the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data;

[0015] When the first SPI interface module is in an idle state, the first SPI interface module is controlled to send data.

[0016] Exemplarily, the second microsystem further includes a second processor module, the second processor module is used to detect the working state of the second SPI interface module and control the second SPI interface module to receive data sent by the first SPI interface module according to the working state, the working state including a data transmission state and an idle state;

[0017] When the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data;

[0018] When the second SPI interface module is in an idle state, the second SPI interface module is controlled to receive data.

[0019] Exemplarily, the second microsystem further includes a storage module, and the storage module is used to store the data.

[0020] Exemplarily, the storage module is a flash memory module.

[0021] Exemplarily, the second processor module also controls the read and write operations of the flash memory module.

[0022] Exemplarily, the second microsystem further includes a second UART0 interface module, and the second UART0 interface module is used to interact with a second peripheral terminal device.

[0023] Exemplarily, the ISA architecture of the first microsystem and the second microsystem adopts 32-bit MIPS-I.

[0024] According to the communication system based on the MIPS architecture processor of the present invention, communication and data storage between two independent microsystems can be realized. The terminal device transmits data to the second microsystem through the connected first microsystem to realize the functions of the microsystem (such as collecting data or storing data), thereby improving the efficiency of the entire system. At the same time, through the SPI interface module, one microsystem can transmit data to more than one microsystem at the same time, so that more and more complex functions can be realized while improving the system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0026] In the attached figure:

[0027] Figure 1 A schematic diagram of the structure of a communication system based on a MIPS architecture processor according to an embodiment of the present invention;

[0028] Figure 2 A schematic flow chart of a data transmission process of a communication system based on a MIPS architecture processor according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0030] In order to fully understand the present invention, a detailed description will be provided in the following description to illustrate the communication system based on the MIPS architecture processor of the present invention. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of communication technology. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other embodiments.

[0031] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of the features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] Now, exemplary embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art. In the accompanying drawings, for the sake of clarity, the thickness of layers and regions is exaggerated, and the same reference numerals are used to represent the same elements, and thus their description will be omitted.

[0033] In order to solve the problems in the prior art, the present invention provides a communication system based on a MIPS architecture processor, comprising:

[0034] A first microsystem, the first microsystem comprising a first UART0 interface module and a first SPI interface module, the first UART0 interface module being used to interact with a first peripheral terminal device;

[0035] The second microsystem comprises a second SPI interface module, and the second SPI interface module is connected to the first SPI interface module to transmit data between the first microsystem and the second microsystem.

[0036] See below Figure 1 and Figure 2 A communication system based on a MIPS architecture processor according to the present invention is exemplarily described. Figure 1 FIG. 1 is a schematic diagram of a communication system based on a MIPS architecture processor according to an embodiment of the present invention. Figure 2 A schematic flow chart of a data transmission process of a communication system based on a MIPS architecture processor according to an embodiment of the present invention is shown.

[0037] like Figure 1 As shown, a communication system based on a MIPS architecture processor according to the present invention includes a first microsystem 1 and a second microsystem 2 .

[0038] The first microsystem 1 and the second microsystem 2 can be circuit boards (development boards) used for embedded system development, on which various devices can be arranged, including a series of hardware components such as a central processing unit, a memory, an input device, an input device, a data path / bus and an external resource interface.

[0039] Continue to view Figure 1 The first microsystem 1 includes a first UART0 interface module and a first SPI interface module, and the first UART0 interface module is used to interact with the first peripheral terminal device 3.

[0040] Exemplarily, the terminal includes a data collection terminal and / or a data processing terminal.

[0041] Exemplarily, the data collection terminal includes instruments and controllers for collecting data, such as electricity metering and collection equipment and gas usage collection equipment.

[0042] Exemplarily, the data processing terminal includes a terminal for processing data, such as a data processor, including but not limited to a computer.

[0043] The UART interface module is a universal serial bus, which is used for asynchronous communication, bidirectional communication, full-duplex transmission and reception. UART converts parallel data into serial data for transmission, and converts received serial data into parallel data.

[0044] The UART0 interface module is usually used in the UART interface module to communicate with the terminal device. By setting the interface level, it can communicate with terminal devices such as computers.

[0045] In one embodiment of the present invention, the first peripheral terminal device 3 is a data output device, which stores a memory and a processor that can execute instructions. When the processor executes the executable program instructions, the data output device outputs data. The data output device can be a personal computing device such as a computer or a tablet computer.

[0046] Continue to view Figure 1 , the second microsystem 2 includes a second SPI interface module.

[0047] The first SPI interface module of the first microsystem 1 is connected to the second SPI interface module of the second microsystem, so as to perform data transmission between the first microsystem 1 and the second microsystem 2 .

[0048] SPI is the abbreviation of Serial Peripheral Interface, which is a high-speed, full-duplex, synchronous communication bus. Unlike the UART interface module, the SPI serial peripheral interface can also connect to multiple peripheral devices at the same time and communicate with them.

[0049] In this embodiment, the first microsystem and the second microsystem are configured as circuit boards (development boards) for embedded system development, on which data output and input pins are provided, such as Figure 1 As shown, the first SPI interface module of the first microsystem 1 is provided with a data output pin 11 (SO) and a data input pin 12 (SI), and the second SPI interface module of the second microsystem 2 is provided with a data output pin 21 (SO) and a data input pin 22 (SI). In this embodiment, by connecting the data output pin 11 (SO) on the first SPI interface module of the first microsystem 1 with the data input pin 22 (SI) on the second SPI interface module of the second microsystem 2, data transmission between the first microsystem and the second microsystem is achieved.

[0050] According to the communication system based on the MIPS architecture processor of the present invention, communication and data storage between two independent microsystems can be realized. The terminal device transmits data to the second microsystem through the connected first microsystem to realize the functions of the microsystem (such as collecting data or storing data), thereby improving the efficiency of the entire system.

[0051] For example, when the first UART0 interface module is connected to the first peripheral terminal device 3 as a computer, a control command is input through the computer and sent to the first UART0 interface module, the first UART0 interface module receives the control command, the processor in the first microsystem reads the control command through the bus, and loads the read data into the first SPI interface module of the first microsystem, and sends the data output pin 11 sent by the first SPI interface module to the data receiving pin 22 of the second SPI interface module of the second microsystem, so that the control command can be transmitted and communicated between the first microsystem and the second microsystem, and when the control command is used to control the data of the second microsystem, the second microsystem can be directly controlled to operate and realize the function of the second microsystem. For example, when the second microsystem is a sensor device, data acquisition can be performed according to the control command, and when the second microsystem has a data storage function, the data storage function can be realized.

[0052] In an example according to the present invention, at least two second microsystems are included, wherein the second SPI interface modules of at least two of the at least two microsystems are connected to the first SPI interface module of the same first microsystem.

[0053] Since SPI can connect to multiple peripheral devices at the same time and communicate with them, in the present invention, multiple second microsystems are set, each of which includes a second SPI interface module, and the second SPI interface modules in the multiple second microsystems are connected to the first SPI interface module of the same first microsystem, so that data can be transmitted to the multiple second microsystems through the same first microsystem, thereby improving system efficiency and realizing more and more complex functions when the multiple second microsystems have different functions.

[0054] Continue to view Figure 1 , exemplarily, the first microsystem 1 further includes a first processor module 13, the first processor module 13 is used to detect the working state of the first UART0 interface module and control the data transmission between the first UART0 interface module and the first peripheral terminal device 3 according to the working state, the working state including the data transmission state and the idle state;

[0055] When the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data from the first peripheral terminal device 3;

[0056] When the first UART0 interface module is in the idle state, the first UART0 interface module is controlled to receive data of the first peripheral terminal device 3.

[0057] The first processor module 13 can be set as a processor core, which is connected to the UART0 interface module through a data bus. During the data transmission of the first microsystem 1, the processor core reads data from the first UART0 interface module through the bus and puts the read data into the register of the processor core.

[0058] Further, exemplarily, the first processor module 13 further detects the working state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the working state, wherein the working state includes a data transmission state and an idle state;

[0059] When the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data;

[0060] When the first SPI interface module is in an idle state, the first SPI interface module is controlled to send data.

[0061] Continue to view Figure 1, connected to the UART0 interface module through the data bus. During the data transmission of the first microsystem 1, the processor core reads data from the first UART0 interface module through the bus and puts the read data into the register of the processor core; at the same time, the processor core loads the data to the first SPI interface module of the first microsystem 1 through the data bus, ready to be sent to the second microsystem.

[0062] Also exemplarily, the second microsystem 2 further includes a second processor module 23, the second processor module 23 is used to detect the working state of the second SPI interface module and control the second SPI interface module to receive data sent by the first SPI interface module according to the working state, the working state including a data transmission state and an idle state;

[0063] When the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data;

[0064] When the second SPI interface module is in an idle state, the second SPI interface module is controlled to receive data.

[0065] The second processor module 23 can be set as a processor core, which is connected to the second SPI interface module through a data bus. In the process of receiving data transmitted by the first microsystem 1, the processor core controls the second SPI interface module to receive data through the bus.

[0066] In one example according to the present invention, the ISA architecture of the first microsystem and the second microsystem adopts 32-bit MIPS-I. Using 32-bit MIPS-I as the ISA architecture allows users to add their own instructions to the developed kernel for easy modification. In the present invention, after the second SPI interface module of the second microsystem is physically connected to the first SPI interface module of the first microsystem, the functions of data transmission, data storage, etc. between the first microsystem and the second microsystem are realized by editing and modifying instructions on the ISA architecture of 32-bit MIPS-I.

[0067] In one example according to the present invention, Figure 1 As shown, a storage module 24 is provided in the second microsystem 2 . When the second SPI interface module of the second microsystem 2 receives data from the first microsystem 1 , the data is stored in the storage module 24 .

[0068] It should be understood that the storage module 24 is provided in the second microsystem 2 to realize the storage function for exemplary purposes only, and those skilled in the art should understand that the second microsystem 2 can be configured as any system unit with a logical function to realize the present invention. For example, the second microsystem 2 includes a sensor for collecting data, a processing unit with a computing function, etc., which are not limited here.

[0069] In one example according to the present invention, the storage module 24 is configured as a flash memory module, so that the second microsystem can implement multiple read and write operations.

[0070] Exemplarily, the second processor module 24 also controls the read and write operations of the flash memory module.

[0071] In one embodiment of the present invention, the flash memory module write operation is maintained at a system clock frequency of 6 MHz, that is, the baud rate is maintained at 19200, so 0x1000 needs to be written to SYS_CTL2_REG (1f800702) before the write operation to set the baud rate.

[0072] Flash module erasure is accomplished by calling a special system function. In C language implementation, the flash module can be erased by jumping to the address through the function pointer. 1K byte of content can be erased by writing any data to 0x1010-[addr]. The address of the system function OS_EfErease for erasing the flash module is: 0x2f8.

[0073] The writing operation of the flash memory module is completed by calling a special system function. In the C language implementation, the function pointer can be used to jump to the address 0x2c4 of the system function to implement the writing of the Flash. It should be noted that a word has four bytes, and the address of a word must match the address of one of the 4 bytes it includes, and the address of consecutive words differs by 4. Therefore, the address should be increased by 4 when storing the next character.

[0074] The read operation of the flash module maintains a baud rate of 9600, so before the write operation, you need to write 0x00 to SYS_CTL2_REG (1f800702) to set the baud rate.

[0075] The read operation of the flash memory module is similar to other storage, and the data read operation can be completed using the MemoryRead32 function.

[0076] The above is for reference Figure 1An exemplary introduction to the communication system based on the MIPS architecture processor according to the present invention. It should be understood that in the above introduction, only the operation process of the first microsystem 1 receiving data from the first peripheral terminal device 3 and then transmitting it to the second microsystem 2 for storage in the storage module 24 is introduced, and the one-way transmission process of the data shown is only exemplary, and those skilled in the art should understand that the data can also be transmitted in the reverse direction.

[0077] For example, Figure 1 As shown, the second microsystem 2 is also provided with a second UART0 interface module for connecting to a second peripheral terminal device 4 .

[0078] Similar to the interaction between the first microsystem 1 and the first peripheral terminal device 3, the second microsystem 2 also transmits data with the second peripheral terminal device 4 through the second UART0 interface module. Similarly, the second SPI interface module in the second microsystem 2 is provided with a data output pin 21 (SO pin) and a data receiving pin 22 (SI pin), wherein the data output pin 21 is connected to the data receiving pin 12 of the first microsystem 1, so as to send the data received from the second peripheral terminal device 4 through the second UART0 interface module to the first microsystem.

[0079] Similarly, just as the storage module is provided in the second microsystem 2 , the first microsystem 1 may also be provided with a storage module for storing data received from the second microsystem 2 .

[0080] In an example according to the present invention, the second peripheral terminal device 4 is a display device. After the processing module 23 of the second microsystem reads data from the memory module 24, the data can be sent to the second peripheral terminal device 4 through the second URAT0 for display.

[0081] See also Figure 1 and Figure 2 The data transmission process of a communication system based on a MIPS architecture processor according to an embodiment of the present invention is schematically described. Figure 2 The data transmission process of the communication system based on the MIPS architecture processor is shown in Figure 1 The experiment was carried out on a communication system based on a MIPS architecture processor.

[0082] See also Figure 2, first confirm the master device, the master device is the microsystem (first microsystem 1 or second microsystem 2) that sends data. This step can be performed through the peripheral terminal device (first peripheral terminal device 3 or second peripheral terminal device 4, such as a computer) connected to the first microsystem and the second microsystem. When data needs to be sent through the microsystem (first microsystem 1 or second microsystem 2), set a command on the peripheral terminal device connected to the microsystem to send data. For example, send a command through the PC connected to the first microsystem 1. At this time, the first microsystem 1 is the master device and the second microsystem 2 is the slave device. While confirming the master device (the first microsystem is the master device), the master device (the first microsystem 1) receives a command from the PC through urat0, thereby turning off the urat0 interface module function and setting the SPI interface module (first SPI interface module) of the master device (the first microsystem 1) to prepare for data transmission. The corresponding slave device (the second microsystem is a slave device) turns off the urat0 function and sets the SPI interface module (second SPI interface module) of the slave device (the second microsystem 2) to prepare for data reception.

[0083] like Figure 2 As shown, the CS in the master device is turned on, the master device (the first processor module 13 in the first microsystem 1) controls the SPI (the first SPI interface module), controls the SPI (the first SPI interface module) to send data, calls the urat_read function return value, obtains characters, controls the SPI (the first SPI interface module) to send data, waits for the SPI (the first SPI interface module) to complete the sending task, and turns off the CS (the first processor module 13 in the first microsystem 1).

[0084] Similarly, the slave device (the second processor module 23 in the second microsystem 2) also controls the second SPI interface module to perform a receiving operation; when the second SPI interface module is in the data transmission state, the second SPI interface module is controlled to suspend receiving data from the first microsystem; when the second SPI interface module completes the current data transmission, the second SPI interface module is controlled to receive data from the first microsystem 1. After completing the data reception from the first microsystem 1, storage and display operations are performed, specifically including: setting the write baud rate of the flash memory module (storage module 24), erasing the flash memory module, storing data in the flash memory module space, setting the read baud rate after a delay of 10ms, and reading and printing the data from the flash memory module space.

[0085] The above is an exemplary introduction to the communication system based on the MIPS architecture processor according to the present invention. According to the present invention, communication and data storage between two independent microsystems can be realized. The terminal device transmits data to the second microsystem through the connected first microsystem to realize the functions of the microsystems (such as collecting data or storing data), thereby improving the efficiency of the entire system. At the same time, through the SPI interface module, one microsystem can transmit data to more than one microsystem at the same time, so that more and more complex functions can be realized while improving the efficiency of the system.

[0086] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0088] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0089] Similarly, it should be understood that in order to streamline the present invention and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0090] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0091] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0092] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0093] The above is only a specific embodiment of the present invention or an explanation of a specific embodiment. The protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A communication system based on a MIPS architecture processor, characterized in that: include: A first microsystem, wherein the first microsystem comprises a first UART0 interface module and a first SPI interface module, wherein the first UART0 interface module is used to interact with a first peripheral terminal device; wherein the first peripheral terminal device comprises a data acquisition terminal and / or a data processing terminal; The second microsystem includes a second SPI interface module, which is connected to the first SPI interface module to receive data sent by the first SPI interface module to realize data transmission between the first microsystem and the second microsystem, wherein the data includes data collected by the data acquisition terminal and / or data processed by the data processing terminal.

2. The communication system based on the MIPS architecture processor according to claim 1, characterized in that: At least two of the second microsystems are included, wherein the second SPI interface modules of at least two of the at least two microsystems are connected to the first SPI interface module of the same first microsystem.

3. The communication system based on the MIPS architecture processor according to claim 1, characterized in that: The first microsystem further includes a first processor module, the first processor module is used to detect the working state of the first UART0 interface module and control the data transmission between the first UART0 interface module and the first peripheral terminal device according to the working state, the working state including the data transmission state and the idle state; When the first UART0 interface module is in the data transmission state, controlling the first UART0 interface module to suspend receiving data from the first peripheral terminal device; When the first UART0 interface module is in the idle state, the first UART0 interface module is controlled to receive data of the first peripheral terminal device.

4. The communication system based on the MIPS architecture processor according to claim 3, characterized in that: The first processor module also detects the working state of the first SPI interface module, and controls the first SPI interface module to send data to the second SPI interface module according to the working state, wherein the working state includes a data transmission state and an idle state; When the first SPI interface module is in the data transmission state, controlling the first SPI interface module to suspend sending data; When the first SPI interface module is in an idle state, the first SPI interface module is controlled to send data.

5. The communication system based on the MIPS architecture processor according to claim 1, characterized in that: The second microsystem further includes a second processor module, the second processor module is used to detect the working state of the second SPI interface module and control the second SPI interface module to receive data sent by the first SPI interface module according to the working state, the working state including a data transmission state and an idle state; When the second SPI interface module is in the data transmission state, controlling the second SPI interface module to suspend receiving data; When the second SPI interface module is in an idle state, the second SPI interface module is controlled to receive data.

6. The communication system based on the MIPS architecture processor according to claim 5, characterized in that: The second microsystem further includes a storage module, and the storage module is used to store the data.

7. The communication system based on the MIPS architecture processor according to claim 6, characterized in that: The storage module is a flash memory module.

8. The communication system based on the MIPS architecture processor according to claim 7, characterized in that: The second processor module also controls the read and write operations of the flash memory module.

9. The communication system based on the MIPS architecture processor according to claim 4, characterized in that: The second microsystem also includes a second UART0 interface module, and the second UART0 interface module is used to interact with a second peripheral terminal device.

10. The communication system based on the MIPS architecture processor according to claim 9, characterized in that: The ISA architecture of the first microsystem and the second microsystem adopts 32-bit MIPS-I.

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