Storage unit, anti-fuse structure, preparation method and programming method thereof

Abstract

The present disclosure provides a memory cell, an anti-fuse structure, and a method for preparing and programming the anti-fuse structure. The anti-fuse structure may include a first conductive layer, an anti-fuse layer, and a second conductive layer. The anti-fuse layer is disposed on the first conductive layer, and the anti-fuse layer includes a magnetic tunnel junction. The second conductive layer is disposed on a side of the anti-fuse layer away from the first conductive layer. The present disclosure enables the memory cell to have a multi-time programmable function.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a storage unit, an anti-fuse structure, and a preparation method and a programming method of the anti-fuse structure. Background Art

[0002] With the exponential growth of memory capacity, dynamic random access memory (DRAM) chips manufactured using semiconductor processes will inevitably produce defective memory cells. The commonly used repair technology in the industry is to use redundant memory cells to permanently replace such defective memory cells. This repair technology requires the use of a non-volatile anti-fuse structure on the chip, which uses the principle that the resistance of the dielectric layer in the anti-fuse structure changes after breakdown to save data.

[0003] However, the existing anti-fuse structure can only enable the memory cell to be programmed once (OTP, one time program). How to design the anti-fuse structure to enable the memory cell to have a multi-time programmable function has always been a problem to be solved in the art.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a memory cell, an anti-fuse structure, and a method for preparing and programming the anti-fuse structure, which can enable the memory cell to have a multi-time programmable function.

[0006] According to one aspect of the present disclosure, an anti-fuse structure is provided, comprising:

[0007] a first conductive layer;

[0008] an anti-fuse layer, disposed on the first conductive layer, and the anti-fuse layer includes a magnetic tunnel junction;

[0009] The second conductive layer is disposed on a side of the anti-fuse layer away from the first conductive layer.

[0010] In an exemplary embodiment of the present disclosure, the anti-fuse structure further includes:

[0011] A substrate having a bearing surface, wherein a groove is formed on the bearing surface;

[0012] An isolation structure is filled in the trench, the first conductive layer is disposed on the isolation structure, and a projection of the first conductive layer on the substrate is located within a projection area of ​​the isolation structure on the substrate.

[0013] In an exemplary embodiment of the present disclosure, a projection of the second conductive layer on the substrate does not overlap with a projection of the first conductive layer on the substrate.

[0014] In an exemplary embodiment of the present disclosure, the anti-fuse structure further includes:

[0015] A spacer is provided, wherein the spacer is located on the sidewalls of the first conductive layer and the anti-fuse layer, and the spacer partially surrounds the first conductive layer.

[0016] In an exemplary embodiment of the present disclosure, the anti-fuse structure further includes:

[0017] a first contact electrode connected to the first conductive layer;

[0018] The second contact electrode is connected to the second conductive layer.

[0019] In an exemplary embodiment of the present disclosure, the anti-fuse structure further includes:

[0020] The protective top layer is arranged on a side of the second conductive layer away from the anti-fuse layer, and the second contact electrode is embedded in the protective top layer.

[0021] In an exemplary embodiment of the present disclosure, the anti-fuse structure further includes:

[0022] A gate oxide layer is disposed between the isolation structure and the first conductive layer.

[0023] In an exemplary embodiment of the present disclosure, the magnetic tunnel junction includes:

[0024] A magnetic reference layer, disposed on the first conductive layer;

[0025] a tunnel barrier layer, disposed on a side of the magnetic reference layer away from the first conductive layer;

[0026] The free layer is arranged on a side of the tunnel barrier layer away from the magnetic reference layer.

[0027] According to one aspect of the present disclosure, a memory cell is provided, comprising the anti-fuse structure described in any one of the above.

[0028] According to one aspect of the present disclosure, a method for preparing an antifuse structure is provided, comprising:

[0029] forming a first conductive layer;

[0030] forming an anti-fuse layer on the first conductive layer, wherein the anti-fuse layer includes a magnetic tunnel junction;

[0031] A second conductive layer is formed on a side of the anti-fuse layer away from the first conductive layer.

[0032] In an exemplary embodiment of the present disclosure, the method for preparing the antifuse structure further includes:

[0033] Providing a substrate, wherein the substrate has a supporting surface;

[0034] forming a groove on the bearing surface;

[0035] filling an isolation structure in the trench;

[0036] A gate oxide layer is formed on the isolation structure, the first conductive layer is formed on a side of the gate oxide layer away from the isolation structure, and a projection of the first conductive layer on the substrate is located within a projection region of the isolation structure on the substrate.

[0037] In an exemplary embodiment of the present disclosure, the method for preparing the antifuse structure further includes:

[0038] forming a first contact electrode, wherein the first contact electrode is connected to the first conductive layer;

[0039] A second contact electrode is formed, wherein the second contact electrode is connected to the second conductive layer.

[0040] In an exemplary embodiment of the present disclosure, the forming of the second contact electrode includes:

[0041] forming a protective top layer on a side of the second conductive layer away from the anti-fuse layer;

[0042] forming an electrode hole in the protective top layer, wherein the electrode hole penetrates the protective top layer;

[0043] A second contact electrode is formed in the electrode hole, and the second contact electrode fills the electrode hole.

[0044] In an exemplary embodiment of the present disclosure, before forming the electrode hole in the protective top layer, the method includes:

[0045] Using a first mask to cover the extended area on the surface of the first conductive layer;

[0046] Forming a spacer, wherein the spacer is located on the sidewalls of the first conductive layer, the antifuse layer, and the protective top layer, and the spacer partially surrounds the first conductive layer, and the surface of the spacer is flush with the upper surface of the protective top layer;

[0047] The first mask is removed to expose the protruding area on the surface of the first conductive layer.

[0048] According to one aspect of the present disclosure, a programming method based on any one of the above anti-fuse structures is provided, comprising:

[0049] Applying a first voltage or a first current to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a first resistance value;

[0050] A second voltage or a second current is applied to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a second resistance value.

[0051] The memory cell, anti-fuse structure, and preparation method and programming method of the anti-fuse structure disclosed in the present invention have a magnetic tunnel junction provided in the anti-fuse layer between the first conductive layer and the second conductive layer. Thus, the resistance value of the anti-fuse layer can be changed by changing the voltage or current applied between the two conductive layers, thereby making the memory cell with the anti-fuse structure have a multi-time programmable function.

[0052] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The above and other features and advantages of the present disclosure will become more apparent by describing in detail its exemplary embodiments with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work.

[0054] Figure 1 is a schematic diagram of an anti-fuse structure according to an embodiment of the present disclosure;

[0055] Figure 2 for Figure 1 A cross-sectional view of the structure in the AA direction;

[0056] Figure 3 for Figure 1 A cross-sectional view of the structure shown in the BB direction;

[0057] Figure 4 is a schematic diagram of a magnetic tunnel junction according to an embodiment of the present disclosure;

[0058] Figure 5 is a flow chart of a method for preparing an anti-fuse structure according to an embodiment of the present disclosure;

[0059] Figure 6 is a flow chart of step S160 in the method for preparing an anti-fuse structure according to an embodiment of the present disclosure;

[0060] Figure 7The present invention is a flowchart of a programming method according to an embodiment of the present invention.

[0061] In the figure: 1. first conductive layer; 2. anti-fuse layer; 21. magnetic reference layer; 22. tunnel barrier layer; 23. free layer; 3. second conductive layer; 4. substrate; 5. isolation structure; 6. first contact electrode; 7. second contact electrode; 8. spacer; 9. protective top layer; 10. gate oxide layer. DETAILED DESCRIPTION

[0062] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the disclosure will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, materials, devices, etc. may be employed. In other cases, known technical solutions are not shown or described in detail to avoid blurring various aspects of the present disclosure. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted.

[0063] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. The terms "a", "an" and "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that in addition to the listed elements / components / etc., additional elements / components / etc. may exist.

[0064] The present disclosure provides an anti-fuse structure. Figures 1 to 3 As shown, the anti-fuse structure may include a first conductive layer 1, an anti-fuse layer 2 and a second conductive layer 3, wherein:

[0065] The anti-fuse layer 2 is disposed on the first conductive layer 1 , and the anti-fuse layer 2 includes a magnetic tunnel junction. The second conductive layer 3 is disposed on a side of the anti-fuse layer 2 away from the first conductive layer 1 .

[0066] The anti-fuse structure of the embodiment of the present disclosure has a magnetic tunnel junction provided in the anti-fuse layer 2 between the first conductive layer 1 and the second conductive layer 3. Therefore, the resistance value of the anti-fuse layer 2 can be changed by changing the voltage or current applied between the two conductive layers, thereby making the storage cell with the anti-fuse structure have a multi-time programmable (MTP) function.

[0067] The following is a detailed description of each part of the embodiment of the present disclosure:

[0068] like Figure 2 and Figure 3 As shown, the material of the first conductive layer 1 can be tungsten or titanium aluminum alloy, but is not limited thereto, and can also be titanium nitride, tantalum nitride, etc.

[0069] like Figure 2 and Figure 3 As shown, the anti-fuse layer 2 is disposed on the first conductive layer 1. Specifically, the anti-fuse layer 2 covers the first conductive layer 1. Figure 4 As shown, the anti-fuse layer 2 includes a magnetic tunnel junction. The magnetic tunnel junction may include a magnetic reference layer 21 (reference layer), a tunnel barrier layer 22 (tunnel barrier) and a free layer 23 (free layer). The magnetic reference layer 21 may be disposed on the first conductive layer 1. The magnetic reference layer 21 covers the first conductive layer 1. The tunnel barrier layer 22 is disposed on a side of the magnetic reference layer 21 away from the first conductive layer 1, that is, the magnetic reference layer 21 is disposed between the first conductive layer 1 and the tunnel barrier layer 22. The free layer 23 is disposed on a side of the tunnel barrier layer 22 away from the magnetic reference layer 21, that is, the tunnel barrier layer 22 is disposed between the magnetic reference layer 21 and the free layer 23.

[0070] In one embodiment, a free layer 23 may also be disposed on the first conductive layer 1. The tunnel barrier layer 22 is disposed on a side of the free layer 23 away from the first conductive layer 1, that is, the free layer 23 is disposed between the first conductive layer 1 and the tunnel barrier layer 22. The magnetic reference layer 21 is disposed on a side of the tunnel barrier layer 22 away from the free layer 23.

[0071] The material of the magnetic reference layer 21 can be CoFeB, and the thickness can be The material of the tunnel barrier layer 22 can be MgO, and the thickness can be The material of the free layer 23 can be CoFeB, and the thickness can be The thickness of the magnetic tunnel junction can be as low as 4 nm, but the embodiments of the present disclosure do not specifically limit this. When the current passing through the antifuse layer 2 changes from 10 μA to 100 μA, its magnetoresistance ratio can change from 10 to 200. When the magnetization directions of the magnetic reference layer 21 and the free layer 23 are consistent, the electron spin directions in the majority state in the two layers of ferromagnetic material are the same, the tunneling probability is high, and the magnetic tunnel junction presents a low resistance state; conversely, when the magnetization directions of the magnetic reference layer 21 and the free layer 23 are inconsistent, the magnetic tunnel junction presents a high resistance state.

[0072] In addition, if Figures 2 to 4 As shown, the anti-fuse layer 2 may also include a pinned layer and a non-magnetic metal layer. The pinned layer covers the first conductive layer 1, the non-magnetic metal layer covers the pinned layer, and the magnetic reference layer 21 covers the non-magnetic metal layer. The material of the pinned layer may be CoFe, and the thickness may be The material of the non-magnetic metal layer can be ruthenium (Ru), and the thickness can be

[0073] like Figure 2 and Figure 3 As shown, the second conductive layer 3 is arranged on the side of the anti-fuse layer 2 away from the first conductive layer 1, that is, the anti-fuse layer 2 is arranged between the second conductive layer 3 and the first conductive layer 1. The second conductive layer 3 covers the anti-fuse layer 2. Specifically, the second conductive layer 3 covers the above-mentioned free layer 23. The material of the second conductive layer 3 can be tungsten, titanium aluminum alloy and polysilicon. Of course, the material of the second conductive layer 3 can also be titanium nitride, tantalum nitride and tungsten nitride.

[0074] like Figures 1 to 3 As shown, the anti-fuse structure of the embodiment of the present disclosure may also include a substrate 4 and an isolation structure 5. The material of the substrate 4 may be undoped single crystal silicon, or of course, single crystal silicon doped with impurities, but it is not limited thereto, and may also be silicon on an insulator, etc. The substrate 4 may have a bearing surface. The bearing surface is arranged opposite to the first conductive layer 1. A groove is formed on the bearing surface. The material of the isolation structure 5 may be silicon oxide, or of course, silicon nitride. The isolation structure 5 may be filled in the groove. Among them, the area of ​​the substrate 4 bearing surface outside the groove is flush with the surface of the isolation structure 5 facing the first conductive layer 1, that is, the isolation structure 5 fills the groove on the bearing surface, and the isolation structure 5 does not extend out of the bearing surface. The first conductive layer 1 may be arranged on the isolation structure 5. The projection of the first conductive layer 1 on the substrate 4 is located within the projection area of ​​the isolation structure 5 on the substrate 4. The projections are all positive projections. In addition, when the first conductive layer 1 is used as a gate, a gate oxide layer 10 may be provided between the first conductive layer 1 and the isolation structure 5.

[0075] Furthermore, if Figures 1 to 3 As shown, the projection of the second conductive layer 3 on the substrate 4 does not overlap with the projection of the first conductive layer 1 on the substrate 4, so that the first conductive layer 1 and the second conductive layer 3 can be conveniently connected to the power supply respectively. The anti-fuse structure of the embodiment of the present disclosure may also include a first contact electrode 6 and a second contact electrode 7. The first contact electrode 6 can be connected to the first conductive layer 1. The second contact electrode 7 can be connected to the second conductive layer 3. The first contact electrode 6 and the second contact electrode 7 are used to connect to the power supply to apply a voltage or current between the first conductive layer 1 and the second conductive layer 3. The anti-fuse structure of the embodiment of the present disclosure may also include a protective top layer 9. The protective top layer 9 is arranged on the side of the second conductive layer 3 away from the anti-fuse layer 2, and the second contact electrode 7 is embedded in the protective top layer 9 and contacts the second conductive layer 3. The anti-fuse structure of the embodiment of the present disclosure may also include a spacer 8. The spacer 8 is located on the sidewalls of the first conductive layer 1 and the anti-fuse layer 2, and the spacer 8 partially surrounds the first conductive layer 1. Among them, the protruding area on the surface of the first conductive layer 1 not surrounded by the spacer 8 can be used to connect to the first contact electrode 6.

[0076] For example, Figures 1 to 3 As shown, the anti-fuse structure of the embodiment of the present disclosure includes a substrate 4, an isolation structure 5, a gate oxide layer 10, a first conductive layer 1, an anti-fuse structure, a second conductive layer 3, a spacer 8, a protective top layer 9, a first contact electrode 6 and a second contact electrode 7. The isolation structure 5 is filled in the groove of the substrate 4. The gate oxide layer 10 covers the isolation structure 5. The first conductive layer 1 covers the gate oxide layer 10. The anti-fuse layer 2 covers the first conductive layer 1. The second conductive layer 3 covers the anti-fuse layer 2. The spacer 8 is located on the sidewalls of the first conductive layer 1 and the anti-fuse layer 2, and the spacer 8 partially surrounds the first conductive layer 1. The first contact electrode 6 is connected to the first conductive layer 1. The second contact electrode 7 is connected to the second conductive layer 3.

[0077] The present disclosure also provides a memory cell. The memory cell includes the anti-fuse structure described in the above embodiment. The anti-fuse structure used in the memory cell of the present disclosure is the same as the anti-fuse structure in the above embodiment, and therefore has the same beneficial effects, which will not be described in detail here.

[0078] The present disclosure also provides a method for preparing an anti-fuse structure. The method is used to prepare the anti-fuse structure described in any of the above embodiments. Figure 5 As shown, the method for preparing the anti-fuse structure may include steps S120 to S140, wherein:

[0079] Step S120: forming a first conductive layer.

[0080] The material of the first conductive layer can be tungsten, titanium aluminum alloy and polysilicon, but is not limited thereto, and can also be titanium nitride, tantalum nitride and tungsten nitride, etc. The first conductive layer can be prepared by vapor deposition on a substrate.

[0081] Step S130 , forming an anti-fuse layer on the first conductive layer, wherein the anti-fuse layer includes a magnetic tunnel junction.

[0082] The anti-fuse layer may be formed by a vapor deposition method, but the embodiments of the present disclosure are not limited thereto. Specifically, step S130 may include: forming a magnetic reference layer on the first conductive layer; forming a tunnel barrier layer on a side of the magnetic reference layer away from the magnetic reference layer; and forming a free layer on a side of the tunnel barrier layer away from the magnetic reference layer. The magnetic reference layer, the tunnel barrier layer, and the free layer form a magnetic tunnel junction to constitute the anti-fuse layer.

[0083] Step S140 , forming a second conductive layer on a side of the antifuse layer away from the first conductive layer.

[0084] The material of the second conductive layer can be tungsten, titanium aluminum alloy, etc. Of course, the material of the second conductive layer can also be titanium nitride, tantalum nitride, etc. The second conductive layer can be formed by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The formation process of the second conductive layer can be the same process as the formation process of the bit line in the memory cell array.

[0085] In the method for preparing the anti-fuse structure of the embodiment of the present disclosure, since the anti-fuse layer between the first conductive layer and the second conductive layer is provided with a magnetic tunnel junction, the resistance value of the anti-fuse layer can be changed by changing the voltage or current applied between the two conductive layers, thereby making the storage unit with the anti-fuse structure have a multi-time programmable function.

[0086] like Figure 5 As shown, before step S120, the method for preparing the anti-fuse structure of the embodiment of the present disclosure may further include steps S100 and S110, wherein:

[0087] Step S100: providing a substrate, wherein the substrate has a carrying surface.

[0088] The material of the substrate may be undoped single crystal silicon, or of course, may be single crystal silicon doped with impurities, but is not limited thereto, and may also be silicon on insulator, etc.

[0089] Step S110 , forming a trench on the bearing surface, filling the trench with an isolation structure, and forming a gate oxide layer on the isolation structure.

[0090] The groove can be formed by etching. The material of the isolation structure can be silicon oxide, or of course, silicon nitride. The area of ​​the substrate's bearing surface outside the groove is flush with the surface of the isolation structure facing the first conductive layer, that is, the isolation structure fills the groove on the bearing surface, and the isolation structure does not extend out of the bearing surface. The gate oxide layer can be prepared by vapor deposition. The first conductive layer can be formed on the side of the gate oxide layer away from the substrate, and the projection of the first conductive layer on the substrate is located within the projection area of ​​the isolation structure on the substrate.

[0091] like Figure 5 As shown, after step S140, the method for preparing the anti-fuse structure according to the embodiment of the present disclosure may further include steps S150 and S160, wherein:

[0092] Step S150: forming a first contact electrode, wherein the first contact electrode is connected to the first conductive layer.

[0093] The material of the first contact electrode may be copper, but is not limited thereto, and may also be other materials.

[0094] Step S160: forming a second contact electrode, wherein the second contact electrode is connected to the second conductive layer.

[0095] The material of the second contact electrode can be the same as that of the first contact electrode, but is not limited thereto and can also be different. For example, the material of the second contact electrode is copper.

[0096] like Figure 6 As shown, the above step S160 may include:

[0097] Step S1601 : forming a protective top layer on a side of the second conductive layer away from the anti-fuse layer.

[0098] The protective top layer can be produced by vapor deposition.

[0099] Step S1602: forming an electrode hole in the protective top layer, wherein the electrode hole penetrates the protective top layer.

[0100] The electrode hole may be formed by etching, for example, by bombardment with high-density plasma, but the embodiments of the present disclosure are not limited thereto.

[0101] Step S1603: forming a second contact electrode in the electrode hole, wherein the second contact electrode fills the electrode hole.

[0102] Both ends of the second contact electrode can extend out of the electrode hole, and one end of the second contact electrode can extend out of the contact surface between the protective top layer and the second conductive layer and contact the second conductive layer, and the other end of the second contact electrode can extend out of the surface of the protective top layer for contacting an external power source.

[0103] In addition, before forming the electrode hole in the protective top layer, the preparation method of the anti-fuse structure of the embodiment of the present disclosure may also include: using a first mask to cover the protruding area on the surface of the first conductive layer; forming a spacer, the spacer is located on the side walls of the first conductive layer, the anti-fuse layer, and the protective top layer, and the spacer partially surrounds the first conductive layer, and the surface of the spacer is flush with the upper surface of the protective top layer; removing the first mask to expose the protruding area on the surface of the first conductive layer.

[0104] The present disclosure also provides a programming method. The programming method is based on the anti-fuse structure described in any of the above embodiments. Figure 7 As shown, the programming method may include step A100 and step A110, wherein:

[0105] Step A100: applying a first voltage or a first current to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a first resistance value.

[0106] Step A110: applying a second voltage or a second current to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a second resistance value.

[0107] In the programming method of the embodiment of the present disclosure, since the anti-fuse layer between the first conductive layer and the second conductive layer is provided with a magnetic tunnel junction, when the voltage between the first conductive layer and the second conductive layer changes from the first voltage to the second voltage, or when the current between the first conductive layer and the second conductive layer changes from the first current to the second current, the resistance value of the anti-fuse layer can be changed from the first resistance value to the second resistance value, so that the anti-fuse structure has a multi-time programmable function.

[0108] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practice. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An anti-fuse structure, characterized in that: include: A substrate having a bearing surface, wherein a groove is formed on the bearing surface; An isolation structure filled in the trench, wherein the material of the isolation structure comprises silicon oxide or silicon nitride; A first conductive layer, wherein the first conductive layer is disposed on the isolation structure, and a projection of the first conductive layer on the substrate is located within a projection area of ​​the isolation structure on the substrate; an anti-fuse layer, disposed on the first conductive layer, and the anti-fuse layer includes a magnetic tunnel junction; The second conductive layer is disposed on a side of the anti-fuse layer away from the first conductive layer.

2. The anti-fuse structure according to claim 1, characterized in that: A projection of the second conductive layer on the substrate does not overlap with a projection of the first conductive layer on the substrate.

3. The anti-fuse structure according to claim 2, characterized in that: The anti-fuse structure further includes: A spacer is provided, wherein the spacer is located on the sidewalls of the first conductive layer and the anti-fuse layer, and the spacer partially surrounds the first conductive layer.

4. The anti-fuse structure according to claim 2, wherein: The anti-fuse structure further includes: a first contact electrode connected to the first conductive layer; The second contact electrode is connected to the second conductive layer.

5. The anti-fuse structure according to claim 4, characterized in that: The anti-fuse structure further includes: The protective top layer is arranged on a side of the second conductive layer away from the anti-fuse layer, and the second contact electrode is embedded in the protective top layer.

6. The anti-fuse structure according to claim 1, wherein: The anti-fuse structure further includes: A gate oxide layer is disposed between the isolation structure and the first conductive layer.

7. The anti-fuse structure according to claim 1, wherein: The magnetic tunnel junction comprises: A magnetic reference layer, disposed on the first conductive layer; a tunnel barrier layer, disposed on a side of the magnetic reference layer away from the first conductive layer; The free layer is arranged on a side of the tunnel barrier layer away from the magnetic reference layer.

8. A storage unit, characterized in that: The anti-fuse structure comprises any one of claims 1-7.

9. A method for preparing an anti-fuse structure, characterized in that: include: Providing a substrate, wherein the substrate has a supporting surface; forming a groove on the bearing surface; filling an isolation structure in the trench; forming a gate oxide layer on the isolation structure; forming a first conductive layer, wherein the first conductive layer is formed on a side of the gate oxide layer away from the isolation structure, and a projection of the first conductive layer on the substrate is located within a projection region of the isolation structure on the substrate; forming an anti-fuse layer on the first conductive layer, wherein the anti-fuse layer includes a magnetic tunnel junction; A second conductive layer is formed on a side of the anti-fuse layer away from the first conductive layer.

10. The method for preparing an anti-fuse structure according to claim 9, characterized in that: The method for preparing the anti-fuse structure further includes: forming a first contact electrode, wherein the first contact electrode is connected to the first conductive layer; A second contact electrode is formed, wherein the second contact electrode is connected to the second conductive layer.

11. The method for preparing an anti-fuse structure according to claim 10, characterized in that: The forming of the second contact electrode comprises: forming a protective top layer on a side of the second conductive layer away from the anti-fuse layer; forming an electrode hole in the protective top layer, wherein the electrode hole penetrates the protective top layer; A second contact electrode is formed in the electrode hole, and the second contact electrode fills the electrode hole.

12. The method for preparing an anti-fuse structure according to claim 11, characterized in that: Before forming the electrode hole in the protective top layer, the method comprises: Using a first mask to cover the extended area on the surface of the first conductive layer; Forming a spacer, wherein the spacer is located on the sidewalls of the first conductive layer, the antifuse layer, and the protective top layer, and the spacer partially surrounds the first conductive layer, and the surface of the spacer is flush with the upper surface of the protective top layer; The first mask is removed to expose the protruding area on the surface of the first conductive layer.

13. A programming method based on the anti-fuse structure according to any one of claims 1 to 7, characterized in that: include: Applying a first voltage or a first current to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a first resistance value; A second voltage or a second current is applied to the first conductive layer and the second conductive layer to change the resistance value of the anti-fuse layer to a second resistance value.

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