Programmable memory device

Abstract

The present disclosure provides a programmable memory element. The programmable memory element includes an active region, a gate structure, and an anti-fuse storage unit. The active region is formed in a substrate and has a linear top view shape. The gate structure is arranged on the substrate and has a linear portion, which intersects with a section of the active region, and the section is away from each end of the active region. The anti-fuse storage unit uses a portion of the active region as a terminal and also includes an electrode and a dielectric layer. The electrode is arranged on the portion of the active region and is separated from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.

Description

[0001] This application claims priority to and the benefit of U.S. application No. 16 / 989,268, filed on August 10, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a programmable memory device, and more particularly to a one-time programmable memory device. Background Art

[0003] Nonvolatile memory devices retain data even when their power supply is cut off. Based on the number of times they can be programmed, these devices are further divided into multi-time programmable (MTP) and one-time programmable (OTP) memory devices. Users can program an MTP memory device multiple times to change the data stored in it. On the other hand, an OTP memory device can only be programmed once, and the data stored in the OTP memory device cannot be changed.

[0004] Furthermore, OTP memory devices can be categorized as fuse-type and antifuse-type. A fuse-type OTP memory device is short-circuited before programming and open-circuited after programming. Conversely, an antifuse-type OTP memory device is open-circuited before programming and short-circuited after programming. Compared to fuse-type OTP memory devices, antifuse-type OTP memory devices are more compatible with complementary metal-oxide semiconductor (CMOS) manufacturing processes. However, as the size of antifuse OTP memory devices shrinks, precisely controlling the programming voltage of antifuse OTP memory devices becomes challenging.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present invention. Summary of the Invention

[0006] An object of the present invention is to provide a programmable memory device to solve at least one of the above problems.

[0007] One embodiment of the present disclosure provides a programmable memory device comprising an active region formed in a substrate and having a linear top-view shape; a gate structure disposed on the substrate and having a linear portion intersecting a section of the active region remote from both ends of the active region; and an anti-fuse storage cell using a portion of the active region as a terminal and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and remote from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.

[0008] In some embodiments, the gate structure is formed in a ring shape.

[0009] In some embodiments, one of the end portions of the active region overlaps with a region laterally surrounded by the gate structure.

[0010] In some embodiments, the two ends of the active region are a first end and a second end, the gate structure is closer to the first end of the active region than to the second end of the active region, and the anti-fuse storage unit is closer to the second end of the active region than to the first end of the active region.

[0011] In some embodiments, the programmable memory device further includes an insulating structure formed in the substrate and laterally surrounding the active region.

[0012] In some embodiments, the gate structure overlaps both the insulation structure and the section of the active region.

[0013] In some embodiments, the programmable memory device further includes a gate dielectric layer selectively disposed between the gate structure and the segment of the active region.

[0014] In some embodiments, a thickness of the gate dielectric layer is different from a thickness of the dielectric layer of the anti-fuse storage cell.

[0015] In some embodiments, the programmable memory device further includes a gate spacer covering a sidewall of the gate structure.

[0016] In some embodiments, the programmable memory device further includes a contact plug disposed on the gate structure and electrically connected to the gate structure.

[0017] In some embodiments, the contact plug is disposed away from the active region.

[0018] In some embodiments, a top surface of the contact plug is substantially coplanar with a top surface of the electrode of the antifuse storage unit.

[0019] Another embodiment of the present disclosure provides a programmable memory device having an access transistor including an active region and a gate structure, the active region being formed in a substrate and the gate structure being formed on the substrate, wherein the active region has a linear top-view shape, the gate structure having a first portion and a second portion, the first portion intersecting a section of the active region distal from each end of the active region, and the second portion being laterally distal from the active region; and a capacitor using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and distal from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.

[0020] In some embodiments, the first and second portions of the gate structure are connected to each other.

[0021] In some embodiments, one of the ends of the active region is located between the first and second portions of the gate structure.

[0022] As described above, according to some embodiments of the present disclosure, a programmable memory device includes a memory cell in an anti-fuse OTP memory array and has an access transistor and an anti-fuse storage unit, wherein the anti-fuse access unit is connected to one of the source terminal and the drain terminal of the access transistor. The access transistor has an active region formed in a substrate, and the access transistor has a gate structure formed on the substrate. The active region has a linear top view shape, and the gate structure has a linear portion that intersects with a section of the active region. Such a section of the active region is located away from both ends of the active region and is particularly susceptible to inaccuracies in photolithography and / or etching. Therefore, an overlap area between the gate structure and the active region can be better controlled, so that the gate coupling area and a threshold voltage of the access transistor are less affected by inaccuracies in the manufacturing process of the memory device.

[0023] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art of the present disclosure that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art of the present disclosure that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the disclosure of the present invention may be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

[0025] Figure 1A A schematic plan view of a memory element illustrating some embodiments of the present disclosure.

[0026] Figure 1B It is a schematic cross-sectional view along the section line AA' in FIG1 .

[0027] Figure 2 Example Figure 1A and Figure 1B FIG. 4 is a flow chart of a method for manufacturing a memory element.

[0028] Figures 3A to 3O Example Figure 2 Schematic cross-sectional views of various structures at different stages of the preparation method shown.

[0029] Figure 4 Schematic cross-sectional views of memory elements illustrating some embodiments of the present disclosure.

[0030] Figure 5 A schematic plan view of a memory element illustrating some embodiments of the present disclosure.

[0031] The reference numerals are as follows:

[0032] 10: Memory element

[0033] 10a: Memory element

[0034] 10b: Memory element

[0035] 100: Base

[0036] 102: Insulation structure

[0037] 104: Channel Area

[0038] 106: Gate dielectric layer

[0039] 106': Dielectric material

[0040] 108: Gate structure

[0041] 108': Gate structure

[0042] 110: doping area

[0043] 112: doping area

[0044] 114: Contact embolism

[0045] 116: dielectric layer

[0046] 116': dielectric layer

[0047] 118: Electrode

[0048] 120: Isolation layer

[0049] 122: Isolation layer

[0050] AA: Active Area

[0051] AF: Antifuse storage cell

[0052] AF': Antifuse storage cell

[0053] CL: Contact layer

[0054] CL': contact material layer

[0055] CM: Conductive material

[0056] E: End

[0057] E1: End

[0058] E2: End

[0059] GE: Gate electrode

[0060] GE': Gate electrode layer

[0061] GS: Gate spacer

[0062] GS': Gap sublayer

[0063] RS: Depression

[0064] T: Access transistor

[0065] S11: Step

[0066] S13: Step

[0067] S15: Step

[0068] S17: Step

[0069] S19: Steps

[0070] S21: Step

[0071] S23: Step

[0072] S25: Step

[0073] S27: Step

[0074] S29: Step

[0075] S31: Step

[0076] S33: Step

[0077] S35: Step

[0078] S37: Step

[0079] S39: Step

[0080] S41: Step

[0081] W1: Opening

[0082] W2: Opening DETAILED DESCRIPTION

[0083] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0084] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0085] Figure 1A A schematic plan view of a memory element 10 illustrating some embodiments of the present disclosure. Figure 1B For the Figure 1A Schematic cross-sectional view of the section line AA'.

[0086] Please refer to Figure 1A and Figure 1BIn some embodiments, memory device 10 is a memory cell in an antifuse one-time programmable (OTP) memory array. In some embodiments, memory device 10 includes an access transistor T and an antifuse storage cell AF. Antifuse storage cell AF is electrically connected to a source / drain terminal of access transistor T. When memory device 10 is selected for programming, access transistor T is turned on, and a high bias voltage across antifuse storage cell AF causes dielectric breakdown of antifuse storage cell AF. This forms a fixed conductive path across antifuse storage cell AF, significantly reducing the resistance of antifuse storage cell AF. On the other hand, if memory device 10 is not selected during a programming operation, memory device 10 remains in a high-resistance state. During a read operation, access transistor T is also turned on, and a current flowing through access transistor T and antifuse storage cell AF is detected, for example, by a sense amplifier (not shown) connected to the antifuse OTP memory array. If the memory device 10 has been selected for programming, a low resistance state of the anti-fuse storage cell AF can be detected. Conversely, if the memory device 10 has not been selected for programming, a high resistance state of the anti-fuse storage cell can be identified.

[0087] An active region AA of the access transistor T is defined in a substrate 100. The active region AA is a well region, which includes the source, drain, and channel regions of the access transistor T. One of the source and drain regions (e.g., doped regions 110 and 112 described in the following paragraphs) also functions as a terminal of the antifuse storage cell AF. The substrate 100 can be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. For example, a semiconductor material of the semiconductor wafer or SOI wafer can include an elemental semiconductor (e.g., Si, Ge, or the like), a compound semiconductor (e.g., a III-V compound semiconductor, SiC, or the like), a semiconductor alloy (e.g., SiGe or a III-V semiconductor alloy), or a combination thereof. In some embodiments, the substrate 100 is doped with a first conductivity type or a second conductivity type, where the second conductivity type is complementary to the first conductivity type. For example, the first conductivity type can be N-type, and the second conductivity type can be P-type, and so on.

[0088] The active area AA may be defined in the substrate 100 by an insulating structure 102. To be more specific, a plurality of active areas AA may be laterally surrounded by the insulating structure 102. In some embodiments, as Figure 1BAs shown, the insulating structure 102 is a shallow trench isolation structure. In such an embodiment, the insulating structure 102 extends from a top surface of the substrate 100 into the substrate 100 to a depth. The depth of the insulating structure 102 may be greater than the depth of the active area AA. Alternatively, the depth of the insulating structure 102 may be less than or equal to the depth of the active area AA. The insulating structure 102 is made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0089] The access transistor T may include a channel region 104, a gate dielectric layer 106, a gate structure 108, and doped regions 110, 112. The gate structure 108 may function as a gate terminal of the access transistor T, and the plurality of doped regions 110, 112 may function as source and drain terminals of the access transistor T. Furthermore, the channel region 104 and the plurality of doped regions 110, 112 are formed in a shallow portion of the active area AA. The channel region 104 and the plurality of doped regions 110, 112 extend from the upper surface of the substrate 100 into the substrate 100 to a depth that is less than the depth of the active area AA, and the channel region 104 is located between the plurality of doped regions 110, 112. Furthermore, the channel region 104 overlaps both the gate dielectric layer 106 and the gate structure 108, and the gate dielectric layer 106 is disposed between the channel region 104 and the gate structure 108. In some embodiments, the conductivity type of the channel region 104 is complementary to the conductivity type of the doped regions 110 and 112. For example, if the access transistor T is an N-type transistor, the conductivity type of the channel region 104 may be P-type, while the conductivity type of the doped regions 110 and 112 may be N-type. Alternatively, if the access transistor T is a P-type transistor, the conductivity type of the channel region 104 may be N-type, while the conductivity type of the doped regions 110 and 112 may be P-type. Furthermore, the conductivity type of the active region AA may be the same as the conductivity type of the channel region 104, except that the doping concentration of the active region AA may be lower than that of the channel region 104. In some embodiments, a material of the gate dielectric layer 106 may include silicon oxide or a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than 4).

[0090] In some embodiments, the gate structure 108 includes a gate electrode GE and at least one contact layer CL, and the contact layer CL is disposed on the gate electrode GE. Figure 1BAs shown, two contact layers CL are stacked on the gate electrode GE. The gate electrode GE and the multiple contact layers CL are each made of a conductive material. In some embodiments, the conductive materials used to form the gate electrode GE and the multiple contact layers CL are different from each other. For example, the gate electrode GE may be made of polysilicon, the lower contact layer CL may be made of titanium nitride, and the upper contact layer CL may be made of tungsten. Furthermore, the gate electrode GE may have a thickness that is greater than the thickness of each of the multiple contact layers CL. In addition, the thickness of each of the multiple contact layers CL may be different from each other. For example, the thickness of the lower contact layer CL may be less than the thickness of the upper contact layer CL. Furthermore, in some embodiments, the access transistor T further includes a gate spacer GS. The gate spacer GS covers the sidewalls of the gate dielectric layer 106 and the gate structure 108 and may be made of an isolation material (e.g., silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof). In those embodiments where the gate structure 108 includes a plurality of contact layers CL disposed on the gate electrode GE, an uppermost surface of the plurality of contact layers CL may be slightly lower than an uppermost end of the gate spacer GS. Figure 1A and Figure 1B Described as a single layer, the gate spacer GS may alternatively comprise multiple layers made of the same or different isolation materials.

[0091] like Figure 1A As shown, the active region AA has a linear top view shape, and the gate structure 108 is formed in a ring shape. A linear portion of the active region AA intersects with a linear portion of the gate structure 108 and is covered by the linear portion of the gate structure 108. Such an overlapping portion of the active region AA is away from the multiple ends E of the active region AA. In some embodiments, one end E of the active region AA (also marked as an end E1) overlaps with an area surrounded by the ring-shaped gate structure 108, while the other end E of the active region AA (also marked as an end E2) is arranged away from the gate structure 108. The channel region 104 is located in the portion where the active region AA overlaps with the gate structure 108 and is therefore not shown. Figure 1A On the other hand, the doped regions 110 and 112 extend from the overlapping portion to the ends E1 and E2 of the active region AA. In other words, the doped regions 110 and 112 may not be covered by the gate structure 108. In some embodiments, the portion where the active region AA overlaps with the gate structure 108 is closer to the end E1 of the active region AA than to the other end E2 of the active region AA. In such an embodiment, one of the doped regions 110 and 112 is larger than the other. For example, Figure 1AAs shown, the portion where the active area AA overlaps with the gate structure 108 is closer to the end E1 where the active area AA overlaps with the region surrounded by the gate structure 108, compared to the end E2 where the active area AA is away from the gate structure 108. Accordingly, the doped region 112 extending to the end E2 where the active area AA is away from the gate structure 108 is larger than the doped region 110 extending to the end E1 where the active area AA is away from the gate structure 108. Furthermore, in some embodiments, the gate dielectric layer 106 is selectively formed between the gate structure 108 and the active area AA (e.g., Figure 1B In these embodiments, a portion of the gate structure 108 is separated from the active area AA by the gate dielectric layer 106, while the remaining portion of the gate structure 108 contacts the insulating structure 102 without a gate dielectric layer therebetween.

[0092] See also Figure 1A In some embodiments, the gate structure 108 is formed in a shape close to a rectangular ring, which can be divided into four line segments. A first line segment of the gate structure 108 (eg Figure 1A The right line segment of the gate structure 108 shown in FIG. 1 intersects the active region AA. A second line segment of the gate structure 108 (eg Figure 1A The left line segment of the gate structure 108 is shown as substantially parallel to the first line segment of the gate structure 108. The third and fourth line segments of the gate structure 108 (eg Figure 1A The upper and lower line segments of the gate structure 108 are substantially perpendicular to the first and second line segments of the gate structure 108 and extend between the first and second line segments of the gate structure 108. In some embodiments, a width of the second line segment of the gate structure 108 is greater than each width of the first, third, and fourth line segments of the gate structure 108. In these embodiments, the region surrounded by the gate structure 108 is offset from a center of the gate structure. For example, such a region is offset from the center of the gate structure 108 to a right side of the gate structure 108 (e.g., Figure 1A shown).

[0093] Furthermore, a contact plug 114 may be disposed on the gate structure 108. In those embodiments where the gate structure 108 includes a gate electrode GE and a contact layer CL, the contact plug 114 is vertically disposed on the contact layer CL. In addition, in those embodiments where the gate structure 108 is formed in a shape close to a rectangular ring, the contact plug 114 is vertically disposed on a line segment of the gate structure 108 having a relatively large width (e.g., see FIG. 1 ). Figure 1A Furthermore, in some embodiments, as Figure 1AAs shown, the contact plug 114 has a linear top-view shape, with an extension direction thereof intersecting (or perpendicular to) an extension direction of the linear active area AA. The contact plug 114 is made of a conductive material. For example, the conductive material may include tungsten, copper, the like, or a combination thereof.

[0094] In some embodiments, the antifuse storage cell AF is a capacitor. During a programming operation, a high bias voltage is applied across the two terminals of the antifuse storage cell AF, causing the two terminals to short-circuit due to dielectric breakdown between the terminals. In such embodiments, the antifuse storage cell AF has a dielectric layer 116 disposed between the two terminals. Dielectric breakdown during the programming operation occurs in the dielectric layer 116. In some embodiments, the doped region 112 can function as one of the terminals of the antifuse storage cell AF. In these embodiments, the dielectric layer 116 is disposed on the doped region 112. In some embodiments, a material of the dielectric layer 116 can be the same as that of the gate dielectric layer 106. Alternatively, the dielectric layer 116 and the gate dielectric layer 106 can be made of different materials. Furthermore, in some embodiments, the thickness of the dielectric layer 116 can be greater than the thickness of the gate dielectric layer 106. In other embodiments, the thickness of the dielectric layer 116 can be equal to or less than the thickness of the gate dielectric layer 106. Furthermore, the other terminal of the anti-fuse storage unit AF can be an electrode 118, which is vertically placed on the dielectric layer 116. In some embodiments, Figure 1A As shown, electrode 118 is formed in a linear shape, and an extension direction of linear electrode 118 can be substantially aligned with an extension direction of linear active area AA. In these embodiments, dielectric layer 116 interposed between electrode 118 and doped region 112 can also have a linear shape, and a sidewall of dielectric layer 116 can be substantially coplanar with a sidewall of electrode 118. Electrode 118 is made of a conductive material. For example, this conductive material can include tungsten, copper, the like, or a combination thereof.

[0095] In some embodiments, a plurality of isolation layers 120 and 122 are stacked on the substrate 100. The gate dielectric layer 106, the gate structure 108, and the gate spacer GS of the access transistor T are formed in the isolation layer 120 and are laterally surrounded by the isolation layer 120. In some embodiments, an upper surface of the isolation layer 120 is substantially aligned with the uppermost end of the gate spacer GS and is slightly higher than an upper surface of the uppermost contact layer CL. In addition, a lower portion of the dielectric layer 116 and the electrode 118 of the anti-fuse storage cell AF are also formed in the isolation layer 120 and are laterally surrounded by the isolation layer 120. On the other hand, the isolation layer 122 is disposed on the isolation layer 120. In this manner, the upper surface of the uppermost contact layer CL of the access transistor T is covered by the isolation layer 122, and the contact plug 114 placed vertically on the uppermost contact layer CL is laterally surrounded by the isolation layer 122. Similarly, the upper portion of the electrode 118 of the anti-fuse storage cell AF is laterally surrounded by the isolation layer 122. Isolation layers 120 and 122 are each made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the isolation materials used to form isolation layers 120 and 122 may be different from each other. In other embodiments, isolation layers 120 and 122 may be made of the same isolation material.

[0096] As described above, the active region AA of the access transistor T in the memory device 10 is formed in a linear shape and intersects a linear portion of the gate structure 108, located in a region away from the two ends E1 and E2 of the active region AA. During manufacturing, the ends E1 and E2 of the active region AA are particularly susceptible to photolithography and / or etching inaccuracies, and the size and / or shape of each end E1 and E2 may deviate from the original layout design. Furthermore, if an active region of a transistor overlaps with a gate structure at one end of the transistor, it becomes difficult to control a gate coupling region and the threshold voltage of the transistor. In contrast, because the various embodiments of the present disclosure avoid using either end E1 or E2 of the active region AA as a gate coupling region for the access transistor T, the aforementioned problems are effectively avoided. Therefore, the gate coupling region and the threshold voltage of the access transistor T according to the various embodiments of the present disclosure can be better controlled.

[0097] Figure 2 Example Figure 1A and Figure 1B FIG. 1 is a flow chart of a method for manufacturing a memory element 10 . Figures 3A to 3O For example Figure 2 The schematic cross-sectional views of the various structures at different stages are shown. Figures 3A to 3O The cross-sectional view shown is along Figure 1A Cut along the section line AA' depicted in FIG.

[0098] Please refer to Figure 2 and Figure 3A , step S11 is performed, and a recess RS is formed on a surface of the substrate 100. The recess RS defines a position of the insulating structure 102 to be formed next. In other words, the recess RS will accommodate the insulating structure 102 to be formed in the next step. Figure 1A As described above, the active region AA is laterally surrounded by the insulating structure 102. Therefore, the portion of the substrate 100 laterally surrounded by the recess RS defines a location of the active region AA to be formed subsequently. In some embodiments, a method for forming the recess RS may include a photolithography process and an etching process (e.g., an anisotropic etching process).

[0099] Please refer to Figure 2 and Figure 3B , step S13 is performed, and an isolation material is filled into the recess RS to form the insulating structure 102. The isolation material can be filled by a deposition process, such as a chemical vapor deposition (CVD) process. In some embodiments, the isolation material filling the recess RS may initially extend over the upper surface of the substrate 100, and a planarization process may be performed to remove portions of the isolation material located on the upper surface of the substrate 100. For example, the planarization process may include a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof.

[0100] Please refer to Figure 2 and Figure 3C , step S15 is performed to form the active area AA. In some embodiments, a method for forming the active area AA includes performing an ion implantation process on the portion of the substrate 100 laterally surrounded by the insulating layer 102. In these embodiments, during the ion implantation process, the insulating structure 102 can function as a mask, and the formation of the active area AA can be considered a self-aligned process.

[0101] Please refer to Figure 2 and Figure 3D , step S17 is performed, and the channel region 104 is formed in the active region AA. In some embodiments, a method for forming the channel region 104 includes forming a mask pattern (not shown) on the substrate 100. The mask pattern has an opening for defining a position of the channel region 104. After the mask pattern is formed, an ion implantation process is performed to form the channel region 104. The mask pattern is used to define a doping region (e.g., a span of the channel region 104) for this ion implantation process. After the channel region 104 is formed, the mask pattern can be removed. In some embodiments, the mask pattern is a photoresist pattern. In other embodiments, the mask pattern is a hard mask pattern and can be made of the following materials: silicon oxide, silicon nitride, the like, or a combination thereof.

[0102] Please refer to Figure 2 and Figure 3E , step S19 is performed, and a dielectric material 106', a gate electrode layer GE', and at least one contact material layer CL' (e.g., two contact material layers CL') are formed on the substrate 100. In some embodiments, the dielectric material layer 106' is selectively formed on the active area AA, while the gate electrode layer GE' and the contact material layer CL' are formed entirely on the substrate 100. In such an embodiment, a method for forming the gate dielectric material layer 106' may include an oxidation process, while the method for forming the gate electrode layer GE' and the contact material layer CL' may each include a deposition process (e.g., a CVD process). In other embodiments, the dielectric material layer 106' entirely covers the substrate 100 and can be formed by a deposition process (e.g., a CVD process).

[0103] Please refer to Figure 2 and Figure 3F Step S21 is then performed to pattern the dielectric material layer 106', the gate electrode layer GE', and the contact material layer CL' to form the gate dielectric layer 106, the gate electrode GE, and the contact layer CL, respectively. The gate dielectric layer 106 and a portion of the gate structure 108 (including the gate electrode GE and the contact layer CL) overlap the channel region 104. In some embodiments, a method for patterning these layers includes a photolithography process and one or more etching processes.

[0104] Please refer to Figure 2 and Figure 3G , step S23 is performed, and a gap sublayer GS' is formed on the current structure. The gap sublayer GS' may entirely cover the exposed surfaces of the insulating structure 102, the active area AA, the channel region 104, the gate dielectric layer 106, and the gate structure 108. In some embodiments, a method for forming the gap sublayer GS' includes a deposition process, such as a CVD process.

[0105] Please refer to Figure 2 and Figure 3H , step S25 is performed, and the spacer sublayer GS' is partially removed to form the gate spacer GS. In some embodiments, a method for forming the gate spacer GS includes performing an anisotropic etching process. During the anisotropic etching process, the horizontally extending portions of the spacer sublayer GS' are removed while the vertically extending portions of the spacer sublayer GS' are formed to form the gate spacer GS. Furthermore, in some embodiments, a surface portion of the topmost contact layer CL may be consumed during the anisotropic etching process. As a result, an upper surface of the topmost contact layer CL may be slightly lower than the uppermost end of the gate spacer GS.

[0106] Please refer to Figure 2 and Figure 3I, step S27 is performed, and doped regions 110 and 112 are formed in the active area AA. One method for forming the doped regions 110 and 112 may include an ion implantation process. During this ion implantation process, the gate structure 108, the gate spacer GS, and the insulating structure 102 function as masks, so that the formation of the doped regions 110 and 112 can be a self-aligned process. The portions of the active area AA not covered by the gate structure 108 and the gate spacer GS can be subjected to the ion implantation process, while the portions of the active area AA covered by the gate structure 108 and the gate spacer GS are not subjected to the ion implantation process. Furthermore, a heat treatment may be performed so that the dopants introduced into the exposed portions of the active area AA can diffuse into an area covered by the gate spacer GS.

[0107] Please refer to Figure 2 and Figure 3J , step S29 is performed, and an isolation layer 120 is formed on the substrate 100. In some embodiments, a method for forming the isolation layer 120 includes a deposition process, such as a CVD process. The isolation layer 120 may initially cover an upper surface of the gate structure 108, and then a planarization process may be performed to remove portions of the isolation layer 120 located on the gate structure 108. The gate structure 108 and the gate spacer GS are laterally surrounded by the uniformly formed isolation layer 120. For example, the planarization process may include a CMP process, an etching process, or a combination thereof. In some embodiments, during the planarization process, a surface portion of the uppermost contact layer CL may be consumed. Therefore, an upper surface of the uppermost contact layer CL may be slightly lower than the uppermost end of the gate spacer GS.

[0108] Please refer to Figure 2 and Figure 3K , step S31 is performed, and isolation layer 122 is formed on isolation layer 120. In some embodiments, a method for forming isolation layer 120 includes a deposition process, such as a CVD process. In addition, a planarization process may be performed on isolation layer 120. For example, the planarization process may include a CMP process, an etching process, or a combination thereof.

[0109] Please refer to Figure 2 and Figure 3L , step S33 is performed, and an opening W1 is formed in the stack of isolation layers 120 and 122. Opening W1 is filled with dielectric layer 116 and electrode 118 of antifuse storage cell AF in a subsequent step. A method for forming opening W1 may include a photolithography process and one or more etching processes.

[0110] Please refer to Figure 2 and Figure 3M, step S35 is performed, and a dielectric layer 116 is formed in the opening W1. In some embodiments, the dielectric layer 116 selectively covers a portion of the doped region 112 exposed by the opening W1. In these embodiments, a method for forming the dielectric layer 116 may include an oxidation process, and the formation of the dielectric layer 116 may be considered a self-aligned process.

[0111] Please refer to Figure 2 and Figure 3N , step S37 is performed, and an opening W2 is formed in the isolation layer 122. Providing the opening W2 defines a location for the contact plug 114 to be formed subsequently. The opening W2 penetrates the isolation layer 122 and exposes a portion of the gate structure 108. For example, an upper surface of the uppermost contact layer CL of the gate structure 108 is exposed through the opening W2. In some embodiments, a method for forming the opening W2 includes a photolithography process and an etching process.

[0112] Please refer to Figure 2 and Figure 3O Step S39 is then executed, and a conductive material CM is formed on the current structure. The conductive material CM will be patterned to form the electrode 118 and the contact plug 114 in the following steps. The conductive material now fills the openings W1 and W2 and covers an upper surface of the isolation layer 122. In some embodiments, a method for forming the conductive material CM includes a deposition process (e.g., a physical vapor deposition (PVD) process), a plating process, or a combination thereof.

[0113] Please refer to Figure 2 and Figure 1B , step S41 is performed, and portions of the conductive material CM located on the upper surface of the isolation layer 122 are removed. On the other hand, portions of the conductive material CM remain in the openings W1 and W2, forming the electrode 118 and the contact plug 114. In some embodiments, a planarization process is used to form the electrode 118 and the contact plug 114. For example, the planarization process includes a CMP process, an etching process, or a combination thereof.

[0114] At this point, the fabrication method for forming the memory device 10 is complete. The memory device 10 may also undergo other processing steps for forming additional devices, for example, a plurality of additional devices such as a word line, a bit line, and a source line.

[0115] Figure 4 Schematic cross-sectional view of a memory element 10a illustrating some embodiments of the present disclosure. Figure 1B and Figure 4 ,like Figure 4 The memory element 10a shown is similar to Figure 1B The memory element 10 shown, except for the Figure 4 In the memory device 10a shown, a dielectric layer 116' of an antifuse storage cell AF' also covers the sidewalls of the isolation layers 120 and 122. In some embodiments, the dielectric layer 116' is conformally formed on the surface of the antifuse storage cell AF'. Figure 3M In the opening W1 shown, the electrode 118 is then filled into the recess defined by the dielectric layer 116'. Thus, a lower surface and a sidewall of the electrode 118 are covered by the dielectric layer 116'. In these embodiments, the dielectric layer 116' is formed by a deposition process, such as a CVD process.

[0116] Figure 5 Schematic diagram of a memory element 10b illustrating some embodiments of the present disclosure. Figure 5 The memory element 10b shown is similar to Figure 1A The memory element 10 shown in FIG. will only be described with respect to the differences therebetween, and similar or identical parts will not be repeated. Figure 5 In some embodiments, the gate structure 108' is formed as an open ring rather than a closed ring. For example, Figure 5 As shown, a top-view shape of the gate structure 108 ′ may resemble a rotated C. The region overlapping the end E1 of the active region AA is not completely surrounded by the gate structure 108 ′.

[0117] As described above, some embodiments of the present disclosure include a programmable memory device comprising a memory cell in an anti-fuse OTP memory array, and having an access transistor and an anti-fuse storage unit, wherein the anti-fuse access unit is connected to one of the source terminal and the drain terminal of the access transistor. The access transistor has an active region formed in a substrate, and the access transistor has a gate structure formed on the substrate. The active region has a linear top view shape, and the gate structure has a linear portion that intersects with a section of the active region. Such a section of the active region is located away from both ends of the active region and is particularly susceptible to inaccuracies in photolithography and / or etching. Therefore, an overlap area between the gate structure and the active region can be better controlled, so that the gate coupling area and a threshold voltage of the access transistor are less affected by inaccuracies in the manufacturing process of the memory device.

[0118] One embodiment of the present disclosure provides a programmable memory device comprising an active region formed in a substrate and having a linear top-view shape; a gate structure disposed on the substrate and having a linear portion intersecting a section of the active region remote from both ends of the active region; and an anti-fuse storage cell using a portion of the active region as a terminal and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and remote from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.

[0119] Another embodiment of the present disclosure provides a programmable memory device having an access transistor including an active region and a gate structure, the active region being formed in a substrate and the gate structure being formed on the substrate, wherein the active region has a linear top-view shape, the gate structure having a first portion and a second portion, the first portion intersecting a section of the active region distal from each end of the active region, and the second portion being laterally distal from the active region; and a capacitor using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and distal from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.

[0120] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0121] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will appreciate from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of the present invention.

Claims

1. A programmable memory device comprising: an active region formed in a substrate and having a linear top-view shape; a gate structure disposed on the substrate and having a linear portion intersecting a section of the active region away from two ends of the active region; and An antifuse memory cell uses a portion of the active region as a terminal and further includes an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and away from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode; A contact plug is disposed on the gate structure and electrically connected to the gate structure. The contact plug is disposed away from the active region and has a linear top view shape, an extension direction of which intersects an extension direction of the linear active region.

2. The programmable memory device as claimed in claim 1, wherein the gate structure is formed in a ring shape. 3 . The programmable memory device as claimed in claim 2 , wherein one of the end portions of the active region overlaps with a region laterally surrounded by the gate structure.

4. The programmable memory element as described in claim 1, wherein the two ends of the active region are a first end and a second end, the gate structure is closer to the first end of the active region than to the second end of the active region, and the anti-fuse storage unit is closer to the second end of the active region than to the first end of the active region. 5 . The programmable memory device as claimed in claim 1 , further comprising an insulating structure formed in the substrate and laterally surrounding the active region. 6 . The programmable memory device as claimed in claim 5 , wherein the gate structure overlaps with both the isolation structure and the section of the active region. 7 . The programmable memory device of claim 6 , further comprising a gate dielectric layer selectively disposed between the gate structure and the segment of the active region. 8 . The programmable memory device as claimed in claim 7 , wherein a thickness of the gate dielectric layer is different from a thickness of the dielectric layer of the anti-fuse storage cell.

9. The programmable memory device as claimed in claim 1, further comprising a gate spacer covering a sidewall of the gate structure. 10 . The programmable memory device as claimed in claim 1 , wherein an upper surface of the contact plug and an upper surface of the electrode of the anti-fuse storage unit are coplanar.

11. A programmable memory device comprising: an access transistor comprising an active region and a gate structure, the active region being formed in a substrate, the gate structure being formed on the substrate, wherein the active region has a linear top-view shape, the gate structure having a first portion and a second portion, the first portion intersecting a section of the active region away from each end of the active region, and the second portion being laterally disposed away from the active region; and a capacitor using a portion of the active region as a terminal and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and away from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region; A contact plug is disposed on the gate structure and electrically connected to the gate structure. The contact plug is disposed away from the active region and has a linear top view shape, an extension direction of which intersects an extension direction of the linear active region.

12. The programmable memory device of claim 11, wherein the first and second portions of the gate structure are connected to each other. 13 . The programmable memory device as claimed in claim 11 , wherein one of the ends of the active region is located between the first and second portions of the gate structure.

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