Three-dimensional semiconductor device and method of manufacturing the same

Abstract

A three-dimensional semiconductor device includes: a conductive layer on a substrate and including an impurity of a first conductivity type; a base layer on the conductive layer; a stack including a lower insulating film and a gate electrode and a molded insulating layer on the lower insulating film, wherein the base layer includes a high dielectric material; a vertical structure including a vertical channel layer through the stack structure and a vertical insulating layer provided between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extension region extending in a width direction in the insulating base layer; and an isolation structure through the stack structure, the insulating base layer, and the conductive layer and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extension region of the vertical structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0102564, filed on August 21, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a three-dimensional semiconductor device and a method for manufacturing the same. Background Technology

[0004] Electronic products are becoming increasingly smaller and require higher data throughput. In other words, as the size of electronic products decreases, their data throughput requirements also increase. Therefore, the semiconductor devices used in such electronic products need to have high integration. To improve the integration of semiconductor devices, three-dimensional semiconductor devices with three-dimensional (e.g., vertical) transistor structures can be used instead of planar transistor structures. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a three-dimensional semiconductor device includes: a conductive layer disposed on a substrate and including impurities of a first conductivity type; an insulating substrate layer disposed on the conductive layer; a stacked structure including a lower insulating film disposed on the insulating substrate layer and a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the lower insulating film, wherein the insulating substrate layer includes a high dielectric material; a vertical structure including a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extension region extending in the width direction in the insulating substrate layer; and an isolation structure passing through the stacked structure, the insulating substrate layer and the conductive layer, and extending in a direction parallel to the upper surface of the substrate, wherein the conductive layer has an extension portion extending along the surface of the vertical channel layer in the extension region of the vertical structure.

[0006] According to an exemplary embodiment of the present invention, a three-dimensional semiconductor device includes: a conductive layer disposed on a substrate; an insulating substrate layer disposed on the conductive layer and having a plurality of support regions in contact with the substrate; a stacked structure having a plurality of gate electrodes and a plurality of molded insulating layers alternately disposed on the insulating substrate layer; a vertical structure including a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having a first extension region extending in the insulating substrate layer in a width direction and having a convex surface; and an isolation structure passing through the stacked structure, the insulating substrate layer and the conductive layer, extending in a first direction parallel to the upper surface of the substrate, and having a second extension region in the insulating substrate layer extending in a second direction intersecting the first direction and parallel to the upper surface of the substrate, wherein the conductive layer has an extension portion extending along the surface of the vertical channel layer, and the upper end of the extension portion is connected in the first extension region of the vertical structure to the lower end of the vertical insulating layer on the surface of the vertical channel layer.

[0007] According to an exemplary embodiment of the present invention, a three-dimensional semiconductor device includes: a conductive layer disposed on a substrate and including impurities of a first conductivity type; an insulating layer disposed on the conductive layer; a stacked structure including a lower insulating film disposed on the insulating layer and a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the lower insulating film, wherein the insulating layer includes a high dielectric material; a vertical structure including a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having a first region in the insulating layer, wherein one side of the first region in the insulating layer is stacked with the lowest gate electrode of the gate electrodes in a direction perpendicular to the upper surface of the substrate; and a conductive film extending from the conductive layer and covering at least a portion of the vertical channel layer in the first region, wherein the conductive film includes impurities of the first conductivity type. Attached Figure Description

[0008] The above and other features of the inventive concept will be more clearly understood by describing in detail, in conjunction with the accompanying drawings, exemplary embodiments of the inventive concept:

[0009] Figure 1 This is an equivalent circuit diagram of a memory cell array of a three-dimensional (3D) semiconductor device according to an exemplary embodiment of the present invention;

[0010] Figure 2 This is a schematic plan view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to a concept of the present invention;

[0011] Figure 3 It is intercepted along line I-I' Figure 2 A cross-sectional view of the 3D semiconductor device shown;

[0012] Figure 4 yes Figure 3 An enlarged cross-sectional view of region "A" in the 3D semiconductor device shown;

[0013] Figure 5 A three-dimensional semiconductor device according to an exemplary embodiment of the present invention and Figure 3 A magnified view of the area corresponding to region "A";

[0014] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This is a cross-sectional view illustrating the process of a method for manufacturing a 3D semiconductor device according to various exemplary embodiments of the present invention;

[0015] Figure 14A , Figure 14B and Figure 14C They are Figure 7 , Figure 8 and Figure 11 A magnified view of a portion of the image;

[0016] Figure 15 This is a schematic plan view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to a concept of the present invention;

[0017] Figure 16 It is shown Figure 15 An enlarged cross-sectional view of region "B" in the 3D semiconductor device shown; and

[0018] Figure 17 A three-dimensional semiconductor device according to an exemplary embodiment of the present invention and Figure 15 A magnified view of the area corresponding to region "B". Detailed Implementation

[0019] In the following description, exemplary embodiments of the inventive concept will be illustrated with reference to the accompanying drawings. The same reference numerals in the drawings may refer to the same elements.

[0020] Figure 1 This is an equivalent circuit diagram of a memory cell array of a three-dimensional (3D) semiconductor device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic plan view illustrating a memory cell array CA of a 3D semiconductor device 100 according to an exemplary embodiment of the present invention. In this case, it can be like... Figure 2 The memory cell array CA is implemented in the same way. Figure 1 The equivalent circuit.

[0021] Reference Figure 1 The memory cell array CA may include a common source line CSL, multiple bit lines BL, multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL, and multiple ground select lines GSL.

[0022] The common source line (CSL) can be a conductive thin film disposed on the substrate 101 or an impurity region formed in the substrate 101 (e.g., Figure 3 The conductive layer 180). Bit lines BL can be arranged in two dimensions, and multiple cell strings CSTR can be connected in parallel to each of the bit lines BL. The cell strings CSTR can be connected together to the common source line CSL. Multiple cell strings CSTR can be disposed between multiple bit lines BL and the common source line CSL. In an exemplary embodiment of the present invention, the common source line CSL can be configured as multiple common source lines, and the multiple common source lines can be arranged in two dimensions. In this case, the same voltage can be applied to the common source lines CSL, or the common source lines CSL can be electrically controlled separately.

[0023] The memory cell array in this embodiment includes a GIDL transistor (GDT) for performing an erase operation on the memory cell array CA using a gate-induced drain leakage (GIDL) method. The GIDL transistor GDT may be located at the bottom of the memory cell array CA. For example, the GIDL transistor GDT may be located between the ground select line GSL and the common source line CSL, and may be referred to as a "bottom GIDL transistor". In an exemplary embodiment of the inventive concept, multiple bottom GIDL transistors may be provided (e.g., two). In an exemplary embodiment of the inventive concept, at least one or more "top GIDL transistors" may be further located between the string select line SSL and the bit line BL. The gate of the GIDL transistor GDT may be connected to a... Figure 1 The line indicated by GIDL in the text.

[0024] Each cell string (CSTR) includes a GIDL transistor (GDT) and a ground select transistor (GST) connected to the common-source line (CSL), a string select transistor (SST) connected to the bit line (BL), and multiple memory cell transistors (MCTs) positioned between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) can be connected in series. The common-source line (CSL) can be connected together to the source of the ground select transistor (GST).

[0025] The ground select line GSL, multiple word lines WL1 to WLn, and multiple string select lines SSL located between the common source line CSL and the bit line BL can be used as the gate electrodes of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. Each of the memory cell transistors MCT can include a data storage element.

[0026] like Figure 2 As shown, the ground select line GSL, word lines WL1 to WLn, and string select line SSL can be sequentially formed above the substrate 101, and an insulating layer 122 is molded (see Figure 101). Figure 3 The gate electrode 130 can be disposed below and / or on each of the gate electrodes 130. The area of ​​the gate electrode 130 can decrease as its distance from the substrate 101 increases. In other words, the area of ​​the uppermost gate electrode 130 can be smaller than the area of ​​the lowermost gate electrode 130. Bit line ( Figure 3 The BL in the diagram can be a conductive pattern, such as a metal line spaced apart from and disposed above the substrate 101.

[0027] exist Figure 2 In this embodiment, the memory cell array CA can be divided by an isolation structure IA. The string select line SSL of the gate electrode 130 can be divided by a select line cut region SLC. In an exemplary embodiment of the present invention, the isolation structure IA can be disposed in a structure in which the gaps are filled with one or more insulating materials. For example, the insulating material may include silicon oxide, silicon nitride, or silicon oxynitride.

[0028] The memory cell array CA may include a gate electrode 130 and a molded insulating layer 122 extending in the third direction Z (see...). Figure 3 Multiple vertical structures CS are provided. These vertical structures CS can be spaced apart from each other at predetermined intervals between the isolation structures IA. Support regions 110S can be arranged at regular intervals within the isolation structures IA. The support regions 110S are insulating substrate layers 110 (see...). Figure 3 ) contacts the substrate 101 to support the formation of the conductive layer ( Figure 3 180 (which will refer to) Figure 3 (To be described in more detail) the area of ​​space.

[0029] Figure 3 It is along Figure 2 A cross-sectional view of a 3D semiconductor device taken by line I-I'.

[0030] Reference Figure 3 The semiconductor device 100 includes a substrate 101 and a stacked structure LS having a molded insulating layer 122 and a plurality of gate electrodes 130 alternately stacked on the substrate 101.

[0031] For example, substrate 101 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In this exemplary embodiment, the plurality of gate electrodes 130 may include a lowermost gate electrode 131, a second lowermost gate electrode 132, an uppermost gate electrode 136, and unit gate electrodes 135-1, 135-2, 135-3, ..., and 135-n stacked between the lowermost gate electrode 131 and the uppermost gate electrode 136. The lowermost gate electrode 131 is an element associated with a GIDL transistor GDT, and the second lowermost gate electrode 132 and the uppermost gate electrode 136 may be elements associated with a ground select transistor GST and a string select transistor SST, respectively. The unit gate electrodes 135-1, 135-2, 135-3, ..., and 135-n may be elements associated with a plurality of memory cell transistors MCT (see...). Figure 1 and Figure 2 The number of unit gate electrodes 135-1, 135-2, 135-3, ... and 135-n can be determined according to the required capacitance of the semiconductor device 100, for example, it can be 30 or more.

[0032] The lowest gate electrode 131 may include multiple other gate electrodes, for example, it may include two gate electrodes.

[0033] In a plan view, the stacked structure LS can have a shape extending in a first direction X and a second direction Y intersecting the first direction X. A plurality of gate electrodes 130 can be sequentially stacked in a third direction Z intersecting both the first direction X and the second direction Y. The first direction X and the second direction Y can be substantially parallel to the upper surface of the substrate 101, and the third direction Z can be substantially perpendicular to the upper surface of the substrate 101. The plurality of gate electrodes 130 can be spaced apart from each other by a molded insulating layer 122.

[0034] For example, the molded insulating layer 122 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film. For example, the plurality of gate electrodes 130 may include metals and / or conductive metal nitrides, such as polysilicon (poly-Si) or tungsten (W).

[0035] The stacked structure LS may further include a lower insulating film 111 disposed on the lower surface facing the substrate 101. The lower insulating film 111 may include, for example, a silicon oxide film, a silicon nitride film, a high-dielectric film (e.g., an aluminum oxide film, a hafnium oxide film, etc.) or a combination thereof. The thickness of the lower insulating film 111 may be less than the thickness of the molded insulating layer 122. In other words, the lower insulating film 111 may be thinner than the molded insulating layer 122.

[0036] The stacked structure LS includes a channel hole CH formed in a third direction Z perpendicular to the upper surface of the substrate 101. A vertical structure CS is disposed in the channel hole CH. The vertical structure CS may include a vertical channel layer 150 passing through the stacked structure LS and a vertical insulating layer 171 disposed between the vertical channel layer 150 and a plurality of gate electrodes 130. The vertical structure CS may also include an insulating core 160 disposed in the vertical channel layer 150 in a third direction (e.g., the Z direction). The vertical insulating layer 171 may have a tubular shape or a macaroni shape with openings at the top and bottom ends.

[0037] The vertical structure CS can be electrically connected to the conductive layer 180 while passing through the stacked structure LS. Multiple vertical structures CS can be configured in the stacked structure LS, and in a plan view, multiple vertical structures CS can be arranged in a first direction and a second direction (e.g., the X and Y directions). Figure 2 As shown, multiple vertical structures CS can be arranged in a zigzag pattern. For example, in Figure 2 In this case, the vertical structure CS extending in the X direction can be arranged in a zigzag pattern.

[0038] The vertical insulating layer 171 may include memory elements of a flash memory device. For example, the vertical insulating layer 171 may include a charge storage film 171b of the flash memory device. Data stored in the vertical insulating layer 171 can be altered using Fowler-Nordheim tunneling caused by the voltage difference between the vertical channel layer 150 and the gate electrode 130. Alternatively, the vertical insulating layer 171 may also include a thin film capable of storing information based on other operating principles, such as a thin film for phase-change memory or a thin film for variable resistance memory.

[0039] The vertical insulating layer 171 may further include a tunneling insulating film 171c between the charge storage film 171b and the vertical channel layer 150. The tunneling insulating film 171c may directly contact the vertical channel layer 150. In an exemplary embodiment of the present invention, the vertical insulating layer 171 may further include a barrier insulating film 171a interposed between the charge storage film 171b and the gate electrode 130. For example, the charge storage film 171b may include a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, or nanocrystalline silicon or a stacked trapping layer. The tunneling insulating film 171c may include a material with a band gap larger than that of the charge storage film 171b. For example, the tunneling insulating film 171c may be a silicon oxide layer. The barrier insulating film 171a may include a material with a band gap larger than that of the charge storage film 171b. For example, the barrier insulating film 171a may be a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0040] In this embodiment, the vertical structure CS is shown to have substantially the same width in the vertical direction (Z direction), but the vertical structure CS (or channel hole CH) may have a shape in which its width narrows toward the substrate 101.

[0041] Reference Figure 3 The planar insulating layers 172 can be respectively disposed on the upper and lower surfaces of the gate electrode 130. Each of the planar insulating layers 172 can extend between each of the gate electrodes 130 and the vertical insulating layer 171. The planar insulating layer 172 can be composed of one or more thin films. In an exemplary embodiment of the present invention, the planar insulating layer 172 may include a barrier insulating film for charge trapping flash memory transistors.

[0042] A wiring (bit line 195) can be disposed on the stacked structure LS to traverse the upper surface of the stacked structure LS. The bit line 195 can be connected to the pad PD disposed on the top of the vertical structure CS via a contact via 193. An interlayer insulating layer 191 can be inserted between the bit line 195 and the stacked structure LS, and the contact via 193 can pass through the interlayer insulating layer 191. The interlayer insulating layer 191 may include a first insulating film 191a disposed on the stacked structure LS to cover the pad PD of the vertical structure CS, and a second insulating film 191b disposed on the first insulating film 191a to cover the isolation structure IA.

[0043] The semiconductor device 100 according to this embodiment includes a conductive layer 180 forming a common source line disposed between a substrate 101 and a stacked structure LS. An insulating substrate layer 110 may be disposed on the conductive layer 180 to cover the conductive layer 180. The insulating substrate layer 110 (in this case, the insulating substrate layer 110 may also be referred to as an etch stop layer) may have a support region 110S in contact with a portion of the substrate 101. The support region 110S is supported on the substrate where the conductive layer 180 (see [reference]) is formed. Figure 11 The components of the space previously created by removing the lower sacrificial layer. For example... Figure 2 As shown, the support regions 110S can be arranged at regular intervals in the region where the isolation structure IA is to be formed.

[0044] The conductive layer 180 may include a conductive material doped with impurities of a first conductivity type. For example, the conductive layer 180 may include polysilicon (poly-Si) doped with n-type impurities. The insulating substrate layer 110 may serve as an etch stop layer and may include a high-dielectric material that has etch selectivity relative to the material of the stacked structure LS (e.g., molded insulating layer 122). The insulating substrate layer 110 used in this embodiment may include a high-dielectric material. For example, the insulating substrate layer 110 may include alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) or praseodymium oxide (Pr2O3). For example, the insulating substrate layer 110 may include Al2O3 or HfO2.

[0045] Because the insulating substrate layer 110 used in this embodiment is formed from a high-dielectric film with relatively high etch selectivity, the location of the initial via (e.g., inside the insulating substrate layer 110) in the channel via (CH) formation process can be relatively precise. Unlike conventional conductive etch stop layers (e.g., polysilicon layers), the electrically insulating insulating substrate layer 110 can alleviate the electrical stress on adjacent transistors (e.g., GIDL transistors).

[0046] In this embodiment, the vertical structure CS has an end extending into the insulating substrate layer 110, and this end of the vertical structure CS has a first extension region EA extending in the width direction within the insulating substrate layer 110. For example, the first extension region EA may extend in the Y direction. Additionally, the first extension region EA may have a bottle shape with a convex surface. The first extension region EA may extend in the width direction after etching to the insulating substrate layer 110, which serves as an etch stop layer, followed by isotropic etching (e.g., wet etching), to form a lower sacrificial layer 105 (see...). Figure 7 Obtained through exposure processing.

[0047] The first extension region EA of the vertical structure CS can be connected to the conductive layer 180. The vertical structure CS may include a conductive film 185 extending from the bottom of the contact conductive layer 180 of the vertical structure CS along the surface of the vertical channel layer 150 in the first extension region EA. For example, the side of the first extension region EA may be covered by the conductive film 185. Figure 4 It is shown Figure 3 The image shows a magnified cross-sectional view of the magnified region "A" of the semiconductor device shown.

[0048] Reference Figure 4 The first extended region EA may include a protruding end portion of the insulating core 160 in the width direction and a portion of the vertical channel layer 150 disposed along the surface of the protruding end portion. The conductive film 185 may be disposed on the surface of the portion of the vertical channel layer 150 disposed at the bottom of the first extended region EA to contact the conductive layer 180.

[0049] The conductive film 185 may be an element extending from the conductive layer 180 and may comprise the same conductive material as the conductive material of the conductive layer 180. The conductive film 185 is also referred to as an "extension portion of the conductive layer 180". The extension portion extends along the surface of the vertical channel layer 150 in a first extension region EA of the vertical structure CS. The conductive film 185 may be a conductive material doped with a high concentration of a first conductivity type impurity IP (e.g., an n-type impurity) (indicated by +) in the same or similar manner as the conductive layer 180. The first conductivity type impurity IP can diffuse from the conductive film 185 to the portion of the vertical channel layer 150 adjacent to the conductive film 185. For example, the conductive layer 180 and the conductive film 185 may comprise polycrystalline silicon doped with an n-type impurity. In an exemplary embodiment of the inventive concept, the vertical channel layer 150 may also comprise polycrystalline silicon as the same material as the conductive layer 180 and the conductive film 185. Additional heat treatment processes may be performed to effectively induce this impurity diffusion.

[0050] In this embodiment, the portion of the vertical channel layer 150 adjacent to the conductive film 185 may have a region (indicated by +) in which impurities of a first conductivity type diffuse. The portion of the vertical channel layer 150 adjacent to the conductive film 185 may include the portion of the vertical channel layer 150 adjacent to the lowermost gate electrode 131. For example, impurities of a first conductivity type in the conductive film 185 may diffuse into the portion of the vertical channel layer 150 adjacent to the lowermost gate electrode 131. For example, the portion of the vertical channel layer 150 adjacent to the lowermost gate electrode 131 has a region (indicated by +) in which impurities of a first conductivity type diffuse.

[0051] As a result, even when the portion of the channel region used to form the GIDL transistor is located at the lower end of the memory cell array CA, this portion can still be doped with impurities of a first conductivity type (e.g., n-type). For example, the impurity concentration in the channel region of the GIDL transistor can be 2 to 10 counts / cm² based on X-ray fluorescence (XRF). 3 Within the range.

[0052] Thus, the conductive material doped with a high concentration of impurities (IP) constituting the conductive layer 180 (which constitutes the common source electrode line CSL) can extend to the first extension region EA in contact with the conductive layer 180 by forming a conductive film 185. By utilizing the conductive film 185, the impurities IP can be effectively diffused to the portion of the vertical channel layer 150 adjacent to the conductive film 185.

[0053] like Figure 4 As shown, the conductive film 185 can extend to the upper half of the first extension region EA. For example, the conductive film 185 can extend close to the upper portion of the insulating substrate layer 110. The conductive film 185, which serves as an impurity source, can be positioned closer to the channel region of the GIDL transistor, for example, the portion of the vertical channel layer 150 adjacent to the lowermost gate electrode 131.

[0054] The conductive film 185 can be formed during the process of forming the conductive layer 180. For example, during the process of removing the lower sacrificial layer filling the space for the conductive layer 180, the portion of the vertical insulating layer 171 disposed in the first extension region EA is removed. In this case, the conductive film 185 can also be formed in the space in which the portion of the vertical insulating layer 171 has been removed while the conductive material for the conductive layer 180 is being filled. As a result, as Figure 4 As shown, the upper end of the conductive film 185 can be connected to the lower end of the remaining vertical insulating layer 171.

[0055] The width W of the first extended region EA disposed in the insulating substrate layer 110 can be greater than the width of the adjacent vertical structure CS. The width W of the first extended region EA can be determined by the etching position of the channel hole CH (before the etching process for extension), the thickness t of the insulating substrate layer 110 as an etch stop layer, etc. The deviation of the thickness t of the insulating substrate layer 110 and the maximum width W of the first extended region EA can both be within ±30%. For example, the thickness t of the insulating substrate layer 110 can be in the range of 30 nm to 50 nm, and the maximum width W of the first extended region EA can be in the range of 30 nm to 60 nm.

[0056] Semiconductor device 100 may include an isolation structure IA passing through the stacked structure LS, the insulating substrate layer 110, and the conductive layer 180. The isolation structure IA may be formed as a portion passing through the substrate 101. Figure 2 As shown, the isolation structure IA can extend in a direction parallel to the upper surface of the substrate 101. The isolation structure IA can have a second extension region ER extending in the width direction within the insulating substrate layer 110.

[0057] Similar to the first extended region EA, the substrate 101 can be exposed by applying isotropic etching after etching to the insulating substrate layer 110, while simultaneously extending the width direction (e.g., Figure 3 The second extended region ER is obtained through a process extending in the Y direction (as shown in the image). The isolation structure IA can be formed by filling with insulating material 175. Since the horizontal height of the insulating substrate layer 110 in the support region 110S is slightly lower than the horizontal height of the insulating substrate layer 110 in other regions, the horizontal heights of the second extended region ER of the isolation structure IA located in the support region 110S and in regions other than the support region 110S can be slightly different from each other. Furthermore, since the etch stop position can be formed at the initial hole (see...), Figure 9 The processing of the second extension regions ER differs from that of the support region 110S, therefore, the shapes of the second extension regions ER can be different from each other. For example, the second extension region ER in the support region 110S can be closer to the substrate 101 than the second extension region ER in the regions other than the support region 110S.

[0058] In this embodiment, the upper end of the conductive film 185 is disposed on the upper half of the first extended region EA, adjacent to the lowermost gate electrode 131. However, in another exemplary embodiment of the present invention, when the upper end of the conductive film 185 is located below the lower insulating film 111, the position of the upper end of the conductive film 185 can be determined based on the etching process of removing the lower sacrificial layer during the formation of the conductive layer 180 (see...). Figure 12 To make various changes.

[0059] Figure 5 This is a cross-sectional view illustrating another exemplary embodiment of a semiconductor device according to the present invention, and can be compared with a corresponding Figure 4 The enlarged cross-sectional view corresponds to region "A".

[0060] Reference Figure 5 Except that the upper end of the conductive film 185' is disposed in the lower half of the first extended region EA, the semiconductor device according to this embodiment and Figure 1 to Figure 3 The semiconductor device 100 shown is similar. Therefore, unless otherwise stated, the components of this embodiment can be compared with those of the referenced semiconductor device 100. Figure 1 to Figure 3 The semiconductor device 100 shown corresponds to the component described.

[0061] Similar to the previous embodiments, the vertical structure CS used in this embodiment can be connected to the conductive layer 180 via a conductive film 185' disposed in the first extension region EA. Since the conductive film 185' extends from the conductive layer 180, the conductive layer 180 and the conductive film 185' can be integrally formed using the same material.

[0062] The conductive film 185' of the vertical structure CS can be disposed in the portion of the first extended region EA that contacts the conductive layer 180, for example, in the bottom portion of the first extended region EA. Alternatively, the conductive film 185' can extend from the bottom portion of the first extended region EA. The upper end of the conductive film 185' can be disposed in the lower half of the first extended region EA. In this case, since the conductive film 185' contacts the portion of the vertical channel layer 150 disposed in the first extended region EA, impurities (IP) can diffuse through the contact portion to the portion of the vertical channel layer 150 adjacent to the lowermost gate electrode 131. Thus, as long as the upper end of the conductive film 185' does not contact the gate electrode 130 through the lower insulating film 111, the position of the upper end of the conductive film 185' can be determined by the etching process that removes the lower sacrificial layer during the formation of the conductive layer 180 (see...). Figure 12 To make various changes.

[0063] Based on such Figure 3 The memory cell array CA shown illustrates a semiconductor device 100 according to the foregoing example embodiment, but the semiconductor device 100 may have a structure in which peripheral circuitry is stacked, for example, perpendicular to the upper surface of the substrate 101 in the Z direction, such as a peripheral upper cell or peripheral upper cell (COP) structure.

[0064] Figure 6 to Figure 13 Is with Figure 3 The corresponding cross-sectional view illustrates the process of manufacturing a 3D semiconductor device according to an exemplary embodiment of the present invention. Figure 14A to Figure 14C They are Figure 7 , Figure 8 and Figure 12 A magnified view of a portion of the image.

[0065] Reference Figure 6 A lower sacrificial layer 105 and an etch stop layer 110 (referred to as an "insulating substrate layer") are formed on the substrate 101, and a molded stack structure (MLS) is formed on the etch stop layer 110. Then, a channel hole CH is formed in the molded structure MLS.

[0066] Substrate 101 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Lower sacrificial layer 105 may be a defined conductive layer (…). Figure 3The lower sacrificial layer 105 may include a material that has etch selectivity relative to the etch stop layer 110. For example, the lower sacrificial layer 105 may include silicon oxide, silicon oxynitride, or silicon nitride. In this embodiment, the lower sacrificial layer 105 may have a vertical insulating layer (see [reference]). Figure 3 The structure is similar to the three-layer structure in 171), and may include, for example, silicon oxide 105a / silicon nitride 105b / silicon oxide 105c.

[0067] An etch stop layer 110 is formed to cover the lower sacrificial layer 105. The etch stop layer 110 may be a high-dielectric layer with etch selectivity relative to the material of the molded stacked structure MLS. The etch stop layer 110 may include the high-dielectric layer shown above, and may include, for example, Al2O3 or HfO2. The etch stop layer 110 may include a support region 110S such that space is maintained even after the lower sacrificial layer 105 is removed. The support region 110S may be the region from which the lower sacrificial layer 105 is removed, and may be configured as the region of the etch stop layer 110 in direct contact with the underlying structure (e.g., substrate 101).

[0068] The molded stacked structure MLS may include a lower insulating film 111 disposed on an etch stop layer 110 and a sacrificial layer 121 and a molded insulating layer 122 alternately disposed on the lower insulating film 111. For example, the lower insulating film 111 may include a material similar to that of the molded insulating layer 122. The sacrificial layer 121 may include a sacrificial material having etch selectivity relative to the molded insulating layer 122. For example, the molded insulating layer 122 may include silicon oxide or silicon nitride, and the sacrificial layer 121 may include silicon, silicon oxide, silicon carbide, or silicon nitride.

[0069] In this embodiment, the thicknesses of the lower insulating film 111 and the molded insulating layer 122 may be different. The lower insulating film 111 may be formed to have a relatively thin thickness. The uppermost insulating layer 122T may be formed to have a relatively large thickness. Exemplary embodiments of the inventive concept are not limited thereto, and the thickness and / or number of the insulating layer 120 and the sacrificial layer 121 may be varied.

[0070] Next, a channel via CH can be formed in the molded structure MLS. An anisotropic etching process can be used to form the channel via CH to pass through the sacrificial layer 121, the molded insulating layer 122, and the lower insulating film 111. In an exemplary embodiment of the inventive concept, the inner sidewalls of the channel via CH may not be substantially perpendicular to the upper surface of the substrate 101. For example, the width of the channel via CH may decrease as the channel via CH gets closer to the upper surface of the substrate 101. In this etching process, the end position of the channel via CH can be controlled relatively precisely by utilizing an etch stop layer 110 formed of a high-dielectric material. In this embodiment, the end (e.g., the bottom) of the channel via CH may be located within the etch stop layer 110. For example, the end of the channel via CH may protrude into the etch stop layer 110 by passing through the lower insulating film 111 directly above the etch stop layer 110. Prior to forming the channel via CH, select line cut regions SLC for string select lines SSL can be formed between the channel via CHs.

[0071] Reference Figure 7 The portion of the channel hole CH in the etch stop layer 110 extends in the width direction, thereby exposing the lower sacrificial layer 105.

[0072] This process can be performed by an isotropic etching process (e.g., wet etching) capable of selectively etching the etch stop layer 110. Figure 14A As shown, isotropic etching can be performed on the ends of the channel hole CH to provide a first extended space CH_E having a convex bottle shape. During this etching process, the lower sacrificial layer 105 can be exposed through the bottom surface of the first extended space CH_E. The exposed portion of the lower sacrificial layer 105 can serve as a channel through which the portion of the vertical insulating layer 171 to be formed in the first extended space CH_E can be removed in a subsequent process of removing the lower sacrificial layer 105.

[0073] Reference Figure 8 A vertical structure CS can be formed in the channel hole CH.

[0074] A vertical structure CS can be formed by sequentially forming a vertical insulating layer 171, a vertical channel layer 150, and an insulating core 160 on the inner wall of the channel hole CH and on the surface exposed by the first extended space CH_E. For example... Figure 14BAs shown, a vertical insulating layer 171 can be conformally formed on the inner wall of the channel hole CH and the exposed surface of the first extended space CH_E. As described above, the vertical insulating layer 171 used in this embodiment can be formed by sequentially depositing a barrier insulating film 171a, a charge storage film 171b, and a tunneling insulating film 171c. Next, a vertical channel layer 150 can be formed on the surface of the vertical insulating layer 171. The vertical insulating layer 171 and / or the vertical channel layer 150 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0075] The insulating core 160 can fill the internal space of the vertical channel layer 150. For example, the insulating core 160 can comprise silicon oxide, silicon nitride, or silicon oxynitride, and can be formed, for example, from spin-coated glass (SOG) oxide. As described above, the vertical insulating layer 171, the vertical channel layer 150, and the insulating core 160 are formed sequentially to form a vertical structure CS, such as... Figure 14B As shown, the vertical structure CS can have a first extended region EA with a protruding bottle shape in the first extended space CH_E.

[0076] Next, some portions of the upper ends of the vertical channel layer 150 and the insulating core 160 are recessed using an etch-back process to form pads (PDs) using conductive material. After forming a conductive material layer to fill the recessed areas to form the pads (PDs), a planarization process can be performed to expose the uppermost insulating layer 122T. The pads (PDs) are connected to the vertical channel layer 150 and can provide contact areas for connection to bit lines, etc., in subsequent processing.

[0077] Reference Figure 9 The opening OP' is formed to pass through the molded stacked structure MLS and the etch stop layer 110 to connect to the lower sacrificial layer 105.

[0078] Before forming the opening OP', a first insulating film 191a (also referred to as a "protective insulating film") can be formed to cover the pads PD in the molded stacked structure MLS. The protective insulating film 191a can protect the uppermost insulating layer 122T, the pads PD, and the vertical structure CS in subsequent etching processes. The opening OP' can be formed by forming a mask using photolithography and performing anisotropic etching using that mask. The opening OP' can be a trench extending in a certain direction (e.g., the Y direction). The opening OP' can expose a portion of the etch stop layer 110. In other words, a portion of the etch stop layer 110 can be exposed through the opening OP'.

[0079] With the formation of channel holes CH (see) Figure 6 Similar to the aforementioned process, in addition, in this etching process, the end position of the opening OP' can be controlled relatively precisely using the etch stop layer 110 formed of a high dielectric material.

[0080] Reference Figure 10 The second extended space OP_E' can be formed by extending the opening OP' located in the etch stop layer 110 to expose the lower sacrificial layer 105.

[0081] Compared with the above extended processing (see Figure 7 Similarly, this process can be performed by an isotropic etching process (e.g., wet etching) capable of selectively etching the etch stop layer 110. Isotropic etching can be performed on the end of the opening OP to form a second extended space OP_E' having a bottle shape with a convex surface. In this etching process, the lower sacrificial layer 105 can be exposed through the bottom surface of the second extended space OP_E'.

[0082] Reference Figure 11 An insulating spacer 175 is formed on the inner sidewall of the opening OP, and the opening OP extends to a portion of the substrate 101 by means of the insulating spacer 175.

[0083] After forming the insulating spacer 175 on the inner surface of the opening OP, an anisotropic etching process can be performed to open the bottom surface of the opening OP, thereby exposing the lower sacrificial layer 105 to the bottom surface of the opening OP. The opening OP can then extend to a portion of the substrate 101 using the insulating spacer 175 thus obtained. As a result, since the lower sacrificial layer 105 can be exposed at the lower end of the opening OP, it can be removed through the opening OP.

[0084] Reference Figure 12 At least a portion of the vertical insulating layer 171 disposed in the etch stop layer 110 can be removed together with the lower sacrificial layer 105 through the opening OP.

[0085] In the process of removing the lower sacrificial layer 105 through the opening OP, the molded stacked structure MLS can be protected from damage by the insulating spacer 175. The lower sacrificial layer 105 is removed to form the space OB for the common source electrode (or conductive layer 180), and as... Figure 14C As shown, the vertical insulating layer 171 disposed in the first extension region EA is partially removed, thereby providing an empty space OB_E in the first extension region EA while simultaneously connecting to the lower sacrificial layer 105 during an additional etching process. The empty space OB_E may be formed into a conductive film in a subsequent process. Figure 13 The area of ​​“185”.

[0086] When performing additional etching, the vertical insulating layer 171 can be gradually removed upwards from the bottom surface of the first extended region EA. As described above, the area where the vertical insulating layer 171 is etched can be located below the lower insulating film 111. This etching path can travel through the convex surface of the extended region EA. Since etching occurs subsequently as the etchant passes through the convex surface of the extended region EA, it is effective to prevent the etching from reaching the lower insulating film 111 due to rapid over-etching.

[0087] Reference Figure 13 The conductive layer 180 can be formed by filling the spaces OB and OB_E obtained by the aforementioned process with a conductive material doped with impurities IP of the first conductivity type.

[0088] The conductive layer 180 can be formed by depositing a conductive material doped with impurities of a first conductivity type in the space OB where the lower sacrificial layer 105 has been removed. In the process of forming the conductive layer 180, a conductive film 185 connected to the conductive layer 180 can be formed in the space OB_E where the vertical insulating layer 171 has been removed.

[0089] The conductive film 185 may comprise the same conductive material as the conductive layer 180 as an element extending from the conductive layer 180. The conductive film 185 may be formed from a conductive material doped with a high concentration of impurities of a first conductivity type (IP) in the same or similar manner as the conductive layer 180. For example, the conductive layer 180 and the conductive film 185 may comprise polycrystalline silicon doped with n-type impurities. As described above, the impurity IP can diffuse through the conductive film 185 into the adjacent vertical channel layer 150. To effectively induce this impurity diffusion, an additional heat treatment process may be performed.

[0090] Next, the insulating spacer 175 is removed from the opening OP, and the sacrificial layer 121 exposed through the opening OP is removed, and as follows Figure 13 As shown, a planar insulating layer 172 and a gate electrode 130 can be formed. Next, as... Figure 3 As shown, an isolation structure IS can be formed by filling the opening OP with insulating material, and processing for on-line routing including bit line BL can be performed.

[0091] In the foregoing embodiment, the end of the vertical structure CS is shown located in the insulating substrate layer 110 (e.g., an etch stop layer), but the end of the channel hole CH may also be located below the etch stop layer depending on the etching process that forms the channel hole CH. In this case, the conductive film 185 may also be disposed in the extension region EA, which has a convex surface located in the insulating substrate layer 110, and impurities may diffuse through the conductive film 185 in the channel region of the GIDL transistor.

[0092] Figure 15 This is a schematic plan view illustrating an exemplary three-dimensional semiconductor device according to a concept of the present invention. Figure 16 It is shown Figure 15 An enlarged cross-sectional view of region "B" in the three-dimensional semiconductor device shown.

[0093] Reference Figure 15 and Figure 16 The semiconductor device, except that the bottom surface of the vertical structure CS' is located at a lower horizontal height than the bottom surface of the insulating substrate layer 110, can be connected with... Figure 1 to Figure 3 The semiconductor device 100 shown is similar. Furthermore, unless otherwise stated, the components of this embodiment may be similar to... Figure 1 to Figure 3 The components of the semiconductor device 100 shown are the same or similar.

[0094] Similar to the previous embodiments, the vertical structure CS' used in this embodiment may include a first extended region EA' in the insulating substrate layer 110, and may include a conductive film 185' extending along the surface of the vertical channel layer 150. In this case, the end or bottom surface of the vertical structure CS' may be located below the bottom surface of the insulating substrate layer 110. In other words, the channel hole forming process (see...) can be performed. Figure 6 The vertical channel layer 150 extends through the bottom surface of the insulating substrate layer 110. In this case, the first extension region EA' can be formed only in the insulating substrate layer 110, which has relatively high etch selectivity, but the end of the channel hole CH can be disposed in the lower sacrificial layer 105 (in the conductive layer 180 in the final structure). Therefore, the vertical channel layer 150 can extend into the interior of the lower sacrificial layer 105 (in the conductive layer 180 in the final structure). In an exemplary embodiment of the inventive concept, the insulating core 160 can also be located in the lower sacrificial layer 105 (in the conductive layer 180 in the final structure) below the lower surface of the insulating substrate layer 110.

[0095] In this embodiment, during the formation of the conductive layer 180, a portion of the vertical insulating layer 171 located in the first extended region EA' is partially removed, and this portion is filled with the same material as the removed conductive layer 180, thereby forming a conductive film 185'. Since the conductive film 185' is formed of a conductive material doped with impurities similar to those in the conductive layer 180, these impurities can diffuse into the adjacent vertical channel layer 150.

[0096] Figure 17 This is a schematic plan view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to the concept of the present invention.

[0097] Reference Figure 17Except for the vertical structure CS″ extending into a portion of the substrate 101, the semiconductor device according to this embodiment can be connected with... Figure 1 to Figure 3 , Figure 15 and Figure 16 The semiconductor device shown is similar. Unless otherwise specifically stated, the components of this embodiment may be similar to those shown. Figure 1 to Figure 3 , Figure 15 and Figure 16 The components of the semiconductor devices shown are the same or similar.

[0098] Similar to the previous embodiments, the vertical structure CS″ used in this embodiment may include a first extension region EA″ in the insulating substrate layer 110, and may include conductive films (185a and 185b) extending along the surface of the vertical channel layer 150 of the first extension region EA″. In this case, the vertical structure CS can pass through the conductive layer 180, and its bottom surface can be located in the substrate 101. Similar to the previous embodiments, this can also be understood as wherein the channel hole (see...) is formed... Figure 6 In the case of the process passing through the lower sacrificial layer 105, since the end of the channel hole CH is located in a portion of the substrate 101, the vertical insulating layer 171 and the vertical channel layer 150 can extend to the region of the substrate 101 disposed below the conductive layer 180. In an exemplary embodiment of the inventive concept, the end of the insulating core 160 may also be located in a region of the substrate 101.

[0099] Furthermore, in this embodiment, during the process of forming the conductive layer 180, not only can the vertical insulating layer 171 in the first extended region EA″ be ​​partially removed, but the vertical insulating layer 171 disposed in the substrate 101 can also be partially removed. However, a portion of the vertical insulating layer 171 can remain in the substrate 101. The upper conductive film 185a and the lower conductive film 185b can be formed by filling the removed areas with the same material as the conductive layer 180. In this case, similar to the conductive films 185 and 185' in the aforementioned embodiments, the upper conductive film 185a can help diffuse impurities into the adjacent vertical trench layer 150.

[0100] As described above, according to exemplary embodiments of the present invention, since GIDL transistors are formed on top of a stacked structure without the use of ion implantation processes that can lead to failure, a semiconductor device and a method thereof with excellent reliability can be provided.

[0101] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and alterations may be made thereto without departing from the scope of the inventive concept as set forth in the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: A conductive layer disposed on a substrate and comprising impurities of a first conductivity type; An insulating substrate layer is disposed on the conductive layer; A stacked structure comprising a lower insulating film disposed on the insulating substrate layer and a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the lower insulating film, wherein the insulating substrate layer comprises a high dielectric material; A vertical structure comprising a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extension region extending in the width direction within the insulating substrate layer; and An isolation structure extends through the stacked structure, the insulating substrate layer, and the conductive layer, and extends in a direction parallel to the upper surface of the substrate. The conductive layer has an extension portion that contacts the bottom of the vertical channel layer in the extension region of the vertical structure and extends from the bottom of the vertical channel layer along the surface of the vertical channel layer.

2. The three-dimensional semiconductor device according to claim 1, wherein, The concentration of impurities of the first conductivity type in the portion of the vertical channel layer adjacent to the extension is higher than the concentration of impurities of the first conductivity type in the portion of the vertical channel layer adjacent to the plurality of gate electrodes.

3. The three-dimensional semiconductor device according to claim 1, wherein, The concentration of impurities of the first conductivity type in the portion of the vertical channel layer adjacent to the lowermost gate electrode among the plurality of gate electrodes is higher than the concentration of impurities of the first conductivity type in the portion of the vertical channel layer adjacent to the uppermost gate electrode among the plurality of gate electrodes.

4. The three-dimensional semiconductor device according to claim 1, wherein, The conductive layer comprises polycrystalline silicon with n-type impurities.

5. The three-dimensional semiconductor device according to claim 1, wherein, Each of the extended regions has a convex surface.

6. The three-dimensional semiconductor device according to claim 1, wherein, The extended portion extends to the upper half of the extended region.

7. The three-dimensional semiconductor device according to claim 1, wherein, The upper end of the extension is located below the lower insulating film.

8. The three-dimensional semiconductor device according to claim 1, wherein, The upper end of the extension is connected to the lower end of the vertical insulating layer.

9. The three-dimensional semiconductor device according to claim 1, wherein, The insulating substrate layer has a support region that contacts the substrate.

10. The three-dimensional semiconductor device according to claim 1, wherein, The deviation between the maximum width of the extended region and the thickness of the insulating substrate layer is within ±30%.

11. The three-dimensional semiconductor device according to claim 10, wherein, The thickness of the insulating substrate layer is 30 nm to 50 nm, and the maximum width of the extended region is 30 nm to 60 nm.

12. The three-dimensional semiconductor device according to claim 1, wherein, The insulating substrate layer includes aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (ZrO2), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) or praseodymium oxide (Pr2O3).

13. The three-dimensional semiconductor device according to claim 1, wherein, The vertical structure also includes an insulating core disposed in the vertical channel layer in a direction perpendicular to the upper surface of the substrate. The insulating core has an extension region extending in the width direction within the insulating substrate layer.

14. The three-dimensional semiconductor device according to claim 1, wherein, The isolation structure is in contact with the substrate.

15. A three-dimensional semiconductor device, comprising: A conductive layer is disposed on the substrate; An insulating substrate layer is disposed on the conductive layer and has a plurality of support regions in contact with the substrate; A stacked structure having multiple gate electrodes and multiple molded insulating layers alternately disposed on the insulating substrate layer; A vertical structure includes a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having a first extension region in the insulating substrate layer, the first extension region extending in the width direction and having a convex surface; as well as An isolation structure extends through the stacked structure, the insulating substrate layer, and the conductive layer in a first direction parallel to the upper surface of the substrate, and has a second extending region in the insulating substrate layer, the second extending region extending in a second direction intersecting the first direction and parallel to the upper surface of the substrate. The conductive layer has an extension portion that contacts the bottom of the vertical channel layer and extends from the bottom of the vertical channel layer along the surface of the vertical channel layer, and the upper end of the extension portion is connected to the lower end of the vertical insulating layer on the surface of the vertical channel layer in the first extension region of the vertical structure.

16. The three-dimensional semiconductor device according to claim 15, wherein, The insulating substrate layer comprises a high dielectric material.

17. The three-dimensional semiconductor device according to claim 15, wherein, The conductive layer and the vertical channel layer comprise polycrystalline silicon.

18. The three-dimensional semiconductor device according to claim 15, wherein, The lower end of the vertical channel layer is located below the lower surface of the insulating substrate layer.

19. The three-dimensional semiconductor device according to claim 15, wherein, The bottom surface of the vertical trench layer is located below the upper surface of the substrate.

20. A three-dimensional semiconductor device, comprising: A conductive layer disposed on a substrate and comprising impurities of a first conductivity type; An insulating layer disposed on the conductive layer; A stacked structure comprising a lower insulating film disposed on the insulating layer and a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on the lower insulating film, wherein the insulating layers comprise a high dielectric material; A vertical structure includes a vertical channel layer passing through the stacked structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes. The vertical structure has a first region in the insulating layer, wherein one side of the first region in the insulating layer is stacked with the lowest gate electrode of the gate electrodes in a direction perpendicular to the upper surface of the substrate; and A conductive film that contacts the bottom of the vertical channel layer and extends from the bottom of the vertical channel layer along the surface of the vertical channel layer from the conductive layer, and covers at least a portion of the vertical channel layer in the first region, wherein the conductive film includes impurities of the first conductivity type.

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