Pixel array substrate

Abstract

The present invention discloses a pixel array substrate, comprising a plurality of gate elements and a plurality of switching elements. The plurality of gate elements comprise an nth gate element and an mth gate element. The plurality of switching elements comprise an nth switching element and an mth switching element electrically connected to the nth gate element and the mth gate element, respectively. The peripheral portion of each switching element comprises a first straight segment. The peripheral portion of the nth switching element further comprises a first transverse segment, and the first transverse segment of the nth switching element and the first straight segment of the nth switching element belong to a first conductive layer and a second conductive layer, respectively. The peripheral portion of the mth switching element spans the first transverse segment of the peripheral portion of the nth switching element.

Description

Technical Field

[0001] The invention relates to a pixel array substrate. Background Art

[0002] With the development of display technology, people's demand for display devices is no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect display devices to have narrow borders or even no borders.

[0003] Generally speaking, a display device includes a pixel array disposed in an active area, a data driving circuit disposed above or below the active area, and a gate driving circuit disposed on the left side, right side, or both sides of the active area. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit can be disposed on a single side of the display area. When the gate driving circuit is disposed on a single side of the display area, the gate line extending in the horizontal direction must be electrically connected to the gate driving circuit through a switching element extending in the vertical direction. However, when the switching element is disposed in the display area, the switching element is bound to be adjacent to the data line; the coupling effect between the switching element and the data line will cause the data signal on the data line to shift, thereby affecting the display quality. Summary of the invention

[0004] The invention provides a pixel array substrate with good performance.

[0005] A pixel array substrate according to an embodiment of the present invention comprises a substrate, a plurality of data lines, a plurality of gate elements, a plurality of pixel structures and a plurality of switching elements. The substrate has an active region and a peripheral region outside the active region. A plurality of data lines are disposed on the substrate and arranged in a first direction. A plurality of gate elements are disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are disposed on the active region of the substrate and are electrically connected to the plurality of data lines and the plurality of gate elements. A plurality of switching elements are disposed on the substrate and are electrically connected to the plurality of gate elements respectively, wherein each switching element comprises a main portion disposed in the active region and a peripheral portion disposed in the peripheral region, and a plurality of main portions of the plurality of switching elements are arranged in the first direction. A plurality of gate elements are arranged in sequence in the second direction, and a plurality of gate elements comprise an nth gate element and an mth gate element, wherein n and m are positive integers, and n and m are different. A plurality of switching elements comprise an nth switching element and an mth switching element electrically connected to the nth gate element and the mth gate element respectively. The peripheral portion of each switching element includes a first straight section extending in the second direction, and the first straight section has a signal input terminal. The peripheral portion of the nth switching element further includes a first transverse section, the first transverse section extends in the first direction, the first straight section of the nth switching element is electrically connected to the first transverse section of the nth switching element, and the first transverse section of the nth switching element and the first straight section of the nth switching element belong to different first conductive layers and second conductive layers respectively. The peripheral portion of the mth switching element spans the first transverse section of the peripheral portion of the nth switching element.

[0006] In one embodiment of the present invention, the first straight segment of the peripheral portion of the nth transfer element and the first straight segment of the peripheral portion of the mth transfer element are arranged sequentially in a first direction, the main portion of the nth transfer element and the main portion of the mth transfer element are arranged sequentially in a third direction, and the first direction is opposite to the third direction.

[0007] In one embodiment of the present invention, the above-mentioned multiple gate elements are arranged in sequence in the second direction, and the multiple gate elements include a kth gate element, k is a positive integer, and n, m and k are different from each other; the multiple switching elements further include a kth switching element electrically connected to the kth gate element; the peripheral portion of the kth switching element further includes a first transverse segment, the first transverse segment of the peripheral portion of the kth switching element extends in the first direction, the first transverse segment of the peripheral portion of the kth switching element and the first vertical segment of the peripheral portion of the kth switching element belong to different first conductive layers and second conductive layers respectively; the peripheral portions of a switching elements of the multiple switching elements span the first transverse segment of the peripheral portion of the nth switching element, and the peripheral portions of b switching elements of the multiple switching elements span the first transverse segment of the peripheral portion of the kth switching element, a and b are positive integers, and a and b are different.

[0008] In an embodiment of the present invention, the above-mentioned plurality of gate elements further includes a p-th gate element and a q-th gate element. The n-th gate element, the m-th gate element, the p-th gate element, and the q-th gate element are arranged in sequence in the second direction, where p and q are positive integers, and n < m < p < q. The plurality of transfer elements further includes a p-th transfer element and a q-th transfer element electrically connected to the p-th gate element and the q-th gate element respectively. The first straight segments of the peripheral portions of the n-th transfer element, the m-th transfer element, the p-th transfer element, and the q-th transfer element are arranged in sequence in the first direction. The peripheral portion of the q-th transfer element further includes a first transverse segment. The first transverse segment of the peripheral portion of the q-th transfer element extends along the third direction from the first straight segment of the q-th transfer element. The first direction is opposite to the third direction. The first straight segment of the peripheral portion of the q-th transfer element is electrically connected to the first transverse segment of the peripheral portion of the q-th transfer element. The first straight segment and the first transverse segment of the peripheral portion of the q-th transfer element belong to different first conductive layer and second conductive layer respectively. The peripheral portion of the p-th transfer element straddles the first transverse segment of the peripheral portion of the q-th transfer element.

[0009] In an embodiment of the present invention, the peripheral portion of the above-mentioned n-th transfer element further includes a second straight segment and a second transverse segment. The second straight segment extends in the second direction, and the second transverse segment extends in the first direction. The first transverse segment of the n-th transfer element is electrically connected to the second straight segment of the peripheral portion of the n-th transfer element. The second straight segment of the peripheral portion of the n-th transfer element is electrically connected to the second transverse segment of the n-th transfer element. The first transverse segment and the second transverse segment of the peripheral portion of the n-th transfer element belong to the first conductive layer, and the first straight segment and the second straight segment of the peripheral portion of the n-th transfer element belong to the second conductive layer.

[0010] In an embodiment of the present invention, the above-mentioned plurality of gate elements further includes an l-th gate element, where l is a positive integer, and n, m, and l are different from each other. The plurality of transfer elements further includes an l-th transfer element electrically connected to the l-th gate element. The l-th transfer element straddles the second transverse segment of the peripheral portion of the n-th transfer element.

[0011] In one embodiment of the present invention, the above-mentioned multiple gate elements further include an r-th gate element, r is a positive integer, and n, m and r are different from each other; the multiple switching elements further include an r-th switching element electrically connected to the r-th gate element; the peripheral portion of the r-th switching element further includes a first transverse section and a second straight section, the first transverse section of the peripheral portion of the r-th switching element extends in the first direction, the first straight section of the r-th switching element is electrically connected to the first transverse section of the r-th switching element, the second straight section of the peripheral portion of the r-th switching element extends in the second direction, the second straight section of the peripheral portion of the r-th switching element is electrically connected to the first transverse section of the r-th switching element, the first transverse section of the r-th switching element belongs to the first conductive layer, and the first straight section and the second straight section of the r-th switching element belong to the second conductive layer; the first straight section of the peripheral portion of the n-th switching element and the second straight section of the peripheral portion of the r-th switching element are substantially aligned in the second direction.

[0012] A pixel array substrate of one embodiment of the present invention includes a substrate, a plurality of data lines, a plurality of gate elements, a plurality of pixel structures, a plurality of switching elements, and an insulating layer. The substrate has an active area and a peripheral area outside the active area. A plurality of data lines are arranged on the substrate and arranged in a first direction. A plurality of gate elements are arranged on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are arranged on the active area of ​​the substrate and are electrically connected to the plurality of data lines and the plurality of gate elements. A plurality of switching elements are arranged on the substrate, wherein each switching element includes a main portion arranged in the active area, and the plurality of main portions of the plurality of switching elements are arranged in the first direction. An insulating layer is arranged between the plurality of main portions of the plurality of switching elements and the plurality of gate elements, wherein the plurality of main portions of the plurality of switching elements are electrically connected to the plurality of gate elements through a plurality of contact windows of the insulating layer. A plurality of pixel structures are arranged into a plurality of pixel rows and a plurality of pixel columns, wherein the plurality of pixel columns are arranged in sequence in a first direction, and the plurality of pixel rows are arranged in sequence in a second direction, and the coordinates of a pixel structure located at the x-th pixel row and the y-th pixel row are (x-1, y-1), and x and y are positive integers. A plurality of contact windows include a first contact window and a second contact window. A plurality of pixel structures include a first pixel structure adjacent to the first contact window. A plurality of pixel structures include a second pixel structure adjacent to the second contact window. The coordinates of the first pixel structure are (x1-1, y1-1), wherein x1 and y1 satisfy one of the following: (x1-1)=[(a / c)·(y1-1)]+b1, wherein a is the ratio of the width of the active region in the first direction to the width of the active region in the second direction, c is the number of switching elements electrically connected to a gate element, and |b1|>1. The coordinates of the second pixel structure are (x2-1, y2-1), where x2 and y2 satisfy the following two: (x2-1) = [(a / c)·(y2-1)] + b2, where a is the ratio of the width of the active area in the first direction to the width of the active area in the second direction, c is the number of switching elements electrically connected to a gate element, and |b2|>1.

[0013] In one embodiment of the present invention, 1<|b1|<20.

[0014] In one embodiment of the present invention, 1<|b2|<20. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a top view of a pixel array substrate 10 according to an embodiment of the present invention.

[0016] Figure 2 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10 according to an embodiment of the present invention.

[0017] Figure 3 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 10 according to an embodiment of the present invention.

[0018] Figure 4 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention.

[0019] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 10 according to an embodiment of the present invention.

[0020] Figure 6 FIG. 1 is a top view of a pixel array substrate 10A according to an embodiment of the present invention.

[0021] Figure 7 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10A according to an embodiment of the present invention.

[0022] Figure 8 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention.

[0023] Fig. 9 FIG. 1 is a top view of a pixel array substrate 10B according to an embodiment of the present invention.

[0024] Fig.10 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10B according to an embodiment of the present invention.

[0025] Fig.11 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention.

[0026] Wherein, the reference numerals are:

[0027] 10, 10A, 10B: Pixel array substrate

[0028] 100: Base

[0029] 100a: Active zone

[0030] 100a-1, 100a-2, 100a-3, 100a-4: sub-active area

[0031] 100b: Peripheral area

[0032] 200, 200-1, 200-2, 200-3, 200-4, 200-5, 200-6, 200-7, 200-8, 200-9: Transition components

[0033] 210: Main part

[0034] 220: Peripheral Department

[0035] 221: Straight segment

[0036] 221-1: First straight section

[0037] 221-2: Second straight section

[0038] 222: Horizontal section

[0039] 222-1: First transverse section

[0040] 222-2: Second transverse section

[0041] 300: Insulation layer

[0042] 310, 320: contact window

[0043] 310-1: First contact window

[0044] 310-2: Second contact window

[0045] C: Pixel Column

[0046] DL: Data line

[0047] D1, D2: distance

[0048] d1: first direction

[0049] d2: second direction

[0050] d3:Third direction

[0051] GD, GD1, GD2, GD3, GD4, GD5, GD6, GD7, GD8, GD9: Gate elements

[0052] GL: Gate Line

[0053] L: Pseudo-diagonal

[0054] PX: Pixel structure

[0055] PX1: First pixel structure

[0056] PX2: Second pixel structure

[0057] p1: spacing

[0058] R: row of pixels

[0059] r1: local

[0060] W1, W2: Width DETAILED DESCRIPTION

[0061] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0062] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0063] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0065] Figure 1 FIG. 1 is a top view of a pixel array substrate 10 according to an embodiment of the present invention.

[0066] Figure 2 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10 according to an embodiment of the present invention. Figure 2 correspond Figure 1 The local r1.

[0067] Figure 1 The active region 100a of the substrate 100, the peripheral region 100b of the substrate 100, a plurality of gate elements GD and a plurality of main portions 210 of a plurality of transfer elements 200 are depicted, and the Figure 2 The plurality of data lines DL, the plurality of pixel structures PX and the plurality of peripheral portions 220 of the plurality of transfer elements 200 .

[0068] Please refer to Figure 1 and Figure 2The pixel array substrate 10 includes a substrate 100. The substrate 100 has an active region 100a and a peripheral region 100b outside the active region 100a. In this embodiment, the peripheral region 100b may be a region located on a single side of the substrate 100, but the invention is not limited thereto.

[0069] For example, in this embodiment, the material of the substrate 100 may be glass. However, the present invention is not limited thereto, and according to other embodiments, the material of the substrate 100 may also be quartz, organic polymer, or opaque / reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.

[0070] The pixel array substrate 10 further includes a plurality of data lines DL and a plurality of gate elements GD, which are disposed on the substrate 100. Each gate element GD includes at least one gate line GL. The plurality of data lines DL are arranged in a first direction d1. The plurality of gate elements GD are arranged in a second direction d2. The first direction d1 is interlaced with the second direction d2. For example, in the present embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the present invention is not limited thereto.

[0071] In the present embodiment, the gate element GD and the data line DL may belong to different first conductive layers and second conductive layers, respectively. For example, in the present embodiment, the first conductive layer and the second conductive layer may be a first metal layer and a second metal layer, respectively, the gate element GD may selectively belong to the first metal layer, and the data line DL may selectively belong to the second metal layer, but the present invention is not limited thereto.

[0072] Based on the consideration of conductivity, in the present embodiment, the gate element GD and the data line DL are made of metal material. However, the present invention is not limited thereto, and according to other embodiments, the gate element GD and the data line DL may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0073] The pixel array substrate 10 further includes a plurality of pixel structures PX disposed on the active region 100a of the substrate 100 and electrically connected to a plurality of data lines DL and a plurality of gate elements GD. For example, in the present embodiment, each pixel structure PX may include a thin film transistor (not shown) and a pixel electrode (not shown), wherein a source and a gate of the thin film transistor may be electrically connected to a corresponding data line DL and a corresponding gate line GL, respectively, and the pixel electrode is electrically connected to a drain of the thin film transistor.

[0074] The plurality of pixel structures PX are arranged into a plurality of pixel rows R and a plurality of pixel columns C. The plurality of pixel columns C are arranged sequentially in a first direction d1. The plurality of pixel structures PX of each pixel column C are arranged sequentially in a second direction d2. The plurality of pixel rows R are arranged sequentially in the second direction d2. The plurality of pixel structures PX of each pixel row R are arranged sequentially in the first direction d1.

[0075] For example, in the present embodiment, a plurality of pixel structures PX of the same pixel column C may be selectively electrically connected to the same data line DL, and a plurality of pixel structures PX of two adjacent pixel rows R may be electrically connected to different plurality of gate elements GD, respectively. In short, in the present embodiment, the pixel array substrate 10 may adopt a driving method of one data line and one gate line (1D1G). However, the present invention is not limited thereto, and in other embodiments, the pixel array substrate may also adopt a driving method of two data lines and one gate line (2D1G), two data lines and half gate line (2DhG), or other driving methods.

[0076] The pixel array substrate 10 further includes a plurality of transfer elements 200 disposed on the substrate 100. Each transfer element 200 includes a main portion 210 disposed in the active area 100a and a peripheral portion 220 disposed in the peripheral area 100b. The plurality of main portions 210 of the plurality of transfer elements 200 are arranged in the first direction d1. For example, in the present embodiment, the plurality of data lines DL and the plurality of main portions 210 of the plurality of transfer elements 200 may belong to the same conductive layer, such as but not limited to: the second metal layer mentioned above.

[0077] Figure 3 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 10 according to an embodiment of the present invention. Figure 3 correspond Figure 2 A contact window 310 is provided.

[0078] Please refer to Figure 2 and Figure 3 , the plurality of transfer elements 200 are electrically connected to the plurality of gate elements GD, respectively. Specifically, in the present embodiment, the pixel array substrate 10 further includes an insulating layer 300, which is disposed between the plurality of main parts 210 of the plurality of transfer elements 200 and the plurality of gate elements GD. The plurality of main parts 210 of the plurality of transfer elements 200 are electrically connected to the plurality of gate elements GD through the plurality of contact windows 310 of the insulating layer 300.

[0079] In this embodiment, the material of the insulating layer 300 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0080] Please refer to Figure 1 and Figure 2 For example, in the present embodiment, the same gate element GD can be electrically connected to four adapter elements 200. All the multiple adapter elements 200 of the pixel array substrate 10 can be divided into four adapter element groups. The multiple main parts 210 of the multiple adapter elements 200 of each adapter element group are respectively electrically connected to all the multiple gate elements GD of the pixel array substrate 10. The four adapter element groups can be respectively arranged in the multiple sub-active areas 100a-1, 100a-2, 100a-3, and 100a-4 of the active area 100a of the substrate 100. However, the present invention is not limited to this, and the number of adapter elements 200 electrically connected to the same gate element GD can be determined according to actual needs; in other embodiments, the number of adapter elements 200 electrically connected to the same gate element GD can also be other positive integers other than 4.

[0081] The plurality of pixel structures PX are arranged into a plurality of pixel rows R and a plurality of pixel columns C. The plurality of pixel columns C are sequentially arranged in a first direction d1, and the plurality of pixel rows R are sequentially arranged in a second direction d2. The coordinates of a pixel structure PX located at the x-th pixel row C and the y-th pixel row R are (x-1, y-1), where x and y are positive integers.

[0082] For example, in this embodiment, the coordinates of a pixel structure PX (not shown) located at the first pixel row C at the bottom of the sub-active region 100 a - 1 and the first pixel line R at the leftmost side of the sub-active region 100 a - 1 are (0, 0).

[0083] Please refer to Figure 2 and Figure 3 The main parts 210 of the plurality of transfer elements 200 are electrically connected to the plurality of gate elements GD through the plurality of contact windows 310 of the insulating layer 300. Figure 2 The plurality of contact windows 310 include a first contact window 310-1 and a second contact window 310-2. The plurality of pixel structures PX include a first pixel structure PX1 adjacent to the first contact window 310-1. The plurality of pixel structures PX include a second pixel structure PX2 adjacent to the second contact window 310-2.

[0084] Please refer to Figure 1 and Figure 2, the coordinates of the first pixel structure PX1 are (x1-1, y1-1), wherein x1 and y1 satisfy one of the following: (x1-1)=[(a / c)·(y1-1)]+b1, wherein [] is a Gaussian symbol, which represents unconditional discarding of decimal points, a is a ratio of a width W1 of an active area 100a of the pixel array substrate 10 in a first direction d1 to a width W2 of an active area 100a of the pixel array substrate 10 in a second direction d2, c is the number of transfer elements 200 electrically connected to a single gate element GD, and |b1|>1.

[0085] The coordinates of the second pixel structure PX2 are (x2-1, y2-1), where x2 and y2 satisfy the following two: (x2-1) = [(a / c)·(y2-1)]+b2, where [] is a Gaussian symbol, which represents unconditional discarding of decimal points, a is the ratio of the width W1 of the active area 100a of the pixel array substrate 10 in the first direction d1 to the width W2 of the active area 100a of the pixel array substrate 10 in the second direction d2, c is the number of transfer elements 200 electrically connected to a single gate element GD, and |b2|>1.

[0086] It is worth noting that |b1| is not equal to |b2|. Please refer to Figure 1 and Figure 2 In short, in the present embodiment, a sub-active region 100a-1 of the active region 100a has a pseudo-diagonal line L, and the pseudo-diagonal line L passes through a pixel structure PX with coordinates (0,0). (a / c) in the above formulas 1 and 2 is the inverse of the slope of the pseudo-diagonal line L, and |b1| can reflect the distance D1 of the first pixel structure PX1 deviating from the pseudo-diagonal line L in the first direction d1, and |b2| can reflect the distance D2 of the second pixel structure PX2 deviating from the pseudo-diagonal line L in the first direction d1. |b1| is not equal to |b2|, which means that the distance D1 of the first pixel structure PX1 deviating from the pseudo-diagonal line L in the first direction d1 is not equal to the distance D2 of the second pixel structure PX2 deviating from the pseudo-diagonal line L in the first direction d1.

[0087] In other words, the plurality of contact windows 310 (or the plurality of connection points between the plurality of adapter elements 200 and the plurality of gate elements GD) are randomly distributed on the quasi-diagonal line L and / or on both sides of the quasi-diagonal line L, so that the plurality of pixel structures PX with abnormal brightness (e.g., too bright) due to the coupling effect between the adapter element 200 and the data line DL are also randomly distributed on the quasi-diagonal line L and / or on both sides of the quasi-diagonal line L. Since the plurality of pixel structures PX with abnormal brightness (e.g., too bright) are randomly distributed on the quasi-diagonal line L and / or on both sides of the quasi-diagonal line L, it is difficult for the human eye to perceive the display screen abnormality (e.g., the bright line corresponding to the quasi-diagonal line L) caused by the coupling effect between the adapter element 200 and the data line DL.

[0088] For example, in this embodiment, 1<|b1|<20. That is, the plurality of pixel structures PX are arranged at a pitch p1 in the first direction d1, and the distance D1 of the first pixel structure PX1 from the pseudo-diagonal line L in the first direction d1 is preferably greater than one pitch p1 and less than 20 pitches p1, but the present invention is not limited thereto.

[0089] For example, in this embodiment, 1<|b2|<20. That is, the plurality of pixel structures PX are arranged at a pitch p1 in the first direction d1, and the distance D2 of the second pixel structure PX2 from the pseudo-diagonal line L in the first direction d1 is preferably greater than one pitch p1 and less than 20 pitches p1, but the present invention is not limited thereto.

[0090] Figure 4 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention. Figure 4 correspond Figure 3 Multiple peripheral portions 220 of multiple transition elements 200 on the peripheral area 100b.

[0091] Please refer to Figure 2 and Figure 4 The peripheral portion 220 of each adapter element 200 is electrically connected to the main portion 210 of the adapter element 200. The peripheral portion 220 of each adapter element 200 includes at least one straight segment 221 extending in the second direction d2. The at least one straight segment 221 of the peripheral portion 220 of each adapter element 200 includes a first straight segment 221-1, wherein the first straight segment 221-1 has a signal input end, and the signal input end is a portion of the peripheral portion 220 of the adapter element 200 that is closest to the driving element (e.g., a chip not shown).

[0092] Please refer to Figure 2In the present embodiment, the main parts 210 of the plurality of adapter elements 200 are randomly interspersed in the active region 100a, and the main parts 210 of the plurality of adapter elements 200 are not arranged in accordance with the arrangement order of the plurality of gate elements GD electrically connected thereto. For example, the plurality of gate elements GD include a gate element GD1, a gate element GD2, a gate element GD3, a gate element GD4, a gate element GD5, a gate element GD6, a gate element GD7, a gate element GD8, and a gate element GD9 arranged in sequence in the first direction d1, and the gate elements GD1, the gate elements GD2, the gate elements GD3, the gate elements GD4, the gate elements GD5, the gate elements GD6, the gate elements GD7, the gate elements GD8, and the gate elements GD9 are electrically connected to a adapter element 200-1, a adapter element 200-2, a adapter element 200-3, a adapter element 200-4, and a adapter element 200-5. 00-4, a transfer element 200-5, a transfer element 200-6, a transfer element 200-7, a transfer element 200-8 and a transfer element 200-9, and the main part 210 of the transfer element 200-1, the main part 210 of the transfer element 200-2, the main part 210 of the transfer element 200-3, the main part 210 of the transfer element 200-4, the main part 210 of the transfer element 200-5, the main part 210 of the transfer element 200-6, the main part 210 of the transfer element 200-7, the main part 210 of the transfer element 200-8 and the main part 210 of the transfer element 200-9 are not arranged in sequence in the second direction d2.

[0093] Please refer to Figure 2 and Figure 4 However, in order to match the arrangement of multiple output pins of a driving element (e.g., a chip not shown), the multiple first straight sections 221-1 of the multiple peripheral portions 220 of the multiple adapter elements 200 having multiple signal input terminals still need to be arranged in sequence in the first direction d1. Therefore, at least a portion of the multiple peripheral portions 220 of the multiple adapter elements 200 also needs to include at least one transverse section 222 that belongs to a different film layer from the straight section 221 and extends in the first direction d1, so that the main portion 210 thereof is electrically connected to the first straight section 221-1 that is not aligned with the main portion 210 thereof through at least one transverse section 222, wherein at least one transverse section 222 will cross over the peripheral portions 220 of other adapter elements 200.

[0094] For example, in this embodiment, the peripheral portion 220 of the adapter element 200-2 also includes at least one transverse segment 222 belonging to a different film layer from at least one vertical segment 221 thereof, so as to electrically connect its main portion 210 to the first vertical segment 221-1 that is not aligned with its main portion 210 through at least one transverse segment 222, wherein at least one transverse segment 222 spans over the peripheral portion 220 of other adapter elements 200-3.

[0095] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate 10 according to an embodiment of the present invention. Figure 5 correspond Figure 4 A contact window 320 is provided.

[0096] Please refer to Figure 4 and Figure 5 In the present embodiment, a plurality of peripheral portions 220 of certain adapter elements 200 are connected by at least one longitudinal segment 221 and at least one transverse segment 222, wherein at least one longitudinal segment 221 extends in a second direction d2, and at least one transverse segment 222 extends in a first direction d1, and at least one transverse segment 222 and at least one longitudinal segment 221 belong to different first conductive layers and second conductive layers, respectively, and at least one longitudinal segment 221 is electrically connected to at least one transverse segment 222 through a contact window 320 of an insulating layer 300.

[0097] exist Figure 2 and Figure 4 In the figure, thin lines represent the transverse segments 222 belonging to the first conductive layer, and thick lines represent the vertical segments 221 belonging to the second conductive layer.

[0098] Please refer to Figure 2 and Figure 4, a plurality of gate elements GD are arranged in sequence in the second direction d2, the plurality of gate elements GD include an nth gate element GD and an mth gate element GD, n and m are positive integers, and n and m are different. A plurality of switching elements 200 include an nth switching element 200 and an mth switching element 200 electrically connected to the nth gate element GD and the mth gate element GD, respectively. At least one straight section 221 of the peripheral portion 220 of each switching element 200 includes a first straight section 221-1 extending in the second direction d2, and the first straight section 221-1 has a signal input terminal. The peripheral portion 220 of the nth switching element 200 may include at least one transverse section 222. At least one transverse section 222 of the peripheral portion 220 of the nth adapter element 200 may include a first transverse section 222-1, a first straight section 221-1 of the peripheral portion 220 of the nth adapter element 200 is electrically connected to the first transverse section 222-1 of the peripheral portion 220 of the nth adapter element 200, and the first transverse section 222-1 of the peripheral portion 220 of the nth adapter element 200 and the first straight section 221-1 of the peripheral portion 220 of the nth adapter element 200 belong to different first conductive layers and second conductive layers, respectively. In particular, the peripheral portion 220 of the mth adapter element 200 crosses over the first transverse section 222-1 of the peripheral portion 220 of the nth adapter element 200.

[0099] For example, in the present embodiment, n and m may be 2 and 3 respectively, and the plurality of adapter elements 200 may include a second adapter element 200-2 and a third adapter element 200-3 electrically connected to the second gate element GD2 and the third gate element GD3 respectively. The peripheral portion 220 of the second adapter element 200-2 includes a first transverse segment 222-1, the first transverse segment 222-1 extends in the first direction d1, the first straight segment 221-1 of the peripheral portion 220 of the second adapter element 200 is electrically connected to the first transverse segment 222-1 of the peripheral portion 220 of the second adapter element 200, and the first transverse segment 222-1 of the peripheral portion 220 of the second adapter element 200 and the first straight segment 221-1 of the peripheral portion 220 of the second adapter element 200 belong to different first conductive layers and second conductive layers respectively. In particular, the peripheral portion 220 of the third adapter element 200 - 3 spans over the first transverse section 222 - 1 of the peripheral portion 220 of the second adapter element 200 .

[0100] Please refer to Figure 2 and Figure 4In the present embodiment, the peripheral portion 220 of each adapter element 200 includes a first straight segment 221-1 having a signal input end, and the first straight segment 221-1 of the peripheral portion 220 of the n-th adapter element 200 and the first straight segment 221-1 of the peripheral portion 220 of the m-th adapter element 200 are arranged in sequence in the first direction d1, but the main portion 210 of the n-th adapter element 200 and the main portion 210 of the m-th adapter element 200 are arranged in sequence in a third direction d3 opposite to the first direction d1.

[0101] For example, in this embodiment, n and m may be 2 and 3 respectively, the first straight segment 221-1 of the peripheral portion 220 of the second transfer element 200-2 and the first straight segment 221-1 of the peripheral portion 220 of the third transfer element 200-3 are arranged in sequence in the first direction d1, but the main portion 210-2 of the second transfer element 200-2 and the main portion 210-3 of the third transfer element 200-3 are arranged in sequence in a third direction d3 opposite to the first direction d1.

[0102] Please refer to Figure 2 and Figure 4 In the present embodiment, a plurality of gate elements GD are sequentially arranged in the second direction d2, and the plurality of gate elements GD include an nth gate element GD, an mth gate element GD, and a kth gate element GD, n, m, and k are positive integers, and n, m, and k are different from each other. A plurality of adapter elements 200 include an nth adapter element 200, an mth adapter element 200, and a kth adapter element 200 electrically connected to the nth gate element GD, the mth gate element GD, and the kth gate element GD, respectively. The peripheral portion 220 of the kth adapter element 200 may include at least one transverse segment 222. The at least one transverse segment 222 of the peripheral portion 220 of the kth adapter element 200 includes a first transverse segment 222-1. The first transverse segment 222-1 of the peripheral portion 220 of the kth adapter element 200 extends in the first direction d1. The first transverse section 222-1 of the peripheral portion 220 of the kth adapter element 200 and the first straight section 221-1 of the peripheral portion 220 of the kth adapter element 200 belong to different first conductive layers and second conductive layers, respectively. The peripheral portion 220 of a adapter element 200 of the plurality of adapter elements 200 spans the first transverse section 222-1 of the peripheral portion 220 of the nth adapter element 200, and the peripheral portion 220 of b adapter elements 200 of the plurality of adapter elements 200 spans the first transverse section 222-1 of the peripheral portion 220 of the kth adapter element 200, where a and b are positive integers and are different from each other.

[0103] For example, in the present embodiment, n, m and k may be 2, 3 and 9 respectively, the plurality of gate elements GD are sequentially arranged in the second direction d2, and the plurality of gate elements GD include a second gate element GD2, a third gate element GD3 and a ninth gate element GD9. The plurality of adapter elements 200 include a second adapter element 200-2, a third adapter element 200-3 and a ninth adapter element 200-9 electrically connected to the second gate element GD2, the third gate element GD3 and the ninth gate element GD9 respectively. The peripheral portion 220 of the 9th adapter element 200-9 further includes a first transverse section 222-1. The first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200 extends in the first direction d1. The first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200-9 and the first vertical section 221-1 of the peripheral portion 220 of the 9th adapter element 200-9 belong to different first conductive layers and second conductive layers, respectively. The peripheral portions 220 of four adapter elements 200 (for example, the peripheral portion 220 of the third adapter element 200-3, the peripheral portion 220 of the ninth adapter element 200-3, the peripheral portion 220 of the fourth adapter element 200-4, and the peripheral portion 220 of the fifth adapter element 200-5) span the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200. The peripheral portions 220 of five adapter elements 200 (for example, the peripheral portion 220 of the fourth adapter element 200-4, the peripheral portion 220 of the fifth adapter element 200-5, the peripheral portion 220 of the sixth adapter element 200-6, the peripheral portion 220 of the seventh adapter element 200-6, and the peripheral portion 220 of the eighth adapter element 200-8) span the first transverse section 222-1 of the peripheral portion 220 of the ninth adapter element 200-9.

[0104] In short, in this embodiment, the number of first transverse segments 222 - 1 of one adapter element 200 spanned by the peripheral portions 220 of other adapter elements 200 is different from the number of first transverse segments 222 - 1 of another adapter element 200 spanned by the peripheral portions 220 of other adapter elements 200 .

[0105] Please refer to Figure 2 and Figure 4, in this embodiment, the multiple gate elements GD include the nth gate element GD, the mth gate element GD, the pth gate element GD, and the qth gate element GD arranged in sequence in the second direction d2, where n, m, p, and q are positive integers, and n < m < p < q; the multiple转接 elements 200 include the nth转接 element 200, the mth转接 element 200, the pth转接 element 200, and the qth转接 element 200 electrically connected to the nth gate element GD, the mth gate element GD, the pth gate element GD, and the qth gate element GD respectively; the first straight segments 221-1 of the peripheral portions 220 of the nth转接 element 200, the first straight segments 221-1 of the peripheral portions 220 of the mth转接 element 200, the first straight segments 221-1 of the peripheral portions 220 of the pth转接 element 200, and the first straight segments 221-1 of the peripheral portions 220 of the qth转接 element 200 are arranged in sequence in the first direction d1; the peripheral portion 220 of the nth转接 element 200 includes at least one transverse segment 222, at least one transverse segment 222 of the nth转接 element 200 includes a first transverse segment 222-1, the first straight segment 221-1 of the nth转接 element 200 is electrically connected to the first transverse segment 222-1 of the nth转接 element 200, the first transverse segment 222-1 of the nth转接 element 200 extends from the first straight segment 221-1 of the nth转接 element 200 along the first direction d1, and the peripheral portion 220 of the mth转接 element 200 straddles the first transverse segment 222-1 of the peripheral portion 220 of the nth转接 element 200; the peripheral portion 220 of the qth转接 element 200 includes at least one transverse segment 222, at least one transverse segment 222 of the qth转接 element 200 includes a first transverse segment 222-1, the first straight segment 221-1 of the peripheral portion 220 of the qth转接 element 200 is electrically connected to the first transverse segment 222-1 of the peripheral portion 220 of the qth转接 element 200, and the first straight segment 221-1 of the peripheral portion 220 of the qth转接 element 200 and the first transverse segment 222-1 of the peripheral portion 220 of the qth转接 element 200 belong to different first conductive layers and second conductive layers respectively; the peripheral portion 220 of the pth转接 element 200 straddles the first transverse segment 222-1 of the peripheral portion 220 of the qth转接 element 200, the first transverse segment 222-1 of the peripheral portion 220 of the qth转接 element 200 extends from the first straight segment 221-1 of the qth转接 element 200 along a third direction d3, and the first direction d1 is opposite to the third direction d3.

[0106] For example, in the present embodiment, n, m, p and q may be 2, 3, 8 and 9 respectively, the plurality of gate elements GD include a second gate element GD2, a third gate element GD3, an eighth gate element GD8 and a ninth gate element GD9 arranged in sequence in the second direction d2; the plurality of adapter elements 200 include a second adapter element 200-2, a third adapter element 200-3, an eighth adapter element 200-8 and a ninth adapter element 200-9 electrically connected to the second gate element GD2, the third gate element GD3, the eighth gate element GD8 and the ninth gate element GD9 respectively; the first straight section 220 of the peripheral portion 220 of the second adapter element 200-2 1-1, the first straight section 221-1 of the peripheral portion 220 of the third adapter element 200-3, the first straight section 221-1 of the peripheral portion 220 of the eighth adapter element 200-8 and the first straight section 221-1 of the peripheral portion 220 of the ninth adapter element 200-9 are arranged in sequence in the first direction d1; the peripheral portion 220 of the second adapter element 200-2 includes a first transverse section 222-1, the first straight section 221-1 of the peripheral portion 220 of the second adapter element 200-2 is electrically connected to the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200-2, the first straight section 221-1 of the peripheral portion 220 of the second adapter element 200-2 and the second The first transverse section 222-1 of the peripheral portion 220 of the adapter element 200-2 belongs to different first conductive layers and second conductive layers respectively; the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200-2 extends from the first straight section 221-1 of the peripheral portion 220 of the second adapter element 200-2 along the first direction d1, and the peripheral portion 220 of the third adapter element 200-3 spans the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200-2; the peripheral portion 220 of the ninth adapter element 200-9 further includes the first transverse section 222-1, and the first straight section 221-1 of the peripheral portion 220 of the ninth adapter element 200-9 is electrically connected to The first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200-9, the first straight section 221-1 of the peripheral portion 220 of the 9th adapter element 200-9 and the first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200-9 belong to different first conductive layers and second conductive layers respectively; the peripheral portion 220 of the 8th adapter element 200-8 spans the first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200-9, and the first transverse section 222-1 of the peripheral portion 220 of the 9th adapter element 200 extends from the first straight section 221-1 of the 9th adapter element 200 along the third direction d3, and the first direction d1 is opposite to the third direction d3.

[0107] In short, in the present embodiment, multiple first transverse sections 222-1 of multiple peripheral portions 220 of multiple adapter elements 200 are spanned by peripheral portions 220 of other adapter elements 200; in particular, the first transverse section 222-1 of one adapter element 200 is spanned by at least one peripheral portion 220 of at least one adapter element 200 located on the right side of its first straight section 221-1, and the first transverse section 222-1 of another adapter element 200 is spanned by at least one peripheral portion 220 of at least one adapter element 200 located on the left side of its first straight section 221-1.

[0108] Please refer to Figure 2 and Figure 4 In this embodiment, at least one straight section 221 of the peripheral portion 220 of the nth adapter element 200 may selectively include a second straight section 221-2 in addition to the first straight section 221-1; at least one transverse section 222 of the peripheral portion 220 of the nth adapter element 200 may selectively include a second transverse section 222-2 in addition to the first transverse section 222-1; the second straight section 221-2 extends in the second direction d2, the second transverse section 222-2 extends in the first direction d1, and the first transverse section 222 of the peripheral portion 220 of the nth adapter element 200 may selectively include a second transverse section 222-2. The segment 222-1 is electrically connected to the second straight segment 221-2 of the peripheral portion 220 of the nth adapter element 200, the second straight segment 221-2 of the peripheral portion 220 of the nth adapter element 200 is electrically connected to the second transverse segment 222-2 of the peripheral portion 220 of the nth adapter element 200, the first transverse segment 222-1 and the second transverse segment 222-2 of the peripheral portion 220 of the nth adapter element 200 belong to the first conductive layer, and the first straight segment 221-1 and the second straight segment 221-2 of the peripheral portion 220 of the nth adapter element 200 belong to the second conductive layer.

[0109] For example, in this embodiment, n may be 2; the peripheral portion 220 of the second adapter element 200-2 includes a second straight segment 221-2 and a second transverse segment 222-2 in addition to the first straight segment 221-1 and the first transverse segment 222-1; the second straight segment 221-2 extends in the second direction d2; the second transverse segment 222-2 extends in the first direction d1; the first transverse segment 222-1 of the peripheral portion 220 of the second adapter element 200-2 is electrically connected to the first transverse segment 222-2 of the second adapter element 200-2; The second straight section 221-2 of the peripheral portion 220, the second straight section 221-2 of the peripheral portion 220 of the second adapter element 200-2 is electrically connected to the second transverse section 222-2 of the peripheral portion 220 of the second adapter element 200-2, the first transverse section 222-1 and the second transverse section 222-2 of the peripheral portion 220 of the second adapter element 200 belong to the first conductive layer, and the first straight section 221-1 and the second straight section 221-2 of the peripheral portion 220 of the second adapter element 200 belong to the second conductive layer. In short, in this embodiment, at least one peripheral portion 220 of the adapter element 200 can selectively have more than two turning points.

[0110] Please refer to Figure 2 and Figure 4 In the present embodiment, a plurality of gate elements GD are sequentially arranged in the second direction d2, and the plurality of gate elements GD include an nth gate element GD, an mth gate element GD, and a lth gate element GD, n, m, and l are positive integers, and n, m, and l are different from each other; a plurality of adapter elements 200 include an nth adapter element 200, an mth adapter element 200, and a lth adapter element 200 electrically connected to the nth gate element GD, the mth gate element GD, and the lth gate element GD, respectively; a peripheral portion 220 of the mth adapter element 200 spans over a first transverse segment 222-1 of a peripheral portion 220 of the nth adapter element 200, and a peripheral portion 220 of the lth adapter element 200 spans over a second transverse segment 222-2 of a peripheral portion 220 of the nth adapter element 200.

[0111] For example, in this embodiment, n, m and l are 2, 3 and 7 respectively, the peripheral portion 220 of the third adapter element 200-2 spans the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200-2, and the peripheral portion 220 of the seventh adapter element 200-7 spans the second transverse section 222-2 of the peripheral portion 220 of the second adapter element 200. In short, in this embodiment, the peripheral portion 220 of at least one adapter element 200 may selectively include a plurality of transverse sections 222, and the plurality of transverse sections 222 may be spanned by the plurality of peripheral portions 220 of different adapter elements 200, but the present invention is not limited thereto.

[0112] Please refer to Figure 2 and Figure 4 In the present embodiment, a plurality of gate elements GD are sequentially arranged in the second direction d2, and the plurality of gate elements GD include an nth gate element GD, an mth gate element GD, and an rth gate element GD, where n, m, and r are positive integers, and n, m, and r are different from each other; a plurality of transfer elements 200 include an nth transfer element 200, an mth transfer element 200, and an rth transfer element 200 electrically connected to the nth gate element GD, the mth gate element GD, and the rth gate element GD, respectively; a peripheral portion 220 of the rth transfer element 200 further includes a first transverse segment 222-1 and a second straight segment 221-2, the first transverse segment 222-1 of the peripheral portion 220 of the rth transfer element 200 extends in the first direction d1, and the first straight segment 221-2 of the peripheral portion 220 of the rth transfer element 200 extends in the first direction d1. The first straight section 221-1 of the peripheral portion 220 of the rth adapter element 200 is electrically connected to the first transverse section 222-1 of the peripheral portion 220 of the rth adapter element 200, the second straight section 221-2 of the peripheral portion 220 of the rth adapter element 200 extends in the second direction d2, the second straight section 221-2 of the peripheral portion 220 of the rth adapter element 200 is electrically connected to the first transverse section 222-1 of the peripheral portion 220 of the rth adapter element 200, the first transverse section 222-1 of the peripheral portion 220 of the rth adapter element 200 belongs to the first conductive layer, and the first straight section 221-1 and the second straight section 221-2 of the rth adapter element 200 belong to the second conductive layer; the first straight section 221-1 of the peripheral portion 220 of the nth adapter element 200 and the second straight section 221-2 of the peripheral portion 220 of the rth adapter element 200 are substantially aligned in the second direction d2.

[0113] For example, n, m and r are 2, 3 and 9 respectively, the peripheral portion 220 of the third adapter element 200-3 spans the first transverse section 222-1 of the peripheral portion 220 of the second adapter element 200-2; the peripheral portion 220 of the ninth adapter element 200-9 also includes a first transverse section 222-1 and a second straight section 221-2, the first transverse section 222-1 of the peripheral portion 220 of the ninth adapter element 200 extends in the first direction d1, and the first straight section 221-1 of the ninth adapter element 200 is electrically connected to the first transverse section 222-1 of the ninth adapter element 200 200, the first lateral segment 222-1 of the peripheral portion 220 of the 9th adapter element 200-9 extends in the second direction d2, and the second straight segment 221-2 of the peripheral portion 220 of the 9th adapter element 200-9 is electrically connected to the first lateral segment 222-1 of the 9th adapter element 200; in particular, the first straight segment 221-1 of the peripheral portion 220 of the 2nd adapter element 200 and the second straight segment 221-2 of the peripheral portion 220 of the 9th adapter element 200 are substantially aligned in the second direction d2.

[0114] In short, in this embodiment, the first straight section 221 - 1 of the peripheral portion 220 of one adapter element 200 and the second straight section 221 - 2 of the peripheral portion 220 of another adapter element 200 may be substantially aligned in the second direction d2 , but the invention is not limited thereto.

[0115] It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0116] Figure 6 FIG. 1 is a top view of a pixel array substrate 10A according to an embodiment of the present invention.

[0117] Figure 7 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10A according to an embodiment of the present invention. Figure 7 correspond Figure 6 The local r1.

[0118] Figure 8 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention. Figure 8 correspond Figure 7 Multiple peripheral portions 220 of multiple transition elements 200 on the peripheral area 100b.

[0119] exist Figure 7 and Figure 8 In the figure, thin lines represent the transverse segments 222 belonging to the first conductive layer, and thick lines represent the vertical segments 221 belonging to the second conductive layer.

[0120] Please refer to Figure 6 , Figure 7 and Figure 8 The pixel array substrate 10A of the present embodiment is similar to the above-mentioned pixel array substrate 10, and the main difference between the two is that: in the present embodiment, the plurality of pixel structures PX of the same pixel column C can be selectively electrically connected to different plurality of data lines DL, each gate element GD can include two adjacent gate lines GL, and the plurality of pixel structures PX of two adjacent pixel rows R can be electrically connected to the two gate lines GL of the same gate element GD, respectively. In short, in the present embodiment, the pixel array substrate 10 can adopt a two data lines and half gate line (2DhG) driving method.

[0121] Please refer to Figure 6 , Figure 7 and Figure 8In addition, the spanning relationship between the plurality of peripheral portions 220 of the pixel array substrate 10A of the present embodiment is slightly different from the spanning relationship between the plurality of peripheral portions 220 of the aforementioned pixel array substrate 10. A person skilled in the art can compare the spanning relationship between the plurality of peripheral portions 220 of the pixel array substrate 10. Figure 2 and Figure 7 (and / or compare Figure 4 and Figure 8 ) can be known, and I will not elaborate on them one by one here.

[0122] Fig. 9 FIG. 1 is a top view of a pixel array substrate 10B according to an embodiment of the present invention.

[0123] Fig.10 FIG. 1 is an enlarged schematic diagram of a local portion r1 of a pixel array substrate 10B according to an embodiment of the present invention. Fig.10 correspond Fig. 9 The local r1.

[0124] Fig.11 FIG. 2 is an enlarged schematic diagram of a plurality of peripheral portions 220 of a plurality of adapter components 200 according to an embodiment of the present invention. Fig.11 correspond Fig.10 Multiple peripheral portions 220 of multiple transition elements 200 on the peripheral area 100b.

[0125] exist Fig.10 and Fig.11 In the figure, thin lines represent the transverse segments 222 belonging to the first conductive layer, and thick lines represent the vertical segments 221 belonging to the second conductive layer.

[0126] Please refer to Fig. 9 , Fig.10 and Fig.11 The pixel array substrate 10B of this embodiment is similar to the above-mentioned pixel array substrate 10A, and the main difference between the two is that: Figure 6 , Figure 7 and Figure 8 In the embodiment of FIG. 1 , the number of transfer elements 200 electrically connected to the same gate element GD is 4; however, Fig. 9 , Fig.10 and Fig.11 In the embodiment of FIG. 1 , the number of transfer elements 200 electrically connected to the same gate element GD is three.

[0127] Please refer to Fig. 9 , Fig.10 and Fig.11 In addition, the spanning relationship between the plurality of peripheral portions 220 of the pixel array substrate 10B of the present embodiment is slightly different from the spanning relationship between the plurality of peripheral portions 220 of the aforementioned pixel array substrate 10A. A person skilled in the art can compare the spanning relationship between the plurality of peripheral portions 220 of the pixel array substrate 10B and the aforementioned pixel array substrate 10A. Figure 7 and Fig.10 (and / or compare Figure 8 and Fig.11 ) can be known, and I will not elaborate on them one by one here.

[0128] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A pixel array substrate, characterized in that: include: A substrate having an active region and a peripheral region outside the active region; A plurality of data lines are disposed on the substrate and arranged in a first direction; A plurality of gate elements are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction; A plurality of pixel structures are disposed on the active region of the substrate and are electrically connected to the data lines and the gate elements; as well as A plurality of transfer elements are disposed on the substrate and are electrically connected to the gate elements respectively, wherein each of the transfer elements includes a main portion disposed in the active region and a peripheral portion disposed in the peripheral region, and the main portions of the transfer elements are arranged in the first direction; The gate elements include an nth gate element and an mth gate element, n and m are positive integers, and n and m are different; The switching elements include an nth switching element and an mth switching element electrically connected to the nth gate element and the mth gate element respectively; The peripheral portion of each switching element includes a first straight section extending in the second direction, and the first straight section has a signal input end; The peripheral portion of the nth adapter element further includes a first transverse segment extending in the first direction, the first straight segment of the peripheral portion of the nth adapter element is electrically connected to the first transverse segment of the peripheral portion of the nth adapter element, and the first transverse segment of the peripheral portion of the nth adapter element and the first straight segment of the peripheral portion of the nth adapter element belong to different first conductive layers and second conductive layers respectively; The peripheral portion of the m-th adapter element spans across the first transverse segment of the peripheral portion of the n-th adapter element.

2. The pixel array substrate according to claim 1, wherein: The first straight section of the peripheral portion of the nth transfer element and the first straight section of the peripheral portion of the mth transfer element are arranged sequentially in the first direction, the main portion of the nth transfer element and the main portion of the mth transfer element are arranged sequentially in a third direction, and the first direction is opposite to the third direction.

3. The pixel array substrate according to claim 1, wherein: The gate elements are arranged in sequence in the second direction, and the gate elements include a kth gate element, k is a positive integer, and n, m and k are different from each other; the switching elements further include a kth switching element electrically connected to the kth gate element; the peripheral portion of the kth switching element further includes a first transverse segment, and the first transverse segment of the peripheral portion of the kth switching element extends in the first direction. The first transverse segment of the peripheral portion of the kth switching element and the first vertical segment of the peripheral portion of the kth switching element belong to different first conductive layers and second conductive layers respectively; the peripheral portion of a switching element of the switching elements spans the first transverse segment of the peripheral portion of the nth switching element, and the peripheral portion of b switching elements of the switching elements spans the first transverse segment of the peripheral portion of the kth switching element, and a and b are positive integers, and a and b are different.

4. The pixel array substrate according to claim 1, wherein: The gate elements further include a p-th gate element and a q-th gate element. The n-th gate element, the m-th gate element, the p-th gate element and the q-th gate element are sequentially arranged in the second direction. p and q are positive integers, and n <m<p<q; The switching elements further include a p-th switching element and a q-th switching element electrically connected to the p-th gate element and the q-th gate element, respectively, and the first straight section of the peripheral portion of the n-th switching element, the first straight section of the peripheral portion of the m-th switching element, the first straight section of the peripheral portion of the p-th switching element, and the first straight section of the peripheral portion of the q-th switching element are arranged in sequence in the first direction; The peripheral portion of the qth adapter element further includes a first transverse section, the first transverse section of the peripheral portion of the qth adapter element extends from the first straight section of the peripheral portion of the qth adapter element along a third direction, the first direction is opposite to the third direction, the first straight section of the peripheral portion of the qth adapter element is electrically connected to the first transverse section of the peripheral portion of the qth adapter element, and the first straight section of the peripheral portion of the qth adapter element and the first transverse section of the peripheral portion of the qth adapter element belong to different first conductive layers and second conductive layers respectively; The peripheral portion of the p-th transition element spans over the first transverse section of the peripheral portion of the q-th transition element.

5. The pixel array substrate according to claim 1, wherein: The peripheral portion of the nth switching element further includes a second straight section and a second transverse section, the second straight section extends in the second direction, the second transverse section extends in the first direction, the first transverse section of the peripheral portion of the nth switching element is electrically connected to the second straight section of the peripheral portion of the nth switching element, the second straight section of the peripheral portion of the nth switching element is electrically connected to the second transverse section of the peripheral portion of the nth switching element, the first transverse section and the second transverse section of the peripheral portion of the nth switching element belong to the first conductive layer, and the first straight section and the second straight section of the peripheral portion of the nth switching element belong to the second conductive layer.

6. The pixel array substrate according to claim 5, characterized in that: The gate elements further include a lth gate element, l is a positive integer, and n, m and l are different from each other; the switching elements further include a lth switching element electrically connected to the lth gate element; The first transition element spans the second transverse section of the peripheral portion of the nth transition element.

7. The pixel array substrate according to claim 1, wherein: The gate elements further include an r-th gate element, r is a positive integer, and n, m and r are different from each other; the switching elements further include an r-th switching element electrically connected to the r-th gate element; the peripheral portion of the r-th switching element further includes a first transverse section and a second straight section, the first transverse section of the peripheral portion of the r-th switching element extends in the first direction, the first straight section of the peripheral portion of the r-th switching element is electrically connected to the first transverse section of the peripheral portion of the r-th switching element, and the peripheral portion of the r-th switching element The second straight section of the edge extends in the second direction, the second straight section of the peripheral portion of the rth switching element is electrically connected to the first transverse section of the peripheral portion of the rth switching element, the first transverse section of the peripheral portion of the rth switching element belongs to the first conductive layer, the first straight section and the second straight section of the peripheral portion of the rth switching element belong to the second conductive layer; the first straight section of the peripheral portion of the nth switching element and the second straight section of the peripheral portion of the rth switching element are substantially aligned in the second direction.

8. A pixel array substrate, characterized in that: include: A substrate having an active region and a peripheral region outside the active region; A plurality of data lines are disposed on the substrate and arranged in a first direction; A plurality of gate elements are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction; A plurality of pixel structures are disposed on the active region of the substrate and are electrically connected to the data lines and the gate elements; A plurality of transfer elements are disposed on the substrate, wherein each of the transfer elements includes a main portion disposed in the active region, and the main portions of the transfer elements are arranged in the first direction; and An insulating layer is disposed between the main parts of the switching elements and the gate elements, wherein the main parts of the switching elements are electrically connected to the gate elements through a plurality of contact windows of the insulating layer; The pixel structures are arranged into a plurality of pixel rows and a plurality of pixel columns, wherein the pixel columns are arranged sequentially in the first direction, and the pixel rows are arranged sequentially in the second direction, and a coordinate of a pixel structure located at the x-th pixel row and the y-th pixel row is (x-1, y-1), and x and y are positive integers; The contact windows include a first contact window and a second contact window; The pixel structures include a first pixel structure adjacent to the first contact window; The pixel structures include a second pixel structure adjacent to the second contact window; A coordinate of the first pixel structure is (x1-1, y1-1), wherein x1 and y1 satisfy one of the following: (x1-1)=[(a / c)·(y1-1)]+b1, wherein a is a ratio of a width of the active region in the first direction to a width of the active region in the second direction, c is a number of switching elements electrically connected to a gate element, and |b1|>1; A coordinate of the second pixel structure is (x2-1, y2-1), wherein x2 and y2 satisfy the following two: (x2-1)=[(a / c)·(y2-1)]+b2, wherein a is the ratio of the width of the active region in the first direction to the width of the active region in the second direction, c is the number of switching elements electrically connected to a gate element, and |b2|>1; |b1| is not equal to |b2|.

9. The pixel array substrate according to claim 8, wherein: 1<|b1|<20。 10. The pixel array substrate according to claim 9, wherein: 1<|b2|<20。

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