Display panel and display device including the same

Abstract

A display panel and a display device including the display panel are provided. The display panel includes: a substrate including a first region and a second region surrounding the first region; a plurality of display elements located in the second region and including a first display element and a second display element spaced apart from each other, and the first region is located between the first display element and the second display element; a first initialization voltage line extending in a first direction and electrically connected to the first display element; a second initialization voltage line extending in the first direction and electrically connected to the second display element; an auxiliary voltage line disposed on a layer different from the layer on which the first initialization voltage line and the second initialization voltage line are disposed and electrically connecting the first initialization voltage line and the second initialization voltage line spaced apart from each other; and a first insulating layer covering the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line and disposed below the plurality of display elements.

Description

Technical Field

[0001] Aspects of one or more example embodiments relate to a display panel and a display device including the display panel. Background Art

[0002] Recently, the use of display devices has become more diverse. As display devices have become thinner and lighter, their range of use has gradually expanded.

[0003] As display devices are used in various ways, their shapes can be designed in various ways. In addition, functions that can be combined with or related to display devices are increasing.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0005] As a way to increase functions that can be combined with or related to display devices, one or more example embodiments include a display device including a component area located inside a display area where a camera, sensors, etc. can be arranged.

[0006] Additional aspects will be set forth in part in the following description, will become apparent in part from the description, or may be learned by practice of the disclosed example embodiments.

[0007] According to one or more example embodiments, a display panel includes: a substrate including a first region and a second region surrounding the first region; a plurality of display elements arranged in the second region and including a first display element and a second display element spaced apart from each other, and the first region is located between the first display element and the second display element; a first initialization voltage line extending in a first direction and electrically connected to the first display element; a second initialization voltage line extending in the first direction and electrically connected to the second display element; an auxiliary voltage line arranged on a layer different from the layer on which the first initialization voltage line and the second initialization voltage line are arranged and electrically connecting the first initialization voltage line and the second initialization voltage line spaced apart from each other; and a first insulating layer covering the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line and arranged below the plurality of display elements.

[0008] According to some example embodiments, each of the plurality of display elements may include a pixel electrode, a counter electrode located above the pixel electrode, and an emission layer located between the pixel electrode and the counter electrode, and the auxiliary voltage line may be arranged below the pixel electrode, where the first insulating layer is located between the auxiliary voltage line and the pixel electrode.

[0009] According to some example embodiments, the display panel may further include a second insulating layer disposed between the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line.

[0010] According to some example embodiments, the display panel may further include thin film transistors and storage capacitors, the thin film transistors and the storage capacitors being electrically connected to corresponding ones of the plurality of display elements, wherein the first initialization voltage line and the second initialization voltage line may include a material that is the same as a material of one of the electrodes of the storage capacitor.

[0011] According to some example embodiments, the storage capacitor may include a bottom electrode and a top electrode, and the first initialization voltage line and the second initialization voltage line may include a material that is the same as a material of the top electrode.

[0012] According to some example embodiments, the display panel may further include contact metal connecting one of the thin film transistors to the corresponding display element, and the auxiliary voltage line may include a material that is the same as a material of the contact metal.

[0013] According to some example embodiments, the display panel may further include an intermediate metal layer disposed between the first initialization voltage line and the auxiliary voltage line and between the second initialization voltage line and the auxiliary voltage line.

[0014] According to some example embodiments, the display panel may further include: a first scan line extending in a first direction and electrically connected to a first display element; and a second scan line extending in the first direction and electrically connected to a second display element, wherein the first scan line may be spaced apart from the second scan line, and a first region is located between the first scan line and the second scan line.

[0015] According to some example embodiments, the display panel may further include: a first emission control line extending in a first direction and electrically connected to a first display element; and a second emission control line extending in the first direction and electrically connected to a second display element, wherein the first emission control line may be spaced apart from the second emission control line, and a first region is located between the first emission control line and the second emission control line.

[0016] According to some example embodiments, the display panel may further include an initialization power line disposed in an outer region of the substrate, wherein the initialization power line may be disposed between the substrate and the first insulating layer.

[0017] According to some example embodiments, the display panel may further include: a first data line extending in a second direction intersecting the first direction and connected to a first display element; and a second data line extending in the second direction and connected to a second display element, wherein the initialization power line may include a material that is the same as a material of the first data line or the second data line.

[0018] According to one or more embodiments, a display device including at least one component area disposed inside a display area and a non-display area surrounding the display area includes: a plurality of display elements constituting the display area, each of the plurality of display elements including a pixel electrode, an emission layer, and a counter electrode sequentially stacked; a first initialization voltage line electrically connected to a first display element among the plurality of display elements and extending in a first direction in the display area; a second initialization voltage line electrically connected to a second display element among the plurality of display elements, extending in the first direction in the display area, and spaced apart from the first initialization voltage line, and the at least one component area is located between the first initialization voltage line and the second initialization voltage line; an auxiliary voltage line electrically connecting the first initialization voltage line to the second initialization voltage line; and a first insulating layer disposed between the auxiliary voltage line and the pixel electrode.

[0019] According to some example embodiments, the display device may further include a second insulating layer disposed between the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line.

[0020] According to some example embodiments, the display device may further include a thin film transistor and a storage capacitor, the thin film transistor being electrically connected to a corresponding display element among the plurality of display elements, the storage capacitor including a bottom electrode and a top electrode, wherein the first initialization voltage line and the second initialization voltage line may include a material same as that of the top electrode of the storage capacitor.

[0021] According to some example embodiments, the display device may further include a contact metal connecting one of the thin film transistors to the corresponding display element, wherein the auxiliary voltage line may include a material same as that of the contact metal.

[0022] According to some example embodiments, the first initialization voltage line and the second initialization voltage line may be disposed on the same layer.

[0023] According to some example embodiments, the display device may further include an intermediate metal layer disposed between the first initialization voltage line and the auxiliary voltage line and between the second initialization voltage line and the auxiliary voltage line.

[0024] According to some example embodiments, the display device may further include: a first scan line extending in the first direction and electrically connected to the first display element; and a second scan line extending in the first direction and electrically connected to the second display element, wherein the first scan line may be spaced apart from the second scan line, and the at least one component area is located between the first scan line and the second scan line.

[0025] According to some example embodiments, the display device may further include: a first emission control line extending in a first direction and electrically connected to a first display element; and a second emission control line extending in the first direction and electrically connected to a second display element, wherein the first emission control line may be spaced apart from the second emission control line, and the at least one component area is located between the first emission control line and the second emission control line.

[0026] According to some example embodiments, the display device may further include an initialization power line disposed in a non-display area.

[0027] According to some example embodiments, the initialization power line may be disposed under a first insulating layer.

[0028] According to some example embodiments, the display device may further include: a first data line extending in a second direction intersecting the first direction and connected to a first display element; and a second data line extending in the second direction and connected to a second display element, wherein the initialization power line may include a material having the same material as the first data line or the second data line.

[0029] According to some example embodiments, the at least one component area may include a first component area and a second component area arranged along the first direction.

[0030] According to some example embodiments, a first initialization voltage line may be located on one side of the first component area, a second initialization voltage line may be located on one side of the second component area, and the first component area and the second component area may be located between the first initialization voltage line and the second initialization voltage line spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features, and characteristics of certain example embodiments of the disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to some example embodiments;

[0033] Figures 2A to 2D is a cross-sectional view of a display device according to some example embodiments;

[0034] Figures 3A to 3C is a cross-sectional view of a display device according to some example embodiments;

[0035] Figure 4A is a plan view of a display panel according to some example embodiments;

[0036] Figure 4B is a plan view of a display panel according to some example embodiments;

[0037] Figure 5 is an equivalent circuit diagram of one of the pixels of a display panel according to some example embodiments;

[0038] Figure 6A and Figure 6B is a plan view of one of the pixels of a display panel according to some example embodiments;

[0039] Figure 7A shows a cross-sectional view of the pixel taken along the line Aa - Aa' and the line Ba - Ba' of Figure 6A ; Figure 7B shows a cross-sectional view of the pixel taken along the line Ab - Ab' and the line Bb - Bb' of Figure 6B ;

[0040] Figure 8A and Figure 8B is a plan view of the wiring around the component area according to some example embodiments;

[0041] Figure 9A and Figure 9B are cross-sectional views of the wiring taken along the line IX - IX' of Figure 8A and Figure 8B respectively;

[0042] Figure 10 is a plan view of a display panel according to some example embodiments;

[0043] Figure 11 is a plan view of the wiring around a plurality of component areas according to some example embodiments;

[0044] Figure 12 is a plan view of the wiring around the second non-display area according to some example embodiments; and

[0045] Figure 13A and Figure 13B are cross-sectional views of a display device according to some example embodiments. DETAILED DESCRIPTION

[0046] Aspects of some embodiments will now be described in more detail with reference to their examples shown in the drawings, in which like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by reference to the drawings to explain aspects of the present description. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] In the following, aspects of some example embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or corresponding elements, and their repeated description is omitted.

[0048] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another.

[0049] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0050] It will also be understood that the term "comprising" and its variants as used herein specify the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0051] It will be understood that when a layer, region, or element is referred to as being "formed on" another layer, region, or element, the layer, region, or element may be formed directly or indirectly on the other layer, region, or element. That is, for example, there may be intermediate layers, regions, or elements.

[0052] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0053] When a certain embodiment can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0054] In this specification, "A and / or B" means A or B, or A and B. In this specification, "at least one of A and B" means A or B, or A and B.

[0055] It will be understood that when a layer, region or element is referred to as being "connected" to another layer, region or element, the layer, region or element may be "directly connected" to the other layer, region or element, and / or may be "indirectly connected" to the other layer, region or element, with other layers, regions or elements disposed therebetween. For example, it will be understood that when a layer, region or element is referred to as being "electrically connected" to another layer, region or element, the layer, region or element may be "directly electrically connected" to the other layer, region or element, and / or may be "indirectly electrically connected" to the other layer, region or element, with other layers, regions or elements disposed therebetween.

[0056] In the following examples, the x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0057] Figure 1 is a perspective view of a display device 1 according to some example embodiments.

[0058] Referring to Figure 1 , the display device 1 may include a display area DA that emits light and a non-display area NDA that does not emit light. The display device 1 may display an image by using light emitted from a plurality of pixels P (see Figure 4A ) arranged in the display area DA.

[0059] The display device 1 may include, for example, a component area OA located within or at least partially within the display area DA. That is, the component area OA may be at least partially surrounded by the display area DA. For example, as Figure 1 shown, according to some example embodiments, the component area OA may be completely surrounded by the display area DA.

[0060] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 surrounds the component area OA, and the second non-display area NDA2 surrounds the exterior of the display area DA. For example, the first non-display area NDA1 may completely surround the component area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0061] Thus, according to some example embodiments, the display device 1 may include a component area OA located within or surrounded by the first non-display area NDA1, and both the first non-display area NDA1 and the component area OA may be located within the display area DA. However, embodiments of the present invention are not limited to the component area OA being completely located within the display area DA. For example, according to some example embodiments, the component area OA may extend outside the boundary or edge of the display area DA. Additionally, according to some example embodiments, the first non-display area NDA1 or the second non-display area NDA2 may be omitted, or the first non-display area NDA1 and the second non-display area NDA2 may be connected to each other or merged with each other.

[0062] As described below with reference to Figure 2A the component area OA may be a location where the component 20 is disposed. The component area OA may be a transmissive area through which light and / or sound output from the component to the outside or traveling from the outside toward the component may pass. According to some example embodiments, in the case where light passes through the component area OA, the light transmittance may be 50% or greater (or according to some example embodiments, 70% or greater, 75% or greater, 80% or greater, 85% or greater, or 90% or greater).

[0063] Hereinafter, although the display device 1 is described in the context of an organic light-emitting display device as an example, the display device according to embodiments of the present disclosure is not limited thereto. According to some example embodiments, the display device 1 may be various display devices, such as, for example, an inorganic light-emitting display and a quantum dot light-emitting display. For example, the emission layer of the display element provided to the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

[0064] Although the component area OA is shown as being disposed on one side (upper right side) of the display area DA in Figure 1 , embodiments of the present disclosure are not limited thereto. For example, according to the design of the display device 1 (and / or the position of the component area OA), the shape of the display area DA may be circular, elliptical, or a polygon such as a triangle or a pentagon, or any other suitable shape. The position of the component area OA may be variously changed. For example, the component area OA may be disposed in the upper central portion of the plane (e.g., x-y plane) of the display area DA.

[0065] Figures 2A to 2D is a cross-sectional view of the display device 1 according to an embodiment. For example, Figures 2A to 2D may correspond to a cross-section taken along the line II-II' of Figure 1 .

[0066] Referring to Figure 2A, the display device 1 may include a display panel 10 and a component 20. The display panel 10 includes display elements, and the component 20 corresponds to the component area OA.

[0067] The display panel 10 may include a substrate 100, a package substrate 300, and a display layer 200 between the substrate 100 and the package substrate 300. The package substrate 300 serves as a package member facing the substrate 100. A sealing material (sealant) 350 covering the lateral sides of the display layer 200 may be disposed between the substrate 100 and the package substrate 300. Although in Figure 2A it is shown that the sealing material 350 is disposed on two opposite sides of the component area OA, when viewed in a direction perpendicular to the main surface of the substrate 100 (e.g., when viewed from a plan view or a direction perpendicular to the flat surface of the display panel 10), the component area OA may be completely surrounded by the sealing material 350.

[0068] The substrate 100 may include glass or a polymer resin. The polymer resin may include any suitable polymer resin material (e.g., polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyacrylate, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP)). The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing the above polymer resin and an inorganic layer. The package substrate 300 may include any suitable package substrate material, such as glass or a polymer resin.

[0069] The display layer 200 may include a circuit layer, an organic light-emitting diode OLED, and an insulating layer IL between the circuit layer and the organic light-emitting diode OLED. The circuit layer includes a thin-film transistor TFT, and the organic light-emitting diode OLED serves as a display element connected to the thin-film transistor TFT. The thin-film transistor TFT and the organic light-emitting diode OLED connected thereto may be disposed in the display area DA. Some wirings WL of the display layer 200 may be located in the first non-display area NDA1. The wirings WL may provide signals or voltages (e.g., set or predetermined signals or voltages) to the pixels P spaced apart from each other between which the component area OA is located. Although in Figure 2A it is shown that the wirings WL in the first non-display area NDA1 do not overlap with the sealing material 350, according to some exemplary embodiments, a part of the sealing material 350 may overlap with the wirings WL.

[0070] The display panel 10 may include a through hole 10H corresponding to the component area OA. For example, the substrate 100 may include a through hole 100H corresponding to the component area OA, and the encapsulation substrate 300 may include a through hole 300H corresponding to the component area OA. The display layer 200 may include a through hole corresponding to the component area OA.

[0071] According to some example embodiments, elements such as an input sensing member, an anti-reflection member, and a transparent window may be further disposed on the display panel 10. The input sensing member senses a touch input, and the anti-reflection member includes a polarizer and a retarder or a color filter and a black matrix.

[0072] The component 20 may be located in the component area OA. The component 20 may be an electronic component that uses light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance or identify a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. The electronic component that uses light may use light in various wavelength bands such as visible light, infrared light, and ultraviolet light. As Figure 2A shown, in the case where the display panel 10 includes the through hole 10H corresponding to the component area OA, the light or sound output from or received by the electronic component can be utilized more effectively.

[0073] Different from the display panel 10 including the through hole 10H corresponding to the component area OA, some elements of the display panel 10 may not include a through hole. For example, as Figure 2B shown, the encapsulation substrate 300 includes the through hole 300H corresponding to the component area OA, but the substrate 100 may not include a through hole.

[0074] Optionally, as Figure 2C and Figure 2D shown, neither the substrate 100 nor the encapsulation substrate 300 may include a through hole corresponding to the component area OA. In Figure 2C this case, the sealing material 350 may be disposed in the first non-display area NDA1 to surround the component area OA.

[0075] Different from Figure 2C this, in Figure 2D this case, the sealing material 350 may not be provided around the component area OA. The external sealing material 360 may be located in the second non-display area NDA2, and the display layer 200 may be isolated from the external air by bonding the substrate 100 to the encapsulation substrate 300. According to some example embodiments, Figures 2A to 2C the display device 1 of

[0076] Figure 2DThe insulating layer IL may have an opening IL-OP corresponding to the component area OA. According to some example embodiments, in the component area OA, no element may be disposed between the substrate 100 and the encapsulation substrate 300. According to some example embodiments, a part of an inorganic insulating layer (multiple inorganic insulating layers) such as a buffer layer may be retained in the component area OA.

[0077] Although the component 20 is shown below the display panel 10, i.e., on one side of the substrate 100, the component 20 may be at least partially inserted and located inside the through hole 10H to overlap with the lateral sides of the through hole 10H defined in the Figures 2A to 2D display panel 10. Figure 2A

[0078] The component 20 may include another member in addition to the electronic element. According to some example embodiments, in the case where the display device 1 is used as a smart watch or a dashboard for a vehicle, the component 20 may be a member such as a clock hand or a needle indicating information (e.g., set or predetermined information) (e.g., the speed of the vehicle, etc.). Optionally, the component 20 may include an element such as an accessory that enhances the aesthetic of the display panel 10.

[0079] Figures 3A to 3C is a cross-sectional view of the display device 1 according to other embodiments and may correspond to the cross-section of the display device 1 taken along the Figure 1 line II-II'.

[0080] Referring to Figure 3A and similar to the display device 1 described with reference to Figure 2A , the display device 1 may include a display panel 10 and a component 20. In addition, according to some example embodiments, the display device 1 may further include an input sensing member, an anti-reflection member, a window, etc. disposed on the display panel 10 for sensing touch input.

[0081] Different from the display panel 10 including the sealing material 350 and the encapsulation substrate 300 as the encapsulation member described above with reference to Figure 2A , the display panel 10 according to the present embodiment may include a thin film encapsulation layer 300' as the encapsulation member. When the display panel 10 includes the thin film encapsulation layer 300' as the encapsulation member, the flexibility of the display panel 10 can be further improved. Hereinafter, for the sake of convenience of description, the differences will be mainly described.

[0082] The thin film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, as Figure 3A ​As shown, the thin film encapsulation layer 300' may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0083] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a suitable inorganic encapsulation layer material, for example, at least one inorganic insulating material selected from the group consisting of aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc peroxide (ZnO2), silicon oxide (SiO2), silicon nitride (SiN x ) and silicon oxynitride (SiON). The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0084] The display panel 10 may include a through hole 10H corresponding to the component area OA. For example, the substrate 100 may include a through hole 100H corresponding to the component area OA, the display layer 200 may include a through hole 200H corresponding to the component area OA, and the thin film encapsulation layer 300' may include a through hole 300H corresponding to the component area OA. The thin film encapsulation layer 300' (for example, the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320) may all include holes corresponding to the component area OA. The size of the holes in the organic encapsulation layer 320 may be larger than the size of the holes in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, so that the first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 around the component area OA.

[0085] Unlike Figure 3A , some components of the display panel 10 may not include through holes. As Figure 3B shown, the display layer 200 may include a through hole 200H corresponding to the component area OA, the thin film encapsulation layer 300' may include a through hole 300H corresponding to the component area OA, but the substrate 100 may not include a through hole.

[0086] According to some example embodiments, as Figure 3C shown, all of the substrate 100, the display layer 200, and the thin film encapsulation layer 300' may not include through holes corresponding to the component area OA.

[0087] As Figure 3B and Figure 3C shown, even if the substrate 100 does not include the through hole 100H, at least a part of the portion of the display layer 200 corresponding to the component area OA will be removed, so that the light transmittance of the electronic component as the component 20 can be ensured.

[0088] In the case where the thin film encapsulation layer 300' does not include a through hole, at least one inorganic encapsulation layer and at least one organic encapsulation layer can both cover the portion of the substrate 100 in the component area OA. For example, the display layer 200 disposed between the substrate 100 and the thin film encapsulation layer 300' may not cover the portion of the substrate 100 corresponding to the component area OA. The portion of the substrate 100 corresponding to the component area OA may be covered by the thin film encapsulation layer 300'.

[0089] Although in Figures 3A to 3C it is shown that all the insulating layers IL corresponding to the component area OA are removed, in the display panel 10 according to some example embodiments, some of the layers (being multiple layers) of the insulating layers IL corresponding to the component area OA may be removed.

[0090] Although in Figures 3A to 3C it is shown that the component 20 is located below the display panel 10, that is, on one side of the substrate 100, the component 20 may be at least partially inserted and located inside the through hole 10H to overlap with the lateral sides of the through hole 10H defined in the Figure 3A display panel 10.

[0091] Figure 4A and Figure 4B are plan views of the display panel 10 according to some example embodiments, Figure 5 and

[0092] is an equivalent circuit diagram of one of the pixels P of the display panel 10 according to some example embodiments. Figure 4A Referring to

[0093] As Figure 5 shown, the pixel P may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. The plurality of thin film transistors and the storage capacitor may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0094] The plurality of thin film transistors may include a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0095] The signal lines include a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The scan line SL transmits a scan signal Sn to the switching thin-film transistor T2 and the compensation thin-film transistor T3. The previous scan line SL-1 transmits a previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7. The emission control line EL transmits an emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6. The data line DL intersects with the scan line SL and transmits a data signal Dm.

[0096] The driving voltage line PL transmits a driving voltage ELVDD (also referred to as the first power) to the driving thin-film transistor T1. The initialization voltage line VL transmits an initialization voltage Vint that initializes the driving thin-film transistor T1 and the pixel electrode of the organic light-emitting diode OLED.

[0097] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL through the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode OLED through the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supplies a driving current I OLED to the organic light-emitting diode OLED.

[0098] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL. The switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1 and is simultaneously connected to the driving voltage line PL through the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0099] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin film transistor T3 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and is simultaneously connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the drive gate electrode G1 of the drive thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and the drive thin film transistor T1 can be compensated by electrically connecting the drive gate electrode G1 of the drive thin film transistor T1 to the drive drain electrode D1.

[0100] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL. The first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 and transmits the initialization voltage Vint to the drive gate electrode G1 of the drive thin film transistor T1, thereby initializing the voltage of the drive gate electrode G1 of the drive thin film transistor T1.

[0101] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL. The operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0102] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0103] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to an emission control signal En transmitted through an emission control line EL, so that a driving voltage ELVDD is transmitted to the organic light emitting diode OLED, thereby causing a driving current I OLED to flow through the organic light emitting diode OLED.

[0104] A second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to a previous scan line SL-1, and a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to an emission control drain electrode D6 of the emission control thin film transistor T6 and a pixel electrode of the organic light emitting diode OLED. A second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to a first initialization source electrode S4 of the first initialization thin film transistor T4 and an initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to a previous scan signal Sn-1 transmitted through the previous scan line SL-1 and can initialize the pixel electrode of the organic light emitting diode OLED.

[0105] Although Figure 5 it is shown that the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, the embodiments are not limited thereto. For example, according to some example embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., a next scan line) and driven in response to a signal transmitted through the separate signal line.

[0106] A second storage capacitor plate Cst2 of the storage capacitor Cst is connected to a driving voltage line PL, and a counter electrode of the organic light emitting diode OLED is connected to a common voltage ELVSS (also referred to as a second power). Thus, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1 OLED and emit light concurrently to display an image.

[0107] Although in Figure 5 it is shown that both the compensation thin film transistor T3 and the first initialization thin film transistor T4 have dual gate electrodes, both the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0108] Referring again to Figure 4A, each pixel P can be electrically connected to a driving circuit disposed in a non-display area NDA (e.g., the second non-display area NDA2). The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power supply line 160, the second power supply line 170, the first initialization power supply line 181, and the second initialization power supply line 182 can be disposed in the second non-display area NDA2.

[0109] The first scan driving circuit 110 can supply a scan signal Sn to each pixel P through a scan line SL. The first scan driving circuit 110 can provide an emission control signal En to each pixel P through an emission control line EL. The second scan driving circuit 120 can be parallel to the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. Some pixels P disposed in the display area DA can be electrically connected to the first scan driving circuit 110. Other pixels P not connected to the first scan driving circuit 110 can be electrically connected to the second scan driving circuit 120. According to some example embodiments, one of the first scan driving circuit 110 and the second scan driving circuit 120 can be omitted.

[0110] The terminal 140 can be disposed on one side of the substrate 100. The terminal 140 can be exposed without being covered by an insulating layer and electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB can be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits power or signals of a controller to the display panel 10. The printed circuit board PCB can transmit control signals generated by the controller to the first scan driving circuit 110 and the second scan driving circuit 120.

[0111] The data driving circuit 150 can be electrically connected to a data line DL. A data signal Dm of the data driving circuit 150 can be provided to each pixel P through a connection line 151 connected to the terminal 140 and a data line DL connected to the connection line 151. Although the data driving circuit 150 is shown disposed on the printed circuit board PCB in Figure 4A and Figure 4B , according to some example embodiments, the data driving circuit 150 can be disposed on the substrate 100. For example, the data driving circuit 150 can be disposed between the terminal 140 and the first power supply line 160.

[0112] The first power supply line 160 may include a first sub-line 162 and a second sub-line 163 that are parallel to each other and extend in the x direction, and the display area DA is located between the first sub-line 162 and the second sub-line 163. The driving voltage line PL extending across the display area DA may be connected to the first sub-line 162 and the second sub-line 163. The second power supply line 170 may have an annular shape that has an open side and partially surrounds the display area DA. As described above, the first power supply line 160 may supply the first power ELVDD (see Figure 5 ) to each pixel P, and the second power supply line 170 may supply the second power ELVSS (see Figure 5 ) to each pixel P.

[0113] The first initialization power supply line 181 and the second initialization power supply line 182 may be arranged in the second non-display area NDA2. The first initialization power supply line 181 has a shape that at least surrounds the left side of the display area DA and may extend in the y direction, and the second initialization power supply line 182 has a shape that at least surrounds the right side of the display area DA and may extend in the y direction. For example, the first initialization power supply line 181 and the second initialization power supply line 182 may be spaced apart from each other, and the display area DA is between the first initialization power supply line 181 and the second initialization power supply line 182. The first initialization power supply line 181 and the second initialization power supply line 182 may extend in the y direction, and a part of the first initialization power supply line 181 and the second initialization power supply line 182 may have a shape that bends toward the display area DA along the edge corner of the display area DA. The first initialization power supply line 181 and the second initialization power supply line 182 may supply an initialization voltage to each pixel P through the initialization voltage line VL.

[0114] The component area OA may be located inside the display area DA. A plurality of pixels P may be arranged around the component area OA. A plurality of pixels P may surround the component area OA.

[0115] As Figure 4A shown, the component area OA may be arranged in the upper right part of the display area DA. According to some example embodiments, as Figure 4B shown, the component area OA may be arranged in the upper central part of the display area DA. For example, in the case where the component area OA is arranged in the central part of the display area DA, the difference in emission characteristics between the pixels P on the left side of the component area OA and the pixels P on the right side of the component area OA may be reduced. According to some example embodiments, the component area OA may be arranged at various positions inside the display area DA, such as the upper left part, the lower right part, the lower left part, and the central part inside the display area DA. Although in Figure 4A and Figure 4BA component area OA is shown, but according to some example embodiments, the component area OA may be set to a plurality of component areas inside the display area DA.

[0116] A bypass line may be arranged in the first non-display area NDA1, and the bypass line applies a signal or power (e.g., a set or predetermined signal or power) to pixels P spaced apart from each other around the component area OA. The related structure will be described below with reference to FIG. 8.

[0117] Referring to Figure 4A and Figure 4B The display panel 10 described may have the pattern of the substrate 100. For example, the substrate 100 may include a first area, a second area, a third area, and a fourth area. The first area corresponds to the component area OA, the second area corresponds to the display area DA, the third area corresponds to the first non-display area NDA1, and the fourth area corresponds to the second non-display area NDA2. A plurality of pixels P are arranged in the second area of the substrate 100 to constitute the display area DA of the display panel 10 where an image can be displayed. The fourth area of the substrate 100 is the outer area of the substrate 100 surrounding the second area. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power supply line 160, the second power supply line 170, the first initialization power supply line 181, and the second initialization power supply line 182 may be arranged in the fourth area.

[0118] Figure 6A and Figure 6B is a plan view of one of the pixels P of the display panel 10 according to some example embodiments, Figure 7A showing a cross-sectional view of the pixel P taken along the Figure 6A lines Aa - Aa' and Ba - Ba', Figure 7B showing a cross-sectional view of the pixel P taken along the Figure 6B lines Ab - Ab' and Bb - Bb'.

[0119] Referring to Figure 6A and Figure 7A the driving thin film transistor T1, the switching thin film transistor T2, the compensating thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be arranged along the semiconductor layer 1130.

[0120] Some regions of the semiconductor layer 1130 may correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensating thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensating thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be connected to each other and may have a shape that bends in various directions.

[0121] The semiconductor layer 1130 is located on the substrate 100. In Figure 7A a part of the semiconductor layer 1130 (for example, the driving semiconductor layer 1130a, the compensating semiconductor layer 1130c, and the emission control semiconductor layer 1130f) is shown to be located on the substrate 100.

[0122] The buffer layer IL1 may be formed under the semiconductor layer 1130, and the buffer layer IL1 includes inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0123] The semiconductor layer 1130 may include a channel region, a source region, and a drain region, and the source region and the drain region are on two opposite sides of the channel region. The source region and the drain region may be the source electrode and the drain electrode of the thin film transistor, respectively. Hereinafter, for convenience of description, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0124] The driving thin film transistor T1 includes a driving gate electrode G1, a driving source electrode S1, and a driving drain electrode D1. The driving gate electrode G1 overlaps with the driving channel region C1, and the driving source electrode S1 and the driving drain electrode D1 are on two opposite sides of the driving channel region C1. The driving channel region C1 that overlaps with the driving gate electrode G1 may be formed with a long channel length in a narrow space by having a structure that bends in various shapes. For example, when the length of the driving channel region is formed to be long, the driving range of the gate voltage becomes wider, and the gray scale of the light emitted from the organic light emitting diode OLED can be controlled more finely and the display quality can be improved.

[0125] The switching thin film transistor T2 includes a switching gate electrode G2, a switching source electrode S2, and a switching drain electrode D2. The switching gate electrode G2 overlaps with the switching channel region, and the switching source electrode S2 and the switching drain electrode D2 are on two opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0126] The compensation thin film transistor T3 is a double-gate thin film transistor and may include a compensation gate electrode G3, a compensation source electrode S3, and a compensation drain electrode D3. The compensation gate electrode G3 overlaps with two compensation channel regions C3, and the compensation source electrode S3 and the compensation drain electrode D3 are on two opposite sides of the compensation channel region C3. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through the node connection line 1174 described below.

[0127] The first initialization thin film transistor T4 is a double-gate thin film transistor and may include a first initialization gate electrode G4, a first initialization source electrode S4, and a first initialization drain electrode D4. The first initialization gate electrode G4 overlaps with two first initialization channel regions, and the first initialization source electrode S4 and the first initialization drain electrode D4 are on two opposite sides of the first initialization channel region.

[0128] The operation control thin film transistor T5 may include an operation control gate electrode G5, an operation control source electrode S5, and an operation control drain electrode D5. The operation control gate electrode G5 overlaps with the operation control channel region, and the operation control source electrode S5 and the operation control drain electrode D5 are on two opposite sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0129] The emission control thin film transistor T6 may include an emission control gate electrode G6, an emission control source electrode S6, and an emission control drain electrode D6. The emission control gate electrode G6 overlaps with the emission control channel region, and the emission control source electrode S6 and the emission control drain electrode D6 are on two opposite sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0130] The second initialization thin film transistor T7 may include a second initialization gate electrode G7, a second initialization source electrode S7, and a second initialization drain electrode D7. The second initialization gate electrode G7 overlaps with the second initialization channel region, and the second initialization source electrode S7 and the second initialization drain electrode D7 are on two opposite sides of the second initialization channel region.

[0131] The above thin film transistors may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0132] The gate insulating layer IL2 (see Figure 7A ) may be disposed on the semiconductor layer 1130. The scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1 may be disposed on the gate insulating layer IL2.

[0133] The gate insulating layer IL2 may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. The scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1 may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and their alloys.

[0134] The scan line SL may extend in the x direction. Some regions of the scan line SL may correspond to the switching gate electrode G2 and the compensation gate electrode G3, respectively. For example, the regions of the scan line SL that overlap with the switching thin film transistor T2 and the compensation thin film transistor T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0135] The previous scan line SL-1 may extend in the x direction and some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, the region of the previous scan line SL-1 that overlaps with the channel region of the first initialization thin film transistor T4 may be the first initialization gate electrode G4, and the region of the previous scan line SL-1 that overlaps with the channel region of the second initialization thin film transistor T7 may be the second initialization gate electrode G7.

[0136] The emission control line EL may extend in the x direction. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, the region of the emission control line EL that overlaps with the channel region of the operation control thin film transistor T5 may be the operation control gate electrode G5, and the region of the emission control line EL that overlaps with the channel region of the emission control thin film transistor T6 may be the emission control gate electrode G6.

[0137] The driving gate electrode G1 is an island-type electrode and may be connected to the compensation thin film transistor T3 through the node connection line 1174.

[0138] The electrode voltage line HL and the initialization voltage line VL may be disposed above the scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1, and the first interlayer insulating layer IL3 (see Figure 7A ) including inorganic materials is therebetween.

[0139] As Figure 6A shown, the electrode voltage line HL may extend in the x direction to cross the data line DL and the driving voltage line PL. A part of the electrode voltage line HL may cover at least a part of the driving gate electrode G1 and together with the driving gate electrode G1 form a storage capacitor Cst. For example, the driving gate electrode G1 may be used as the first storage capacitor plate Cst1 (or bottom electrode) of the storage capacitor Cst, and a part of the electrode voltage line HL may be used as the second storage capacitor plate Cst2 (or top electrode) of the storage capacitor Cst.

[0140] The second storage capacitor plate Cst2, which is part of the electrode voltage line HL, is electrically connected to the driving voltage line PL. As shown in Figure 6A , the electrode voltage line HL is connected to the driving voltage line PL arranged on the electrode voltage line HL through the contact hole 1158. The electrode voltage line HL may have the same voltage level (constant voltage, such as +5V) as the driving voltage line PL. The electrode voltage line HL is a kind of driving voltage line in the lateral (x direction).

[0141] Since the driving voltage line PL extends in the y direction and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x direction intersecting the y direction, a plurality of driving voltage lines PL and electrode voltage lines HL can form a mesh structure in the display area DA.

[0142] The initialization voltage line VL may extend in the x direction. The initialization voltage line VL may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the initialization connection line 1173. The initialization voltage line VL may be arranged on the first interlayer insulating layer IL3. For example, the initialization voltage line VL may be arranged on the same layer (e.g., the first interlayer insulating layer IL3) as the layer on which the electrode voltage line HL and / or the second storage capacitor plate Cst2 serving as the top electrode of the storage capacitor Cst is arranged, and may include the same material as the second storage capacitor plate Cst2.

[0143] The electrode voltage line HL and the initialization voltage line VL may include metals such as Mo, Al, Cu, and Ti and their alloys.

[0144] The data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the first connection metal (or contact metal) 1175 may be arranged above the second storage capacitor plate Cst2 and the electrode voltage line HL, and the second interlayer insulating layer IL4 including an inorganic material (see Figure 7A ) is therebetween. Since the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the first connection metal 1175 are formed during the same process, they may include the same material. The data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the first connection metal 1175 may include a single layer or multiple layers including at least one of Al, Cu, Ti, etc. According to some exemplary embodiments, the driving voltage line PL and the data line DL may have a multilayer structure of Ti / Al / Ti.

[0145] The data line DL can extend in the y direction and be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A part of the data line DL can be the switching source electrode S2 (i.e., the electrode layer).

[0146] As described above, the driving voltage line PL can extend in the y direction and be connected to the electrode voltage line HL through the contact hole 1158. In addition, the driving voltage line PL can be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL can be connected to the operation control source electrode S5 through the contact hole 1155.

[0147] One end of the initialization connection line 1173 can be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the contact hole 1152, and the other end of the initialization connection line 1173 can be connected to the initialization voltage line VL through the contact hole 1151.

[0148] One end of the node connection line 1174 can be connected to the compensation drain electrode D3 through the contact hole 1156, and the other end of the node connection line 1174 can be connected to the driving gate electrode G1 through the contact hole 1157.

[0149] The first planarization insulating layer IL5 can be located on the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the first connection metal 1175. The first planarization insulating layer IL5 can include an organic insulating material containing a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, and / or a blend thereof.

[0150] As Figure 6B and Figure 7B shown, the second connection metal 1176 can be further disposed on the first planarization insulating layer IL5. The second connection metal 1176 can be disposed on the first planarization insulating layer IL5, and the second connection metal 1176 can be covered by the second planarization insulating layer IL6. The second planarization insulating layer IL6 can include a suitable organic insulating material such as acrylic-based, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The second connection metal 1176 can include a single layer or multiple layers containing at least one of Al, Cu, Ti, etc. The second connection metal 1176, the driving voltage line PL, and the data line DL can include a multi-layer structure of Ti / Al / Ti.

[0151] The first connecting metal 1175 can be connected to the drain region of the emission control thin film transistor T6 through the contact hole 1153. The first connecting metal 1175 can be the emission control drain electrode D6 of the emission control thin film transistor T6. The second connecting metal 1176 can be connected to the first connecting metal 1175 through the contact hole 1163 formed in the first planarization insulating layer IL5, and the pixel electrode 210 can be electrically connected to the second connecting metal 1176 through the contact hole CH defined in the second planarization insulating layer IL6. As Figure 6A and Figure 7A shown, in the case where the second connecting metal 1176 and the second planarization insulating layer IL6 are omitted, the pixel electrode 210 can be electrically connected to the first connecting metal 1175 through the contact hole CH defined in the first planarization insulating layer IL5.

[0152] The pixel electrode 210 can include a reflective layer containing, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof. According to some example embodiments, the pixel electrode 210 can further include a layer including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) on or under the reflective layer.

[0153] The pixel defining layer PDL can be disposed on the pixel electrode 210, and the pixel defining layer PDL covers the edge of the pixel electrode 210. The pixel defining layer PDL can include an opening exposing a part of the pixel electrode 210. The intermediate layer 220 can be stacked with the opening.

[0154] The intermediate layer 220 includes an emission layer 222 on a part of the pixel electrode 210 exposed through the opening of the pixel defining layer PDL. The emission layer 222 can include a polymeric organic material or a low molecular weight organic material that emits light of an emission color (e.g., a set or predetermined color). According to some example embodiments, as Figure 7A shown, the intermediate layer 220 can include a first functional layer 221 under the emission layer 222 and / or a second functional layer 223 on the emission layer 222.

[0155] The first functional layer 221 can include a single layer or multiple layers. For example, in the case where the first functional layer 221 includes a polymeric material, the first functional layer 221 can be a hole transport layer (HTL) having a single layer structure. The first functional layer 221 can include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer 221 includes a low molecular weight material, the first functional layer 221 can include a hole injection layer (HIL) and a hole transport layer (HTL).

[0156] The second functional layer 223 may be omitted. For example, in the case where the first functional layer 221 and the emission layer 222 include a polymer material, the second functional layer 223 may be formed to make the characteristics of the organic light emitting diode (OLED) excellent. The second functional layer 223 may include a single layer or multiple layers. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0157] The counter electrode 230 faces the pixel electrode 210, and the intermediate layer 220 is between the counter electrode 230 and the pixel electrode 210. The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi)transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. Optionally, the counter electrode 230 may further include a layer including ITO, IZO, ZnO, or In2O3 on / under the (semi)transparent layer including the above materials.

[0158] According to some example embodiments, the display layer 200 disposed on the substrate 100 may be covered by the encapsulation member described above with reference to Figures 3A to 3C description.

[0159] Figure 8A and Figure 8B are plan views of the wiring WL (see Figure 2A ) around the component area OA. Figure 9A and Figure 9B are cross-sectional views of the wiring WL taken along the lines IX-IX' of Figure 8A and Figure 8B respectively. For ease of description, Figure 8A and Figure 8B show eight data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7, eight driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, and PL7, eight scan lines SL0, SL1, SL2, SL3, SL4, SL5, SL6, and SL7, eight emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, and EL7, and eight initialization voltage lines VL0, VL1, VL2, VL3, VL4, VL5, VL6, and VL7 around the component area OA.

[0160] Referring to Figure 8A , the data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7 and the driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, and PL7 may extend in the y direction.

[0161] Some of the driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, and PL7, such as PL0 and PL7, may continuously extend to cross the display area DA, but the other driving voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 around the component area OA will be disconnected or separated around the component area OA. The driving voltage lines among the disconnected driving voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 that are located above the component area OA can be connected to the second sub-line 163 described above with reference to Figure 4A and Figure 4B The driving voltage lines among the disconnected driving voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 that are located below the component area OA can be connected to the first sub-line 162.

[0162] Some of the data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7, such as DL1, DL2, DL3, DL4, DL5, and DL6, can bypass the edge of the component area OA around the component area OA. For example, each of the data lines DL1, DL2, DL3, DL4, DL5, and DL6 that connects the pixels P below and above the component area OA arranged in Figure 8A may include a portion extending in the y direction in the display area DA and a portion bypassing the edge of the component area OA in the first non-display area NDA1.

[0163] Although in Figure 8A the bypassing portion of each of the data lines DL1, DL2, DL3, DL4, DL5, and DL6 is shown as an arc-shaped curve, the bypassing portion may have a stepped structure.

[0164] In Figure 8A the pixels P located above and below the component area OA can be electrically connected to one of the data lines DL1, DL2, DL3, DL4, DL5, and DL6 that bypass the component area OA, and can receive the data signal Dm from the data lines DL1, DL2, DL3, DL4, DL5, and DL6. For example, the data lines DL1, DL2, and DL3 among the data lines DL1, DL2, DL3, DL4, DL5, and DL6 can be bent along the left edge of the component area OA, and the data lines DL4, DL5, and DL6 can be bent along the right edge of the component area OA. The data lines DL1, DL2, and DL3 are collectively referred to as the first data lines, and the data lines DL4, DL5, and DL6 are collectively referred to as the second data lines. Although for ease of description, in Figure 8AThree detour data lines DL1, DL2, and DL3 are shown arranged on the left side around the component area OA, and three detour data lines DL4, DL5, and DL6 are arranged on the right side around the component area OA. However, the number of data lines detouring around the component area OA and arranged on one side can be three or more.

[0165] The scan lines SL0, SL1, SL2, SL3, SL4, SL5, SL6, and SL7 and the emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, and EL7 can extend in the x - direction intersecting the y - direction. Some of the scan lines SL0, SL1, SL2, SL3, SL4, SL5, SL6, and SL7 and the emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, and EL7 (for example, the scan lines SL1, SL2, SL3, SL4, SL5, and SL6 and the emission control lines EL1, EL2, EL3, EL4, EL5, and EL6) can be disconnected around the component area OA. In Figure 8A the plan view, the portions of the scan lines SL1, SL2, SL3, SL4, SL5, and SL6 located on the left side of the component area OA are collectively referred to as the first scan lines, and the portions of the scan lines SL1, SL2, SL3, SL4, SL5, and SL6 located on the right side of the component area OA are collectively referred to as the second scan lines. The portions of the emission control lines EL1, EL2, EL3, EL4, EL5, and EL6 located on the left side of the component area OA are collectively referred to as the first emission control lines, and the portions of the emission control lines EL1, EL2, EL3, EL4, EL5, and EL6 located on the right side of the component area OA are collectively referred to as the second emission control lines. As described above with reference to Figure 4A and Figure 4B since the first scan driving circuit 110 and the second scan driving circuit 120 are arranged on two opposite sides of the display area DA, the first scan lines and the first emission control lines arranged on the left side of the component area OA in Figure 8A the plan view can be connected to the first scan driving circuit 110. In Figure 8A the plan view, the second scan lines and the second emission control lines arranged on the right side of the component area OA can be connected to the second scan driving circuit 120.

[0166] The initialization voltage lines VL0, VL1, VL2, VL3, VL4, VL5, VL6, and VL7 can extend in the x - direction. Some of the initialization voltage lines VL1, VL2, VL3, VL4, VL5, and VL6 around the component area OA can be disconnected around the component area OA. In Figure 8AIn the plan view, the portions of the initialization voltage lines VL1, VL2, VL3, VL4, VL5, and VL6 that are located on the left side of the component region OA are collectively referred to as the first initialization voltage line VL-A, and the portions of the initialization voltage lines VL1, VL2, VL3, VL4, VL5, and VL6 that are located on the right side of the component region OA are collectively referred to as the second initialization voltage line VL-B. The first initialization voltage line VL-A located on the left side of the component region OA can be separated from the second initialization voltage line VL-B located on the right side of the component region OA, and the component region OA is between the first initialization voltage line VL-A and the second initialization voltage line VL-B.

[0167] The first initialization voltage line VL-A and the second initialization voltage line VL-B that are separated from each other can be respectively connected to the first initialization power line 181 and the second initialization power line 182 described above with reference to Figure 4A and Figure 4B For example, when the first initialization voltage line VL-A and the second initialization voltage line VL-B are separated from each other around the component region OA, a difference may occur between the initialization voltage applied to the pixels P arranged around the component region OA and the initialization voltage applied to other pixels P. In this case, the quality of the image displayed by the pixels P may deteriorate.

[0168] In contrast, according to some example embodiments, since the first initialization voltage line VL-A and the second initialization voltage line VL-B are connected to the auxiliary voltage line VL-R, the above problems can be prevented or minimized.

[0169] The auxiliary voltage line VL-R may have an annular shape extending along the circumferential direction of the component region OA. According to some example embodiments, as shown in Figure 8A , the auxiliary voltage line VL-R may have a linear structure adjacent to the boundary between the third region and the second region and arranged in the third region. According to some example embodiments, as shown in Figure 8B , the auxiliary voltage line VL-R may have a plate-like structure covering substantially the entire third region of the substrate 100. The auxiliary voltage line VL-R may be arranged on a layer different from the layer on which the initialization voltage lines VL0, VL1, VL2, VL3, VL4, VL5, VL6, and VL7 are arranged, and the initialization voltage lines that are separated from each other around the component region OA can be electrically connected through the first contact hole CNT1 and the second contact hole CNT2.

[0170] For example, the first initialization voltage line VL-A can be connected to the auxiliary voltage line VL-R through the first contact hole CNT1, and the second initialization voltage line VL-B can be connected to the auxiliary voltage line VL-R through the second contact hole CNT2. As described with reference to Figure 6AAs described, the initialization voltage lines VL0, VL1, VL2, VL3, VL4, VL5, VL6, and VL7 are disposed on the first interlayer insulating layer IL3. In Figure 9A and Figure 9B , a first initialization voltage line VL-A and a second initialization voltage line VL-B spaced apart from each other around the component area OA are disposed on the first interlayer insulating layer IL3.

[0171] The auxiliary voltage line VL-R may be disposed above the first initialization voltage line VL-A and the second initialization voltage line VL-B, and one or more insulating layers are between the auxiliary voltage line VL-R and the first initialization voltage line VL-A and the second initialization voltage line VL-B. For example, as shown in Figure 9A , the auxiliary voltage line VL-R may be disposed on the second interlayer insulating layer IL4 and may be covered by the first planarization insulating layer IL5 and the second planarization insulating layer IL6 disposed below the pixel electrode 210 (see Figure 7B ). A part of the auxiliary voltage line VL-R may be connected to the first initialization voltage line VL-A through the first contact hole CNT1 of the second interlayer insulating layer IL4. Similarly, another part of the auxiliary voltage line VL-R may be connected to the second initialization voltage line VL-B through the second contact hole CNT2 of the second interlayer insulating layer IL4. Since the auxiliary voltage line VL-R may be formed on the second interlayer insulating layer IL4 in the same process as the node connection line 1174 and the first connection metal 1175, the auxiliary voltage line VL-R may be formed of the same material as the node connection line 1174 and the first connection metal 1175.

[0172] According to some example embodiments, as shown in Figure 9B , the auxiliary voltage line VL-R may be disposed on the first planarization insulating layer IL5 and covered by the second planarization insulating layer IL6 disposed below the pixel electrode 210 (see Figure 7B ). A part of the auxiliary voltage line VL-R may be connected to the interposer metal layer 1177 through the contact hole of the first planarization insulating layer IL5, and the interposer metal layer 1177 may be connected to the first initialization voltage line VL-A through the first contact hole CNT1 of the second interlayer insulating layer IL4. Similarly, another part of the auxiliary voltage line VL-R may be connected to the interposer metal layer 1177 through the contact hole of the first planarization insulating layer IL5, and the interposer metal layer 1177 may be connected to the second initialization voltage line VL-B through the second contact hole CNT2 of the second interlayer insulating layer IL4.

[0173] Since the disconnected initialization voltage lines VL1, VL2, VL3, VL4, VL5, and VL6 are connected as a whole through the auxiliary voltage line VL-R, both the initialization voltage lines and the auxiliary voltage line VL-R can have the same voltage level. Therefore, the occurrence of a voltage deviation due to disconnection from the initialization voltage lines can be minimized.

[0174] Figure 10 is a plan view of the display panel 10 according to some example embodiments.

[0175] The display panel 10 may include a plurality of component regions OA1 and OA2. According to some example embodiments, Figure 10 shows that the display panel 10 includes two component regions OA1 and OA2.

[0176] Pixels P may be spaced apart from each other around the plurality of component regions OA1 and OA2. Pixels P may not be arranged in the region between the plurality of component regions OA1 and OA2. For example, as Figure 10 shown, a first non-display region NDA1 may surround the plurality of component regions OA1 and OA2. Since Figure 10 the description of other elements of the display panel 10 shown is the same as the description made with reference to Figure 4A and Figure 4B is omitted.

[0177] Figure 11 is a plan view of the wiring WL (see Figure 2A ) around the plurality of component regions OA1 and OA2 according to some example embodiments.

[0178] Referring to Figure 11 , each of the initialization voltage lines VL1, VL2, VL3, VL4, VL5, and VL6 may include a portion that is disconnected around the plurality of component regions OA1 and OA2. The driving voltage lines PL1', PL2', PL3', PL4', PL5', PL6', and PL7' have a structure similar to that of the driving voltage lines PL1, PL2, PL3, PL4, PL5, PL6, and PL7 described with reference to Figure 8A , and the data lines DL1', DL2', DL3', DL4', DL5', DL6', and DL7' have a structure similar to that of the data lines DL1, DL2, DL3, DL4, DL5, DL6, and DL7 described with reference to Figure 8A . According to some example embodiments, Figure 11Shows a first initialization voltage line VL-A on the left side of the first component area OA1, a second initialization voltage line VL-B on the right side of the second component area OA2, and a third initialization voltage line VL-C between the first component area OA1 and the second component area OA2. The first initialization voltage line VL-A, the second initialization voltage line VL-B, and the third initialization voltage line VL-C may be spaced apart from each other.

[0179] The first initialization voltage line VL-A may be connected to the third initialization voltage line VL-C through a first auxiliary voltage line VL-R1. The third initialization voltage line VL-C may be connected to the second initialization voltage line VL-B through a second auxiliary voltage line VL-R2.

[0180] Each of the first auxiliary voltage line VL-R1 and the second auxiliary voltage line VL-R2 may be disposed on a layer different from the layer on which the first initialization voltage line VL-A, the second initialization voltage line VL-B, and the third initialization voltage line VL-C are disposed. For example, the first auxiliary voltage line VL-R1 may be connected to the first initialization voltage line VL-A through a first contact hole CNT1 and connected to the third initialization voltage line VL-C through a second contact hole CNT2. Similarly, the second auxiliary voltage line VL-R2 may be connected to the third initialization voltage line VL-C through a first contact hole CNT1' and connected to the second initialization voltage line VL-B through a second contact hole CNT2'.

[0181] The cross-section corresponding to the connection between the first auxiliary voltage line VL-R1 and the first initialization voltage line VL-A and the connection between the first auxiliary voltage line VL-R1 and the third initialization voltage line VL-C may have the same structure as that described above with reference to Figure 9A and Figure 9B The cross-section corresponding to the connection between the second auxiliary voltage line VL-R2 and the third initialization voltage line VL-C and the connection between the second auxiliary voltage line VL-R2 and the second initialization voltage line VL-B may have the same structure as that described above with reference to Figure 9A and Figure 9B described.

[0182] Figure 12 is a plan view of the wiring around the second non-display area NDA2 according to some exemplary embodiments and may correspond to the area XII of Figure 10 and Figure 13A and Figure 13B are cross-sectional views of the display device 1 according to an embodiment and may correspond to the cross-section taken along the line XIII-XIII' of Figure 12 described.

[0183] Refer to Figure 12, the first initialization power line 181 may be connected to a plurality of initialization voltage lines VL1, VL2, VL3, and VL4 that cross the display area DA. The first initialization power line 181 may include a portion extending in the y direction and a portion extending in a direction inclined with respect to the y direction. Figure 12 Mainly shows a portion of the first initialization power line 181 extending in the inclined direction.

[0184] As Figure 10 shown, the corners of the display area DA may have a rounded structure. When the corner is magnified, the pixels P may be arranged in a stepped structure as Figure 12 shown. In order to provide an initialization voltage to the pixels P arranged in a stepped structure while effectively using the space of the second non-display area NDA2, a portion of the first initialization power line 181 may extend in the inclined direction, for example, as Figure 12 shown, extending in a direction between the x direction and the y direction.

[0185] The first initialization power line 181 may include a plurality of connection lines VL-L extending from one side of the first initialization power line 181. Each connection line VL-L may be electrically connected to a corresponding initialization voltage line among the plurality of initialization voltage lines VL1, VL2, VL3, and VL4.

[0186] The first initialization power line 181 may be arranged on a layer different from the layer on which the initialization voltage lines VL1, VL2, VL3, and VL4 are arranged and may be electrically connected to the initialization voltage lines VL1, VL2, VL3, and VL4 through the third contact hole CNT3.

[0187] According to some example embodiments, as Figure 13A shown, the first initialization power line 181 may be arranged on the second interlayer insulating layer IL4. The initialization voltage line VL2 may be arranged on the first interlayer insulating layer IL3. Among the plurality of initialization voltage lines VL1, VL2, VL3, and VL4, the second initialization voltage line VL2 arranged on the first interlayer insulating layer IL3 is shown in Figure 13A . The connection line VL-L extending from the first initialization power line 181 may be connected to the second initialization voltage line VL2 through a contact hole formed in the second interlayer insulating layer IL4, and the contact hole formed in the second interlayer insulating layer IL4 corresponds to the third contact hole CNT3 described with reference to Figure 12 .

[0188] The first initialization power line 181 arranged on the second interlayer insulating layer IL4 may include the same as those referred to above with reference to Figure 6A and Figure 7AThe material of the described data line DL and / or driving voltage line PL is the same. Additionally, the first initialization power supply line 181 may include the same material as that of the node connection line 1174 and the first connection metal 1175.

[0189] According to some example embodiments, as Figure 13B shown, the first initialization power supply line 181 may be disposed on the first planarization insulating layer IL5. The connection line VL-L extending from the first initialization power supply line 181 may be connected to the metal layer ML through a contact hole formed in the first planarization insulating layer IL5, and the metal layer ML may be connected to the initialization voltage line (e.g., the second initialization voltage line VL2) through a contact hole formed in the second interlayer insulating layer IL4. The contact hole formed in the first planarization insulating layer IL5 and the contact hole formed in the second interlayer insulating layer IL4 may correspond to the third contact hole CNT3 described with reference to Figure 12 description.

[0190] The first initialization power supply line 181 disposed on the first planarization insulating layer IL5 may include the same material as the second connection metal 1176 described above with reference to Figure 6B and Figure 7B description.

[0191] For example, although Figures 12 to 13B the first initialization power supply line 181 is mainly described, the structure described with reference to Figures 12 to 13B also applies to the second initialization power supply line 182 (see Figure 10 ), and also applies to the first initialization power supply line 181 and the second initialization power supply line 182 described with reference to Figure 4A and Figure 4B description.

[0192] According to some example embodiments, as described above, a display panel having improved reliability and a reduced non-display area and a display device including the display panel may be provided.

[0193] Any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware can be used to implement the electronic or electrical devices and / or any other related devices or components according to the embodiments of the present invention described herein. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. Additionally, the various components of these devices can be implemented on a flexible printed circuit membrane, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Further, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using standard memory devices (such as, by way of example, random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media such as, by way of example, CD-ROM or flash drive. Additionally, those skilled in the art should recognize that, without departing from the spirit and scope of the exemplary embodiments of the present invention, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0194] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made herein without departing from the spirit and scope defined by the claims.

Claims

1. A display panel, the display panel comprising: a substrate including a first region and a second region surrounding the first region, the first region including a first component region and a second component region adjacent to each other, the first component region and the second component region being a first through hole and a second through hole spaced apart from each other; a plurality of display elements located in the second region and including a first display element and a second display element spaced apart from each other, and the first region being located between the first display element and the second display element; a plurality of first initialization voltage lines extending in a first direction and electrically connected to the first display element; a plurality of second initialization voltage lines extending in the first direction and electrically connected to the second display element, the plurality of second initialization voltage lines being spaced apart from the plurality of first initialization voltage lines, and the first region including the first component region and the second component region being located between the plurality of first initialization voltage lines and the plurality of second initialization voltage lines; a plurality of third initialization voltage lines extending in the first direction between the first component region and the second component region and spaced apart from the plurality of first initialization voltage lines and the plurality of second initialization voltage lines, wherein the plurality of third initialization voltage lines includes more than two third initialization voltage lines; an auxiliary voltage line arranged on a layer different from the layer on which the plurality of first initialization voltage lines, the plurality of second initialization voltage lines, and the plurality of third initialization voltage lines are arranged; and a first insulating layer covering the plurality of first initialization voltage lines, the plurality of second initialization voltage lines, and the auxiliary voltage line and arranged below the plurality of display elements; wherein the auxiliary voltage line includes a first auxiliary voltage line and a second auxiliary voltage line; wherein the first auxiliary voltage line is located between the plurality of first initialization voltage lines and the plurality of third initialization voltage lines, and at least a part of the first auxiliary voltage line electrically connects a corresponding first initialization voltage line among the plurality of first initialization voltage lines to a corresponding third initialization voltage line among the plurality of third initialization voltage lines; wherein the second auxiliary voltage line is located between the plurality of third initialization voltage lines and the plurality of second initialization voltage lines, and at least a part of the second auxiliary voltage line electrically connects a corresponding third initialization voltage line among the third initialization voltage lines to a corresponding second initialization voltage line among the plurality of second initialization voltage lines; and wherein the first auxiliary voltage line and the second auxiliary voltage line respectively surround the first through hole and the second through hole, and both have a closed loop shape.

2. The display panel according to claim 1, wherein, Each of the plurality of display elements includes a pixel electrode, a counter electrode located above the pixel electrode, and an emission layer located between the pixel electrode and the counter electrode; and the auxiliary voltage line is located below the pixel electrode, and the first insulating layer is located between the auxiliary voltage line and the pixel electrode.

3. The display panel according to claim 1, wherein the display panel further comprises a second insulating layer disposed between the plurality of first initialization voltage lines, the plurality of second initialization voltage lines, and the auxiliary voltage line.

4. The display panel according to claim 1, wherein the display panel further comprises: a plurality of thin film transistors and storage capacitors, the plurality of thin film transistors and the storage capacitors being electrically connected to corresponding ones of the plurality of display elements, wherein the plurality of first initialization voltage lines and the plurality of second initialization voltage lines comprise a material the same as that of one of the electrodes of the storage capacitor.

5. The display panel according to claim 4, wherein, The storage capacitor comprises a bottom electrode and a top electrode, and the plurality of first initialization voltage lines and the plurality of second initialization voltage lines comprise a material the same as that of the top electrode.

6. The display panel according to claim 4, wherein the display panel further comprises a contact metal connecting one of the plurality of thin film transistors to the corresponding display element, Among them, the auxiliary voltage line comprises a material the same as that of the contact metal.

7. The display panel according to claim 1, wherein the display panel further comprises an intermediate metal layer between the plurality of first initialization voltage lines and the auxiliary voltage line and between the plurality of second initialization voltage lines and the auxiliary voltage line.

8. The display panel according to claim 1, wherein the display panel further comprises: a first scan line extending in the first direction and electrically connected to the first display element; and a second scan line extending in the first direction and electrically connected to the second display element, wherein the first scan line is spaced apart from the second scan line, and the first region is located between the first scan line and the second scan line.

9. The display panel according to claim 1, wherein the display panel further comprises: a first emission control line extending in the first direction and electrically connected to the first display element; and a second emission control line extending in the first direction and electrically connected to the second display element, wherein the first emission control line is spaced apart from the second emission control line, and the first region is located between the first emission control line and the second emission control line.

10. The display panel according to claim 1, wherein the display panel further includes an initialization power line located in an outer region of the substrate, where, The initialization power supply line is disposed between the substrate and the first insulating layer.

11. The display panel according to claim 10, wherein the display panel further comprises: a first data line extending in a second direction intersecting the first direction and connected to the first display element; and a second data line extending in the second direction and connected to the second display element, wherein the initialization power supply line comprises a material the same as that of the first data line or the second data line.

12. A display device, the display device comprising at least one component region inside a display region and a non-display region surrounding the display region, the display device comprising: a plurality of display elements located in the display region, each of the plurality of display elements comprising a pixel electrode, an emission layer, and a counter electrode stacked in sequence; A plurality of first initialization voltage lines, electrically connected to a first display element among the plurality of display elements and extending in a first direction in the display area; A plurality of second initialization voltage lines, electrically connected to a second display element among the plurality of display elements, extending in the first direction in the display area, and spaced apart from the plurality of first initialization voltage lines, and the at least one component area is located between the plurality of second initialization voltage lines and the plurality of first initialization voltage lines, the at least one component area includes a first component area and a second component area arranged along the first direction, the first component area and the second component area are a first through hole and a second through hole spaced apart from each other; A plurality of third initialization voltage lines, extending in the first direction between the first component area and the second component area, and spaced apart from the plurality of first initialization voltage lines and the plurality of second initialization voltage lines, wherein, the plurality of third initialization voltage lines includes more than two third initialization voltage lines, An auxiliary voltage line, arranged on a layer different from the layer on which the plurality of third initialization voltage lines are arranged; and A first insulating layer, arranged between the auxiliary voltage line and the pixel electrode, wherein, the auxiliary voltage line includes a first auxiliary voltage line and a second auxiliary voltage line, wherein, the first auxiliary voltage line is located between the plurality of first initialization voltage lines and the plurality of third initialization voltage lines, and at least a part of the first auxiliary voltage line electrically connects a corresponding first initialization voltage line among the plurality of first initialization voltage lines to a corresponding third initialization voltage line among the plurality of third initialization voltage lines, wherein, the second auxiliary voltage line is located between the plurality of third initialization voltage lines and the plurality of second initialization voltage lines, and at least a part of the second auxiliary voltage line electrically connects a corresponding third initialization voltage line among the plurality of third initialization voltage lines to a corresponding second initialization voltage line among the plurality of second initialization voltage lines, and wherein, the first auxiliary voltage line and the second auxiliary voltage line respectively surround the first through hole and the second through hole, and both have a closed loop shape.

13. The display device according to claim 12, wherein the display device further comprises: A second insulating layer, located between the plurality of first initialization voltage lines and the plurality of second initialization voltage lines and the auxiliary voltage line.

14. The display device according to claim 12, the display device further includes a thin film transistor and a storage capacitor, the thin film transistor is electrically connected to a corresponding display element among the plurality of display elements, and the storage capacitor includes a bottom electrode and a top electrode, Among them, The plurality of first initialization voltage lines and the plurality of second initialization voltage lines include a material same as the material of the top electrode of the storage capacitor.

15. The display device according to claim 14, the display device further includes a contact metal connecting one of the thin film transistors to the corresponding display element, Among them, The auxiliary voltage line includes a material same as the material of the contact metal.

16. The display device according to claim 12, wherein, The multiple first initialization voltage lines and the multiple second initialization voltage lines are arranged on the same layer.

17. The display device according to claim 16, further comprising an intermediate metal layer located between the multiple first initialization voltage lines and the auxiliary voltage line and between the multiple second initialization voltage lines and the auxiliary voltage line.

18. The display device according to claim 12, further comprising: A first scan line extending in the first direction and electrically connected to the first display element; And A second scan line extending in the first direction and electrically connected to the second display element, wherein the first scan line and the second scan line are spaced apart, and the at least one component area is located between the first scan line and the second scan line.

19. The display device according to claim 12, further comprising: A first emission control line extending in the first direction and electrically connected to the first display element; And A second emission control line extending in the first direction and electrically connected to the second display element, wherein the first emission control line and the second emission control line are spaced apart, and the at least one component area is located between the first emission control line and the second emission control line.

20. The display device according to claim 12, wherein the display device further comprises: An initialization power supply line located in the non-display area.

21. The display device according to claim 20, wherein, The initialization power supply line is located below the first insulating layer.

22. The display device according to claim 20, further comprising: A first data line extending in a second direction intersecting the first direction and connected to the first display element; And A second data line extending in the second direction and connected to the second display element, wherein the initialization power supply line includes a material having the same material as the first data line or the second data line.

23. The display device according to claim 12, wherein, The multiple first initialization voltage lines are located on one side of the first component area, and the multiple second initialization voltage lines are located on one side of the second component area, and The first component area and the second component area are located between the multiple first initialization voltage lines and the multiple second initialization voltage lines spaced apart from each other.

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