A single-stage multi-output GIP driving circuit and driving method

Abstract

The present invention discloses a single-stage multi-output GIP driving circuit and a driving method. In a 17T2C dual-output GIP circuit, 17 TFTs are used as switches and two capacitors are coupled. T4 and T14 output GIPs respectively. 2n‑1 , G 2n Scanning signal (gate line), thereby realizing single-stage dual-output GIP driving circuit design. Different from the prior art, the above technical solution proposes a new 17T2C single-stage dual-output GIP circuit to realize a one-stage GIP circuit driving two rows of pixels. While ensuring the consistent charging rate of each row of pixels, it can effectively pull down and maintain the Q point and Gout output potential, improve the stability of the GIP circuit, and achieve a narrow frame design at the same time, thereby increasing the screen-to-body ratio of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a single-stage multi-output GIP driving circuit and a driving method. Background Art

[0002] TFT-LCD, each pixel in the active matrix liquid crystal display has a TFT, whose gate is connected to the horizontal scan line, the drain is connected to the vertical data line, and the source is connected to the pixel electrode. If a certain positive voltage is applied to a certain horizontal scan line, all the TFTs on the scan line will be turned on. At this time, the pixel electrode on the scan line will be connected to the vertical data line, and the video signal voltage on the data line will be written into the pixel, controlling the transmittance of different liquid crystals and thus achieving the effect of controlling color.

[0003] With the development of TFT-LCD display technology, narrow-border display screens have become the main trend in the development of high-quality display screens due to their simplicity, beauty, and large viewing area of ​​the same size. Especially for small-size display screens, the requirements for narrow borders are getting higher and higher. The application of GIP (gate driver in panel) technology has become mainstream. GIP technology uses the array process of liquid crystal display panels to directly manufacture the gate drive circuit on the array substrate to achieve a drive method of scanning the gate line by line. It can replace the traditional gate drive IC, which not only simplifies the IC process and production cost, but also effectively reduces the panel frame design, which is more in line with the development trend of display panels.

[0004] The current mainstream driving method of GIP circuit technology is that a first-level GIP circuit drives a row of pixels. However, this method occupies a large area of ​​the left and right borders, which is not conducive to improving the screen-to-body ratio. Summary of the invention

[0005] To this end, it is necessary to provide a single-stage multi-output GIP driving circuit and driving method, which can effectively pull down and maintain the output potential signals of the Q point and Gout while ensuring the consistency of the charging rate of each row of pixels, thereby improving the stability of the GIP circuit and achieving a narrow bezel design, thereby increasing the screen-to-body ratio of the display panel.

[0006] To achieve the above object, the present embodiment provides a single-stage multi-output GIP driving circuit, including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17; and capacitors C1 and C2;

[0007] The gate of T1 is connected to the gate line G 2(n-1) , the drain of T1 is connected to FW, and the source of T1 is connected to Q1 point;

[0008] The gate of T2 is connected to point Q1, the drain of T2 is connected to point P, and the source of T2 is connected to VGL;

[0009] The gate of T3 is connected to point P, the drain of T3 is connected to point Q1, and the source of T3 is connected to VGL;

[0010] The gate of T4 is connected to Q1, the drain of T4 is connected to CK1, and the source of T4 is connected to the gate line G 2n-1 ;

[0011] The gate of T5 is connected to CK3, and the drain of T5 is connected to the gate line G 2n-1 , the source of T5 is connected to VGL;

[0012] The gate of T6 is connected to point P, and the drain of T6 is connected to gate line G 2n-1 , the source of T6 is connected to VGL;

[0013] The gate of T7 is connected to the gate line G 2(n+1 ), the drain of T7 is connected to BW, and the source of T7 is connected to Q1 point;

[0014] The gate of T8 is connected to CLR, the drain of T8 is connected to point P, and the source of T8 is connected to VGL;

[0015] The gate of T9 is connected to CLR, the drain of T9 is connected to Q1 point, and the source of T9 is connected to VGL;

[0016] The gate of T10 is connected to CLR, and the drain of T10 is connected to the gate line G 2n-1 , the source of T10 is connected to VGL;

[0017] The gate of T11 is connected to CK1, the drain of T11 is connected to CK1, and the source of T11 is connected to point P;

[0018] The gate of T12 is connected to CK3, the drain of T12 is connected to point P, and the source of T12 is connected to VGL;

[0019] The gate of T13 is connected to CLR, and the drain of T13 is connected to the gate line G 2n , the source of T13 is connected to VGL;

[0020] The gate of T14 is connected to Q2, the drain of T14 is connected to CK2, and the source of T14 is connected to G 2n ;

[0021] The gate of T15 is connected to CK4, and the drain of T15 is connected to G2n , the source of T15 is connected to VGL;

[0022] The gate of T16 is connected to point P, and the drain of T16 is connected to point G 2n , the source of T16 is connected to VGL;

[0023] The gate of T17 is connected to VGH, the drain of T17 is connected to Q2, and the source of T17 is connected to Q1;

[0024] One plate of C1 is connected to Q1, and the other plate of C1 is connected to G 2n-1 ;

[0025] One plate of C2 is connected to Q2, and the other plate of C2 is connected to G 2n .

[0026] Furthermore, the GIP driving circuit array is disposed on the display panel and is located on one side of the display panel.

[0027] Furthermore, the display panel is also provided with a CK1 line, a CK2 line, a CK3 line, a CK4 line, a FW line, a BW line, a VGH line, a VGL line and a CLR line, and the CK1 line, the CK2 line, the CK3 line, the CK4 line, the FW line, the BW line, the VGH line, the VGL line and the CLR line are arranged on one side of the GIP driving circuit; the CK1 line, the CK2 line, the CK3 line, the CK4 line, the FW line, the BW line, the VGH line, the VGL line and the CLR line are respectively connected to the CK1, CK2, CK3, CK4, FW, BW, VGH, VGL and CLR in the GIP driving circuit.

[0028] Furthermore, the display panel is an OLED display panel or an LCD display panel.

[0029] Furthermore, it also includes a driver IC, G 2n -1.G 2n , G 2(n-1) and G 2(n+1) Connected with the driver IC.

[0030] Furthermore, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, and T17 are all thin film transistors.

[0031] This embodiment further provides a driving method of a single-stage multi-output GIP driving circuit, which is applied to the gate circuit described in any one of the above embodiments, and includes the following steps:

[0032] In the pre-charge stage, G 2(n-1)and FW write high potential signals, CK1, CK2, CK3, CK4, G 2n-1 and G 2n Write low potential signal;

[0033] In the output stage, CK1 writes a potential signal, G 2n-1 Outputs a potential signal with the same potential as CK1; CK2 writes a potential signal, G 2n Outputs a potential signal with the same potential as CK2; CK3 writes a potential signal, G 2n+1 Outputs a potential signal with the same potential as CK3;

[0034] In the pull-down phase, G 2(n+1) , CK4 and CK3 write high potential signals, BW writes low potential signals, VGL pulls down G 2n-1 Output low potential signal; VGL pulls down G 2n Output low potential signal;

[0035] In the pull-down regulation stage, G 2(n-1) , G 2(n+1) When a low potential signal is written, when a high potential signal is written to CK1, point P is at a high potential; when a high potential signal is written to CK3 and CK4, Q1 and Q2 are at a low potential.

[0036] Different from the existing technology, the above technical solution proposes a new 17T2C single-stage dual-output GIP circuit to realize a one-stage GIP circuit driving two rows of pixels. While ensuring the consistent charging rate of each row of pixels, it can effectively pull down and maintain the Q point and Gout output potential, improve the stability of the GIP circuit, and achieve a narrow bezel design at the same time, thereby increasing the screen-to-body ratio of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A single-stage multi-output GIP driving circuit diagram;

[0038] Figure 2 A module diagram of a single-stage multi-output GIP driving circuit;

[0039] Figure 3 It is the 17T2C circuit level transmission and timing diagram;

[0040] Figure 4 This is the simulation result of 17T2C;

[0041] Figure 5 The simulation results for 17T2C are shown below;

[0042] Figure 6 This is the simulation result of 17T2C; DETAILED DESCRIPTION

[0043] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0044] See also Figures 1 to 6 To achieve the above purpose, the present application provides a single-stage multi-output GIP driving circuit, including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17; also includes capacitors C1 and C2; the gate of T1 is connected to the gate line G 2(n-1) (gate line), the drain of T1 is connected to FW, the source of T1 is connected to Q1 point; the gate of T2 is connected to Q1 point, the drain of T2 is connected to P point, and the source of T2 is connected to VGL; the gate of T3 is connected to P point, the drain of T3 is connected to Q1 point, and the source of T3 is connected to VGL; the gate of T4 is connected to Q1 point, the drain of T4 is connected to CK1, and the source of T4 is connected to the gate line G 2n-1 The gate of T5 is connected to CK3, and the drain of T5 is connected to the gate line G 2n-1 The source of T5 is connected to VGL; the gate of T6 is connected to point P, and the drain of T6 is connected to the gate line G 2n-1 The source of T6 is connected to VGL; the gate of T7 is connected to the gate line G 2(n+1) , the drain of T7 is connected to BW, the source of T7 is connected to Q1 point; the gate of T8 is connected to CLR, the drain of T8 is connected to P point, and the source of T8 is connected to VGL; the gate of T9 is connected to CLR, the drain of T9 is connected to Q1 point, and the source of T9 is connected to VGL; the gate of T10 is connected to CLR, and the drain of T10 is connected to gate line G 2n-1 , the source of T10 is connected to VGL; the gate of T11 is connected to CK1 (i.e., the clock signal), the drain of T11 is connected to CK1, and the source of T11 is connected to point P; the gate of T12 is connected to CK3, the drain of T12 is connected to point P, and the source of T12 is connected to VGL; the gate of T13 is connected to CLR, and the drain of T13 is connected to the gate line G 2n , the source of T13 is connected to VGL; the gate of T14 is connected to Q2, the drain of T14 is connected to CK2, and the source of T14 is connected to G 2n The gate of T15 is connected to CK4, and the drain of T15 is connected to G 2n The source of T15 is connected to VGL; the gate of T16 is connected to point P, and the drain of T16 is connected to G 2n, the source of T16 is connected to VGL; the gate of T17 is connected to VGH, the drain of T17 is connected to Q2, the source of T17 is connected to Q1; one plate of C1 is connected to Q1, and the other plate of C1 is connected to G 2n-1 One plate of C2 is connected to Q2, and the other plate of C2 is connected to G 2n In the 17T2C dual-output GIP circuit, 17 TFTs are used as switches and two capacitors are used for coupling. T4 and T14 output G respectively. 2n-1 , G 2n Scanning signal (gate line), thereby realizing single-stage dual-output GIP driving circuit design. Different from the prior art, the above technical solution proposes a new 17T2C single-stage dual-output GIP circuit to realize a one-stage GIP circuit driving two rows of pixels. While ensuring the consistent charging rate of each row of pixels, it can effectively pull down and maintain the Q point and Gout output potential, improve the stability of the GIP circuit, and achieve a narrow frame design at the same time, thereby increasing the screen-to-body ratio of the display panel.

[0045] In this embodiment, the GIP driving circuit is located on the display panel and on one side of the display panel. It should be noted that the display panel is also provided with CK1 line, CK2 line, CK3 line, CK4 line, FW line, BW line, VGH line, VGL line and CLR line, and the CK1 line, CK2 line, CK3 line, CK4 line, FW line, BW line, VGH line, VGL line and CLR line are respectively connected to CK1, CK2, CK3, CK4, FW, BW, VGH, VGL and CLR in the GIP driving circuit. The CK1 line, CK2 line, CK3 line, CK4 line, FW line, BW line, VGH line, VGL line and CLR line are parallel to each other. The display panel is an OLED display panel or an LCD display panel. It also includes a driving IC, and the gate circuit is connected to the driving IC. T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17 are all thin film transistors. Of course, the gate circuit is not only set in the middle of the display area of ​​the display panel, but the gate circuit can also be used on the left and right sides of the display panel to improve its applicability. T1, T2, T3, T4...T17 can also be MOS tubes (i.e. metal-oxide-semiconductor field effect tubes MOSFET), junction field effect tubes, etc.

[0046] See also Figure 2 In this application, during the pre-charge phase, G 2(n-1) and FW write high potential signal, CK1, CK2, CK3, CK4, G 2n-1 and G 2nWrite low potential signal; in the output stage, CK1 writes potential signal, G 2n-1 Outputs a potential signal with the same potential as CK1; CK2 writes a potential signal, G 2n Outputs a potential signal with the same potential as CK2; CK3 writes a potential signal, G 2n+1 Outputs a potential signal with the same potential as CK3; in the pull-down stage, G 2(n+1) , CK4 and CK3 write high potential signals, BW writes low potential signals, VGL pulls down G 2n-1 Output low potential signal; VGL pulls down G 2n Output low potential signal; in the pull-down voltage stabilization stage, G 2(n-1) , G 2(n+1) Write a low potential signal. When CK1 writes a high potential signal, point P is at a high potential. When CK3 and CK4 write high potential signals, Q1 and Q2 are at a low potential. It should be noted that the operation of the GIP circuit can be divided into three parts: pre-charge, output, shutdown and voltage regulation. The first part (1st) is composed of T1, T7 and T17 to form a pre-charge module, which controls the potential of points Q1 and Q2. FW and BW control forward and reverse scans. When scanning forward, FW is at a high potential and BW is at a low potential, and vice versa for reverse scans. The second part (2nd) is composed of T4, T14, C1 and C2 to form an output module, which controls G 2n-1 and G 2n The third part (3rd) is mainly for shutting down and stabilizing the voltage. T2, T3, T11 and T12 control the pull-up and pull-down modules at Q and P points, and T5 and T6 control G 2n-1 The first output pull-down module is controlled by T15 and T16 G 2n The second output pull-down module, T8, T9, T10 and T13, are pulled down by the CLR signal in the V-blanking area (blank time within a frame) at the Q and P points, and G 2n-1 and G 2n Output module.

[0047] See also Figure 3 , the application 17T2C GIP circuit level transmission and working waveform timing diagram: G 2n-1 , G 2n The working waveform can be divided into 4 stages, t1 is the pre-charge stage, t2 is the output stage, t3 and t4 are the pull-down and pull-down maintenance stages, and the forward scan is used as an example to explain step by step. In the GIP circuit, the TFT device is used as a switch. When the Gate is at a high potential, the Source and Drain are connected, and the TFT is turned on. When the Gate is at a low potential, the TFT is turned off. FW, BW, VGH and VGL are DC signals, and STV, RST and CLR are AC signals, which are only turned on once in one frame.

[0048] At t1 stage: STV / G 2(n-1) , VGH signal is high, T1 / T17 is turned on, FW is input at high potential, Q1 / Q2 is high potential; T2 is turned on, VGL pulls down P point, P point is low potential; T4 / T14 is turned on, CK1 / CK2 is input at low potential, G 2n-1 , G 2n Low potential; so in the t1 stage, T1 / T17 is turned on, FW is at high potential, charging the capacitors C1 / C2, and the Q1 / Q2 points are pre-charged to a high potential.

[0049] At t2: STV / G 2(n-1) 、RST / G 2(n+1) The signal is low, T1T7 is closed, Q1 maintains high potential, T4 is open, CK1 high potential input, G 2n-1 The potential changes from low to high, C1 is coupled, the potential at Q1 becomes 2 times the voltage, and G is stabilized. 2n-1 Output high potential; when CK1 changes from high potential to low potential, G 2n-1 Output low potential; similarly, Q2 maintains high potential, T14 is turned on, CK2 inputs low potential, G 2n When CK2 changes from low potential to high potential, C2 is coupled, and the potential at Q2 becomes 2 times the voltage, stabilizing G 2n Output high potential; Q1 point high potential, T2 open, VGL pulls down P point, P point low potential. So in the t2 output stage, T1 / T7 is closed, Q1 / Q2 points maintain the high potential of the t1 stage, and the high and low potential changes of CK1 / CK2 control G 2n-1 , G 2n Output signal.

[0050] At t3: RST / G 2(n+1) The signal is high, T7 is turned on, BW is low and input to Q1, VGH signal turns on T17, Q1 / Q2 is low, T4 / T14 is turned off; during this period, CK3 is high, T12 is turned on, P is low, T6 / T16 is turned off, T5 is turned on, VGL pulls down G 2n-1 Output low potential; CK4 high potential, T15 open, VGL pulls down G 2n Output low potential. So in the t3 stage, T7 is turned on, pulling down the potential of Q1 / Q2, VGL pulls down VGL pulls down G 2n-1 , G 2n Output.

[0051] At t4: STV / G 2(n-1) 、RST / G 2(n+1)The signal is low, T1T7 is closed, Q1 / Q2 maintains the low potential of the t3 stage, T2 / T4 / T14 is closed, when CK1 is high, T11 diode is turned on, P point is high, T3 / T6 / T16 is turned on; VGL pulls down P point through T3, VGL pulls down G point through T6 / T16 2n-1 , G 2n Output; when CK3 / CK4 is high, T5 / T15 is turned on, and VGL pulls down G 2n-1 , G 2n Therefore, in the t4 stage, the Q1 / Q2 point is kept at a low potential, and the CK signal controls the alternate opening of T5 / T6 and T15 / T16, so that VGL pulls down G 2n-1 , G 2n Output.

[0052] See also Figures 4 to 6 , in the simulation result diagram of the 17T2C GIP circuit of the present application: In the simulation result diagram, it can be seen that the output signal of each level of GIP is turned on normally step by step, the potentials of point P, point Q1 and point Q2 are normal, and the pixel charging rates of the two Gout signals (gate output signals) output by the same GIP circuit are also the same (this application takes the 6.55" IGZOHD product as an example for simulation, and the charging rates of the pixels of adjacent output signals are all 95%). And P is charged by unidirectional conduction by TFT diode connection, which effectively maintains the high potential of point P and prevents CK from affecting the coupling effect of point Q through the off-state capacitance of T4 / T14.

[0053] It should be noted that, although the above embodiments have been described in this article, the scope of patent protection of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields are all included in the scope of protection of the patent of the present invention.

Claims

1. A single-stage multi-output GIP driving circuit, characterized in that: Including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17; also including capacitors C1, C2; The gate of T1 is connected to the gate line G 2(n-1) , the drain of T1 is connected to FW, and the source of T1 is connected to Q1 point; The gate of T2 is connected to point Q1, the drain of T2 is connected to point P, and the source of T2 is connected to VGL; The gate of T3 is connected to point P, the drain of T3 is connected to point Q1, and the source of T3 is connected to VGL; The gate of T4 is connected to Q1, the drain of T4 is connected to CK1, and the source of T4 is connected to the gate line G 2n-1 ; The gate of T5 is connected to CK3, and the drain of T5 is connected to the gate line G 2n-1 , the source of T5 is connected to VGL; The gate of T6 is connected to point P, and the drain of T6 is connected to gate line G 2n-1 , the source of T6 is connected to VGL; The gate of T7 is connected to the gate line G 2(n+1) , the drain of T7 is connected to BW, and the source of T7 is connected to Q1 point; The gate of T8 is connected to CLR, the drain of T8 is connected to point P, and the source of T8 is connected to VGL; The gate of T9 is connected to CLR, the drain of T9 is connected to Q1 point, and the source of T9 is connected to VGL; The gate of T10 is connected to CLR, and the drain of T10 is connected to the gate line G 2n-1 , the source of T10 is connected to VGL; The gate of T11 is connected to CK1, the drain of T11 is connected to CK1, and the source of T11 is connected to point P; The gate of T12 is connected to CK3, the drain of T12 is connected to point P, and the source of T12 is connected to VGL; The gate of T13 is connected to CLR, and the drain of T13 is connected to the gate line G 2n , the source of T13 is connected to VGL; The gate of T14 is connected to Q2, the drain of T14 is connected to CK2, and the source of T14 is connected to G 2n ; The gate of T15 is connected to CK4, and the drain of T15 is connected to G 2n , the source of T15 is connected to VGL; The gate of T16 is connected to point P, and the drain of T16 is connected to point G 2n , the source of T16 is connected to VGL; The gate of T17 is connected to VGH, the drain of T17 is connected to Q2, and the source of T17 is connected to Q1; One plate of C1 is connected to Q1, and the other plate of C1 is connected to G 2n-1 ; One plate of C2 is connected to Q2, and the other plate of C2 is connected to G 2n .

2. A single-stage multi-output GIP driving circuit according to claim 1, characterized in that: The GIP driving circuit array is disposed on the display panel and is located at one side of the display panel.

3. A single-stage multi-output GIP driving circuit according to claim 2, characterized in that: The display panel is also provided with a CK1 line, a CK2 line, a CK3 line, a CK4 line, a FW line, a BW line, a VGH line, a VGL line and a CLR line, and the CK1 line, the CK2 line, the CK3 line, the CK4 line, the FW line, the BW line, the VGH line, the VGL line and the CLR line are arranged on one side of the GIP driving circuit; the CK1 line, the CK2 line, the CK3 line, the CK4 line, the FW line, the BW line, the VGH line, the VGL line and the CLR line are respectively connected to the CK1, CK2, CK3, CK4, FW, BW, VGH, VGL and CLR in the GIP driving circuit.

4. The single-stage multi-output GIP driving circuit according to claim 2, characterized in that: The display panel is an OLED display panel or an LCD display panel.

5. The single-stage multi-output GIP driving circuit according to claim 1, characterized in that: Also includes driver IC, G 2n-1 , G 2n , G 2(n-1) and G 2(n+1) Connected with the driver IC.

6. The single-stage multi-output GIP driving circuit according to claim 1, characterized in that: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, and T17 are all thin film transistors.

7. A driving method for a single-stage multi-output GIP driving circuit, characterized in that: A single-stage multi-output GIP driving circuit as claimed in any one of claims 1 to 6, comprising the following steps: In the pre-charge stage, G 2(n-1) and FW write high potential signal, CK1, CK2, CK3, CK4, G 2n-1 and G 2n Write low potential signal; In the output stage, CK1 writes a potential signal, G 2n-1 Outputs a potential signal with the same potential as CK1; CK2 writes a potential signal, G 2n Outputs a potential signal with the same potential as CK2; CK3 writes a potential signal, G 2n+1 Outputs a potential signal with the same potential as CK3; In the pull-down phase, G 2(n+1) , CK4 and CK3 write high potential signals, BW writes low potential signals, VGL pulls down G 2n-1 Output low potential signal; VGL pulls down G 2n Output low potential signal; In the pull-down regulation stage, G 2(n-1) , G 2(n+1) When a low potential signal is written, when a high potential signal is written to CK1, point P is at a high potential; when a high potential signal is written to CK3 and CK4, Q1 and Q2 are at a low potential.

Images