Structure and method for forming a semiconductor device

Abstract

The present disclosure relates to structures and methods for forming semiconductor devices. According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, wherein the semiconductor layer has a first conductivity type. The method also includes etching through a first opening of a mask layer to form a first injection surface on the semiconductor layer, and forming a plurality of raised regions of conductive material including the conductive layer above the semiconductor layer. The method also includes using the plurality of raised regions as part of a first injection mask to perform a first injection of a dopant having a second conductivity type into the semiconductor layer to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode. The diode extends vertically from the upper surface of the semiconductor layer to the insulating layer.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and, in particular embodiments, to structures and methods of forming semiconductor devices having PN junctions. Background Art

[0002] Semiconductor devices can include various active and passive devices integrated on a semiconductor substrate. One type of passive device is a diode. A diode includes a PN junction and is used in many semiconductor applications. A diode can be manufactured simultaneously with other components (e.g., transistors, capacitors, resistors, etc.).

[0003] The diode can be directly implanted into the semiconductor substrate. The diode directly implanted into the semiconductor substrate may include a parasitic PN junction, which may affect the behavior of the circuit including the diode. For example, the effects due to the parasitic PN junction may be seen during the startup and / or latching of the circuit. On the other hand, the dopant diffusion process can also be used to manufacture the diode. However, the mask used for the dopant diffusion may require strict alignment that may be difficult to establish. Defects caused by variations in alignment accuracy may lead to unpredictability in the diode characteristics.

[0004] Compatibility of the diode manufacturing process flow with other process flows (e.g., complementary metal oxide semiconductor (CMOS) process flows, capacitor process flows, non-volatile memory (NVM) process flows, and other process flows) may be desirable in order to reduce complexity and cost and / or increase yield. Additionally, it may also be desirable to reduce or eliminate the presence of parasitic PN junctions and improve alignment accuracy so that the predictability and performance of the manufactured diodes can be improved. Summary of the invention

[0005] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, wherein the semiconductor layer has a first conductivity type. The method also includes etching through a first opening of a mask layer to form a first injection surface on the semiconductor layer, and forming a plurality of protruding regions of a conductive material including the conductive layer above the semiconductor layer. The method also includes using the plurality of protruding regions as part of a first injection mask to perform a first injection of a dopant having a second conductivity type into the semiconductor layer to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode, and the diode extending vertically from the upper surface of the semiconductor layer to the insulating layer.

[0006] According to one embodiment of the present invention, a method for manufacturing an integrated circuit includes: forming an insulating layer on a surface of a semiconductor substrate, the insulating layer including an active region at a first position of the semiconductor substrate; forming a semiconductor layer having a first conductivity type and covering the insulating layer; forming a gate dielectric layer on the semiconductor layer; forming a conductive layer on the gate dielectric layer; patterning the semiconductor layer, the gate dielectric layer and the conductive layer simultaneously to form a self-aligned diode region on the insulating layer and at a second position of the semiconductor substrate. The method also includes: patterning the conductive layer to form a control gate covering a floating gate at a first position, and forming a protrusion region covering the semiconductor layer at a second position; and using a plurality of protrusion regions as a hard mask, implanting a second conductivity type dopant into a first region of the semiconductor layer, so that the staggered regions below the plurality of protrusion regions remain doped with the first conductivity type, so as to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode, wherein the diode extends vertically from the upper surface of the semiconductor layer to the insulating layer.

[0007] The integrated circuit includes: a semiconductor substrate; an insulating layer covering the semiconductor substrate; a semiconductor layer of a first conductivity type covering the insulating layer, the semiconductor layer including a longitudinal length; and a plurality of protrusion regions covering the semiconductor layer and spaced apart from each other. Each of the plurality of protrusion regions includes a longitudinal length equal to the longitudinal length of the semiconductor layer. The integrated circuit also includes a PN junction sequence in the semiconductor layer, wherein each PN junction is located at an edge of an associated protrusion region and extends vertically from an upper surface of the semiconductor layer to the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other advantages and features of the invention will become apparent from a careful reading of the manner of construction and embodiments of the invention, which are not limiting in any way, and of the accompanying drawings, in which:

[0009] Figure 1 A conventional electronic circuit including a diode bridge is shown;

[0010] Figure 2 A semiconductor device including a semiconductor substrate during fabrication according to an embodiment of the present invention is illustrated.

[0011] Figure 3 illustrates a semiconductor device during fabrication and after forming an insulating layer over a semiconductor substrate according to one embodiment of the present invention;

[0012] Figure 4 illustrates a semiconductor device during fabrication and after forming a semiconductor layer over an insulating layer according to one embodiment of the present invention;

[0013] Figure 5illustrates a semiconductor device during fabrication and after forming a dielectric layer and a conductive layer over a semiconductor layer in accordance with an embodiment of the present invention;

[0014] Fig. 6A and Figure 6B A semiconductor device is illustrated during fabrication and after etching a stack according to an embodiment of the present invention, wherein Fig. 6A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 6B A top view of a semiconductor device is shown;

[0015] Fig. 7A and Figure 7B A semiconductor device is illustrated during fabrication and after etching the conductive layer and the dielectric layer to form a raised region according to one embodiment of the present invention, wherein Fig. 7A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 7B A top view of a semiconductor device is shown;

[0016] Fig. 8A and Figure 8B A semiconductor device is illustrated during manufacture and after forming a first implant mask layer according to an embodiment of the present invention; wherein Fig. 8A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 8B A top view of a semiconductor device is shown;

[0017] Fig. 9A and Fig. 9B A semiconductor device is illustrated during manufacture and after forming a second implant mask layer according to an embodiment of the present invention; wherein Fig. 9A FIG. 4 shows a cross-sectional view of a semiconductor device, and Fig. 9B A top view of a semiconductor device is shown; and

[0018] Fig. 10A and Fig. 10B An exemplary semiconductor device according to an embodiment of the present invention is shown, wherein Fig. 10A shows a cross-sectional view of a semiconductor device, and Fig. 10B A top view of a semiconductor device is shown.

[0019] Unless otherwise indicated, corresponding reference numerals in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the scope of the features. DETAILED DESCRIPTION

[0020] The manufacture and use of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein can be applied to a variety of specific situations. The specific embodiments discussed are only illustrative of specific ways to manufacture and use the various embodiments, and should not be interpreted in a limited scope.

[0021] The inventors have found that recurring problems are encountered when using diodes whose doped regions are directly implanted into a semiconductor substrate. These adverse effects may be caused, for example, by parasitic PN junctions and may seriously affect the startup or latching of the circuit. It may then be desirable to avoid these parasitic effects in a way that is simple and compatible with other process flows (e.g., NVM technology). Such compatibility may be in contrast to, for example, a capacitor process flow, which may have additional mask steps to provide contacts with additional layers.

[0022] The inventors have also discovered that some dopant diffusion processes in conventional diode manufacturing methods are poorly controlled. For example, masks used in dopant diffusion processes may have limited alignment accuracy. Alignment defects in masks may result in defects that make diode characteristics unpredictable. Therefore, it is desirable to reduce the alignment requirements for masks used in doping processes while still maintaining process flow compatibility.

[0023] The configurations and embodiments of the invention relate to PN junction diodes and in some embodiments to polysilicon based diodes for forming bridge rectifiers (Graetz bridges) in integrated circuits, for example in contactless telecommunication technology and incorporating, for example, non-volatile memories.

[0024] Figure 1 A conventional electronic circuit CI suitable for contactless applications is shown, comprising a diode bridge DBr (typically a Graetz bridge) for transferring a direct voltage VDC from the voltage present at terminals AC0 and AC1 of an antenna ANT1 of the circuit, the antenna ANT1 being coupled to an antenna ANT2 of a reader RD.

[0025] In this application, the circuit CI comprises a latch circuit LTC, typically having four transistors T2-T5 adapted for storing digital data elements. Also shown is a reset transistor T1 , which is controlled by a signal TX delivered by processing means COM of the circuit.

[0026] The latch LTC is formed in a frame structure N-ISO, which is itself formed in a semiconductor substrate PSUB. The transistors T1-T3 are formed in a frame structure PW, which is itself formed in a frame structure N-ISO. The interface between the differently doped frame structures forms diodes Dpwniso and Dnisopsub.

[0027] A current flows in the antenna ANT1 in a direction representing a data element stored in the latch LTC so that this element can be read by the reader RD.

[0028] The diode of the polysilicon based bridge DBr is usually formed directly in the substrate PSUB or the frame structure N-ISO, and this may introduce undesired bipolar effects.

[0029] According to various embodiments, a method for manufacturing multiple diodes includes: simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region, and simultaneously etching through a first opening and a second opening in a mask layer to form a first injection surface and a second injection surface; performing a first injection to inject a dopant having a second conductivity type (for example, P-type) into the semiconductor layer at the first injection surface, the semiconductor layer being located on an insulating layer covering the semiconductor and being covered by protruding regions spaced apart from each other to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming multiple diodes, and the multiple diodes extending to the insulating layer at the edge of the protruding region.

[0030] The raised area formed in conjunction with the formation of the floating gate of a floating gate transistor of a non-volatile memory can thus advantageously be used as a hard mask for implantation, thereby making it possible to clearly define the position of the PN junction and therefore the size of the space charge region, while at the same time using conventional implantation masks that can also be used for the manufacture of non-volatile memories without the need to provide strict alignment of these masks.

[0031] Furthermore, the implantation of the junction till the insulating layer makes it possible to suppress bipolar parasitic effects with the underlying substrate.

[0032] Additionally, since the semiconductor layer and the conductive layer are etched simultaneously during the formation of the self-aligned diode region, the longitudinal dimension of the protruding region can be advantageously self-aligned. By simultaneously forming the first injection surface and the second injection surface, the lateral dimension of the protruding region can also be advantageously controlled with high precision. In this way, the alignment limitation of the etching mask step can be advantageously overcome. In addition, compared with conventional methods, since two sets of openings are formed simultaneously, the mask step can be eliminated, which can advantageously promote compatibility with other process flows (e.g., NVM technology).

[0033] Although it is also possible to form an implant of the second conductivity type (e.g., P-type) between each protruding region to create a series of diodes from beginning to end, it is advantageous to alternate P-type implants with N-type implants to form PN diodes that are easily used in a Graetz bridge.

[0034] Therefore, according to some embodiments, the method also includes performing a second injection to inject a dopant having a first conductivity type (e.g., N-type) into the semiconductor layer, so that the first injection of the dopant (e.g., P-type) and the second injection of the dopant (e.g., N-type) respectively define a first region in the semiconductor layer that is over-doped with the second conductivity type (e.g., P+ type) relative to the rest of the semiconductor layer, and a second region that is over-doped with the first conductivity type (e.g., N+ type) relative to the rest of the semiconductor layer, the first region is located between the two second regions and is separated from the two second regions by two interlaced regions of the semiconductor layer respectively located under two adjacent protrusion regions, and each diode is formed at the junction between the first region and the interlaced region.

[0035] According to one embodiment, the first region is of P+ conductivity type forming an anode of the diode, the second region is of N+ conductivity type forming a cathode of the diode together with the staggered region, and the method further comprises forming contacts on the first and second regions.

[0036] The insulating layer may be of a shallow trench type, and the semiconductor layer may be formed by depositing polysilicon on the insulating layer and implanting a dopant having the first conductivity type.

[0037] Advantageously, the raised region comprises a dielectric layer encapsulated by the gate material.

[0038] According to one embodiment, the formation of the semiconductor layer is performed simultaneously with the formation of the floating gate of the floating gate transistor, and the formation of the protrusion region is performed simultaneously with the formation of the control gate of the floating gate transistor.

[0039] According to various embodiments, an integrated circuit includes: a semiconductor layer having a first conductivity type on top of an insulating layer covering a semiconductor substrate; protrusion regions having equal lateral and longitudinal dimensions and spaced apart from each other on the semiconductor layer, the longitudinal dimensions being the same as corresponding dimensions of the underlying semiconductor layer; and a PN junction sequence forming a diode, the diode extending in the semiconductor layer to the insulating layer at the edge of the protrusion region.

[0040] According to some embodiments, an integrated circuit includes a first region in a semiconductor layer that is over-doped with a second conductivity type relative to the rest of the semiconductor layer, and a second region that is over-doped with a first conductivity type relative to the rest of the semiconductor layer, the first region being located between the two second regions, and separated from the two second regions by two staggered regions of the semiconductor layer respectively located under two adjacent protrusion regions, each diode being formed at a junction between the first region and the staggered region, the junction forming a diode.

[0041] According to one embodiment, the first region is of P+ conductivity type forming an anode of the diode, the second region is of N+ conductivity type forming a cathode of the diode together with the staggered region, and the first and second regions further comprise contacts on their surfaces.

[0042] The semiconductor layer may be a polysilicon layer.

[0043] The raised region may include a dielectric layer capped by a gate material.

[0044] Advantageously, the diodes form a Graetz bridge current bridge rectifier.

[0045] According to one embodiment, wherein the integrated circuit further includes floating gate transistors each including a floating gate and a control gate, the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the protrusion region is located at the same level as the control gates of the floating gate transistors.

[0046] The integrated circuit may also include non-volatile memory having floating gate transistors.

[0047] In other words, various embodiments described herein relate to a diode having well-defined lateral and longitudinal dimensions and being completely insulated from a substrate. Thus, the behavior of the diode can advantageously be strictly controlled, and parasitic effects due to PN junctions between the doped regions of the diode and the substrate do not occur.

[0048] The various embodiments described herein can also be advantageously fully compatible with the technical constraints of using and manufacturing non-volatile memories (particularly non-volatile memories including floating gate transistors) without adding additional mask steps. For example, the method of manufacturing a diode as described above can allow the diode to be manufactured using an NVM array. Flexibility in the location of the diode can also be advantageously achieved (e.g., placing the diode inside rather than at the periphery).

[0049] For example, the proposed embodiment mode enables formation of a diode without adding any steps and, in particular, without adding a mask step that is essential for alignment for manufacturing a floating gate transistor.

[0050] Furthermore, the embodiments described herein may be optimized with respect to technical areas, particularly with respect to the control of dopant diffusion regions.

[0051] The embodiments described herein can also advantageously allow for a reduction in the surface area occupied by the diode. Due to the alignment limitations of the masking steps, the manufacturing process can limit the size of the protruding region used as a hard mask when multiple masking steps are used to define the protruding region. The manufacturing process of the following embodiments can allow for a smaller lateral size of the protruding region, which can advantageously reduce the use of surface area and / or improve the performance of the diode.

[0052] The following figures illustrate embodiments of a fabrication process for forming a semiconductor device including a series of diodes. Figure 2-Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B and Fig. 9A , Fig. 9B Illustrated are cross-sectional views of a semiconductor device during various stages of fabrication in accordance with an embodiment of the present invention.

[0053] Figure 2 FIG. 1 illustrates a semiconductor device including a semiconductor substrate during manufacture according to an embodiment of the present invention. Figure 2 , the semiconductor substrate 1 may be a reference Figure 1 The substrate PSUB itself or the frame-shaped structure formed in the substrate (for example, refer again to Figure 1 , frame structure N-ISO).

[0054] Figure 3 FIG. 1 illustrates a semiconductor device during manufacturing and after forming an insulating layer over a semiconductor substrate according to an embodiment of the present invention. Figure 3 , an insulating layer 3 is formed on the surface of the semiconductor substrate 1. The insulating layer 3 may be formed on the surface of the semiconductor substrate 1, for example, by a method for forming a shallow insulating trench.

[0055] Figure 4 FIG. 1 illustrates a semiconductor device during manufacturing and after forming a semiconductor layer over an insulating layer according to an embodiment of the present invention. Figure 4 , a semiconductor layer 5 (eg, a polysilicon layer doped with a first conductivity type (eg, N-type)) is formed on the insulating layer 3. In a conventional method for manufacturing a nonvolatile memory, this step may be performed in conjunction with a step of forming a polysilicon floating gate of a floating gate transistor.

[0056] Figure 5 FIG. 1 illustrates a semiconductor device during fabrication and after forming a dielectric layer and a conductive layer over a semiconductor layer according to an embodiment of the present invention. Figure 5, a dielectric layer 7 is formed on the surface of the semiconductor layer 5, and a conductive layer 9 is formed on the dielectric layer 7. For example, according to a conventional method for manufacturing a non-volatile memory (during which a control gate of a floating gate transistor is formed), the conductive layer 9 may be a semiconductor layer such as a polysilicon layer, which generally includes a dielectric layer encapsulated by a polysilicon layer.

[0057] The control gate is formed, for example, at Figure 5 The control gate can also be formed according to any other gate material (for example, metal). Therefore, in an alternative embodiment, the conductive layer 9 can be replaced by a metal layer. Additionally, structures called "dummy objects" can be added to the functional structure to avoid periodic interruptions that may be harmful, for example, in certain steps of integrated circuit manufacturing. Dummy objects usually do not have any supplementary functions.

[0058] Fig. 6A and Figure 6B A semiconductor device is illustrated during fabrication and after etching a stack according to an embodiment of the present invention, wherein Fig. 6A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 6B A top view of a semiconductor device is shown.

[0059] refer to Fig. 6A and Figure 6B , a first etching mask layer 31 is deposited on the conductive layer 9. The conductive layer 9, the dielectric layer 7 and the semiconductor layer 5 are patterned using a process common to the floating gate process. This etching is common to the non-volatile floating gate etching, so no additional mask is required. Specifically, as Figure 6B As shown in the top view of FIG. 1 , an island including a semiconductor layer 5 and a conductive layer 9 (ie, a self-aligned diode region 35 ) is formed on the insulating layer 3 .

[0060] The self-aligned diode region 35 includes a longitudinal dimension L 1 Advantageously, the longitudinal dimension L 1 35. The self-aligned diode region 35 may be formed in the semiconductor layer 5 and the conductive layer 9. Such self-alignment may provide the benefit of precisely defining the longitudinal dimensions of the diode formed in the self-aligned diode region 35. In contrast, conventional methods may require additional masking steps and may have larger, more varied longitudinal dimensions that may differ between the semiconductor layer and the conductive layer. Additionally, the self-aligned diode region 35 may have any suitable width and may extend beyond the boundaries of the features shown.

[0061] Fig. 7A and Figure 7B A semiconductor device is illustrated during fabrication and after etching the conductive layer and the dielectric layer to form a raised region according to one embodiment of the present invention, wherein Fig. 7A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 7B A top view of a semiconductor device is shown.

[0062] refer to Fig. 7A and Figure 7B , the conductive layer 9 is patterned to form the protruding region 51. Specifically, a plurality of openings are simultaneously formed in the second etching mask layer 32. The plurality of openings include one or more first openings 6, and also include one or more second openings 8. Advantageously, the protruding region 51 separating the plurality of openings is formed in a single masking step, so that the protruding region width W of the protruding region 51 is 1 Free from potential alignment errors.

[0063] In addition, the first opening 6 and the second opening 8 may have a first opening width W defined by the patterning process of the second etching mask layer 32. 2 and the second opening width W 3 Therefore, the influence of potential alignment errors can be advantageously avoided. 2 and the second opening width W 3 It can be the same or different. It is also conceivable that the widths of the individual first openings can be different from each other. Similarly, the widths of the individual second openings can also be different from each other.

[0064] The protruding region 51 may advantageously be a pseudo control gate designated in the context of a method for manufacturing a floating gate transistor. The protruding region 51 may be formed by etching the conductive layer 9 and the dielectric layer 7 through the first opening 6 and the second opening 8. In one embodiment, the etching process includes more than one etching step. Each of the protruding regions 51 includes two protruding region edges 53. The protruding region edges 53 define a width W of the protruding region 51. 1 .

[0065] like Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B As shown, the raised region 51 is used as a hard mask to form an implantation of dopants in the semiconductor layer 5 .

[0066] Fig. 8A and Figure 8B A semiconductor device is illustrated during fabrication and after forming a first implant mask layer according to an embodiment of the present invention, wherein Fig. 8A FIG. 4 shows a cross-sectional view of a semiconductor device, and Figure 8B A top view of a semiconductor device is shown.

[0067] refer to Fig. 8A and Figure 8B, a first implant mask layer 33 is formed and patterned to define a first implant surface 10. The first implant mask layer 33 may be subject to a certain amount of alignment error (eg, due to W 4 Advantageously, the alignment error that may be introduced due to the limitation of the implantation mask process does not affect the first opening width W 2 , the first opening width W 2 The lateral dimensions of the first injection surface 10 are defined.

[0068] The first implantation surface 10 covers the portion of the semiconductor layer 5 between the two protruding regions 51 and may overflow onto a portion of the strip of the protruding regions 51 as shown. 4 Parts of the raised areas 51 may be exposed. Thus, even if the first implantation surface 10 is poorly aligned relative to the designated implantation surface (i.e., the surface of the semiconductor layer 5 between the two raised areas 51), the resulting implanted area will be precisely and regularly defined by the raised area edges 53 of the raised areas 51. Thus, in particular in methods including forming floating gate transistors, the first implantation 40 does not require a supplementary critical masking step. This may allow a good degree of control over the implantation surface and, therefore, may allow a lateral distribution of dopants in the semiconductor layer 5.

[0069] like Figure 8B As schematically shown in , a first implantation 40 is performed to dope the first implantation surface 10 with a first dopant of a second conductivity type. As shown, in one embodiment, the second conductivity type is p-type. Alternatively, the second conductivity type may also be n-type. The first dopant concentration in the semiconductor layer 5 may be high (p+) so that the semiconductor layer 5 is overdoped relative to the doping of the semiconductor layer 5 at the first implantation surface 10 (which may have the first conductivity type). In the case where the first dopant is of an opposite conductivity type compared to the semiconductor layer 5, the first implantation 40 may be a compensation doping process.

[0070] Fig. 9A and Fig. 9B A semiconductor device is illustrated during fabrication and after forming a second implant mask layer according to an embodiment of the present invention, wherein Fig. 9A FIG. 4 shows a cross-sectional view of a semiconductor device, and Fig. 9B A top view of a semiconductor device is shown.

[0071] refer to Fig. 9A and Fig. 9B , a second implant mask layer 34 is formed and patterned to define the second implant surface 13. The second implant mask layer 34 may also be subject to a certain amount of alignment error (such as caused by W 5Qualitatively depicted). Similar to the first implant, advantageously, the alignment error that may be introduced due to the limitations of the implant mask process does not affect the second opening width W 3 , the second opening width W 3 The lateral dimensions of the second injection surface 13 are defined.

[0072] A first implantation region 11-11' is formed below the first implantation surface 10 by the first implantation 40. The first implantation region 11-11' comprises a first strongly doped region 11 extending from the first implantation surface 10. Due to dopant diffusion, the first implantation region 11-11' also comprises a first deeper, less strongly doped region 11'. In one embodiment, the first deeper, less strongly doped region 11' extends to the insulating layer 3. The first implantation region 11-11' may be overdoped relative to the remaining semiconductor layer 5. For example, the dopant concentration in the first implantation region 11-11' may be 100 times higher.

[0073] The second implantation surface 13 covers the portion of the semiconductor layer 5 between the two protruding regions 51 and may overflow onto a portion of the strip of the protruding region 51 as shown. 5 Portions of the raised area 51 may be exposed. Thus, similar to the first implant surface 10, even if the second implant surface 13 is misaligned relative to the designated implant surface, the resulting implanted area will be precisely and regularly defined by the raised area edge 53 of the raised area 51. Thus, in particular in methods including forming floating gate transistors, the second implant 43 also does not require additional critical masking steps. This may allow a good degree of control over the implant surface and, therefore, may allow a lateral distribution of dopants in the semiconductor layer 5.

[0074] like Fig. 9B As schematically shown in FIG. 4 , a second implantation 43 is performed to dope the second implantation surface 13 with a second dopant of the first conductivity type. As shown in the figure, in one embodiment, the first conductivity type is n-type. Alternatively, the first conductivity type may also be p-type. The second dopant concentration in the semiconductor layer 5 may be high (n+) to overdope the semiconductor layer 5 at the second implantation surface 13.

[0075] Fig. 10A and Fig. 10B An exemplary semiconductor device according to an embodiment of the present invention is shown, wherein Fig. 10A shows a cross-sectional view of a semiconductor device, and Fig. 10B A top view of a semiconductor device is shown. Fig. 10A and Fig. 10B A semiconductor device can use the embodiment methods illustrated and described herein (eg, Figures 2 to 9B One or more steps) to form.

[0076] refer to Fig. 10A and Fig. 10B , a second implantation region 14-14' is formed below the second implantation surface 13 by a second implantation 43. The second implantation region 14-14' includes a second strongly doped region 14 extending from the second implantation surface 13. Due to dopant diffusion, the region 14-14' also includes a second deeper, weakly doped region 14'. In one embodiment, the second deeper, weakly doped region 14' extends to the insulating layer 3.

[0077] Similar to the first implanted regions 11-11', the second implanted regions 14-14' may be overdoped relative to the remaining semiconductor layer 5. Specifically, the region of the semiconductor layer 5 below the protruding region 51 is not implanted and forms the staggered region 12, which may have a lower dopant concentration than the first implanted regions 11-11' and the second implanted regions 14-14'.

[0078] The thickness of the semiconductor layer 5 and the implantation depth of the dopant can be advantageously designed so that the first dopant of the first implantation 40 and / or the second dopant of the second implantation 43 diffuses over the entire thickness of the semiconductor layer 5 up to the insulating layer 3. Therefore, the PN junction between the first implantation region 11-11' and the staggered region 12 extends to the insulating layer 3 and is located at the edge of the protruding region edge 53 in the semiconductor layer 5. Therefore, the diode D 1 , D 2 , D 3 Advantageously, it may be completely insulated from the semiconductor substrate 1 .

[0079] Since the dopant implantation is not isotropic, the term “edge of the protruding region” refers to a region adjacent to or close to the geometrical projection of the outline of the protruding region in the semiconductor layer 5 .

[0080] Therefore, the first injection regions 11-11' form anode regions, and the second injection regions 14-14' and the interleaved region 12 form three diodes D 1 , D 2 , D 3 Thus, for example, after forming the spacer 15 by self-aligning the silicided area of ​​the semiconductor layer 5 not covered by the spacer 15, the cathode 17 and the anode 19 are formed. A cathode contact 21 and an anode contact 23 are also formed to electrically contact the cathode 17 and the anode 19, respectively. For example, the cathode contact 21 and the anode contact 23 may be metal contacts.

[0081] Across the self-aligned diode region 35, the cathode 17 and the anode 19 are separated by a longitudinal dimension L 1Similarly, cathode 17 and anode 19 are defined by lateral dimensions W due to the use of raised regions 51 formed in a single masking step as a hard mask during implantation. 1 , W 2 , W 3 Precisely laterally defined. That is, the longitudinal and lateral dimensions of the diode are defined with little or no alignment error.

[0082] Advantageously, due to the increased precision, the width W of the raised area 51 can be reduced. 1 In various embodiments, the width W 1 Between about 0.5 μm and about 0.9 μm, and in one embodiment about 0.7 μm. 2 and W 3 Can be similarly reduced. For example, in one embodiment, the width W 1 , W 2 , W 3 can be substantially equal and are both approximately 0.7 μm. In another embodiment, the width W 1 , W 2 , W 3 All are about 0.5μm.

[0083] Vertical size L 1 Can be compared to the width W 1 , W 2 , W 3 In various embodiments, the longitudinal dimension L 1 Between about 150 μm to about 500 μm, and in one embodiment about 200 μm.

[0084] One of every two regions between two strips of the protruding region 51 is doped with the first conductivity type, while the other is doped with the second conductivity type. Thus, three diodes D 1 , D 2 , D 3 However, depending on the specific design details of a given application, there may be more or fewer diodes.

[0085] Additionally, at least one cathode region (ie, second implant region 14-14') is provided for two different diodes (eg, diode D 1 and D 2 ) may be shared and located between two corresponding anode regions (ie, first injection regions 11-11'). Furthermore, at least one anode region may be shared by two different diodes (eg, diode D 2 and D 3 ) are common and located between two corresponding cathode regions.

[0086] This configuration with a common electrode may be advantageous for constructing a Graetz bridge type diode bridge (with an anode node common to both diodes and a cathode node common to both diodes).

[0087] Although the present invention has been described with reference to the exemplary embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. For example, for the second implant 43, in a manner similar to the first implant 40, it is feasible to implant a dopant having a second conductivity type, thereby forming a series of diodes connected head to tail between the implanted region and the staggered region, and the respective cathodes can be electrically connected via contacts extending in a plane other than the plane of the drawing. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

[0088] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the overall description and claims submitted herein.

[0089] Example 1. A method for manufacturing a semiconductor device, the method comprising: simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, the semiconductor layer having a first conductivity type; etching through a first opening in a mask layer to form a first injection surface on the semiconductor layer, and forming a plurality of raised regions of a conductive material including the conductive layer above the semiconductor layer; and using the plurality of raised regions as part of a first injection mask, performing a first injection of a dopant having a second conductivity type into the semiconductor layer to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode, the diode extending vertically from an upper surface of the semiconductor layer to the insulating layer.

[0090] Example 2. The method of Example 1, wherein the semiconductor layer is polysilicon.

[0091] Example 3. The method of one of Examples 1 or 2, wherein the conductive layer is polysilicon.

[0092] Example 4. The method of one of Examples 1 to 3, wherein a width of the first opening is between about 0.5 μm and about 0.9 μm.

[0093] Example 5. The method according to one of Examples 1 to 4 further includes: etching through a second opening of the mask layer to form a second injection surface on the semiconductor layer, wherein etching through the second opening is performed simultaneously with etching through the first opening; and using a plurality of protrusion regions as part of a second injection mask, performing a second injection of dopants having a first conductivity type into the semiconductor layer, so that each diode includes a heavily doped region of the first conductivity type adjacent to a lightly doped region of the first conductivity type, and the lightly doped region of the first conductivity type is adjacent to a doped region of the second conductivity type.

[0094] Example 6. The method of one of Examples 1 to 5, wherein each of the plurality of raised regions has a width between about 0.5 μm and about 0.9 μm.

[0095] Example 7. A method for manufacturing an integrated circuit, the method comprising: forming an insulating layer above a surface of a semiconductor substrate, the insulating layer including an active region at a first position of the semiconductor substrate; forming a semiconductor layer having a first conductivity type and covering the insulating layer; forming a gate dielectric layer above the semiconductor layer; forming a conductive layer above the gate dielectric layer; patterning the semiconductor layer, the gate dielectric layer, and the conductive layer simultaneously to form a self-aligned diode region on the insulating layer and at a second position of the semiconductor substrate; patterning the conductive layer to form a control gate covering a floating gate at a first position, and to form a protruding region covering the semiconductor layer at a second position; and using a plurality of protruding regions as hard masks, injecting a second conductive type dopant into a first region of the semiconductor layer so that staggered regions below the plurality of protruding regions remain doped with the first conductive type to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode, and the diode extending vertically from the upper surface of the semiconductor layer to the insulating layer.

[0096] Example 8. The method of Example 7, wherein the semiconductor layer is polysilicon.

[0097] Example 9. The method of one of Examples 7 or 8, wherein the conductive layer is polysilicon.

[0098] Example 10. The method of one of Examples 7 to 9, wherein each distance separating adjacent protruding regions in the plurality of protruding regions is between about 0.5 μm and about 0.9 μm.

[0099] Example 11. The method of one of Examples 7 to 10, further comprising: using the plurality of raised regions as a hard mask to implant a dopant of the first conductivity type into a second region of the semiconductor layer, the second region of the semiconductor layer being more heavily doped than the staggered region.

[0100] Example 12. A method according to one of Examples 7 to 11, wherein patterning the conductive layer to form a plurality of protruding regions includes: simultaneously forming a first opening and a second opening in the mask layer, the first opening directly covering the first region, and the second opening directly covering the second region.

[0101] Example 13. An integrated circuit comprising: a semiconductor substrate; an insulating layer covering the semiconductor substrate; a semiconductor layer of a first conductivity type covering the insulating layer, the semiconductor layer comprising a longitudinal length; a plurality of protrusion regions covering the semiconductor layer and spaced apart from each other, each of the plurality of protrusion regions comprising a longitudinal length equal to the longitudinal length of the semiconductor layer; and a PN junction sequence in the semiconductor layer, each PN junction being located at an edge of an associated protrusion region and extending vertically from an upper surface of the semiconductor layer to the insulating layer.

[0102] Example 14. The integrated circuit of Example 13, wherein the semiconductor layer is polysilicon.

[0103] Example 15. The integrated circuit of one of Examples 13 or 14, wherein each of the plurality of raised regions is polysilicon.

[0104] Example 16. An integrated circuit according to one of Examples 13 to 15, further comprising a plurality of diodes, each diode comprising a PN junction in a PN junction sequence and a heavily doped region of the first conductivity type adjacent to a lightly doped region of the first conductivity type, the lightly doped region of the first conductivity type adjacent to a doped region of the second conductivity type.

[0105] Example 17. The integrated circuit of one of Examples 13 to 16, wherein the lateral width of each protruding region is substantially equal and is between about 0.5 μm and about 0.9 μm.

[0106] Example 18. The integrated circuit of one of Examples 13 to 17, wherein each distance separating adjacent ones of the plurality of protruding regions is between about 0.5 μm and about 0.9 μm.

[0107] Example 19. The integrated circuit of one of Examples 13 to 18, further comprising a plurality of diodes connected as a rectifier, each of the plurality of diodes comprising a PN junction in a PN junction sequence.

[0108] Example 20. The integrated circuit of one of Examples 13 to 19, wherein the rectifier comprises a Graetz bridge.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on the insulating layer, the semiconductor layer having a first conductivity type; Etching through the first opening of the mask layer to form a first implantation surface on the semiconductor layer and to form a plurality of raised areas above the semiconductor layer, the plurality of raised areas comprising conductive material of the conductive layer; as well as Using the multiple protrusion areas as part of a first injection mask, a first injection of a dopant having a second conductivity type into the semiconductor layer is performed to form a PN junction sequence in the semiconductor layer, wherein the PN junction sequence forms a diode that extends vertically from the upper surface of the semiconductor layer to the insulating layer. The method of claim 1 , wherein the semiconductor layer is polysilicon. The method of claim 1 , wherein the conductive layer is polysilicon. The method according to claim 1 , wherein a width of the first opening is between 0.5 μm and 0.9 μm.

5. The method according to claim 1, further comprising: etching through a second opening of the mask layer to form a second implantation surface on the semiconductor layer, wherein etching through the second opening is performed simultaneously with etching through the first opening; as well as Using the multiple protrusion regions as part of a second injection mask, a second injection of dopants having the first conductivity type into the semiconductor layer is performed so that each diode includes a heavily doped region of the first conductivity type adjacent to a lightly doped region of the first conductivity type, and the lightly doped region of the first conductivity type is adjacent to a doped region of the second conductivity type. 6 . The method according to claim 5 , wherein a width of each of the plurality of protrusion regions is between 0.5 μm and 0.9 μm.

7. A method of manufacturing an integrated circuit, the method comprising: forming an insulating layer over a surface of a semiconductor substrate, the insulating layer including an active region at a first location of the semiconductor substrate; forming a semiconductor layer having a first conductivity type and covering the insulating layer; forming a gate dielectric layer over the semiconductor layer; forming a conductive layer on the gate dielectric layer; simultaneously patterning the semiconductor layer, the gate dielectric layer, and the conductive layer to form a self-aligned diode region on the insulating layer at a second location on the semiconductor substrate; patterning the conductive layer to form a control gate covering the active region at the first position and to form a plurality of protrusion regions covering the semiconductor layer at the second position; as well as Using the multiple protrusion areas as a hard mask, a second conductive type dopant is injected into the first region of the semiconductor layer so that the interlaced areas below the multiple protrusion areas remain doped with the first conductive type to form a PN junction sequence in the semiconductor layer, the PN junction sequence forming a diode that extends vertically from the upper surface of the semiconductor layer to the insulating layer. The method of claim 7 , wherein the semiconductor layer is polysilicon.

9. The method of claim 7, wherein the conductive layer is polysilicon. 10 . The method of claim 7 , wherein each distance separating adjacent ones of the plurality of protrusion regions is between 0.5 μm and 0.9 μm.

11. The method according to claim 7, further comprising: Using the plurality of raised regions as a hard mask, a dopant of the first conductivity type is implanted into a second region of the semiconductor layer, the second region of the semiconductor layer being more heavily doped than the staggered regions.

12. The method of claim 11, wherein patterning the conductive layer to form the plurality of raised areas comprises: A first opening and a second opening are simultaneously formed in the mask layer, the first opening directly covering the first region, and the second opening directly covering the second region.

13. An integrated circuit comprising: Semiconductor substrate; an insulating layer covering the semiconductor substrate; a semiconductor layer of the first conductivity type covering the insulating layer, the semiconductor layer comprising a longitudinal length; a plurality of protrusion regions covering the semiconductor layer and spaced apart from each other, each of the plurality of protrusion regions comprising a longitudinal length equal to the longitudinal length of the semiconductor layer; as well as A PN junction sequence in the semiconductor layer, each PN junction is located at an edge of an associated protruding region and vertically extends from an upper surface of the semiconductor layer to the insulating layer.

14. The integrated circuit of claim 13, wherein the semiconductor layer is polysilicon.

15. The integrated circuit of claim 13, wherein each of the plurality of raised regions is polysilicon.

16. The integrated circuit of claim 13, further comprising: A plurality of diodes, each diode comprising a PN junction in the PN junction sequence and a heavily doped region of the first conductivity type adjacent to a lightly doped region of the first conductivity type, wherein the lightly doped region of the first conductivity type is adjacent to a doped region of the second conductivity type. 17 . The integrated circuit of claim 13 , wherein a lateral width of each of the protruding regions is substantially equal and is between 0.5 μm and 0.9 μm. 18 . The integrated circuit of claim 13 , wherein each distance separating adjacent ones of the plurality of protruding regions is between 0.5 μm and 0.9 μm.

19. The integrated circuit of claim 13, further comprising: A plurality of diodes are connected as a rectifier, each diode in the plurality of diodes comprising a PN junction in the PN junction sequence.

20. The integrated circuit of claim 19, wherein the rectifier comprises a Graetz bridge.

Images