Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application provides a semiconductor device and a manufacturing method of a semiconductor device, which reduces manufacturing cost and improves characteristics. The semiconductor device has a main terminal, one end of which is respectively joined to a circuit pattern in an element region, and the other end of which extends from one side of a metal base substrate to the outside of the metal base substrate. Further, the semiconductor device has a control terminal, which is disposed in a control region and includes a control wiring portion, the control region being adjacent to the other side of the metal base substrate opposite to the one side to which the main terminal is joined, and a sealing member, which seals a main surface of the metal base substrate and the control region. Such a semiconductor device directly joins the main terminal to the circuit pattern on which the first and second semiconductor elements are disposed. Therefore, compared with the case where they are joined by a bonding wire, the resistance can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] In recent years, a semiconductor device includes a semiconductor element and a control IC (Integrated Circuit) that achieves drive control and the like of the semiconductor element. The semiconductor element is, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like. Such a semiconductor device has a substrate provided with a semiconductor element and a case that houses the substrate, and is sealed by a sealing resin. The case is embedded with a main terminal that is formed integrally with a main electrode electrically connected to the semiconductor element, and a control terminal that is electrically connected to the control IC. In addition, the control IC is provided in a region of the case where the control terminal is arranged.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-146704 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the above-described semiconductor device, a molding process for molding the main terminal and the control terminal integrally with the case and a bonding process for bonding the substrate to such a case are required. Furthermore, a process for electrically connecting a circuit pattern provided with the semiconductor element to the main terminal molded integrally with the case by a bonding wire is also required. Thus, a large number of processes and components are required when manufacturing the semiconductor device, and the manufacturing cost is high. In addition, further improvement in electrical characteristics and thermal characteristics is also sought.

[0008] The present application has been made in view of the circumstances, and aims to provide a semiconductor device and a manufacturing method of a semiconductor device that are reduced in manufacturing cost and improved in characteristics.

[0009] TECHNICAL SOLUTION

[0010] According to one aspect of the present application, there is provided a semiconductor device including: a plurality of semiconductor elements; a substrate having an insulating layer and a plurality of circuit patterns formed on the insulating layer, and the plurality of circuit patterns provided with the plurality of semiconductor elements in element regions provided on a main surface; a plurality of main terminals having one end portions joined to the plurality of circuit patterns in the element regions and the other end portions extending from a first side portion of the substrate to an outside of the substrate; a plurality of control terminals disposed in a control region including control wiring portions, the control region being adjacent to a second side portion of the substrate opposite to the first side portion; and a sealing member sealing the main surface and the control region of the substrate.

[0011] Further, according to one aspect of the present application, there is provided a method of manufacturing a semiconductor device including: a preparation step of preparing a substrate having an insulating layer and a plurality of circuit patterns formed on the insulating layer, a plurality of main terminals, and a plurality of control wiring; a disposition step of disposing the plurality of circuit patterns in element regions provided on a main surface of the substrate, the one end portions of the plurality of main terminals in a manner that the other end portions of the plurality of main terminals extend from a first side portion of the substrate to an outside of the substrate, and the plurality of control wiring in a control region adjacent to a second side portion of the substrate opposite to the first side portion; a joining step of joining the one end portions of the plurality of main terminals disposed on the plurality of circuit patterns of the substrate; and a sealing step of sealing the main surface and the control region of the substrate with a sealing member.

[0012] Technical Effects

[0013] According to the disclosed technology, manufacturing cost can be reduced, and characteristics can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a diagram illustrating an appearance of a semiconductor device of an embodiment.

[0015] Figure 2 is a side sectional view of a semiconductor device of an embodiment.

[0016] Figure 3 is a top sectional view of a semiconductor device of an embodiment.

[0017] Figure 4 is a flowchart illustrating a method of manufacturing a semiconductor device of an embodiment.

[0018] Figure 5 is a diagram for explaining a joining step of an external connection terminal included in a method of manufacturing a semiconductor device of an embodiment.

[0019] Figure 6FIG. 1 is a view for explaining a bonding step of a suspension terminal included in a manufacturing method of a semiconductor device according to an embodiment.

[0020] Figure 7 FIG. 1 is a view for explaining a bonding step of a semiconductor element, an electronic component, and a connection step using a bonding wire included in a manufacturing method of a semiconductor device according to an embodiment.

[0021] Figure 8 FIG. 1 is a view for explaining a sealing step included in a manufacturing method of a semiconductor device according to an embodiment.

[0022] Symbol Explanation

[0023] 10 Semiconductor device

[0024] 21a First semiconductor element

[0025] 21b Second semiconductor element

[0026] 22 Metal base substrate

[0027] 22a Element region

[0028] 23 Insulating layer

[0029] 24a, 24b, 24c, 24d Circuit pattern

[0030] 24e, 24f, 24g Fixing pattern

[0031] 25 Heat dissipation plate

[0032] 26 Bonding wire

[0033] 30, 31, 32, 33 Control terminal

[0034] 30a Control region

[0035] 34 Control wiring portion

[0036] 40, 41a, 41b, 41c, 41d Main terminal

[0037] 41a1, 42a1, 43a1 Bonding portion

[0038] 41a2, 42a2, 43a2 Association portion

[0039] 41a3 Terminal portion

[0040] 42, 43, 44 Suspension terminal

[0041] 42a3, 43a3 Suspension portion

[0042] 50 Electronic component

[0043] 60 sealing member

[0044] 80 molding die

[0045] 81 upper die

[0046] 82 lower die

[0047] 83 flow path

[0048] 84 chamber DETAILED DESCRIPTION

[0049] Hereinafter, an embodiment will be described with reference to the drawings. Note that in the following description, "front surface" and "upper surface" mean a surface facing the upper side in the semiconductor device 10 of FIG. 1. Similarly, "upper" means a direction of the upper side in the semiconductor device 10 of FIG. 1. "Back surface" and "lower surface" mean a surface facing the lower side in the semiconductor device 10 of FIG. 1. Similarly, "lower" means a direction of the lower side in the semiconductor device 10 of FIG. 1. As necessary, the same directionality is indicated in other drawings. "Front surface", "upper surface", "upper", "back surface", "lower surface", "lower", and "side surface" are merely expressions for determining relative positional relationships and do not limit the technical idea of the present application. For example, "upper" and "lower" do not necessarily mean vertical directions with respect to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Figure 2 Figure 2 The semiconductor device of the embodiment will be described with reference to FIG. 1. Figure 2 is a diagram illustrating the appearance of the semiconductor device of the embodiment. Note that Figure 2 (A) of FIG. 1 is a side view of the semiconductor device 10 (viewed from the (B) of FIG. 1 is a top view of the semiconductor device 10.

[0050] is a side sectional view of the semiconductor device of the embodiment. Note that Figures 1-3 is a top sectional view of the semiconductor device of the embodiment. Note that Figure 1 is a sectional view at a single-dot chain line X-X of Figure 1 is a sectional view at a single-dot chain line X-X of Figure 1 is a sectional view at a single-dot chain line X-X of Figure 1 is a diagram corresponding to a top view of Figure 2 Figure 3 First, as Figure 2 Figure 3 Figure 3 Figure 2 Figure 3 Figure 1

[0051] First, as Figure 1 ​​​​​​​As shown, the semiconductor device 10 is sealed with the sealing member 60 so as to have a three-dimensional shape. Note that the sealing member 60 of the semiconductor device 10 can have a cubic shape with a curvature at the corners. Further, the semiconductor device 10 extends a plurality of control terminals 30 and a plurality of main terminals 40 from both sides of the long side of the sealing member 60. Note that in this embodiment, the control terminals and the main terminals are not distinguished and are described as the control terminals 30 and the main terminals 40.

[0052] The semiconductor device 10 of this kind Figure 2 and Figure 3 The structure shown is sealed with the sealing member 60. That is, the semiconductor device 10 has six sets of the first semiconductor element 21a and the second semiconductor element 21b, the metal base substrate 22, the control terminals 30 (including the control terminals 31 to 33), the main terminals 40 (including the main terminals 41a to 41d), and the electronic component 50. Further, the semiconductor device 10 appropriately connects between the control terminals 30, the electronic component 50, the first semiconductor element 21a, the second semiconductor element 21b, and the main terminals 40 with the bonding wires 26. Note that in Figure 3 , the illustration of the bonding wires connected to the electronic component 50 is omitted. Also, the semiconductor device 10 of this kind is sealed with the sealing member 60. Note that the bonding wires 26 are composed of a metal such as aluminum or copper, which has excellent conductivity, or an alloy containing at least one of these metals. Further, the diameter of these bonding wires 26 is preferably 100 μm or more and 1 mm or less.

[0053] The first semiconductor element 21a includes a switching element such as an IGBT or a power MOSFET. When the first semiconductor element 21a is an IGBT, it has a collector as the main electrode on the back side and a gate and emitter as the main electrodes on the front side. When the first semiconductor element 21a is a power MOSFET, it has a drain as the main electrode on the back side and a gate and source as the main electrodes on the front side. The back side of the first semiconductor element 21a is bonded to the circuit patterns 24a, 24b, 24c, and 24d on the metal substrate 22 by solder (not shown). The second semiconductor element 21b includes a diode such as an SBD (Schottky Barrier Diode) or an FWD (Free Wheeling Diode). This second semiconductor element 21b has an output electrode (cathode) as the main electrode on the back side and an input electrode (anode) as the main electrode on the front side. The back side of the second semiconductor element 21b is bonded to the circuit patterns 24a, 24b, 24c, and 24d by solder (not shown). It should be noted that, instead of the first semiconductor element 21a and the second semiconductor element 21b, an RC (Reverse-Conducting) IGBT, which simultaneously possesses the functions of an IGBT and a FWD, can also be used. Furthermore, in Figure 3 The example shown only illustrates the case where six sets of first semiconductor elements 21a and second semiconductor elements 21b are provided. However, the number of sets is not limited to six; it can be set to a number corresponding to the specifications of the semiconductor device 10.

[0054] The metal substrate 22 has an insulating layer 23, circuit patterns 24a, 24b, 24c, 24d formed on the insulating layer 23, fixing patterns 24e, 24f, 24g, and a heat sink 25 formed on the back side of the insulating layer 23. The insulating layer 23 is composed of any one of epoxy resin, epoxy resin mixed with inorganic fillers, polyimide, or polytetrafluoroethylene. It should be noted that the thickness of the insulating layer 23 is preferably 0.09 mm or more and 0.15 mm or less. The circuit patterns 24a, 24b, 24c, 24d and the fixing patterns 24e, 24f, 24g are made of a metal with excellent conductivity, such as copper or a copper alloy. It should be noted that... Figure 2 and Figure 3The shapes of the circuit patterns 24a, 24b, 24c, 24d and the fixation patterns 24e, 24f, 24g are one example. Such circuit patterns 24a, 24b, 24c, 24d and fixation patterns 24e, 24f, 24g are generated by etching a conductive plate or foil formed on one face of the insulating layer 23, or are generated by adhering a conductive plate to one face of the insulating layer 23. Note that the thickness of the circuit patterns 24a, 24b, 24c, 24d and the fixation patterns 24e, 24f, 24g is preferably 0.10 mm or more and 1.00 mm or less, more preferably 0.20 mm or more and 0.50 mm or less. Further, as shown in FIG. 2, the circuit patterns 24a, 24b, 24c, 24d are formed in the element region 22a of the main face of the metal base substrate 22. The circuit patterns 24a, 24b, 24c, 24d have the first semiconductor element 21a and the second semiconductor element 21b adhered thereto by solder (not shown), respectively. Note that the shapes, arrangement positions, and number of the circuit patterns 24a, 24b, 24c, 24d, and the arrangement positions of the first semiconductor element 21a and the second semiconductor element 21b are one example, and are not limited to Figure 2 and Figure 3 Further, as shown in FIG. 2, the circuit patterns 24a, 24b, 24c, 24d are formed in the element region 22a of the main face of the metal base substrate 22. The circuit patterns 24a, 24b, 24c, 24d have the first semiconductor element 21a and the second semiconductor element 21b adhered thereto by solder (not shown), respectively. Note that the shapes, arrangement positions, and number of the circuit patterns 24a, 24b, 24c, 24d, and the arrangement positions of the first semiconductor element 21a and the second semiconductor element 21b are one example, and are not limited to Figure 2 and Figure 3 Further, as shown in FIG. 2, the circuit patterns 24a, 24b, 24c, 24d are formed in the element region 22a of the main face of the metal base substrate 22. The circuit patterns 24a, 24b, 24c, 24d have the first semiconductor element 21a and the second semiconductor element 21b adhered thereto by solder (not shown), respectively. Note that the shapes, arrangement positions, and number of the circuit patterns 24a, 24b, 24c, 24d, and the arrangement positions of the first semiconductor element 21a and the second semiconductor element 21b are one example, and are not limited to Figure 2 and Figure 3 Further, as shown in FIG. 2, the circuit patterns 24a, 24b, 24c, 24d are formed in the element region 22a of the main face of the metal base substrate 22. The circuit patterns 24a, 24b, 24c, 24d have the first semiconductor element 21a and the second semiconductor element 21b adhered thereto by solder (not shown), respectively. Note that the shapes, arrangement positions, and number of the circuit patterns 24a, 24b, 24c, 24d, and the arrangement positions of the first semiconductor element 21a and the second semiconductor element 21b are one example, and are not limited to

[0055] The heat sink 25 is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat sink using electroplating. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. Heat dissipation can also be improved by mounting a cooler (not shown) on the back of the heat sink 25 using solder or silver solder. In this case, the cooler is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. Additionally, as the cooler, heat sinks or heat sinks composed of multiple heat sinks, as well as water-cooled cooling devices, can be used. Furthermore, the heat sink can be integrated with such a cooler. In this case, it is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. And, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat sink integrated with the cooler, for example, using electroplating. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, etc. It should be noted that the thickness of the heat sink 25 is preferably 0.1 mm or more and 2.0 mm or less.

[0056] One end of the plurality of main terminals 40 is disposed on the metal substrate 22 Figure 3 On the right side, the other end is from the semiconductor device 10 Figure 3 The right-side side (first side) extends outward. Main terminals 41b, 41a, 41c, and 41d of the plurality of main terminals 40 are respectively bonded to circuit patterns 24a, 24b, 24c, and 24d on the metal substrate 22. Furthermore, the main terminal 41a includes a joining portion 41a1, an association portion 41a2, and a terminal portion 41a3. The joining portion 41a1 is parallel to the front surface of the metal substrate 22 and engages with the circuit pattern 24b. The association portion 41a2 is inclined, integrally connecting the joining portion 41a1 and the terminal portion 41a3. The terminal portion 41a3, corresponding to the inclination of the association portion 41a2, moves away from the front surface of the metal substrate 22 and extends outward parallel to the front surface. It should be noted that, although not shown in the figure, the main terminals 41b, 41c, and 41d also have the same structure as the main terminal 41a.

[0057] One end of each of the suspension terminals 42, 43, and 44 is engaged with the previously described fixing patterns 24e, 24f, and 24g, respectively, while the other end faces the outer side of the metal substrate 22. The other end of the suspension terminal 42 is connected to the semiconductor device 10... Figure 3 The upper middle side (third side) is exposed, and the other end of the suspension terminal 43 is exposed from the semiconductor device 10. Figure 3 The lower middle side (fourth side) is exposed, and the other end of the suspension terminal 44 is exposed from the semiconductor device 10. Figure 3The right side surface (first side surface) is exposed. Note that, as will be described later, the suspension terminals 42, 43, 44 are removed from the portions extending from the semiconductor device 10, and the other end portions of the respective suspension terminals do not extend from the side surface of the semiconductor device 10. In addition, as will be described later Figure 6 As shown, the suspension terminals 42, 43 include the bonding portions 42a1, 43a1, the associated portions 42a2, 43a2, and the suspension portions 42a3, 43a3. The suspension terminal 44, although not shown, has the same structure as the suspension terminals 42, 43.

[0058] The plurality of control terminals 30 (including the control terminals 31, 32, 33) are provided in a control region 30a that is adjacent to the other side portion of the metal base substrate 22 opposite to the one side portion to which the plurality of main terminals 40 are bonded. The control region 30a is located at a higher position than the front surface of the metal base substrate 22. The control terminals 30 extend from the side surface of the semiconductor device 10 Figure 3 The left side surface (second side surface) extends outward. The plurality of control terminals 30 also include a control wiring portion 34. The control wiring portion 34 is provided in the control region 30a, and the electronic component 50 is provided to the control wiring portion 34 with solder (not shown). The control wiring portion 34 is located at the same height as the portions of the control terminals 30 extending outward from the side surface. The control wiring portion 34 is located at a higher position than the portions of the main terminals 40 bonded to the circuit patterns 24a, 24b, 24c, 24d and the portions of the suspension terminals 42, 43, 44 bonded to the fixation patterns 24e, 24f, 24g. In addition, the terminal portions 41a3 of the control terminals 30, the main terminals 41a, 41b, 41c, 41d (the terminal portions of the main terminals 41b, 41c, 41d are not shown), and the suspension portions 42a3, 43a3 of the suspension terminals 42, 43, 44 (the suspension portion of the suspension terminal 44 is not shown) are located at the same height.

[0059] The plurality of main terminals 40, the suspension terminals 42, 43, 44, and the control terminals 30 (including the control terminals 31, 32, 33) are composed of a metal such as copper or a copper alloy, which has excellent conductivity. They can also be covered with a metal such as nickel or a nickel alloy.

[0060] The number of electronic components 50 required are respectively joined to the control wiring portion 34 via solder (not shown). In order for the semiconductor device to function as desired, the electronic components 50 are appropriately used, such as a control IC, a thermistor, a capacitor, a resistor, and the like. The sealing member 60 seals the above-described structure. Such a sealing member 60 contains a thermosetting resin such as a maleimide-modified epoxy resin, a maleimide-modified phenol resin, a maleimide resin, and the like, and a filler material contained in the thermosetting resin. As a specific example, there is an epoxy resin containing a filler material such as silicon oxide, aluminum oxide, boron nitride, or aluminum nitride as a filler.

[0061] Next, the semiconductor device 10 is manufactured by Figures 4-8 The manufacturing method of the semiconductor device 10 will be described. Figure 4 is a flowchart showing the manufacturing method of the semiconductor device according to the embodiment. Figure 5 is a view for explaining the joining process of the external connection terminal included in the manufacturing method of the semiconductor device according to the embodiment, Figure 6 is a view for explaining the joining process of the suspension terminal included in the manufacturing method of the semiconductor device according to the embodiment. Note that, Figure 5 and Figure 6 are cross-sectional views corresponding to the positions of the single-dot chain line X-X and the single-dot chain line Y-Y in Figure 3 Figure 7 is a view for explaining the joining process of the semiconductor element and the electronic component and the connection process using the bonding wire in the manufacturing method of the semiconductor device according to the embodiment, Figure 8 is a view for explaining the sealing process included in the manufacturing method of the semiconductor device according to the embodiment. Note that, Figure 7 and Figure 8 are cross-sectional views corresponding to the position of the single-dot chain line X-X in Figure 3

[0062] First, the constituent components of the semiconductor device 10, such as the first semiconductor element 21a, the second semiconductor element 21b, the metal base substrate 22, a lead frame (not shown) in which a plurality of control terminals 30 and a plurality of main terminals 40 and suspension terminals 42, 43, 44 are connected by a tie bar, the electronic components 50, and the raw material of the sealing member 60, are prepared (step S1). Next, the above-described lead frame is placed on the metal base substrate 22 (step S2). At this time, for example, as shown in Figure 5 Figure 5 ​​​The control wiring portion 34 (representing control terminals 31, 32, and 33) is located in the control area 30a. Meanwhile, the connection portion 41a1 (the connection portions of main terminals 41b, 41c, and 41d are not shown) of the main terminals 41a (and similarly for main terminals 41b, 41c, and 41d) included in the lead frame is located on the circuit pattern 24b (circuit patterns 24a, 24c, and 24d) of the metal substrate 22. It should be noted that, at this time, predetermined tools (not shown) are used to maintain the control terminals 30 and the control wiring portion 34 in the control area 30a at a position higher than the main surface of the metal substrate 22.

[0063] Next, as Figure 5 As shown, ultrasonic bonding is used to bond the joint portion 41a1 (in the direction of the dashed arrow) of the main terminal 41a included in the lead frame of the circuit pattern 24b placed on the metal substrate 22. Similarly, ultrasonic bonding is also used to bond the main terminals 41b, 41c, and 41d included in the lead frames of the circuit patterns 24a, 24c, and 24d placed on the metal substrate 22. In addition, simultaneously, as Figure 6 As shown, ultrasonic bonding is used to bond the joint portions 42a1 and 43a1 (in the direction of the dashed arrows) of the suspension terminals 42 and 43 included in the lead frames of the fixing patterns 24e and 24f placed on the metal substrate 22. Similarly, ultrasonic bonding is also used to bond the suspension terminal 44 included in the lead frame of the fixing pattern 24g placed on the metal substrate 22 (step S3). As a result, three of the four sides of the metal substrate 22 are suspended by the main terminals 41a, 41b, 41c, 41d and the suspension terminals 42, 43, 44. As a result, the metal substrate 22 remains horizontal in subsequent processes. In addition, as described above, the thickness of the circuit patterns 24a, 24b, 24c, 24d and the fixing patterns 24e, 24f, 24g of the metal substrate 22 is preferably 0.10 mm or more and 1.00 mm or less, more preferably 0.20 mm or more and 0.50 mm or less. This is approximately 10 times thicker than the insulation layer 23. Therefore, even when ultrasonic bonding is performed on the circuit patterns 24a, 24b, 24c, 24d and the bonding patterns 24e, 24f, 24g on the insulation layer 23, ultrasonic vibrations can be reliably transmitted, and the main terminal 40 and the control terminal 30 can be stably bonded.

[0064] Next, as Figure 7As shown, the first semiconductor element 21a and the second semiconductor element 21b are respectively bonded to the circuit pattern 24b using solder. Similarly, the first semiconductor element 21a and the second semiconductor element 21b are respectively bonded to the circuit patterns 24a, 24c, and 24d using solder. Additionally, the electronic component 50 is bonded to the control wiring section 34 using solder (step S4). Next, as... Figure 7 As shown, the control terminal 30, electronic component 50, first semiconductor element 21a, second semiconductor element 21b, and main terminal 40 are connected by bonding wire 26. Figure 7 Properly connect the main terminals 41a to each other (step S5).

[0065] Next, the upper mold 81 and lower mold 82 of the forming mold 80 are used to form the material as described above. Figure 7 The structure shown is sandwiched in the middle. Therefore, as... Figure 8 As shown, a metal substrate 22, multiple control terminals 30 of the lead frame, multiple main terminals 40, and suspension terminals 42, 43, and 44 are housed in a chamber 84 formed by an upper mold 81 and a lower mold 82. Next, raw material for the sealing member 60 is injected into the chamber 84 through the flow path 83 of the lower mold 82. Thus, the sealing member 60 seals the metal substrate 22, the multiple control terminals 30 of the lead frame, the multiple main terminals 40, and the suspension terminals 42, 43, and 44. At this time, the metal substrate 22 is sealed by maintaining it horizontally using the main terminals 41a, 41b, 41c, and 41d and the suspension terminals 42, 43, and 44. After molding, the upper mold 81 and the lower mold 82 are separated, and the semiconductor device 10 is removed. Finally, remove unwanted parts such as burrs from the sealing component 60, the tie rods of the lead frame, and the portions of the suspension terminals 42, 43, and 44 extending from the semiconductor device 10. This yields... Figures 1-3 The semiconductor device 10 shown (step S6).

[0066] The semiconductor device 10 described above includes the first semiconductor element 21a and the second semiconductor element 21b, a metal base substrate 22 having an insulating layer 23 and circuit patterns 24a, 24b, 24c, and 24d formed on the insulating layer 23, and the circuit patterns 24a, 24b, 24c, and 24d provided in the element region 22a of the main surface of the metal base substrate 22 are provided with the first semiconductor element 21a and the second semiconductor element 21b, respectively. In addition, the semiconductor device 10 includes main terminals 41b, 41a, 41c, and 41d, one end portions of the main terminals 41b, 41a, 41c, and 41d are joined to the circuit patterns 24a, 24b, 24c, and 24d in the element region 22a, respectively, and the other end portions of the main terminals 41b, 41a, 41c, and 41d extend from one side portion of the metal base substrate 22 to the outside of the metal base substrate 22. Further, the semiconductor device 10 includes a control terminal 30 disposed in a control region 30a which is adjacent to the other side portion of the metal base substrate 22 opposite to the one side portion to which the main terminals 41b, 41a, 41c, and 41d are joined, and a sealing member 60 which seals the main surface of the metal base substrate 22 and the control region 30a.

[0067] The semiconductor device 10 directly joins the main terminals 41b, 41a, 41c, and 41d to the circuit patterns 24a, 24b, 24c, and 24d in which the first semiconductor element 21a and the second semiconductor element 21b are disposed. Therefore, compared with a case in which they are joined by bonding wires, it is possible to reduce the resistance. In addition, the semiconductor device 10 uses the metal base substrate 22. Therefore, the semiconductor device 10 can efficiently dissipate heat from the first semiconductor element 21a and the second semiconductor element 21b to the heat sink 25, and can suppress temperature rise. In addition, the control region 30a in which the control wiring portion 34 included in the control terminal 30 is disposed is located at a higher position than the element region 22a of the metal base substrate 22. Therefore, it is possible to suppress the influence of noise generated by each region, and to stably drive the semiconductor device 10. Therefore, it is possible to improve the characteristics of the semiconductor device 10. Further, the semiconductor device 10 does not use a housing in which the control terminal 30 and the main terminals 41b, 41a, 41c, and 41d, and the like are integrally formed. Therefore, it is not necessary to perform a process of forming such a housing and a process of adhering the metal base substrate 22 to the housing. Therefore, it is possible to simplify the manufacturing process of the semiconductor device 10 and reduce the manufacturing cost.

Claims

1. A semiconductor device, characterized by comprising: having: a plurality of semiconductor elements; a substrate having an insulating layer and a plurality of circuit patterns formed on the insulating layer, and the plurality of semiconductor elements are respectively provided on the plurality of circuit patterns in an element region provided on a main surface; a plurality of main terminals including a joint portion at one end portion, the joint portion being directly joined to the plurality of circuit patterns in the element region, and the other end portion extending from a first side portion of the substrate to an outside of the substrate; a plurality of control terminals disposed in a control region and including a control wiring portion, the control region being adjacent to a second side portion of the substrate opposite to the first side portion; and a sealing member sealing the main surface of the substrate and the control region, a fixing pattern is further formed on the insulating layer of the substrate, the semiconductor device further has a suspension terminal having one end portion fixed to the fixing pattern and sealed by the sealing member, three fixing patterns are formed at a first corner between the first side portion and a third side portion of the substrate, a second corner between the second side portion and the third side portion, and a third corner between the second side portion and a fourth side portion, and the suspension terminal is fixed to the fixing patterns, respectively, the third side portion and the fourth side portion being between the first side portion and the second side portion, the suspension terminal extends from the third side portion and the fourth side portion of the substrate to the outside of the substrate.

2. The semiconductor device according to claim 1, wherein the plurality of main terminals extend from a first side surface of the sealing member corresponding to the first side portion, and the plurality of control terminals extend from a second side surface of the sealing member corresponding to the second side portion.

3. The semiconductor device according to claim 1, wherein the suspension terminal having the one end portion fixed to the fixing pattern extends from either of the third side portion and the fourth side portion between the first side portion and the second side portion closest to the fixing pattern to the outside of the substrate.

4. The semiconductor device according to claim 3, wherein the suspension terminal is sealed by the sealing member, and the other end portion of the suspension terminal is exposed from a third side surface or a fourth side surface of the sealing member corresponding to the third side portion or the fourth side portion, respectively.

5. The semiconductor device according to claim 1, wherein the control region is located at a higher position than the main surface of the substrate.

6. The semiconductor device according to claim 1, wherein an electronic component is disposed on the control wiring portion.

7. The semiconductor device according to claim 1, wherein the insulating layer is composed of any one of an epoxy resin, an epoxy resin mixed with an inorganic filler, a polyimide, and a polytetrafluoroethylene.

8. The semiconductor device according to claim 1, wherein all of the side portions are sealed by the sealing member together with the main surface of the substrate.

9. The semiconductor device according to claim 1, wherein three of four edges of the substrate are suspended by the suspension terminal.

10. The semiconductor device according to claim 1, wherein The suspension terminals of the fixing patterns of the second corner portion and the fixing patterns of the third corner portion are respectively extended from the third side portion and the fourth side portion of the substrate to the outside of the substrate.

11. A method of manufacturing a semiconductor device, characterized by Comprise: a preparation step of preparing a substrate having an insulating layer and a plurality of circuit patterns and fixing patterns formed on the insulating layer, a plurality of main terminals, a plurality of control terminals, and a suspension terminal; a disposition step of disposing the plurality of circuit patterns in an element region provided on a main surface of the substrate, disposing one end portion of the plurality of main terminals including a joint portion in a manner that the other end portion of the plurality of main terminals is extended from a first side portion of the substrate to the outside of the substrate, and disposing the plurality of control terminals including a control wiring portion in a control region adjacent to a second side portion of the substrate opposite to the first side portion; a joining step of joining the one end portion of the plurality of main terminals of the plurality of circuit patterns provided on the substrate in a manner that a back surface of the joint portion is directly joined to the plurality of circuit patterns; and a sealing step of sealing the main surface of the substrate and the control region and the suspension terminal with a sealing member, in the disposition step, the suspension terminal is disposed on one end portion of the fixing pattern, in the joining step, the one end portion of the suspension terminal is joined to the fixing pattern, three fixing patterns are formed in a first corner portion between the first side portion and a third side portion of the substrate, a second corner portion between the second side portion and the third side portion, and a third corner portion between the second side portion and a fourth side portion, the third side portion and the fourth side portion being between the first side portion and the second side portion, the suspension terminal is extended from the third side portion and the fourth side portion of the substrate to the outside of the substrate.

12. The method of manufacturing a semiconductor device according to claim 11, wherein in the joining step, the substrate is joined by ultrasonic joining.

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