Structures and methods for improved fin critical dimension control

Abstract

The present disclosure relates to structures and methods for improved fin critical dimension control. A semiconductor structure, comprising: an active semiconductor fin having a first height; a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height; an isolation structure between the active semiconductor fin and the dummy semiconductor fin; and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to structures and methods for improved fin critical dimension control. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth. During the growth, the functionality of semiconductor devices has increased while the feature size or geometry has decreased. FinFETs have been developed to meet the need for continued scaling of integrated circuits and the ever-increasing demand for improved integrated circuit speed. In a FinFET, a channel is formed as a fin-shaped structure extending from a surface of a substrate and a gate that controls the current flowing between the source and drain around the sides of the channel. FinFET architecture provides improved device electrostatic control compared to planar FET counterparts. SUMMARY

[0003] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: an active semiconductor fin having a first height; a dummy semiconductor fin adjacent to the active semiconductor fin, the dummy semiconductor fin having a second height less than the first height; an isolation structure between the active semiconductor fin and the dummy semiconductor fin; and a dielectric cap over the dummy semiconductor fin, wherein the dielectric cap is separated from the active semiconductor fin.

[0004] According to another embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a plurality of active semiconductor fins, wherein each active semiconductor fin of the plurality of active semiconductor fins has a first height; a plurality of dummy semiconductor fins, wherein each dummy semiconductor fin of the plurality of dummy semiconductor fins has a second height less than the first height; a plurality of isolation structures on the substrate, wherein each isolation structure of the plurality of isolation structures separates a respective active semiconductor fin of the plurality of active semiconductor fins or a respective dummy semiconductor fin of the plurality of dummy semiconductor fins from each other; and a dielectric cap over the plurality of dummy semiconductor fins, wherein the dielectric cap is spaced apart from the plurality of active semiconductor fins.

[0005] According to yet another embodiment of the disclosure, a method of forming a semiconductor structure is provided, comprising: etching a semiconductor substrate to form a plurality of semiconductor fins; forming a shallow trench isolation (STI) structure in a trench between the plurality of semiconductor fins; recessing at least one semiconductor fin of the plurality of semiconductor fins to form at least one dummy semiconductor fin; forming a dielectric cap layer over the at least one dummy semiconductor fin and un-recessed semiconductor fins of the plurality of semiconductor fins; and patterning the dielectric cap layer to remove the dielectric cap layer from the un-recessed semiconductor fins of the plurality of semiconductor fins other than the at least one dummy semiconductor fin. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure can best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for the sake of clarity. Like numbers refer to like features throughout the specification and drawings.

[0007] Figure 1 is a perspective view of a FinFET according to some embodiments.

[0008] Figure 2 is a flowchart of a method for fabricating a semiconductor structure according to some embodiments.

[0009] Figure 3A is a top view of a semiconductor structure after forming a stack of a mask layer, a mandrel material layer, and a resist layer on a semiconductor substrate.

[0010] Figure 3B is a cross-sectional view of the semiconductor structure of Figure 3A along line B-B’.

[0011] Figure 4A is a top view of the semiconductor structure of Figure 3A after forming a mandrel structure according to some embodiments.

[0012] Figure 4B is a cross-sectional view of the semiconductor structure of Figure 4A along line B-B’.

[0013] Figure 5A is a top view of the semiconductor structure of Figure 4A after forming spacers on sidewalls of the mandrel structure according to some embodiments.

[0014] Figure 5B is a cross-sectional view of the semiconductor structure of Figure 5A along line B-B’.

[0015] Figure 6A is a top view of the semiconductor structure after forming a patterned mask layer according to some embodiments. Figure 5A is a cross-sectional view of the semiconductor structure of

[0016] Figure 6B is a cross-sectional view of the semiconductor structure of Figure 6A

[0017] Figure 7A is a top view of the semiconductor structure after forming a semiconductor fin according to some embodiments. Figure 6A is a cross-sectional view of the semiconductor structure of

[0018] Figure 7B is a cross-sectional view of the semiconductor structure of Figure 7A

[0019] Figure 8A is a top view of the semiconductor structure after forming an isolation layer according to some embodiments. Figure 7A is a cross-sectional view of the semiconductor structure of

[0020] Figure 8B is a cross-sectional view of the semiconductor structure of Figure 8A

[0021] is a top view of the semiconductor structure after forming a shallow trench isolation structure according to some embodiments. Figure 9A is a cross-sectional view of the semiconductor structure of Figure 8A

[0022] Figure 9B is a cross-sectional view of the semiconductor structure of Figure 9A

[0023] is a top view of the semiconductor structure after forming a first dummy semiconductor fin according to some embodiments. Figure 10A is a cross-sectional view of the semiconductor structure of Figure 9A

[0024] Figure 10B-10D is a cross-sectional view of the semiconductor structure of Figure 10A

[0025] is a top view of the semiconductor structure after forming a second dummy semiconductor fin according to some embodiments. Figure 11A is a cross-sectional view of the semiconductor structure of Figure 10A

[0026] is a cross-sectional view of the semiconductor structure of Figure 11B 11C Figure 11A is a cross-sectional view of the semiconductor structure of

[0027] Figure 12A is a top view of the semiconductor structure after forming a dielectric cap layer over the active semiconductor fin and the dummy semiconductor fin according to some embodiments. Figure 11A ​​​​​​top view of the semiconductor structure of FIG. 1.

[0028] Figure 12B cross-sectional view of the semiconductor structure of FIG. 1 along line B-B'. Figure 12A top view of the semiconductor structure of FIG. 1.

[0029] Figure 13A top view of the semiconductor structure of FIG. 1. Figure 12A cross-sectional view of the semiconductor structure of FIG. 1 along line B-B'.

[0030] Figure 13B cross-sectional view of the semiconductor structure of FIG. 1 along line B-B'. Figure 13A top view of the semiconductor structure of FIG. 1.

[0031] Figure 14A top view of the semiconductor structure of FIG. 1. Figure 13A cross-sectional view of the semiconductor structure of FIG. 1 along line B-B'.

[0032] Figure 14B cross-sectional view of the semiconductor structure of FIG. 1 along line B-B'. Figure 14A top view of the semiconductor structure of FIG. 1.DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described herein to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, forming a first feature over or on a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper,” etc.) can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] Figure 1is a perspective view of a FinFET 100 according to some embodiments. The FinFET 100 generally includes a plurality of semiconductor fins 110 above a semiconductor substrate 102, and a gate structure 120 above the semiconductor substrate 102 and across the semiconductor fins 110. Shallow trench isolation (STI) structures 130 are located between the semiconductor fins 110 to electrically isolate the semiconductor fins 110.

[0036] In integrated circuits, FinFETs with different fin counts are formed in different regions of a semiconductor substrate. The fabrication technique for fabricating FinFETs with different fin counts is to initially form trenches in the semiconductor substrate to define an array of semiconductor fins that are uniformly spaced across the substrate, and then remove some dummy fins to define active semiconductor fins in device regions. STI structures are then formed to separate and isolate the active semiconductor fins and dummy semiconductor fins from each other. Typically, fabricating the STI structures involves depositing a dielectric material to fill the spaces between the active semiconductor fins and dummy semiconductor fins.

[0037] As FinFETs are scaled to meet increasing performance and size requirements, the width of the fins becomes very small, and the fin pitch has also been significantly reduced. The reduced fin pitch makes it challenging to fill the dielectric between the fins. Therefore, in some cases, a flowable dielectric material is introduced to provide a scalable, defect-free, high-yield dielectric fill between the semiconductor fins. In forming the STI structures, a flowable chemical vapor deposition (FCVD) process is used to deposit the flowable dielectric material to fill the gaps between the semiconductor fins. After the flowable dielectric film is deposited, the flowable dielectric film is cured and then annealed to form a dielectric layer, e.g., silicon dioxide. The flowable dielectric film is typically annealed at a high temperature, e.g., above 1000 °C, to densify the film to obtain the required mechanical properties.

[0038] The high temperature anneal consumes silicon atoms in the active semiconductor fins due to the reaction of silicon atoms with water vapor in the process chamber, which in turn causes a shrinkage of the fin critical dimension (CD). The active semiconductor fins in different device regions with different fin counts experience different flowable dielectric loading effects, i.e., the fin CD loss is different in different device regions. A larger volume of flowable dielectric between adjacent fins has a more significant impact on the fin CD compared to a smaller volume of flowable dielectric. As a result, the final CD of the active semiconductor fins in different device regions varies based on the fin density. The variation in fin CD in different device regions affects the consistency of device performance.

[0039] Improved fin CD control provides more consistent device performance in integrated circuits. In some embodiments, STI structures are formed prior to removal of non-functional dummy fins, such that all semiconductor fins on the semiconductor substrate experience the same dielectric loading environment during high temperature annealing of flowable dielectric material used to form the STI structures. By annealing the flowable dielectric material prior to the fin cut phase, differences in fin CD shrinkage due to different flowable dielectric loading effects in different device regions are avoided. More uniform fin CDs contribute to the production of FinFETs with more consistent device performance.

[0040] Figure 2 is a flowchart of a method 200 for fabricating a semiconductor structure 300 according to some embodiments of the present disclosure. Figures 3A-14B top-down and cross-sectional views of the semiconductor structure 300 at various fabrication stages constructed according to the method 200 of Figure 2 The top-down and cross-sectional views of the semiconductor structure 300 at various fabrication stages constructed according to the method 200 of Figures 3A-14B The semiconductor structure 300 is described. In some embodiments, additional operations are performed prior to, during, or after the method 200, or replace or eliminate some of the operations described. In some embodiments, additional features are added to the semiconductor structure 300. In some embodiments, some of the features described below are replaced or eliminated. Those of ordinary skill in the art will appreciate that although some embodiments are discussed with operations performed in a particular order, these operations can be performed in another logical order.

[0041] Referring to Figure 2 The method 200 includes an operation 202 in which a layer stack is formed over a semiconductor substrate 302. Figure 3A and Figure 3B is a view of the semiconductor structure 300 after formation of a stack of a mask layer 310L, a mandrel material layer 316L, and a resist layer 320L over the semiconductor substrate 302.

[0042] Referring to Figure 3A and Figure 3B In some embodiments, the semiconductor substrate 302 is a bulk semiconductor substrate including one or more semiconductor materials. In some embodiments, the semiconductor substrate 302 includes silicon, silicon germanium, carbon-doped silicon (Si:C), silicon germanium carbide, or other suitable semiconductor materials. In some embodiments, the semiconductor substrate 302 consists entirely of silicon.

[0043] In some embodiments, the semiconductor substrate 302 includes one or more epitaxial layers formed on a top surface of a bulk semiconductor substrate. In some embodiments, the one or more epitaxial layers introduce strain in the semiconductor substrate 302 to improve performance. For example, the epitaxial layer includes a semiconductor material that is different from the semiconductor material of the bulk semiconductor substrate, such as a silicon germanium layer overlying bulk silicon or a silicon layer overlying bulk silicon germanium. In some embodiments, the epitaxial layer(s) incorporated in the semiconductor substrate 302 are formed by selective epitaxial growth, such as metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), or a combination thereof.

[0044] In some embodiments, the semiconductor substrate 302 is an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the SOI substrate includes a semiconductor layer, such as a silicon layer formed on an insulator layer. In some embodiments, the insulator layer is a buried oxide (BOX) layer including silicon oxide or silicon germanium oxide. The insulator layer is disposed on a handle substrate, such as a silicon substrate. In some embodiments, the SOI substrate is formed using separation by implantation of oxygen (SIMOX) or wafer bonding.

[0045] In some embodiments, the semiconductor substrate 302 includes various doped regions formed by processes such as ion implantation and / or diffusion. The doped regions are doped with p-type and / or n-type dopants. The term “p-type” refers to an impurity that, when added to an intrinsic semiconductor, creates a deficiency of valence electrons. Examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, boron difluoride, gallium, and indium. The term “n-type” refers to an impurity that, when added to an intrinsic semiconductor, provides free electrons. Examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, and phosphorus.

[0046] A mask layer 310L is formed over the semiconductor substrate 302. The mask layer 310L includes one or more dielectric layers to protect the underlying semiconductor substrate 302 during subsequent patterning processes. The mask layer 310L is a single layer or multiple layers. In some embodiments, the mask layer 310L has a multi-layer structure including a liner oxide layer 312L and a hard mask layer 314L.

[0047] The liner oxide layer 312L is formed in direct contact with the semiconductor substrate 302. The liner oxide layer 312L includes a material that enhances adhesion between the hard mask layer 314L and the semiconductor substrate 302. In some embodiments, the liner oxide layer 312L includes a dielectric oxide, such as silicon oxide. In some embodiments, the liner oxide layer 312L is formed using a deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other suitable deposition process. Alternatively, the liner oxide layer 312L is formed by thermal oxidation of a surface portion of the semiconductor substrate 302. In some embodiments, the liner oxide layer 312L is formed to have a thickness of about 5 nanometers (nm) to about 15 nm. In some cases, if the thickness of the liner oxide layer 312L is too small, the adhesion between the hard mask layer 314L and the semiconductor substrate 302 is insufficient. On the other hand, in some cases, if the thickness of the liner oxide layer 312L is too large, the production cost increases due to unnecessary material consumption and processing time increase for patterning the liner oxide layer 312L.

[0048] The hard mask layer 314L is formed over the liner oxide layer 312L. The hard mask layer 314L serves as a patterning mask for etching the underlying semiconductor substrate 302. In some embodiments, the hard mask layer 314L includes a dielectric nitride, such as silicon nitride. In some embodiments, the hard mask layer 314L is formed with CVD, PECVD, PVD, or other suitable deposition process. The hard mask layer 314L has a thickness sufficient to provide protection during an etching process based on the material and etchant. In some embodiments, the hard mask layer 314L is formed to have a thickness of about 20 nm to about 60 nm. In some cases, if the thickness of the hard mask layer 314L is too small, sufficient protection is not provided during the etching process. On the other hand, in some cases, if the thickness of the hard mask layer 314L is too large, the production cost increases due to unnecessary material consumption and processing time increase for patterning the liner oxide layer 314L.

[0049] The mandrel material layer 316L is formed over the hard mask layer 314L. The mandrel material layer 316L is used to fabricate the mandrel structure 316 Figure 4A and Figure 4B), which can be used to form sub-lithographic structures using a sidewall image transfer (SIT) process. The mandrel material layer 316L includes a material having a high etch selectivity relative to the material of the hardmask layer 314L. In some embodiments, the mandrel material layer 316L includes amorphous silicon, spin-on carbon (SOC), diamond carbon, amorphous carbon, or a combination thereof. In some embodiments, the mandrel material layer 316L is formed using CVD, PVD, spin-on, or other suitable deposition process. In some embodiments, the mandrel material layer 316L is formed to have a thickness of about 50 nm to about 300 nm. In some cases, if the thickness of the mandrel material layer 316L is too small, there is an increased risk of the mandrel material layer 316L being removed during removal of the patterned resist layer. On the other hand, in some cases, if the thickness of the mandrel material layer 316L is too large, there is an increased production cost due to unnecessary material consumption and processing time to pattern the photoresist layer.

[0050] A resist layer 320L is formed over the mandrel material layer 316L. In some embodiments, the resist layer 320L is a three-layer resist including a planarization layer 322L, an anti-reflective coating (ARC) layer 324L, and a patterned photoresist layer 326.

[0051] The planarization layer 322L is formed in direct contact with the mandrel material layer 316L. In some embodiments, the planarization layer 22L is an organic planarization layer (OPL) that is capable of providing a planarized surface on which the ARC layer 324L is formed. In some embodiments, the planarization layer 322L includes spin-on carbon, diamond-like carbon, polyarylene ether, or polyimide. In some embodiments, the planarization layer 322L is formed by CVD, spin-on, or other suitable deposition process. The planarization layer 322L is formed to have a thickness sufficient to provide a planarized surface. In some embodiments, the thickness of the planarization layer 322L is about 50 nm to about 300 nm. In some cases, if the thickness of the planarization layer 322L is too small, the planarization layer 322L is not capable of providing a planarized surface. On the other hand, in some cases, if the thickness of the planarization layer 22L is too large, there is an increased production cost due to unnecessary material consumption and processing time to pattern the planarization layer 322L.

[0052] An ARC layer 324L is formed over the planarization layer 322L. The ARC layer 324L reduces light reflection from the underlying layers during lithography to increase the precision of the pattern formed in the patterned photoresist layer 326. In some embodiments, the ARC layer 324L includes a nitrogen-free ARC (NFARC) material, such as silicon oxide or carbon-doped silicon oxide. The NFARC material reduces resist poisoning in sensitive photoresists. In some embodiments, the ARC layer 324L is formed using CVD, PVD, atomic layer deposition (ALD), spin-on, or other suitable deposition process. The ARC layer 324L is formed to have a thickness that provides sufficient anti-reflective properties based on the material and wavelength. In some embodiments, the thickness of the ARC layer 324L is about 20 nm to about 100 nm. In some cases, if the thickness of the ARC layer 324L is too small, the ARC layer 324L does not sufficiently reduce light reflection, and thus, the precision of the pattern formed in the patterned photoresist layer 326 is compromised. On the other hand, in some cases, if the thickness of the ARC layer 324L is too large, the production cost increases due to unnecessary material consumption and increased processing time to etch the ARC layer 324L.

[0053] A patterned photoresist layer 326 is formed over the ARC layer 324L. The patterned photoresist layer 326 is used to define the pattern transferred through the ARC layer 324L and the planarization layer 322L to the mandrel material layer 316L. In some embodiments, the patterned photoresist layer 326 includes a plurality of parallel lines that define the mandrel structure 316 subsequently formed. In some embodiments, the patterned photoresist layer 326 is formed by applying a photoresist layer (not shown) over the top surface of the ARC layer 324L, exposing the photoresist layer using a photomask (not shown), and removing the exposed or unexposed portions of the photoresist layer depending on whether a positive resist or a negative resist is used in the photoresist layer with a resist developer.

[0054] Referring to FIG. 4A and Figure 2 Method 200 proceeds to operation 204, where the mandrel material layer 316L is patterned to form the mandrel structure 316. Figure 4A and Figure 4B are views of the semiconductor structure 300 after the mandrel structure 316 is formed in accordance with some embodiments. Figure 3A and Figure 3B are views of the semiconductor structure 300 after the mandrel structure 316 is formed in accordance with some embodiments.

[0055] Referring to FIG. 4A and Figure 4BThe mandrel structure 316 has longitudinal axes that are substantially parallel to each other. The pattern in the patterned photoresist layer 326 is transferred to the ARC layer 324L and the planarization layer 322L, thereby forming the patterned ARC layer 324 and the patterned planarization layer 322. For example, the pattern is transferred by at least one etching process. The etching process used is anisotropic etching, such as dry etching, but any suitable etching process can be used. In some embodiments, the dry etching is reactive ion etching (RIE) or plasma etching. In some embodiments, a single etching process is performed to etch the ARC layer 324L and the planarization layer 322L. In some embodiments, two sequential etching processes are used to etch the ARC layer 324L and the planarization layer 322L, respectively. After the formation of the patterned ARC layer 324 and the patterned planarization layer 322, the patterned photoresist layer 326 is removed, for example, by plasma ashing or wet stripping.

[0056] Next, the mandrel material layer 316L is etched using the patterned ARC layer 324 and the patterned planarization layer 322 as an etching mask to form the mandrel structure 316. In some embodiments, the mandrel material layer 316L is patterned by dry etching, such as RIE or plasma etching.

[0057] After forming the mandrel structure 316, the patterned ARC layer 324 and the patterned planarization layer 322 are removed, for example, by using dry etching or wet etching with a chemical etchant.

[0058] refer to Figure 2 Method 200 proceeds to operation 206, wherein spacer 330 is formed above mask layer 310L. Figure 5A and Figure 5B According to some embodiments, after the spacer 330 is formed Figure 4A and Figure 4B A view of the semiconductor structure at 300°.

[0059] refer to Figure 5A and Figure 5BSpacers 330 are formed on the opposing sidewalls of mandrel structure 316. In some embodiments, spacers 330 are formed by depositing a spacer layer (not shown) over mandrel structure 316 and the topmost surface of mask layer 310L (e.g., the top surface of hardmask layer 314L). The spacer layer includes a material having a high etch selectivity with respect to hardmask layer 314L and mandrel structure 316, such that a subsequent etch process performed on the spacer layer does not etch hardmask layer 314L and mandrel structure 316. In some embodiments, the spacer layer includes a metal-containing material, such as titanium nitride or titanium oxide. In some embodiments, the spacer layer includes a dielectric oxide, such as silicon oxide. In some embodiments, the spacer layer is deposited conformally over mandrel structure 316 and hardmask layer 314L, such that the thickness of the spacer layer on the top surface of hardmask layer 314L and the thickness of the spacer layer on the sidewalls of mandrel structure 316 are substantially the same. The thickness of the spacer layer determines the width of the semiconductor fins that are ultimately formed from semiconductor substrate 302. In some embodiments, the spacer layer is deposited using CVD, PVD, ALD, or other suitable deposition process. The spacer layer is subsequently etched to remove the horizontal portions of the spacer layer, while the vertical portions of the spacer layer that remain on the sidewalls of mandrel structure 316 constitute spacers 330. In some embodiments, an anisotropic etch, such as RIE or plasma etching, is performed to remove the spacer layer from the horizontal surfaces of semiconductor structure 300.

[0060] After spacers 330 are formed, a selective etch process is performed to remove mandrel structure 316 from between spacers 330. In some embodiments, an anisotropic etch, such as RIE or plasma etching, is performed to selectively remove mandrel structure 316 from spacers 330 and hardmask layer 314L. In some embodiments, an isotropic etch (e.g., a wet etch using an etchant solution) is applied to selectively remove mandrel structure 316 from spacers 330 and hardmask layer 314L.

[0061] Referring to Figure 2 Method 200 proceeds to operation 208, in which mask layer 310L is patterned to provide patterned mask layer 210, which defines semiconductor fins 340 Figure 7A and Figure 7B that are subsequently formed. Figure 6A and 6B are views of semiconductor structure 300 after patterned mask layer 310 is formed in accordance with some embodiments. Figure 5A and Figure 5B are views of semiconductor structure 300 after patterned mask layer 310 is formed in accordance with some embodiments.

[0062] Referring to Figure 6A and Figure 6BThe spacer 330 is used as a mask to pattern the mask layer 310L to form a patterned mask layer 310. The patterned mask layer 310 covers portions of the semiconductor substrate 302 during formation of the semiconductor fins 340. For example, to form the patterned mask layer 310, the spacer 330 is used as an etch mask to form the etch hardmask layer 314L and the pad oxide layer 312L by at least one etching process in which openings 315 are formed to expose portions of the semiconductor substrate 302. In some embodiments, a single anisotropic etching process is performed to remove portions of the hardmask layer 314L and the pad oxide layer 312L that are not covered by the spacer 330. In some embodiments, sequential anisotropic etching processes are performed to remove portions of the hardmask layer 314L and the pad oxide layer 312L that are not covered by the spacer 330, respectively. In some embodiments, the anisotropic etching is a dry etching, e.g., RIE or plasma etching. In some embodiments, the dry etching is achieved by a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an oxygen-containing gas, an iodine-containing gas, other suitable gases and / or plasma, or a combination thereof. The remaining portions of the hardmask layer 314L provide the patterned hardmask layer 314, and the remaining portions of the pad oxide layer 312L provide the patterned pad oxide layer 312. Together, the patterned hardmask layer 314 and the patterned pad oxide layer 312 constitute the patterned mask layer 310.

[0063] After the patterned mask layer 310 is formed, the spacer 330 is removed from the top surface of the patterned hardmask layer 314 by an etching process that is anisotropic etching or isotropic etching. In some embodiments, a dry etching using a plasma of CF4, CH2F4, or a combination of CF4and CH2F4is performed to selectively remove the spacer 330 from the patterned hardmask layer 314, the patterned pad oxide layer 312, and the semiconductor substrate 302. In some embodiments, a wet etching using a solution of tetramethylammonium hydroxide (TMAH) or NH3is performed to selectively remove the spacer 330 from the patterned hardmask layer 314, the patterned pad oxide layer 312, and the semiconductor substrate 302.

[0064] Although the patterned mask layer 310 is formed by the SIT process in Figures 3A-6B , in some embodiments, the patterned mask layer 310 is directly patterned from the mask layer 310L using the patterned photoresist layer 326 as an etch mask to form the patterned mask layer 310.

[0065] Referring to Figure 2The method 200 proceeds to operation 210, in which the semiconductor substrate 302 is etched to form a plurality of semiconductor fins 340. Figure 7A and 7B are views of the semiconductor structure 300 after forming the semiconductor fins 340 on the semiconductor substrate 302. Figure 6A and Figure 6B are views of the semiconductor structure 300 after forming the isolation layer 350.

[0066] Referring to Figure 7A and Figure 7B , the semiconductor substrate 302 is etched using the patterned mask layer 310 as an etch mask to form a plurality of semiconductor fins 340 protruding from a base of the semiconductor substrate 302. In some embodiments, the semiconductor substrate 302 is etched using an anisotropic etch. In some embodiments, a dry etch such as RCE or plasma etch is performed. The etching process forms trenches 342 between the semiconductor fins 340, where isolation structures such as shallow trench isolation (STI) structures are subsequently formed.

[0067] In some embodiments, the semiconductor fins 340 are formed to have uniform dimensions and spacing. One or more of the semiconductor fins 340 are dummy fins and will be cut in a subsequent operation according to design specifications. In some embodiments, each semiconductor fin 340 has a height H ranging from about 20 nm to about 200 nm, and a width W ranging from about 5 nm to about 30 nm. Each semiconductor fin 340 is separated from a nearest neighboring semiconductor fin 340 by a spacing S. In some embodiments, the spacing between neighboring semiconductor fins 340 is about 20 nm to about 60 nm. Other heights, widths, and spacings less than or greater than the foregoing ranges are also contemplated by the present disclosure for each semiconductor fin 340. Although the semiconductor fins 340 in Figure 7B have substantially vertical sidewalls, in some embodiments, the semiconductor fins 340 have a tapered shape that is wider at the bottom than at the top.

[0068] Referring to Figure 2 , the method 200 proceeds to operation 212, in which an isolation layer 350 is formed to fill the trenches 342 between the semiconductor fins 340. Figure 8A and Figure 8B are views of the semiconductor structure 300 after forming the isolation layer 350. Figure 7A and Figure 7B are views of the semiconductor structure 300 after forming the isolation layer 350.

[0069] Referring to Figure 8A and Figure 8BA spacer layer 350 is deposited over the semiconductor substrate 302, filling the trenches 342 between adjacent semiconductor fins 340 and the openings 315 in the patterned mask layer 310. In some embodiments, the spacer layer 350 includes silicon dioxide, silicon oxynitride, silicon carbon oxynitride, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, or other suitable dielectric material. In some embodiments, the spacer layer 350 is formed by a flowable chemical vapor deposition (FCVD) process or a spin-on dielectric (SOD) technique. During the FCVD or SOD process, one or more flowable dielectric materials are deposited within the trenches 342 to form a film of flowable dielectric material. As the name suggests, the flowable dielectric material can flow during deposition to fill gaps or spaces having a high aspect ratio. Exemplary flowable dielectric materials include, but are not limited to, silicates, siloxanes, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), perhydrosilazane (TCPS), perhydropolysilazane (PSZ), tetraethyl orthosilicate (TEOS), and silyl amines, e.g., trisilylamine (TSA). The flowable dielectric material is typically over-deposited to completely cover the patterned mask layer 310.

[0070] After the film of flowable dielectric material is formed, the film of flowable dielectric material is cured to harden the film of flowable dielectric material. Curing increases the viscosity of the film of flowable dielectric material. In some embodiments, the film of flowable dielectric material is cured in an oxygen-containing gas, such as an ozone-containing gas. In some embodiments, the film of flowable dielectric material is cured at a temperature in a range from about 100 °C to 600 °C.

[0071] Subsequently, an anneal is performed on the semiconductor structure 300 to densify the film of flowable dielectric material, thereby forming the spacer layer 350. In some embodiments, the anneal is performed in an oxygen-containing gas. In some embodiments, the anneal is performed at a temperature in a range from about 1000 °C to about 1200 °C. In some embodiments, the anneal is a flow anneal process.

[0072] Because the semiconductor fins 340 are uniformly formed on the semiconductor substrate 302, the width (CD) of the semiconductor fins 340 varies little or not at all, as the semiconductor fins 340 experience the same local dielectric environment during the anneal of the flowable dielectric material. Thus, high-temperature annealing of the flowable dielectric material prior to the fin cut process helps to reduce fin CD variation in different device regions due to fin number loading effects, which in turn helps to reduce device performance variation.

[0073] After the anneal, a planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to remove any excess dielectric material, such that the top surface of the spacer layer 350 is coplanar with the top surface of the patterned mask layer 310.

[0074] Referring to Figure 2 Operation 214, the method 200 proceeds to, where the STI structure 352 is formed. Figure 9A and Figure 9B is a view of the semiconductor structure 300 after the STI structure 352 is formed. Figure 8A and Figure 8B is a view of the semiconductor structure 300 after the STI structure 352 is formed.

[0075] Referring to Figure 9A and Figure 9B , the isolation layer 350 is recessed to form the STI structure 352 around the bottom portion of the semiconductor fin 340. After the recessing, the top surface of the STI structure 352 is below the top surface of the semiconductor fin 340. Thus, the upper portion of the semiconductor fin 340 is exposed after the STI structure 352 is formed. In some embodiments, an anisotropic etch is used to recess the isolation layer 350. In some embodiments, the anisotropic etch is a plasma dry etch using a fluorine-based chemistry (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6). The anisotropic etch selectively removes the dielectric material of the isolation layer 350, but does not substantially etch the semiconductor material of the semiconductor fin 340.

[0076] After the STI structure 352 is formed, the patterned hardmask layer 314 and the patterned liner oxide layer 312 are removed from the top surface of the semiconductor fin 340. Thus, the top surface of the semiconductor fin 340 is exposed. In some embodiments, the patterned hardmask layer 314 is removed by a wet etch using hot H3PO4, and the patterned liner oxide layer 312 is removed using diluted HF acid. In some embodiments, the patterned hardmask layer 314 and the patterned liner oxide layer 312 are removed by CMP.

[0077] Referring to Figure 2 Operation 216, the method 200 proceeds to, where the first dummy semiconductor fin 340a is formed. Figures 10A-10D is a view of the semiconductor structure 300 after the first set of semiconductor fins 340 is recessed to form the first dummy semiconductor fin 340a, according to some embodiments. Figure 9A and Figure 9B is a view of the semiconductor structure 300 after the first set of semiconductor fins 340 is recessed to form the first dummy semiconductor fin 340a, according to some embodiments.

[0078] Referring to Figures 10A-10D, a first fin cut process is performed to remove exposed portions of a first set of semiconductor fins 340 that protrude above the STI structures 352, thereby forming first dummy semiconductor fins 340a. Between each pair of adjacent semiconductor fins 340 extending along the X direction, the first set of semiconductor fins 340 includes some semiconductor fins 340 that extend along a first direction (e.g., the X direction) and entire semiconductor fins 340 that extend along a second direction (e.g., the Y direction) that is different from the first direction. In some embodiments, the first dummy semiconductor fins 340a are formed by applying a first mask layer (not shown) over the STI structures 352 and the semiconductor fins 340 and lithographically patterning the first mask layer to form a patterned first mask layer (not shown). The patterned first mask layer includes openings that expose the first set of semiconductor fins 340, which are subsequently recessed in the first fin cut process. In some embodiments, the first mask layer is a photoresist layer. In some embodiments, the first mask layer is a photoresist layer in combination with a hard mask layer(s). Subsequently, the semiconductor fins 340 exposed by the patterned first mask layer are recessed by an etch, such as a wet etch, a dry etch, or a combination thereof. The etch selectively removes the first set of semiconductor fins 340 but does not substantially affect the STI structures 352. In some embodiments, the wet etch includes an etchant solution of TMAH or HF / HNO3 / CH3COOH. In some embodiments, the dry etch includes a bias plasma etch using chlorine-based chemicals (e.g., Cl2, CHCl3, CCl4, and / or BCl3). In some embodiments, the recessing is an isotropic etch using a gas of Cl2 and NF3. After etching the first set of semiconductor fins 340, the patterned first mask layer is removed by, for example, an oxygen-based plasma etch or an ashing.

[0079] In some embodiments, the first dummy semiconductor fins 340a are embedded in the STI structures 352 and have a top surface that is substantially coplanar with a top surface of the STI structures 352. In some embodiments, the top surface of the first dummy semiconductor fins 340a is slightly higher or lower than the top surface of the STI structures 352. In some embodiments, the top surface of the first dummy semiconductor fins 340a is substantially planar, as shown in FIG. 3B. Figure 10B In some embodiments, the top surface of the first dummy semiconductor fins 340a is curved, for example, concave, as shown in FIG. 3C, or convex, as shown in FIG. 3D. Figure 10C In some embodiments, the top surface of the first dummy semiconductor fins 340a is curved, for example, concave, as shown in FIG. 3C, or convex, as shown in FIG. 3D. Figure 10Dembodiments, the semiconductor fins 340 are recessed such that the height Hla, Hlb of the first dummy semiconductor fin 340a is independently about 17% to about 20% of the height H of the semiconductor fins 340. In some embodiments, the height Hla, Hlb of the first dummy semiconductor fin 340a is about 15 nm to about 40 nm. In some embodiments, the height Hla and Hlb of the first dummy semiconductor fin 340a are substantially the same.

[0080] Referring to Figure 2 , the method 200 proceeds to operation 218, where a second dummy semiconductor fin 340b is formed. Figures 11A-11C B is a view of the semiconductor structure 300 after the second set of semiconductor fins 340 is recessed to form the second dummy semiconductor fin 340b, in accordance with some embodiments. Figures 10A-10D

[0081] Referring to Figures 11A-11C , a second fin cut process is performed to remove exposed portions of some semiconductor fins 340 that protrude above the STI structure 352, thereby forming the second dummy semiconductor fin 340b. In some embodiments, the second dummy semiconductor fin 340b is formed by applying a second mask layer (not shown) over the STI structure 352, remaining semiconductor fins 340, and first dummy semiconductor fin 340a, and photo patterning the second mask layer to form a patterned second mask layer (not shown). The patterned second mask layer includes openings that expose a second set of semiconductor fins 340 that are subsequently recessed in the second fin cut process. In some embodiments, the second mask layer is a photoresist layer. In some embodiments, the second mask layer is a photoresist layer in combination with the hard mask layer(s). Subsequently, the second set of semiconductor fins 340 exposed by the patterned second mask layer are recessed by an etch, such as a wet etch, a dry etch, or a combination thereof. The etch selectively removes the second set of semiconductor fins 340, but does not substantially affect the STI structure 352. In some embodiments, the wet etch includes an etchant solution of TMAH or HF / HNO3 / CH3COOH. In some embodiments, the dry etch includes a bias plasma etch using chlorine-based chemicals (e.g., Cl2, CHCl3, CCl4, and / or BCl3). In some embodiments, the recessing is an isotropic etch using a gas of Cl2 and NF3. After etching the second set of semiconductor fins 340, the patterned second mask layer is removed by, for example, an oxygen-based plasma etch or ashing.

[0082] Depending on the etch chemistry and etch time, in some embodiments, the top surface of the second dummy semiconductor fin 340b forms a concave profile, as shown in FIG. 3B, or a convex profile, as shown in FIG. 3C. Figure 11B ​The top surface of the second dummy semiconductor fin 340b is substantially planar in some embodiments, as shown in FIG. 3B. In some embodiments and as shown in FIG. 3B, the second set of semiconductor fins 340 is recessed such that the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is about 6% to about 16% of the height H of the semiconductor fins 340. Further, due to the longer etch time used to form the second dummy semiconductor fin 340b, the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is less than the height H1a, H2b of the first dummy semiconductor fin 340a. In some embodiments, the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is about 3 nm to about 30 nm. Figure 11C Figure 11B In some embodiments and as shown in FIG. 3B, the second set of semiconductor fins 340 is recessed such that the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is about 6% to about 16% of the height H of the semiconductor fins 340. Further, due to the longer etch time used to form the second dummy semiconductor fin 340b, the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is less than the height H1a, H2b of the first dummy semiconductor fin 340a. In some embodiments, the height H2a, H2b, H2c, and H2d of the second dummy semiconductor fin 340b is about 3 nm to about 30 nm.

[0083] In some embodiments, the etch process used to recess the second set of semiconductor fins 340 also etches the STI structure 352 surrounding the second set of semiconductor fins 340. As a result, after the formation of the second dummy semiconductor fin 340b, the top surface of the STI structure 352 surrounding the second dummy semiconductor fin 340b is below the top surface of the STI structure 352 surrounding the uncut set of semiconductor fins 340. In some embodiments, the top surface of the STI structure 352 surrounding the second dummy semiconductor fin 340b also has a recessed profile.

[0084] While two fin cut processes are described, the fin cut process can be performed one or more than two times depending on the arrangement of the semiconductor fins in the semiconductor structure 300 and existing photolithography techniques. Fewer fin cut processes can reduce process time. However, in some cases, additional fin cut processes are used to help ensure that the dummy fins are properly cut. After the fin cut process(s) is complete, the remaining uncut semiconductor fins 340 are referred to as active semiconductor fins 340c. The active semiconductor fins 340c have functionality in the semiconductor structure 300. The dummy semiconductor fins 340a, 340b have no functionality in the semiconductor structure 300, but make the device process more uniform, more reproducible, and improve manufacturing yield. Any number of first dummy semiconductor fins 340a, second dummy semiconductor fins 340b, and active semiconductor fins 340c are contemplated. In some embodiments, the location and number of dummy semiconductor fins 340a, 340b are determined based on the number of active fins and the location of active elements for a design specification for implementing an integrated circuit.

[0085] Referring to FIG. 2, Figure 2 at operation 220, a dielectric cap layer 360L is formed over the active semiconductor fins 340c and the dummy semiconductor fins 340a, 340b. Figure 12A and Figure 12B ​is a view of the semiconductor structure 300 after forming the dielectric cap layer 360L according to some embodiments. Figures 11A-11C is a view of the semiconductor structure 300 after forming the dielectric cap layer 360L according to some embodiments.

[0086] Referring to 12A and Figure 12B A dielectric cap layer 360L is formed over the active semiconductor fin 340c, the dummy semiconductor fins 340a, 340b, and the STI structure 352. In some embodiments, the dielectric cap layer is a single layer and includes a dielectric oxide (e.g., silicon oxide) or a dielectric nitride (e.g., silicon nitride). In some embodiments, the dielectric cap layer 360L has a multi-layer structure including a dielectric liner layer 362L and a dielectric hardmask layer 364L.

[0087] A dielectric liner layer 362L is formed on exposed surfaces of the dummy semiconductor fins 340a, 340b and the active semiconductor fin 340c. In some embodiments, the dielectric liner layer 362L includes thermal oxide formed by a thermal oxidation process. In some embodiments, the dielectric liner layer 362L includes silicon oxide. In some embodiments, the dielectric liner layer 362L is formed using a conformal deposition process (e.g., CVD, ALD, or other suitable deposition process).

[0088] A dielectric hardmask layer 364L is deposited over the dielectric liner layer 362L. In some embodiments, the dielectric hardmask layer 364L includes a dielectric nitride, e.g., silicon nitride. In some embodiments, the dielectric hardmask layer 364L is deposited by a conformal deposition process (e.g., CVD, ALD, or other suitable deposition process).

[0089] Referring to Figure 2 The method 200 proceeds to operation 222, where a dielectric cap 360 is formed covering the dummy semiconductor fins 340a, 340b. Figure 13A and Figure 13B is a view of the semiconductor structure 300 after forming the dielectric cap layer 360L according to some embodiments. Figure 12A and Figure 12B is a view of the semiconductor structure 300 after forming the dielectric cap layer 360L according to some embodiments.

[0090] Referring to Figure 13A and Figure 13BThe portion of the dielectric cap layer 360L covering the active semiconductor fin 340c is removed, forming a dielectric cap 360 covering the area in which the dummy semiconductor fins 340a, 340b are present. In some embodiments, the dielectric cap 360 is formed by a photolithography and etching process. For example, a photoresist layer (not shown) is first formed over the topmost surface of the dielectric cap layer 360L (e.g., the top surface of the dielectric hardmask layer 364L). The photoresist layer is patterned to provide a patterned photoresist layer (not shown). The patterned photoresist layer includes openings (not shown) that expose portions of the dielectric hardmask layer 364L present over the active semiconductor fin 340c. Example photolithography patterning processes include soft baking the photoresist layer, mask alignment, exposure, post-exposure bake, developing the photoresist layer, rinsing, and drying (e.g., hard baking). Next, the exposed portions of the dielectric hardmask layer 364L are removed by anisotropic etching. In some embodiments, dry etching using a plasma generated from a halogen-containing etchant, for example, selected from the group including CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or combinations thereof, is performed to remove the exposed portions of the dielectric hardmask layer 364L. In some embodiments, wet etching using, for example, at least one aqueous etching solution including citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HC1), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), ethylenediaminetetra- olic acid (EDP), tetramethylammonium hydroxide (TMAH), or combinations thereof, is employed to remove the exposed portions of the dielectric hardmask layer 364L. In some embodiments, an etching sequence including both wet and dry etching techniques is used to etch the dielectric hardmask layer 364L. After etching, the remaining portions of the dielectric hardmask layer 364L over the dummy semiconductor fins 340a, 340b constitute the dielectric hardmask 364. If not completely consumed during etching of the dielectric hardmask layer 364L, in some embodiments, the patterned photoresist layer is removed, for example, by ashing, prior to etching the dielectric spacer layer 362L.

[0091] Next, portions of the dielectric liner layer 362L exposed by the dielectric hard mask 364 are removed to form the dielectric liner 362. In some embodiments, the exposed portions of the dielectric liner layer 362L are removed by an anisotropic etch. In some embodiments, a dry etch (e.g., RIE) is performed to selectively etch the dielectric material of the dielectric liner layer 362L selective to the semiconductor material of the active semiconductor fin 340c. In some embodiments, the dielectric liner layer 362L is etched by a wet etch using hot phosphoric acid. After the etching, the remaining portions of the dielectric liner layer 362L over the dummy semiconductor fins 340a, 340b constitute the dielectric liner 362. The dielectric liner 362 and the dielectric hard mask 364 together define the dielectric cap 360.

[0092] The dielectric cap 360 completely covers the dummy semiconductor fins 340a, 340b. Due to the dielectric nature of the dielectric cap 360, the dielectric cap 360 helps prevent the semiconductor material from epitaxially growing from the top surfaces of the dummy semiconductor fins 340a, 340b during a subsequently performed source / drain epitaxial growth. Thus, the dielectric cap 360 helps prevent epitaxial growth from the dummy semiconductor fins 340a, 340b to merge the dummy semiconductor fins 340a, 340b with the adjacent active semiconductor fin 340c. As a result, current leakage of the FinFET due to shorting of the adjacent dummy semiconductor fins 340a, 340b and the active semiconductor fin 340a is reduced or avoided.

[0093] In some embodiments, the dielectric cap 360 is formed to have a thickness in a range of about 10% to 30% of the height H of the semiconductor fin 340. In some embodiments, the dielectric cap has a thickness of about 5 nm to about 15 nm. If the thickness of the dielectric cap 360 is too small, the dielectric cap 360 is not sufficient to prevent epitaxial growth from the dummy semiconductor fins 340a, 20b and shorting of the adjacent FinFET. On the other hand, if the thickness of the dielectric cap 360 is too large, the production cost increases due to unnecessary material consumption and processing time increase to pattern the dielectric cap layer 360L.

[0094] In some embodiments, each sidewall of the dielectric cap 360 is spaced apart from the respective nearest active semiconductor fin 340c by a distance D. In some embodiments, the distance D is about 10% to about 50% of the fin pitch S. In some embodiments, the distance D is about 2 nm to about 30 nm. In some cases, if the distance D is too small, the risk of the dielectric cap 360 adversely affecting the performance of the FinFET formed on the adjacent active semiconductor fin 340c increases. In some cases, if the distance D is too large, the risk of the dielectric cap 360 exposing the outermost dummy semiconductor fin 340a, 340b at the edge of the dielectric cap 360 increases, which results in an epitaxial merge of the adjacent dummy semiconductor fin 340a, 340b and the active semiconductor fin 340a. In some embodiments, each sidewall of the dielectric cap 360 is aligned with the sidewall of the outermost dummy semiconductor fin 340a.

[0095] Referring to Figure 2 , the method 200 proceeds to operation 224, where gate structures 370 and source / drain regions 380 are formed on the respective sets of active semiconductor fins 340c. Figure 14A and Figure 14B are views of the semiconductor structure 300 after the formation of the gate structures 370 and the source / drain regions 380 according to some embodiments. Figure 13A and Figure 13B are views of the semiconductor structure 300 after the formation of the gate structures 370 and the source / drain regions 380 according to some embodiments.

[0096] Referring to 13A and Figure 13B The gate structures 370 are formed on and across the channel portions of the respective active semiconductor fins 340c. Each gate structure 370 includes a gate stack (372, 374, 376) and a gate spacer 378 surrounding the gate stack (372, 374, 376). In some embodiments, each gate stack includes a gate dielectric 372, a gate electrode 374, and a gate cap 376. In some embodiments, the gate stack (372, 374, 376) is formed by deposition and patterning of a gate stack layer. In some embodiments, the patterning of the gate stack layer is achieved by application of a photoresist layer (not shown), lithographic patterning of the photoresist layer, transfer of the pattern in the photoresist layer into the gate stack layer, and removal of the patterned photoresist layer, e.g., by ashing. In some embodiments, the materials of the gate stack (372, 374, 376) are sacrificial materials that are subsequently removed and replaced by a functional gate stack including a functional gate dielectric and a functional gate electrode after the formation of the source / drain regions 380 of the FinFET.

[0097] A gate dielectric 372 is formed over the active semiconductor fin 340c. In some embodiments, the gate dielectric 372 comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Alternatively or additionally, in some embodiments, the gate dielectric 372 comprises a high dielectric constant (high-k) dielectric material having a dielectric constant greater than that of silicon oxide. Exemplary high-k dielectric materials include, but are not limited to, Hf02, Zr02, La203, Al203, Ti02, SrTi03, LaAl03, and Y203. The gate dielectric 372 contacts the STI structure 352 between the active semiconductor fin 340c and the dummy semiconductor fins 340a, 340b.

[0098] A gate electrode 374 is formed over the gate dielectric 372. The gate electrode 374 comprises any suitable conductive material, for example, polysilicon, tungsten, copper, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, or a combination thereof. In some embodiments, the gate electrode 374 contacts the STI structure 352 between the active semiconductor fin 340c and the dummy semiconductor fins 340a, 340b. In some embodiments, the gate electrode 374 is separated from the STI structure 352 by the gate dielectric 372.

[0099] A gate cap 376 is formed over the gate electrode 374. In some embodiments, the gate cap 376 comprises a dielectric material, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or a combination thereof.

[0100] A gate spacer 378 is formed on sidewalls of the gate stack (372, 374, 376). In some embodiments, the gate spacer 378 is used to offset a subsequently formed doped region, for example, a source / drain region 380. In some embodiments, the gate spacer 378 is also used to design or modify the source / drain region 380. The gate spacer 378 comprises a dielectric material, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or a combination thereof. In some embodiments, the gate spacer 378 is formed, for example, by depositing a layer of conformal dielectric material and selectively removing horizontal portions of the deposited layer of conformal dielectric material. Remaining vertical portions of the deposited layer of conformal dielectric material constitute the gate spacer 378.

[0101] Subsequently, a source region and a drain region (collectively, source / drain regions) are formed on portions of each active semiconductor fin 340c located on opposite sides of the corresponding gate structure 370. In some embodiments, as shown in FIG. 4B, the source / drain regions are formed by depositing a layer of conformal dielectric material and selectively removing horizontal portions of the deposited layer of conformal dielectric material. Remaining vertical portions of the deposited layer of conformal dielectric material constitute the source / drain regions. Figure 13AAs shown, the source / drain regions 380 include raised source / drain regions formed on portions of each active semiconductor fin 340c that are not covered by the corresponding gate structure 370. In some embodiments, the raised source / drain regions in the source / drain regions 380 are formed by selective epitaxy. During the selective epitaxy process, the deposited semiconductor material grows only on exposed semiconductor regions, e.g., the top and sidewall surfaces of the portions of the active semiconductor fin 340a on opposite sides of the gate structure 370, and does not grow on dielectric surfaces, e.g., the surfaces of the gate cap 376, gate spacer 378, STI structure 352, and dielectric cap 360. In some embodiments, due to the close proximity of the active semiconductor fin 340c in each device region, the source / drain regions 380 in each device region are merged to form a merged source / drain structure. Thus, the presence of the dielectric cap 360 helps prevent epitaxial growth of semiconductor material on the dummy semiconductor fins 340a, 340b, thereby reducing the risk or preventing merging of the source / drain regions 380 in adjacent device regions of the semiconductor substrate 302.

[0102] In some embodiments, the semiconductor material (i.e., silicon-containing semiconductor material and germanium-containing semiconductor material) of the source / drain regions 380 is deposited as intrinsic semiconductor material, or is deposited with in-situ doping. If the semiconductor material is deposited as intrinsic semiconductor material, the raised source / drain regions are then doped (ex situ) with ion implantation, vapor phase doping, or out-diffusion of dopants from a sacrificial dopant source material. For n-type FETs, the raised source / drain regions are doped with n-type dopants, while for p-type FETs, the raised source / drain regions are doped with p-type dopants. Exemplary n-type dopants include, but are not limited to, phosphorus, arsenic, and antimony. Exemplary p-type dopants include, but are not limited to, aluminum, boron, gallium, and indium. If ex situ doping is employed, in some embodiments, the ion implantation or vapor phase doping also introduces dopants into portions of the active semiconductor fin 340c below the raised source / drain regions. The resulting doped portions (not shown) within each active semiconductor fin 340c constitute planar source / drain regions.

[0103] In some embodiments, the semiconductor structure 300 includes additional features formed by subsequent processes. For example, subsequent processes further form various contacts / vias / lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) over the semiconductor substrate 302 configured to connect various features or structures of the semiconductor structure 300. For example, the multilayer interconnects include vertical interconnects, e.g., conventional vias or contacts, and horizontal interconnects, e.g., metal lines. The various interconnect features are implemented by various conductive materials, including copper, tungsten, cobalt, and / or silicides. In some embodiments, a damascene and / or dual damascene process is used to form cobalt-related multilayer interconnect structures.

[0104] One aspect of the present specification relates to a semiconductor structure. The semiconductor structure includes an active semiconductor fin having a first height; a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height; an isolation structure between the active semiconductor fin and the dummy semiconductor fin; and a dielectric cap over the dummy semiconductor fin, wherein the dielectric cap is separated from the active semiconductor fin. In some embodiments, the dielectric cap completely covers a top surface of at least one dummy semiconductor fin. In some embodiments, the dielectric cap covers a portion of the isolation structure adjacent to the dummy semiconductor fin. In some embodiments, the dielectric cap includes a dielectric liner and a dielectric hardmask. In some embodiments, the dielectric liner includes a dielectric oxide. In some embodiments, the dielectric hardmask includes a dielectric nitride. In some embodiments, a distance between the dielectric cap and the active semiconductor fin is about 10% to about 50% of a spacing between the active semiconductor fin and the dummy semiconductor fin. In some embodiments, the dielectric cap has a thickness of about 5 nm to about 15 nm. In some embodiments, the semiconductor structure further includes a gate structure extending over the active semiconductor fin. In some embodiments, the semiconductor structure further includes a source / drain region over portions of the active semiconductor fin on opposite sides of the gate structure.

[0105] Another aspect of the present specification relates to a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure further includes a plurality of active semiconductor fins. Each active semiconductor fin of the plurality of active semiconductor fins has a first height. The semiconductor structure further includes a plurality of dummy semiconductor fins. Each dummy semiconductor fin of the plurality of dummy semiconductor fins has a second height less than the first height. The semiconductor structure further includes a plurality of isolation structures on the substrate. Each isolation structure of the plurality of isolation structures separates a respective active semiconductor fin of the plurality of active semiconductor fins or a respective dummy semiconductor fin of the plurality of dummy semiconductor fins from each other. The semiconductor structure further includes a dielectric cap over the plurality of dummy semiconductor fins. The dielectric cap is spaced apart from the plurality of active semiconductor fins. In some embodiments, top surfaces of the plurality of dummy semiconductor fins form a concave profile. In some embodiments, at least one dummy semiconductor fin of the plurality of dummy semiconductor fins has a height different from a height of an adjacent dummy semiconductor fin of the plurality of dummy semiconductor fins.

[0106] Yet another aspect of the specification relates to a method of forming a semiconductor structure. The method includes etching a semiconductor substrate to form a plurality of semiconductor fins; forming a shallow trench isolation (STI) structure in a trench between the plurality of semiconductor fins; recessing at least one semiconductor fin of the plurality of semiconductor fins to form at least one dummy semiconductor fin; forming a dielectric cap layer over the at least one dummy semiconductor fin and non-recessed semiconductor fins of the plurality of semiconductor fins; and patterning the dielectric cap layer to remove the dielectric cap layer from the non-recessed semiconductor fins of the plurality of semiconductor fins other than the at least one dummy semiconductor fin. In some embodiments, recessing the at least one semiconductor fin includes removing a portion of the at least one semiconductor fin that protrudes above the STI structure. In some embodiments, forming the STI structure includes depositing a flowable dielectric material to fill the trench between the plurality of semiconductor fins, annealing the flowable dielectric material to form an isolation layer, and recessing the isolation layer to form the STI structure. Recessing the isolation layer exposes a portion of each semiconductor fin of the plurality of semiconductor fins. In some embodiments, forming the dielectric cap layer includes forming a dielectric liner layer over exposed surfaces of the non-recessed semiconductor fins of the plurality of semiconductor fins and the at least one dummy semiconductor fin, and forming a dielectric hardmask layer over the dielectric liner layer. In some embodiments, forming the dielectric liner layer includes depositing a dielectric oxide layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, forming the dielectric liner layer includes forming a thermal oxide layer using a thermal oxidation process. In some embodiments, recessing the at least one semiconductor fin includes recessing a first subset of the plurality of semiconductor fins to form a plurality of first dummy semiconductor fins, and recessing a second subset of the plurality of semiconductor fins to form a plurality of second dummy semiconductor fins.

[0107] The foregoing summary of some embodiments is presented for purposes of illustration and better understanding. Those of ordinary skill in the art will readily and appreciably understand that they can readily employ the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art will also readily appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

[0108] Example 1 is a semiconductor structure comprising: an active semiconductor fin having a first height; a dummy semiconductor fin adjacent to the active semiconductor fin, the dummy semiconductor fin having a second height less than the first height; an isolation structure between the active semiconductor fin and the dummy semiconductor fin; and a dielectric cap over the dummy semiconductor fin, wherein the dielectric cap is separated from the active semiconductor fin.

[0109] Example 2 is the semiconductor structure of Example 1, wherein the dielectric cap completely covers a top surface of the dummy semiconductor fin.

[0110] Example 3 is the semiconductor structure of Example 1, wherein the dielectric cap covers a portion of the isolation structure adjacent to the dummy semiconductor fin.

[0111] Example 4 is the semiconductor structure of Example 1, wherein the dielectric cap comprises a dielectric liner and a dielectric hardmask.

[0112] Example 5 is the semiconductor structure of Example 4, wherein the dielectric liner comprises a dielectric oxide.

[0113] Example 6 is the semiconductor structure of Example 4, wherein the dielectric hardmask comprises a dielectric nitride.

[0114] Example 7 is the semiconductor structure of Example 1, wherein a distance between the dielectric cap and the active semiconductor fin is about 10% to about 50% of a spacing between the active semiconductor fin and the dummy semiconductor fin.

[0115] Example 8 is the semiconductor structure of Example 1, wherein the dielectric cap has a thickness of about 5 nm to about 15 nm.

[0116] Example 9 is the semiconductor structure of Example 1, further comprising: a gate structure extending over the active semiconductor fin.

[0117] Example 10 is the semiconductor structure of Example 9, further comprising: a source / drain region over portions of the active semiconductor fin on opposite sides of the gate structure.

[0118] Example 11 is a semiconductor structure comprising: a substrate; a plurality of active semiconductor fins, wherein each active semiconductor fin of the plurality of active semiconductor fins has a first height; a plurality of dummy semiconductor fins, wherein each dummy semiconductor fin of the plurality of dummy semiconductor fins has a second height that is less than the first height; a plurality of isolation structures on the substrate, wherein each isolation structure of the plurality of isolation structures separates a respective active semiconductor fin of the plurality of active semiconductor fins or a respective dummy semiconductor fin of the plurality of dummy semiconductor fins from one another; and a dielectric cap over the plurality of dummy semiconductor fins, wherein the dielectric cap is spaced apart from the plurality of active semiconductor fins.

[0119] Example 12 is the semiconductor structure of Example 11, wherein top surfaces of the plurality of dummy semiconductor fins form a concave profile.

[0120] Example 13 is the semiconductor structure of Example 11, wherein at least one dummy semiconductor fin of the plurality of dummy semiconductor fins has a different height than an adjacent dummy semiconductor fin of the plurality of dummy semiconductor fins.

[0121] Example 14 is a method of forming a semiconductor structure, comprising: etching a semiconductor substrate to form a plurality of semiconductor fins; forming a shallow trench isolation (STI) structure in a trench between the plurality of semiconductor fins; recessing at least one semiconductor fin of the plurality of semiconductor fins to form at least one dummy semiconductor fin; forming a dielectric cap layer over the at least one dummy semiconductor fin and un-recessed semiconductor fins of the plurality of semiconductor fins; and patterning the dielectric cap layer to remove the dielectric cap layer from the un-recessed semiconductor fins of the plurality of semiconductor fins other than the at least one dummy semiconductor fin.

[0122] Example 15 is the method of Example 14, wherein recessing the at least one semiconductor fin comprises removing a portion of the at least one semiconductor fin that protrudes above the STI structure.

[0123] Example 16 is the method of Example 14, wherein forming the STI structure comprises: depositing a flowable dielectric material to fill the trench between the plurality of semiconductor fins; annealing the flowable dielectric material to form an isolation layer; and recessing the isolation layer to form the STI structure, wherein recessing the isolation layer exposes a portion of each semiconductor fin of the plurality of semiconductor fins.

[0124] Example 17 is the method of Example 14, wherein forming the dielectric cap layer comprises: forming a dielectric liner layer over exposed surfaces of the un-recessed semiconductor fins of the plurality of semiconductor fins and the at least one dummy semiconductor fin; and forming a dielectric hardmask layer over the dielectric liner layer.

[0125] Example 18 is the method of Example 17, wherein forming the dielectric liner layer comprises: depositing a dielectric oxide layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0126] Example 19 is the method of Example 17, wherein forming the dielectric liner layer comprises: forming a thermal oxide layer using a thermal oxidation process.

[0127] Example 20 is the method of Example 14, wherein recessing the at least one semiconductor fin comprises: recessing a first subset of the plurality of semiconductor fins to form a plurality of first dummy semiconductor fins; and recessing a second subset of the plurality of semiconductor fins to form a plurality of second dummy semiconductor fins.

Claims

1. A semiconductor structure, comprising: Active semiconductor fins, with the highest height; A dummy semiconductor fin is adjacent to the active semiconductor fin, and the dummy semiconductor fin has a second height that is smaller than the first height; An isolation structure is located between the active semiconductor fin and the dummy semiconductor fin; A dielectric cap is located above the dummy semiconductor fin, wherein the dielectric cap is separate from the active semiconductor fin; as well as A gate structure extends above the active semiconductor fin, wherein the gate structure is separate from the dummy semiconductor fin, and wherein the gate structure contacts the sidewall of the dielectric cap, and the top surface of the dielectric cap does not have the gate structure.

2. The semiconductor structure of claim 1, wherein, The dielectric cap completely covers the top surface of the dummy semiconductor fin.

3. The semiconductor structure of claim 1, wherein, The dielectric cap covers a portion of the isolation structure adjacent to the dummy semiconductor fin.

4. The semiconductor structure of claim 1, wherein, The dielectric cap includes a dielectric gasket and a dielectric hard mask.

5. The semiconductor structure of claim 4, wherein, The dielectric liner comprises a dielectric oxide.

6. The semiconductor structure of claim 4, wherein, The dielectric hard mask comprises a dielectric nitride.

7. The semiconductor structure of claim 1, wherein, The distance between the dielectric cap and the active semiconductor fin is 10% to 50% of the interval between the active semiconductor fin and the dummy semiconductor fin.

8. The semiconductor structure of claim 1, wherein, The dielectric cap has a thickness of 5 nm to 15 nm.

9. The semiconductor structure of claim 1, further comprising: The source / drain region is located above a portion of the active semiconductor fin on the opposite side of the gate structure.

10. A semiconductor structure, comprising: Substrate; A plurality of active semiconductor fins, wherein each of the plurality of active semiconductor fins has a first height; Multiple dummy semiconductor fins, wherein each of the multiple dummy semiconductor fins has a second height that is less than the first height; Multiple isolation structures are located on the substrate, wherein each of the multiple isolation structures separates a corresponding active semiconductor fin of the multiple active semiconductor fins or a corresponding dummy semiconductor fin of the multiple dummy semiconductor fins from each other. A dielectric cap is located above the plurality of dummy semiconductor fins, wherein the dielectric cap is spaced apart from the plurality of active semiconductor fins; and Multiple gate structures extend above multiple active semiconductor fins, wherein the multiple gate structures are separated from the multiple dummy semiconductor fins, and wherein each of the multiple gate structures contacts a sidewall of a dielectric cap, and the top surface of the dielectric cap does not have the gate structure.

11. The semiconductor structure of claim 10, wherein, The top surfaces of the plurality of dummy semiconductor fins form a concave profile.

12. The semiconductor structure of claim 10, wherein, At least one of the plurality of dummy semiconductor fins has a height different from that of its adjacent dummy semiconductor fins.

13. A method for forming a semiconductor structure, comprising: Etch a semiconductor substrate to form multiple semiconductor fins; A shallow trench isolation (STI) structure is formed in the trench between the plurality of semiconductor fins; At least one of the plurality of semiconductor fins is recessed to form at least one dummy semiconductor fin; A dielectric cap layer is formed over the unrecessed semiconductor fin in the at least one dummy semiconductor fin and the plurality of semiconductor fins; as well as The dielectric cap layer is patterned to remove the dielectric cap layer from the non-recessed semiconductor fins among the plurality of semiconductor fins, excluding the at least one dummy semiconductor fin; Multiple gate structures are formed and extend on the non-recessed semiconductor fins of the multiple semiconductor fins, wherein the multiple gate structures are separated from the at least one dummy semiconductor fin, and wherein each of the multiple gate structures contacts the sidewall of the remaining dielectric cap layer, and the top surface of the remaining dielectric cap layer does not have the gate structure.

14. The method of claim 13, wherein, The recessing of the at least one semiconductor fin includes: removing a portion of the at least one semiconductor fin that protrudes above the STI structure.

15. The method according to claim 13, wherein, The formation of the STI structure includes: Deposit a flowable dielectric material to fill the trenches between the plurality of semiconductor fins; Annealing the flowable dielectric material to form an insulating layer; and The isolation layer is recessed to form the STI structure, wherein the recessed isolation layer exposes a portion of each of the plurality of semiconductor fins.

16. The method according to claim 13, wherein, Forming the dielectric cap layer includes: A dielectric pad layer is formed over the exposed surface of the non-recessed semiconductor fins among the plurality of semiconductor fins and the exposed surface of at least one dummy semiconductor fin: and A dielectric hard mask layer is formed above the dielectric pad layer.

17. The method according to claim 16, wherein, Forming the dielectric liner layer includes depositing a dielectric oxide layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

18. The method according to claim 16, wherein, Forming the dielectric liner layer includes forming a thermal oxide layer using a thermal oxidation process.

19. The method according to claim 13, wherein, The recessed at least one semiconductor fin includes: A first subset of the plurality of semiconductor fins is recessed to form a plurality of first dummy semiconductor fins; and A second subset of the plurality of semiconductor fins is recessed to form a plurality of second dummy semiconductor fins.

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