Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to pass through the active region, the word line extending in a first direction and formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask having a top surface having a height greater than that of the top surface of the active region, the second mask covering the word line, wherein the active region has a strip shape extending to form an acute angle with respect to the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0106645 filed on August 29, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept provides a semiconductor device and a method of manufacturing the same, and more particularly, provides a semiconductor device including a self-aligned contact in an active region and a method of manufacturing the same. Background Art

[0004] As the integration of semiconductor devices increases, design rules for components of semiconductor devices decrease. Therefore, in highly scaled semiconductor devices, the contact formation process for connecting multiple wirings to active areas also becomes increasingly complex and difficult. For example, the reduction in space for contacts causes an increase in misalignment between contacts and active areas, and thus, a reduction in mass production margin occurs. Summary of the invention

[0005] The disclosed embodiments provide a semiconductor device having reduced misalignment between contacts and active regions and a method of manufacturing the semiconductor device.

[0006] According to aspects of the inventive concept, a semiconductor device includes: an active area defined by a device isolation layer formed in a substrate; a word line configured to pass through the active area, the word line extending in a first direction and formed in the substrate; a bit line extending on the word line in a second direction perpendicular to the first direction; a first contact connecting the bit line to the active area; a first mask for forming the active area, the first mask being formed on the active area; and a second mask, the height of the top surface of the second mask being equal to or greater than the height of the top surface of the active area, the second mask covering the word line, wherein the active area has a strip shape extending in an inclined direction forming an acute angle relative to the first direction.

[0007] In addition, according to aspects of the inventive concept, a semiconductor device includes: an active area, defined by a device isolation layer formed in a substrate; a word line, constructed to pass through the active area, the word line including a buried structure extending in a first direction; a bit line, extending on the word line in a second direction perpendicular to the first direction; a capacitor, located on top of the bit line; a first contact, connecting the bit line to the active area; a second contact, connecting the capacitor to the active area; a first mask, used to form the active area, at least a portion of the first mask remaining on the active area; and a second mask, the height of the top surface of the second mask being equal to or greater than the height of the top surface of the active area, the second mask covering the word line, wherein the active area has a shape extending in an inclined direction relative to the first direction, and the first contact has a shape in which the width in the inclined direction narrows toward the bottom of the first contact.

[0008] Furthermore, according to aspects of the inventive concept, a method for manufacturing a semiconductor device includes: defining an active region by forming a device isolation layer in a substrate by using a first mask; forming a trench in the substrate that passes through the active region and extends in a first direction, and forming a conductive layer filling a bottom of the trench after applying an insulating layer on the substrate to form a buried word line; forming a second mask filling a top of the trench on the word line; recessing the device isolation layer by using the first mask and the second mask so that a side surface of a top of the active region is exposed; forming a mask pattern that exposes the first mask corresponding to a central portion of the active region, and removing the exposed first mask and the removed first mask by using the mask pattern; The method comprises the steps of: forming a first additional insulating layer and a second additional insulating layer on the entire surface of the substrate, and forming a buffer insulating layer filling a space between two first masks adjacent to each other in a first direction by removing a portion of the second additional insulating layer; forming a first contact by filling the contact hole with a conductive layer; and forming a bit line extending in a second direction perpendicular to the first direction on the word line, the bit line being connected to the first contact, wherein the active area has a shape extending in an inclined direction relative to the first direction, and wherein the first contact is self-aligned with the active area by the first mask and the second mask arranged around the contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1D are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept;

[0011] Figure 2 It is shown Figure 1A A plan view of a concept of self-alignment of a first contact in a semiconductor device;

[0012] FIG. 3A to FIG. 3C is a plan view of a semiconductor device according to an embodiment of the inventive concept;

[0013] FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 16A , FIG. 6B to FIG. 16B , FIG. 6C to FIG. 16C and FIG. 6D to FIG. 16D It shows the manufacturing Figure 1A A plan view and a cross-sectional view of a semiconductor device process;

[0014] FIG. 17A to FIG. 17C It is shown Figure 1A A cross-sectional view of various stacked structures of first contacts and via conductive layers in a semiconductor device of FIG.

[0015] Fig.18A and Fig.18B are cross-sectional views illustrating a process of fabricating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and their repeated descriptions are omitted.

[0017] Figures 1A to 1D 1 is a plan view and a cross-sectional view of a semiconductor device 100 according to an embodiment of the inventive concept. The semiconductor device may be, for example, a semiconductor chip including an integrated circuit formed on a bare die, wherein each figure shows only a representative portion of the semiconductor device. Here, Figure 1B is Figure 1A In the semiconductor device 100, the active region ACT extends along the direction I (corresponding to Figure 1B A cross-sectional view centered on the device isolation layer 120 between two active regions ACT on II') shown in FIG. Figure 1C yes Figure 1A The sectional view of section II-II' in FIG. Figure 1D yes Figure 1A A cross-sectional view of a boundary portion between a cell region and a core region in a semiconductor device 100 in a direction III along which a word line extends.

[0018] Reference Figures 1A to 1D , the semiconductor device 100 of the present example embodiment may include a plurality of active regions ACT defined by a device isolation layer 120 in a substrate 101. Figure 4AAs shown in FIG. 1 , in a top view of the top surface of the semiconductor device 100, the active region ACT may have a strip shape extending in an inclined direction (or referred to as a diagonal direction, xy direction) relative to the first direction (x direction) or the second direction (y direction). It should be noted that Figure 1B and Figure 4B (and other "B" figures) actually spans two active regions with a device isolation layer 120 therebetween. Figure 1B and Figure 4B Will include along the lines Figure 1A , Figure 4A The entire second active area in direction I in the figure (if the figure is continued and direction I is extended to include the second active area).

[0019] The device isolation layer 120 may be formed by forming a trench in the top of the substrate 101 and filling the trench with an insulating layer. Figures 1B to 1D As shown in , according to the width in the first direction (x direction), the device isolation layer 120 may include: a second structure including a first insulating layer 121 and a second insulating layer 123, a first structure including only the first insulating layer 121, and a third structure including the first insulating layer 121, the second insulating layer 123, and the third insulating layer 125. At least one of the first insulating layer 121, the second insulating layer 123, and the third insulating layer 125 may include a material different from each of the other two insulating layers, or be formed of a material different from each of the other two insulating layers. For example, the first insulating layer 121 and the third insulating layer 125 may include an oxide layer or may be an oxide layer, and the second insulating layer 123 includes a nitride layer or is a nitride layer. However, the materials of the first insulating layer 121, the second insulating layer 123, and the third insulating layer 125 are not limited thereto.

[0020] For reference, the device isolation layer 120 may be formed wide and deep between the active regions ACT in the oblique direction (xy direction) along which the active region ACT extends. In addition, the device isolation layer 120 may also be formed wide and deep at the boundary between the cell region Cell and the core region Core. For example, the device isolation layer 120 between the active regions ACT in the oblique direction (xy direction) may have a second structure and may be formed wider and deeper than the first structure. The device isolation layer 120 may be formed in the core region Core to have various widths and depths. In the semiconductor device 100 of this example embodiment, the core region Core may be a peripheral region. The core region Core may represent the region between the cell regions Cell, and the peripheral region may represent the region outside the cell region Cell (for example, so that the peripheral region is not between any two cell regions Cell but outside the outer boundary surrounding a plurality of cell regions Cell). However, in general, the region other than the cell region may be described as a core region or a core / peripheral region. In the semiconductor devices 100 and 100a to 100d of this example embodiment and subsequent example embodiments, the term "core region Core" may be used collectively.

[0021] On the active region ACT, at least a portion of the first mask 110 used to form the active region ACT may remain. Figure 1B and Figure 1C In the embodiment, a portion of the first mask 110 may remain on the top surface of the active area ACT where the second contact 180 is connected to the portion of the active area ACT. Figures 2 to 16D The first mask 110 is described in more detail.

[0022] The semiconductor device 100 of the present example embodiment may include a plurality of word lines 130 extending parallel to each other in a first direction (x direction) through the active region ACT. The word lines 130 may be arranged at equal intervals in a second direction (y direction) and may be formed in a structure buried in the substrate 101. For example, the word lines 130 may be formed in a shape filling the bottom of a trench formed in the substrate 101, and the top surface of the word lines 130 may be lower than the top surface of the active region ACT. On the other hand, as Figure 1B or Figure 1D As shown in , the word line 130 having a relatively wide width on the device isolation layer 120 may be formed deeper than the word line 130 of other portions.

[0023] The gate insulating layer 132 may be between the word line 130 and the active area ACT. In addition, impurity ions may be implanted into the active area ACT on both sides of the word line 130, and a source region / drain region may be formed. Therefore, the word line 130 and the source region / drain region on both sides of the word line 130 may form a buried cell array transistor (BCAT). In some embodiments, the word line 130 may include at least one of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN. However, the material of the word line 130 is not limited thereto. The gate insulating layer 132 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high dielectric layer having a higher dielectric constant than the silicon oxide layer. The gate insulating layer 132 is not limited thereto.

[0024] A second mask 140 may be formed on the word line 130 in the trench. A gate insulating layer 132 may also be formed between the second mask 140 and the active region ACT. Figure 1B As shown in , the height of the top surface of the second mask 140 may be equal to or greater than the height of the top surface of the active area ACT. For example, on the active area ACT, the height of the top surface of the second mask 140 may be substantially the same as the height of the top surface of the first mask 110. Terms such as "same," "equal," "planar," or "coplanar" as used herein encompass equivalence or near equivalence including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. However, in some embodiments, the top surface of the second mask 140 may be lower than the top surface of the first mask 110. Referring to Figures 2 to 16D The second mask 140 is described in more detail.

[0025] The semiconductor device 100 according to the present example embodiment may include a plurality of bit lines 170 extending parallel to each other on the word lines 130 in a second direction (y direction) perpendicular to the word lines 130. The plurality of bit lines 170 may be arranged at equal intervals in the first direction (x direction). Figure 1B is a cross section taken along the inclined direction (xy direction) along which the active area ACT extends, so Figure 1B The width of the bit line 170 is shown as Figure 1C The width of the bit line 170 in FIG.

[0026] The capping insulating layer 172 may be on the bit line 170, and the bit line spacer 174 may be on both sides of the bit line 170 in the first direction (x direction). The bit line spacer 174 may extend in the second direction (y direction) like the bit line 170. Figure 1B and Figure 1CThe bit line spacer 174 is shown as one layer, but the bit line spacer 174 may include a plurality of layers including at least two layers. In some embodiments, the plurality of layers of the bit line spacer 174 may include at least one air gap.

[0027] The semiconductor device 100 according to the present example embodiment may include a first contact 160 that electrically connects the bit line 170 to the active region ACT. The first contact 160 may be under the bit line 170. Figure 1B As shown in , the width of the first contact 160 in the diagonal direction (xy direction) may become narrower toward the bottom side thereof. Figure 1C As shown in , the width of the first contact 160 in the first direction (x direction) may be substantially the same as the width on the bottom and top sides thereof. The first contact 160 may be formed in a shape in which the first contact 160 is self-aligned with the active area ACT by using the first mask 110 and the second mask 140. Figures 2 to 16D The shape and forming method of the first mask 110 are described in more detail.

[0028] The path conductive layer 165 may be between the bit line 170 and the first contact 160. The path conductive layer 165 may extend in the second direction (y direction) like the bit line 170 and may electrically connect the bit line 170 to the first contact 160. The protective insulating layer 162 may be on two (e.g., opposite) side surfaces of the first contact 160 in the first direction (x direction). The first contact 160 may be electrically insulated from the second contact 180 via the protective insulating layer 162 and may also be insulated from the active area ACT. Here, the second contact 180 may be a contact that connects a capacitor (not shown) to the active area ACT. For reference, the first contact 160 may generally be referred to as a direct contact (DC), and the second contact 180 may be referred to as a buried contact (BC). The path conductive layer 165 may extend in the y direction while covering the first contact 160, and may be formed integrally with the first contact 160 or may be formed as a layer separate from the first contact 160. The active region ACT having a stripe shape may be included in the cell region Cell, and the core region Core may surround the cell region Cell. In addition, the transistor in the core region Core may include a gate electrode layer corresponding to the via conductive layer 165 .

[0029] The semiconductor device 100 according to the present example embodiment may include buffer insulating layers 150 alternately arranged with first contacts 160 in a first direction (x direction) and a second direction (y direction). Figure 2As shown in , in the first direction (x direction), the first contacts 160 and the buffer insulating layers 150 may be arranged alternately, and further, in the second direction (y direction), the first contacts 160 and the buffer insulating layers 150 may be arranged alternately. Figure 2 In the embodiment, the portion where the active area ACT is exposed may be a portion where the first contact 160 is arranged.

[0030] Reference Figure 1C , the buffer insulating layer 150 may be on the device isolation layer 120, and the first mask 110 may remain on the active area ACT on both sides of the top of the buffer insulating layer 150 in the first direction (x direction). The buffer insulating layer 150 and the first mask 110 may constitute a first mask structure 110S. Therefore, the first mask structure 110S may be arranged alternately with the first contacts 160 in the first direction (x direction) similarly to the buffer insulating layer 150, and furthermore, in the second direction (y direction), the first mask structure 110S may be arranged alternately with the first contacts 160. As shown in FIG. Figure 1A and Figure 1C As shown in FIG. 1 , in the first direction (x direction), the second contact 180 may be arranged between the first contact 160 and the buffer insulating layer 150, or between the first contact 160 and the first mask structure 110S. In addition, in the second direction (y direction), the word line 130 may be arranged between the first contact 160 and the buffer insulating layer 150, or between the first contact 160 and the first mask structure 110S.

[0031] The second contacts 180 may be on both sides of the first contacts 160 in the first direction (x direction) and penetrate the first mask 110 and the protective insulating layer 162 to be connected to the active region ACT. A fence insulating layer (or referred to as an isolation insulating layer, fence insulating layer) 185 may be between the second contacts 180 in the second direction (y direction). Figure 1B As shown in , the fence insulating layer 185 may be on the word line 130 .

[0032] The second contact 180 may be connected to a capacitor (not shown) via a landing pad 190 disposed upward. Therefore, the capacitor may be electrically connected to the active region ACT via the second contact 180 and the landing pad 190. Figure 1A, the bonding pad 190 may be indicated by a small ring. Typically, when a capacitor is directly connected to an active area ACT via a second contact 180, the area where the second contact 180 contacts the capacitor or the active area ACT may be very small. Therefore, a conductive bonding pad 190 may be introduced to expand the contact area between the second contact 180 and the active area ACT or between the second contact 180 and the capacitor. For example, the bonding pad 190 may be between the capacitor and the second contact 180, and based on the bonding pad 190, the contact area between the second contact 180 and the active area ACT may be expanded. In addition, the second contact 180 may have an effect such as expanding the contact area by contacting the capacitor via the bonding pad 190.

[0033] In the semiconductor device 100 according to the present example embodiment, the first contact 160 may be at the central portion of the active area ACT, and the second contact 180 may be at both (e.g., opposite) ends of the active area ACT. Since the second contact 180 is arranged at both ends of the active area ACT, the bonding pad 190 may be adjacent to each of the two ends of the active area ACT to partially overlap with the second contact 180.

[0034] The word line 130 may be formed in a structure in which the word line 130 is buried in the substrate 101 of the semiconductor device 100 and may be arranged between the first contact 160 and the second contact 180 through the active area ACT. Figure 1A As shown in , two word lines 130 may be arranged to pass through one active region ACT, and by arranging the active region ACT in a shape extending in an inclined direction (xy direction), the word lines 130 and the active region ACT may have an acute angle less than about 90°.

[0035] In addition, in the semiconductor device 100 according to the present example embodiment, the protruding insulating layer 110P may be formed in the core region Core, and the gap-filling insulating layer 155 may be formed on the boundary between the core region Core and the cell region Cell. The protruding insulating layer 110P may be derived from the first mask 110, and the gap-filling insulating layer 155 may be formed when the buffer insulating layer 150 is formed. Therefore, the protruding insulating layer 110P may include the same material as the first mask 110, and the gap-filling insulating layer 155 may include the same material as the buffer insulating layer 150. In the process of forming the corresponding structure, the detailed structure of the protruding insulating layer 110P and the gap-filling insulating layer 155 is described in more detail.

[0036] In the semiconductor device 100 according to the present example embodiment, the first contact 160 that connects the bit line 170 to the active area ACT can be formed into a shape that is self-aligned with the active area ACT by using the first mask 110 and the second mask 140. Therefore, the first contact 160 can reduce the misalignment with the active area ACT, and therefore, the first contact 160 can accurately contact the central portion of the active area ACT. As a result, the semiconductor device 100 according to the present example embodiment can greatly contribute to the increase of the mass production margin based on the reduced misalignment of the first contact 160. In addition, the buffer insulating layer 150 can be formed between the first masks 110 adjacent to each other in the first direction (x direction) and can be formed together with the first mask 110 to constitute the first mask structure 110S. Therefore, it can be stated that the first mask structure 110S (rather than the first mask 110) is used for the self-alignment of the first contact 160 together with the second mask 140.

[0037] In the semiconductor device 100 according to the present example embodiment, a mask pattern including a material that is easily removed in an ashing process may be formed (refer to FIG. 12A to FIG. 12D 270 in the figure), and by using the mask pattern 270, a contact hole for the first contact 160 may be formed in various forms (refer to Figures 2 to 3C H1 to H4 in FIG. 1 ). In addition, based on the shapes of the contact holes H1 to H4, the first contact 160 can be easily formed in various forms while reducing the misalignment of the first contact 160 by sufficiently ensuring the critical dimension (CD) (for example, the width of the first contact 160 in the first direction (x direction)). In addition, after the mask pattern 270 is removed, in the process of forming the gap-filling insulating layer 155 and the first mask structure 110S, by forming a spacer (refer to FIG. 1 ) on the side surface of the first mask structure 110S. Fig.18B 157S in the figure), the width of the first contact 160 in the first direction (x direction) can be adjusted.

[0038] Figure 2 It is shown Figure 1A FIG. 1 is a plan view of a concept of self-alignment of the first contact 160 in the semiconductor device 100. Figures 1A to 1C A description is given together, and the referenced Figures 1A to 1C Description given.

[0039] Reference Figure 2 , in the semiconductor device 100 according to the present example embodiment, the first contact 160 may be formed to be self-aligned with the active area ACT by using the first mask 110 and the second mask 140 . Figure 2A contact hole H1 is shown surrounded by the first mask 110 and the second mask 140 before forming the first contact 160. The active region ACT and the device isolation layer 120 may be exposed at the bottom of the contact hole H1. The first contact 160 may be formed by filling the contact hole H1 with a conductive material such as polysilicon.

[0040] More specifically, the contact hole H1 may be surrounded by the first mask 110 in the first direction (x direction), and may be surrounded by the second mask 140 in the second direction (y direction). In addition, the contact hole H1 may have a structure that narrows toward its bottom in the second direction (y direction) or the oblique direction (xy direction). Therefore, the contact hole H1 may have a shape similar to a circular shape at its top, but may be shaped like a straight strip extending in the first direction (x direction) at its bottom. The second mask 140 and the gate insulating layer 132 may be exposed between the circular strip and the straight strip.

[0041] The first mask 110 and the second mask 140 may be used as an etch stop layer in a planarization process for forming the first contact 160. As described above, two adjacent first masks 110 and the buffer insulating layer 150 may constitute a first mask structure 110S, and thus the misalignment of the first contact 160 and the function as an etch stop layer of the first contact 160 may be described by using the first mask structure 110S instead of the first mask 110. Here, the buffer insulating layer 150 may fill the space between the two first masks 110 in the first direction (x direction), and further, in the second direction (y direction), the buffer insulating layer 150 may fill the space between the first mask 110 and the second mask 140. In the semiconductor device 100 according to the present example embodiment, the first contact 160 may be formed to be self-aligned with the active area ACT by using the first mask structure 110S and the second mask 140, and thus, the misalignment of the first contact 160 with the active area ACT may be reduced.

[0042] FIG. 3A to FIG. 3C is according to an example embodiment and Figure 2 The corresponding plan views of semiconductor devices 100a, 100b and 100c are shown. Figures 1A to 2 A description is given together, and the referenced Figures 1A to 2 Description given.

[0043] Reference Figure 3A , in the semiconductor device 100a of the present example embodiment, the contact hole H2 for the first contact 160 may be formed in a pillar type. For reference, Figure 2The contact hole H1 and the first contact 160 corresponding thereto in the semiconductor device 100 may be formed as a contact type. In the case of the contact type, the top surface of the contact hole H1 may have a circular shape or an elliptical shape, and the first contact 160 may be formed by filling the contact hole H1. The term "contact type" may be attributed to the basic structure of a general contact.

[0044] On the other hand, the column type may be formed such that the insulating layer structure ISp including the first mask structure 110S and the second mask 140 is formed into a cylinder or an elliptical cylinder, and a portion other than the insulating layer structure ISp is exposed as the contact hole H2. The column type structure may also be formed by filling the contact hole H2 with a conductive material and forming the first contact 160. Figure 3A As shown in , the contact holes H2 may have a structure in which the contact holes H2 are completely connected to each other, but in a process of forming a via conductive layer 165 on the first contacts 160, the first contacts 160 adjacent to each other in a diagonal direction (xy direction) may be separated from each other.

[0045] When the contact hole H1 of the contact type and the contact hole H2 of the column type are compared with each other, the shapes may be similar in the first direction (x direction), but may be different in the second direction (y direction). When viewed from the top, the contact hole H1 of the contact type may have a shape that protrudes outward in both directions of the second direction (y direction). On the other hand, the columnar contact hole H2 may have a shape that is concave inward in both directions of the second direction (y direction). In addition, the contact hole H1 of the contact type may be formed in a structure in which they are separated from each other, while the columnar contact hole H2 may be formed in a structure in which they are connected to each other.

[0046] In the semiconductor device 100 a according to the present example embodiment, the first contact 160 may also be formed to be self-aligned with the active area ACT by using the first mask structure 110S and the second mask 140 , and thus, misalignment of the first contact 160 with the active area ACT may be reduced.

[0047] Reference Figure 3B, in the semiconductor device 100b of the present example embodiment, the contact hole H3 for the first contact 160 may be formed as a parallelogram type. The contact hole H3 may be surrounded by the first mask structure 110S in both directions of the first direction (x direction). In addition, the contact hole H3 may be surrounded by the second mask 140 in both directions of the second direction (y direction) or in both directions of the diagonal direction (xy direction), and may partially extend into the second mask 140. The outer line of the contact hole H3 extending into the second mask 140 may have a straight line shape. The contact hole H3 may extend in an inclined direction (xy direction), and the shape of the top surface of the contact hole H3 may be similar to a parallelogram. The portion of the contact hole H3 extending into the second mask 140 may overlap with a portion of the word line 130 located under the second mask 140.

[0048] In the semiconductor device 100 b according to the present example embodiment, the first contact 160 may also be formed to be self-aligned with the active area ACT by using the first mask structure 110S and the second mask 140 , and thus, misalignment of the first contact 160 with the active area ACT may be reduced.

[0049] Reference Figure 3C , in the semiconductor device 100c of the present example embodiment, the contact hole H4 for the first contact 160 may be formed in a line type. The contact hole H4 may form a line while passing through the second mask 140 in a step-like manner in an oblique direction, and the contact hole H4 constituting one line and the contact hole H4 constituting another adjacent line may be separated from each other by the first mask structure 110S and the second mask 140. The portion of the contact hole H3 passing through the second mask 140 may completely overlap the word line 130 under the second mask 140. The contact holes H4 constituting one line have a structure connected to each other, but in the process of forming the via conductive layer 165 located on the first contact 160, the first contacts 160 adjacent to each other in the diagonal direction (xy direction) may be separated from each other.

[0050] In the semiconductor device 100 c according to the present example embodiment, the first contact 160 may also be formed to be self-aligned with the active area ACT by using the first mask structure 110S and the second mask 140 , and thus, misalignment of the first contact 160 with the active area ACT may be reduced.

[0051] FIG. 4A to FIG. 16D It shows the manufacturing Figure 1AThe present invention provides a plan view and a cross-sectional view of a process of a semiconductor device 100. Here, the figure with B in the figure number is a cross-sectional view centered on the device isolation layer 120 between two active regions ACT in the direction I along which the active region ACT extends in the corresponding figure with A in the figure number, the figure with C in the figure number is a cross-sectional view of the II-II' portion of the corresponding figure with A in the figure number, and the figure with D in the figure number is a cross-sectional view in which the figure with A in the figure number is cut along the direction III along which the word line extends to show the boundary between the cell region Cell and the core region Core.

[0052] Reference FIG. 4A to FIG. 4C , a first mask 110 may be formed on the substrate 101 by a photolithography process, and a first trench T1 may be formed by using the first mask 110. As previously discussed, Figure 4B The first trench T1 shown in FIG. 1 is actually positioned between the two active regions ACT in the xy direction, rather than in the Figure 4A . In the cell region Cell, the first mask 110 may have a strip shape extending in an inclined direction (xy direction). The shape of the first mask 110 may correspond to the planar shape of the active region ACT. In addition, although not shown, the shape of the first mask 110 in the core region Core outside the cell region Cell may be different from the strip shape of the first mask 110 in the cell region Cell.

[0053] Before forming the first mask 110, a protective insulating layer 103 may be formed on the top surface of the substrate 101. The protective insulating layer 103 may protect the substrate 101 or the active area ACT from external foreign substances, etc. In addition, the protective insulating layer 103 may be used as an etching stop layer in a subsequent etching process of the material layer. For example, in the semiconductor device 100 according to the present embodiment, the protective insulating layer 103 may include an oxide-based material. However, the material of the protective insulating layer 103 is not limited thereto. The first mask 110 may be formed on the protective insulating layer 103, and the first trench T1 may be formed in the substrate 101 in a shape that penetrates the protective insulating layer 103.

[0054] The first mask 110 may include an insulating material. For example, the first mask 110 may include a material such as SiN, SiO, SiON, SiOC, and a metal oxide or a combination thereof. In the semiconductor device 100 according to the present embodiment, the first mask 110 may include, for example, a nitride-based material. However, the material of the first mask 110 is not limited thereto.

[0055] like Figure 4B and Figure 4CAs shown in , the first trench T1 formed between the active regions ACT adjacent to each other in the diagonal direction (xy direction) can be made deeper than the first trench T1 formed between the active regions ACT adjacent to each other in the first direction (x direction). Fig.6D As shown in the figure, the first trench T1 can be formed wide and deep (for example, wider and deeper than the first trench T1 in the interior of the cell region Cell) in the outside of the cell region Cell (as a boundary portion of the core region Core). Although not shown, the first trench T1 having various widths and depths can be formed in the core region Core. When viewed from a cross section, the first trench T1 may be described as a plurality of first trenches T1 below. For example, different first trenches T1 as shown in the cross section may have different corresponding widths and heights.

[0056] exist Figure 4B and Figure 4C In the embodiment of the present invention, the width of the first trench T1 may have a constant shape at its top and bottom, but the width of the first trench T1 may narrow toward its bottom during the etching process. Therefore, the sidewall of the first trench T1 may not be precisely vertical but may have a slight inclination. The same concept may be applied to the following other trenches.

[0057] Reference FIG. 5A to FIG. 5C , the device isolation layer 120 may be formed by filling the first trench T1 with an insulating material. The device isolation layer 120 may have different stacking structures according to the width of the first trench T1. For example, when the width of the first trench T1 is compared with the width of the active area ACT, and when the width of the first trench T1 is approximately the same as or smaller than the width of the active area ACT (e.g., Figure 5C ), the device isolation layer 120 may have a first structure including only the first insulating layer 121. In addition, when the first trench T1 has a width approximately twice the width of the active area ACT (as shown in FIG. Figure 5B As shown in FIG. 1 , the device isolation layer 120 may have a second structure including a first insulating layer 121 and a second insulating layer 123. Fig.6D As shown in , on the periphery of the cell region Cell (as a boundary portion relative to the core region Core), the first trench T1 may have a very large width (i.e., at least three times the width of the active region ACT). When the first trench T1 has a large width, the device isolation layer 120 may have a third structure in which the third insulating layer 125 is further disposed inside the second insulating layer 123. In the process of filling the first trench T1 with an insulating material, various stacked structures of the device isolation layer 120 may be naturally formed to a certain extent according to the width of the first trench T1.

[0058] Reference FIG. 6A to FIG. 6D After forming the device isolation layer 120, a first protection mask 210 covering the cell region Cell may be formed. The first protection mask 210 may be formed using a photoresist (PR) in a photolithography process. However, the material of the first protection mask 210 is not limited thereto. Fig.6D As shown in , the first protection mask 210 may not accurately cover the cell area Cell, but may also cover a portion of the core area Core. This may be to ensure the process margin in the cell area Cell. Here, the dotted line extending in the third direction (z direction) indicates the boundary between the cell area Cell and the core area Core. In some cases, the boundary between the cell area Cell and the core area Core may be defined by a device isolation layer 120 having a width greater than the width of the device isolation layer between adjacent active areas (e.g., a width of about three times or more than three times the width between adjacent active areas in the x direction).

[0059] Since the first protection mask 210 is formed in the entire cell region Cell, Fig. 6A , the first mask 110 and the device isolation layer 120 may be covered by the first protection mask 210 and may not be seen. For convenience, the first protection mask 210 is omitted and only the first mask 110 and the device isolation layer 120 are shown.

[0060] Reference 7A to 7D , the first mask 110 in the core region Core may be removed by using the first protective mask 210. The first mask 110 in the core region Core may be removed by using the first protective mask 210 in a dry etching process or a wet etching process. For example, when the first mask 110 is removed by wet etching, the first mask 110 may be etched concavely inward at the boundary portion covered by the first protective mask 210. Fig.7D In FIG. 1 , for convenience, the boundary portion is shown in a vertical form.

[0061] When the first mask 110 in the core region Core is removed, the protective insulating layer 103 under the first mask 110 can be used as an etching stop layer. Therefore, after removing the first mask 110, the protective insulating layer 103 can be exposed on the substrate 101 of the core region Core. After removing the first mask 110 in the core region Core, the first protective mask 210 in the cell region Cell can be removed. Therefore, the device isolation layer 120 and the first mask 110 on the active region ACT can be exposed in the cell region Cell. Since the first protective mask 210 is partially formed in the core region Core to ensure process margin, after removing the first protective mask 210, a protruding insulating layer 110P (also described as a protruding insulating layer) derived from the first mask 110 can be formed in the core region Core.

[0062] The protruding insulating layer 110P may have a protruding structure above the substrate 101 and may have a rectangular cross-sectional shape. For example, it may protrude from the cell region Cell and from the side surface of the device isolation layer 120 into the core region Core in a horizontal direction. However, as described above, in the protruding insulating layer 110P, a concave shape may be formed on its side surface. In addition, as described above, Fig.16D As shown in , in the process of removing the first additional insulating layer 152 , a portion of the top surface of the protrusion insulating layer 110P may be removed to form a concave shape on the portion of the top surface of the protrusion insulating layer 110P.

[0063] Reference FIG. 8A to FIG. 8D , a plurality of second trenches T2 may be formed in the substrate 101. The second trenches T2 may extend parallel to each other in the first direction (x direction) and may be formed to pass through the active area ACT. After cleaning the product in which the second trenches T2 are formed on the substrate 101, a gate insulating layer 132, a word line 130, and a second mask 140 may be sequentially formed in the second trenches T2.

[0064] After forming the second trench T2, a gate insulating layer 132 may be formed on the entire surface of the substrate 101. Therefore, the gate insulating layer 132 may cover the inner wall of the second trench T2 of the cell region Cell and the first mask 110 and the protective insulating layer 103 of the core region Core. The gate insulating layer 132 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high dielectric layer having a dielectric constant higher than that of the silicon oxide layer. In the semiconductor device 100 according to the present embodiment, the gate insulating layer 132 may include an oxide-based material. The material of the gate insulating layer 132 is not limited thereto.

[0065] After forming the gate insulating layer 132, a word line 130 having a buried structure may be formed by filling a conductive layer in the bottom of the second trench T2. For example, the top surface of the word line 130 may be lower than the top surface of the substrate 101 or the top surface of the active area ACT. In some embodiments, the word line 130 may include at least one of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN. However, the material of the word line 130 is not limited thereto.

[0066] After forming the word line 130, a second mask 140 may be formed by filling the top of the second trench T2 with an insulating material. Thus, the second mask 140 may be formed on the word line 130 in the second trench T2. Figure 8B As shown in , the top surface of the second mask 140 may have substantially the same height as the top surface of the first mask 110. However, the top surface of the second mask 140 may be lower than the top surface of the first mask 110. However, the height of the top surface of the second mask 140 may be equal to or greater than the height of the top surface of the active area ACT. For example, the top surface of the second mask 140 may be between the top surface of the first mask 110 and the top surface of the active area ACT. Due to the height of the top surface of the second mask 140, when the first contact 160 is subsequently formed by using the first mask 110 and the second mask 140, various changes may be made to the structure of the first contact 160.

[0067] The second mask 140 may include a material similar to or the same as that of the first mask 110. For example, the second mask 140 may include a material such as SiN, SiO, SiON, SiOC, and a metal oxide or a combination thereof. In the semiconductor device 100 according to the present embodiment, the second mask 140 may include, for example, a nitride-based material. However, the material of the second mask 140 is not limited thereto.

[0068] In some embodiments, after forming the word line 130, by using the word line 130 as a mask to implant impurity ions into the active area ACT on both sides of the word line 130, a source region / drain region may be formed on top of the active area ACT. The first contact 160 may be connected to the source region. In some other embodiments, an impurity ion implantation process for forming the source region / drain region may be performed before forming the word line 130.

[0069] Reference 9A to 9D, the third mask 230 may be formed relatively thickly on the entire surface of the substrate 101. The third mask 230 may include, for example, an oxide-based material. However, the material of the third mask 230 is not limited thereto. After forming the third mask 230, a second protective mask 250 may be formed that exposes a portion of the third mask 230 of the cell region Cell and covers a portion of the third mask 230 of the core region Core. The second protective mask 250 may be formed by PR in a photolithography process. However, the material of the second protective mask 250 is not limited thereto.

[0070] Reference FIG. 10A to FIG. 10D , the third mask 230 on the cell region Cell may be removed by using the second protective mask 250. The third mask 230 in the cell region Cell may be removed by a dry etching process or a wet etching process using the second protective mask 250. For example, in the semiconductor device 100 according to the present example embodiment, the third mask 230 may be removed by a dry etching process. When the third mask 230 is removed, the gate insulating layer 132 and / or the second mask 140 may be used as an etching stop layer. In some embodiments, some of the third mask 230 may remain on the second mask 140. After the third mask 230 in the cell region Cell is removed, since the second protective mask 250 is removed, the following may result Fig. 10D The shape of the third mask 230 is shown in FIG.

[0071] Reference FIG. 11A to FIG. 11D After removing the third mask 230 of the cell region Cell, the device isolation layer 120 may be recessed by removing the top of the device isolation layer 120 using the first mask 110 and the second mask 140 as etching masks. In the recess of the device isolation layer 120, the top of the gate insulating layer 132 may be removed. Fig. 11B As shown in , the top surfaces of the first mask 110 and the second mask 140 may be higher than the top surface of the gate insulating layer 132. Fig. 11C As shown in , the first mask 110 and the active area ACT may protrude from the device isolation layer 120 .

[0072] At a boundary portion between the core region Core and the cell region Cell, the third trench T3 may be formed by removing the gate insulating layer 132 and the device isolation layer 120. A portion of the device isolation layer 120 may be more etched due to a difference in etching rates between the gate insulating layer 132 and the device isolation layer 120. However, according to example embodiments, a portion of the device isolation layer 120 may be etched similarly to the gate insulating layer 132, or a portion of the gate insulating layer 132 may be more etched.

[0073] For reference, the recess of the device isolation layer 120 may be formed in a wet etching process or a dry etching process. In addition, due to the difference in selectivity of each material and / or the difference in etching rate for each CD, the recess of the device isolation layer 120 may be configured in various forms. For example, based on the difference in selectivity to the first mask 110 and the second mask 140, the etching depth of the gate insulation layer 132 and the device isolation layer 120 may vary. In addition, based on the width of the first mask 110 and the second mask 140 and the difference in selectivity according to the width of the first mask 110 and the second mask 140, the etching depth of the gate insulation layer 132 and the device isolation layer 120 may vary.

[0074] The third mask 230 of the core region Core may also be removed to a certain thickness in the recess of the device isolation layer 120. However, since the function of the third mask 230 is to protect the core region Core, the third mask 230 may remain in the core region Core with a certain thickness after the device isolation layer 120 is recessed.

[0075] Reference FIG. 12A to FIG. 12D , a mask pattern 270 may be formed on the entire surface of the substrate 101 by using a photolithography process. The mask pattern 270 may include a material that can be easily removed in an ashing process. For example, the mask pattern 270 may include PR or a material with a high carbon content such as a spin-on hard mask (SOH). However, the material of the mask pattern 270 is not limited thereto.

[0076] like Fig. 12A As shown in , the mask pattern 270 may include an open region exposing a portion corresponding to a central portion of the active region ACT. The central portion of the active region ACT exposed through the open region may correspond to a portion where the first contact 160 will be formed.

[0077] After forming the mask pattern 270, the first mask 110 exposed through the opening region and the top of the active region ACT under the first mask 110 may be removed by an etching process using the mask pattern 270 as an etching mask. For example, the etching process may be a dry etching process, and the fourth trench T4 may be formed by an etching process. The fourth trench T4 may have a similar width in the bottom and the top in the first direction (x direction) (for example, based on a sidewall that is only slightly inclined), but may be narrowed toward the bottom in the diagonal direction (xy direction) along which the active region ACT extends. For example, the width difference in the first direction (x direction) between the width of the fourth trench T4 at the bottom at a first vertical height above the bottommost surface of the fourth trench T4 and the width of the fourth trench T4 at the top at a second vertical height higher than the first vertical height may be a first width difference. The width difference in the diagonal direction (xy direction) between the width of the fourth trench T4 at the bottom at a first vertical height above the bottommost surface of the fourth trench T4 and the width of the fourth trench T4 at the top at a second vertical height may be a second width difference, which may be greater than the first width difference.

[0078] like Fig. 12C As shown in , the top surface of the active region ACT and the top surface of the device isolation layer 120 may be exposed in the first direction (x direction) through the fourth trench T4. Fig. 12B As shown in the figure, the top surface of the active area ACT, the second mask 140, and the gate insulating layer 132 may be exposed via the fourth trench T4 in an inclined direction (xy direction). Since the fourth trench T4 is formed to have a downwardly narrowed slope in the inclined direction (xy direction), the second mask 140 and the gate insulating layer 132 may be exposed to the side surface of the fourth trench T4, rather than the bottommost surface of the fourth trench T4. The mask pattern 270 may be exposed to the side surface of the fourth trench T4 in the first direction (x direction). The mask pattern 270 may cover the side surface of the first mask 110 adjacent to the fourth trench T4 and the top of the active area ACT under the first mask 110.

[0079] The shape of the fourth trench T4 and the shape of the first contact 160 to be formed later may be variously changed or selected according to the shape of the opening area of ​​the mask pattern 270. For example, when the opening area of ​​the mask pattern 270 is formed in a circular shape, the fourth trench T4 and the first contact 160 may be formed in a contact shape having a circular top surface. Figure 2 In addition, according to the shape of the opening area of ​​the mask pattern 270, the structure of the fourth trench T4 can be the same as FIG. 3A to FIG. 3C The structure of the contact holes H2 to H4 shown in FIG. 1 corresponds to that of the contact holes H2 to H4 shown in FIG. 2 . However, as described below, Figures 2 to 3C The contact holes H1 to H4 may correspond to the structure of the fourth trench T4 ′ after removing the mask pattern 270 .

[0080] Reference FIG. 13A to FIG. 13D , after forming the fourth trench T4 and subsequently removing the first mask 110 and the top of the active area ACT exposed by the first mask 110, the mask pattern 270 may be removed. The mask pattern 270 may be easily removed by an ashing process. By removing the mask pattern 270, the fourth trench T4' may have a wider width in the first direction (x direction). For example, as the mask pattern 270 covering the side surface of the first mask 110 and the side surface of the top of the active area ACT under the first mask 110 is removed, the width of the fourth trench T4' may increase the thickness of the mask pattern 270 in the first direction (x direction).

[0081] For example, when a plurality of active regions ACT are arranged in the first direction (x direction), the fourth trench T4′ may have a first width (refer to Fig. 15C The first width W1 in the first direction (x direction) corresponds to the distance between the first active region ACT in the plurality of active regions ACT and the third active region ACT in the plurality of active regions ACT. For reference, the width of the fourth trench T4' in the first direction (x direction) may not be related to the size of the opening region of the mask pattern 270 at all. For example, when only the first mask 110 corresponding to the central portion of the active region ACT and the top of the active region ACT under the first mask 110 can be removed by the opening region of the mask pattern 270, regardless of the total size of the opening region of the mask pattern 270, after removing the mask pattern 270, the fourth trench T4' may have the first width W1 in the first direction (x direction).

[0082] Reference FIG. 14A to FIG. 14D , after removing the mask pattern 270, an additional insulating layer may be formed on the entire surface of the substrate 101. The additional insulating layer may include multiple layers. For example, the additional insulating layer may be formed as a double layer of a first additional insulating layer 152 and a second additional insulating layer 154. In the semiconductor device 100 according to the present example embodiment, the first additional insulating layer 152 may be an oxide-based material layer, and the second additional insulating layer 154 may be a nitride-based material layer. However, the materials of the first additional insulating layer 152 and the second additional insulating layer 154 are not limited thereto. In addition, the number of layers of the additional insulating layer is not limited to two. However, as described below, the additional insulating layer may include two or more material layers with different selectivities to apply a wet etching process or a pull-back etching process.

[0083] Since the first additional insulating layer 152 and the second additional insulating layer 154 are formed on the entire substrate 101, Fig.14A , components on the bottom of the first additional insulating layer 152 may not be seen because they are covered by the first additional insulating layer 152 and the second additional insulating layer 154. However, for ease of understanding, components of the first additional insulating layer 152 and the second additional insulating layer 154 are omitted, and corresponding components are shown.

[0084] Reference FIG. 15A to FIG. 15D , after the additional insulating layer is formed, the second additional insulating layer 154 may be removed by a wet etching process. Due to the wet etching characteristics, the portion of the second additional insulating layer 154 that completely fills the narrow portion may not be removed, and only the exposed portion of the second additional insulating layer 154 may be removed. Therefore, the portion of the second additional insulating layer 154 that fills the space between the two first masks 110 adjacent to each other in the first direction (x direction) may remain without being removed. In addition, as Fig.15D As shown in FIG. 1 , a portion of the second additional insulating layer 154 filling the removed portion of the gate insulating layer 132 may also remain without being removed.

[0085] For example, when the first additional insulating layer 152 includes an oxide-based material and the second additional insulating layer 154 includes a nitride-based material, the second additional insulating layer 154 may be removed by a wet etching process using phosphoric acid. In the wet etching process using phosphoric acid, the first additional insulating layer 152 may be used as an etching stop layer. As a result, the second additional insulating layer 154 may remain only between two adjacent first masks 110 and at a portion where the gate insulating layer 132 is removed.

[0086] The portion of the second additional insulating layer 154 that is not removed and remains may be referred to as a buffer insulating layer 150. Fig.15A As shown in , the buffer insulating layer 150 may constitute a first mask structure 110S together with the first mask 110. When viewed in a plan view, the first mask structure 110S may include two first masks 110 and a buffer insulating layer 150 between the two first masks 110 in a first direction (x direction), and include the first mask 110 and the buffer insulating layer 150 outside the first mask 110 on both sides in a second direction (y direction). When forming the first contact 160, the first mask structure 110S may be used together with the second mask 140 for self-alignment relative to the active area ACT. In addition, when forming the buffer insulating layer 150, a gap filling insulating layer 155 may be formed by a second additional insulating layer 154 filling the third trench T3 at the boundary between the core area Core and the cell area Cell.

[0087] The gap-filling insulating layer 155 may have a shape corresponding to the shape of the third trench T3. Fig.13D , the third trench T3 may be formed during a process of removing the device isolation layer 120 by using the first mask 110 and the second mask 140 as masks and removing a portion of the gate insulating layer 132 adjacent to the removed device isolation layer 120. However, due to the difference in etching rate, the device isolation layer 120 may be deeply etched. Therefore, the gap-filling insulating layer 155 may have a shape in which a portion of the gap-filling insulating layer 155 corresponding to the gate insulating layer 132 is higher than a portion of the gap-filling insulating layer 155 corresponding to the device isolation layer 120 with respect to a bottom surface of the gap-filling insulating layer 155.

[0088] Since the first additional insulating layer 152 still remains on the entire substrate 101, Fig.15A , components under the first additional insulating layer 152 may be covered by the first additional insulating layer 152 and may not be seen. However, for ease of understanding, the first additional insulating layer 152 is omitted and corresponding components are shown.

[0089] Reference FIG. 16A to FIG. 16D After forming the first mask structure 110S, a pre-cleaning process may be performed on the entire surface of the substrate 101. In the pre-cleaning process, the first additional insulating layer 152 covering the entire surface of the substrate 101 may be removed. Of course, the first additional insulating layer 152 on the side surface and the bottom surface of the buffer insulating layer 150 may remain without being removed.

[0090] Subsequently, a conductive layer for forming the first contact 160 may be formed on the entire surface of the substrate 101. The conductive layer may include, for example, polysilicon. However, the material of the conductive layer is not limited thereto. The conductive layer may completely fill the fourth trench T4' and may be formed on the first mask structure 110S and the second mask 140 with a certain thickness. Next, a planarization process of the conductive layer may be performed, and the first contact 160 may be formed by retaining the conductive layer only inside the fourth trench T4'. In the planarization process, the first mask structure 110S and the second mask 140 may be used as an etching stop layer.

[0091] As described above, the first contact 160 may be formed in a shape in which the first contact 160 is self-aligned with the active region ACT (e.g., the central portion of the active region ACT) by using the pre-formed first mask structure 110S and the second mask 140. Therefore, the first contact 160 may reduce misalignment with the active region ACT and, therefore, may accurately contact the central portion of the active region ACT.

[0092] After forming the first contact 160, a via conductive layer may be formed (see Figure 1B The via conductive layer 165 may be electrically connected to the first contact 160 thereunder. Figure 3A or Figure 3C In the case where the first contact 160 is formed through the contact holes H2 and H4 as shown in FIG, when the via conductive layer 165 is formed, the first contacts 160 adjacent to each other in the diagonal direction may be insulated from each other. The first contact 160 and the via conductive layer 165 may be formed in various stacked structures, and will be referred to later. FIG. 17A to FIG. 17C A more detailed description thereof is provided.

[0093] After forming the via conductive layer 165, a bit line ( Figure 1B 170 in the first direction (x direction). In addition, a cap insulating layer 172 may be formed on the bit line 170, and a bit line spacer 174 may be formed on both (e.g., opposite) sides of the bit line 170 in the first direction (x direction). A second contact 180 connected to the active region ACT may be formed, and a fence insulating layer 185 may be formed on a side surface of the second contact 180 in the second direction (y direction). A bonding pad 190 may be formed on the second contact 180, and a capacitor (not shown) may be formed on the bonding pad 190.

[0094] The planar gate structure 300 may be formed at an outer portion of the core region Core or the cell region Cell. Figure 1D 300) may include an electrode structure ( Figure 1D 310 in), planar gate insulating layer ( Figure 1D 320 in), gate spacer ( Figure 1D 330) and the gate cap insulation layer ( Figure 1D In addition, the electrode structure 310 may include three electrode layers ( Figure 1D 312, 314 and 316 in the figure). However, the number of electrode layers of the electrode structure 310 is not limited thereto. Meanwhile, a conductive layer ( Figure 1D 190A and 190B in FIG.

[0095] In addition, when the electrode structure 310 of the gate structure 300 includes polysilicon, according to example embodiments, the process of forming the electrode structure 310 of the gate structure 300 of the core region Core and the process of forming the component including polysilicon in the cell region Cell can be performed simultaneously. However, even when the processes are performed together, the thicknesses of the corresponding layers can be the same as or different from each other. For example, the path conductive layer 165 of the cell region Cell and the second electrode layer 314 of the electrode structure 310 of the core region Core can be formed together. Therefore, the energized conductive layer 165 and the second electrode layer 314 of the electrode structure 310 can include the same material. However, the path conductive layer 165 and the second electrode layer 314 can be formed to have the same thickness or different thicknesses.

[0096] FIG. 17A to FIG. 17C It is shown Figure 1A 1 is a cross-sectional view of various stacked structures of the first contact 160 and the via conductive layer 165 in the semiconductor device 100, and is taken along Figure 1A A cross-sectional view taken along line IV-IV'.

[0097] Reference FIG. 17A to FIG. 17C The first contact 160 and the via conductive layer 165 may be formed into various stacked structures. Fig.17A As shown in , the first contact 160 and the via conductive layer 165 may include two different conductive layers and may have a double-layer structure. Fig. 17B As shown in , the path conductive layer 165a may have a structure in which two conductive layers (165-1 and 165-2) are stacked. Therefore, the first contact 160 and the path conductive layer 165a may have a three-layer structure. The path conductive layer 165a is not limited thereto and may include three or more conductive layers.

[0098] like Fig. 17C As shown in , the first contact 160 and the via conductive layer 165 may have a monolithic structure including one conductive layer. When forming the first contact 160, after the conductive layer is formed with a relatively large thickness, and after performing a planarization process so that a certain thickness remains on the first mask structure 110S and the second mask 140, a process of patterning the via conductive layer 165 may be implemented to realize the monolithic structure.

[0099] Although three structures have been exemplified above for the stacked structure of the first contact 160 and the via conductive layer 165, the stacked structure of the first contact 160 and the via conductive layer 165 may have more different structures. In addition, when forming the stacked structure of the first contact 160 and the via conductive layer 165, the stacked structure may be formed together with the conductive layer in the gate structure 300 of the core region Core, or may be formed separately.

[0100] Fig.18A and Fig.18B is a cross-sectional view showing a process of manufacturing a semiconductor device 100d according to an embodiment of the inventive concept, and is similar to Fig. 15C Corresponding cross-sectional views. References to 4A to 16D Description given.

[0101] Reference Fig.18A In the method of manufacturing the semiconductor device 100d according to the present exemplary embodiment, FIG. 15A to FIG. 15D In the embodiment, after removing the second additional insulating layer 154 by wet etching and forming the buffer insulating layer 150, a third additional insulating layer 157 may be further formed on the entire surface of the substrate 101. The third additional insulating layer 157 may cover the top surface of the first mask structure 110S and the inner side of the fourth trench T4'.

[0102] Reference Fig.18B After forming the third additional insulating layer 157, a spacer 157S may be formed on the side surface of the first mask structure 110S by an etching process (e.g., a dry etching process). In the process of forming the spacer 157S, both the third additional insulating layer 157 on the top surface of the first mask structure 110S and the third additional insulating layer 157 on the bottom of the fourth trench T4' may be removed. Therefore, the first additional insulating layer 152 may be exposed on the top surface of the first mask structure 110S and the bottom surface of the fourth trench T4'.

[0103] Afterwards, as in FIG. 16A to FIG. 16D As described in the description of , the first contact 160 may be formed by performing a pre-cleaning process, an electrode film forming process, and a planarization process. Due to the presence of the spacer 157S, the width of the fourth trench T4' in the first direction (x direction) may be reduced to the second width W2, and therefore, the width of the first contact 160 in the first direction (x direction) may be reduced. As a result, the width of the first contact 160 in the first direction (x direction) may be adjusted based on the thickness of the third additional insulating layer 157 and the subsequent thickness of the spacer 157S.

[0104] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, comprising: an active region defined by a device isolation layer formed in the substrate; a word line configured to pass through the active area, the word line extending in a first direction and formed in the substrate; a bit line extending on the word line in a second direction perpendicular to the first direction; a first contact connecting the bit line to the active region; A first mask is used to form an active area, and the first mask is formed on the active area; a second mask, wherein a top surface of the second mask has a height equal to or greater than a top surface of the active region, and the second mask covers the word line; as well as A buffer insulating layer is provided on the device isolation layer, and a first mask is arranged on both sides of the buffer insulating layer on the active area. The active region has a strip shape extending in an inclined direction forming an acute angle with respect to the first direction.

2. The semiconductor device according to claim 1, wherein: The first contact has a shape in which the width in the oblique direction becomes narrower toward the bottom of the first contact.

3. The semiconductor device according to claim 1, further comprising: an additional first mask for forming an additional active region, the additional first mask being formed on the additional active region, The buffer insulating layer is located between the first mask and the additional first mask, and the first mask and the additional first mask are adjacent masks in the first direction.

4. The semiconductor device according to claim 3, wherein: The semiconductor device includes a cell region and a core region, wherein a plurality of active regions having a strip shape are arranged in the cell region, and the core region is around the cell region. At a boundary between the cell region and the core region, a protrusion insulating layer corresponding to the first mask and a gap-filling insulating layer corresponding to the buffer insulating layer are arranged adjacent to each other, A protrusion insulating layer is formed on the substrate and has a concave shape on a portion of a top surface of the protrusion insulating layer, and A gap-filling insulating layer is formed on the device isolation layer and the gate insulating layer, wherein a bottom surface of the gap-filling insulating layer located on the gate insulating layer is higher than a bottom surface of the gap-filling insulating layer located on the device isolation layer. 5 . The semiconductor device according to claim 3 , further comprising a spacer covering a side surface of the first mask and a side surface of the active region under the first mask.

6. The semiconductor device according to claim 3, further comprising a second contact, the second contact penetrating the first mask adjacent to the buffer insulating layer, the second contact being connected to the active region, in, The active region is connected to a capacitor over the bit line via a second contact.

7. The semiconductor device according to claim 3, wherein: The buffer insulating layer is also arranged on the gate insulating layer adjacent to the device isolation layer and the active region along the second direction, and The first mask, the additional first mask and the buffer insulating layer constitute a first mask structure.

8. The semiconductor device according to claim 1, wherein: When viewed from a top surface of the first contact, the first contact has any one of a circular type, an elliptical type, a parallelogram type, and a linear type.

9. The semiconductor device according to claim 8, wherein: When viewed from the top surface of the first contact, the first contact has one of the following shapes: Round or oval shape, a shape that is concave inwardly at both ends in the first direction, A shape extending in the extending direction of the active region while extending to portions of the word line in two opposite directions, and A shape extending in the extending direction of the active region while extending in the second direction to cover the entirety of the two word lines.

10. The semiconductor device according to claim 1, further comprising a via conductive layer extending in the second direction while covering the first contact, in, The via conductive layer is formed integrally with the first contact or is formed as a layer separate from the first contact.

11. The semiconductor device according to claim 10, wherein: The semiconductor device includes a cell region and a core region, wherein the cell region includes an active region in a stripe shape, and the core region is around the cell region, and The transistor in the core region includes a gate electrode layer corresponding to the via conductive layer.

12. A semiconductor device, comprising: an active region defined by a device isolation layer formed in the substrate; a word line configured to pass through the active area, the word line including a buried structure extending in a first direction; a bit line extending on the word line in a second direction perpendicular to the first direction; a first contact connecting the bit line to the active region; a second contact connecting the active region to a capacitor located above the bit line; A first mask, used to form an active region, at least a portion of the first mask remaining on the active region; as well as a second mask, wherein a top surface of the second mask has a height equal to or greater than a top surface of the active region, and the second mask covers the word line; wherein the active region has a shape extending in an inclined direction relative to the first direction, and The first contact has a shape in which the width in the oblique direction becomes narrower toward the bottom of the first contact.

13. The semiconductor device according to claim 12, further comprising a buffer insulating layer located on the device isolation layer between the first mask and an additional first mask adjacent to the first mask in the first direction, in, The buffer insulating layer is one of a plurality of buffer insulating layers alternately arranged with the plurality of first contacts in a first direction and a second direction, The second contact is arranged between the first contact and the buffer insulating layer in the first direction, and The word line is arranged between the first contact and the buffer insulating layer in the second direction.

14. The semiconductor device according to claim 12, wherein: When viewed from a top surface of the first contact, the first contact has any one of a circular type, an elliptical type, a parallelogram type, and a linear type.

15. The semiconductor device according to claim 12, further comprising a via conductive layer extending in the second direction while covering the first contact, in, The via conductive layer is formed integrally with the first contact or is formed as a layer separate from the first contact.

16. The semiconductor device according to claim 12, further comprising: a bit line spacer covering opposite side surfaces of the bit line in the first direction; as well as The fence insulating layer covers the side surfaces of the second contact that are opposite in the second direction.

17. A method for manufacturing a semiconductor device, the method comprising the steps of: defining an active area by forming a device isolation layer in a substrate by using a first mask; forming a trench in the substrate that passes through the active area and extends in a first direction, and forming a conductive layer filling the bottom of the trench after applying an insulating layer on the substrate to form a buried word line; forming a second mask on the word line that fills the top of the trench; recessing the device isolation layer by using a first mask and a second mask so that a side surface of a top portion of the active region is exposed; forming a mask pattern exposing the first mask corresponding to a central portion of the active region, and forming a contact hole by removing the exposed first mask and a top portion of the active region under the removed first mask by using the mask pattern; forming a first additional insulating layer and a second additional insulating layer on the entire surface of the substrate, and forming a buffer insulating layer filling a space between two first masks adjacent to each other in a first direction by removing a portion of the second additional insulating layer; forming a first contact by filling the contact hole with a conductive layer; as well as forming a bit line extending in a second direction perpendicular to the first direction on the word line, the bit line being connected to the first contact, wherein the active region has a shape extending in an inclined direction relative to the first direction, and Wherein, the first contact is self-aligned with the active area by the first mask and the second mask arranged around the contact hole.

18. The method of claim 17, wherein: The semiconductor device includes a cell region and a core region, wherein a strip-shaped active region is defined in the cell region and the core region is located around the cell region. The method further includes: before the step of forming the word line, forming a first protection mask covering the cell region; and removing the first mask located in the core region by using the first protection mask.

19. The method according to claim 17, wherein: In the contact hole forming step, the mask pattern is formed into any one of a circular type, an elliptical type, a parallelogram type, and a linear type, and In the step of forming the first contact, a shape of a top surface of the first contact is determined according to a shape of the mask pattern.

20. The method according to claim 17, further comprising: After the step of forming the first contact, forming a conductive layer on the entire surface of the substrate; And by patterning the conductive layer, via conductive layers are formed that extend in the second direction, cover the first contacts and the additional corresponding first contacts, and are spaced apart from each other in the first direction.

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