Semiconductor device including a separate charge storage layer

Abstract

A semiconductor device is provided. The semiconductor device includes a gate electrode on a substrate and stacked vertically relative to the upper surface of the substrate. The semiconductor device includes an interlayer insulating layer stacked alternately with the gate electrode. In addition, the semiconductor device includes a channel structure passing through the gate electrode. Each of the channel structures includes a channel layer extending vertically relative to the upper surface of the substrate, a tunneling insulating layer on the channel layer, a charge storage layer on the tunneling insulating layer in a corresponding region between the gate electrode and the side surface of the tunneling insulating layer, and a first blocking insulating layer respectively located on the charge storage layer. The first layer of the first blocking insulating layer is located on the upper surface, the lower surface and the side surface of the first layer of the charge storage layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0108801 filed on September 3, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] Semiconductor devices can have relatively high data processing capabilities even though their size is becoming smaller. Therefore, it would be desirable to increase the integration of semiconductor elements constituting such semiconductor devices. Therefore, as a method of increasing the integration of semiconductor devices, a semiconductor device having a vertical transistor structure (instead of a conventional planar transistor structure) is proposed. Summary of the invention

[0005] An aspect of the inventive concept is to provide a semiconductor device having improved reliability.

[0006] According to some embodiments of the present inventive concept, a semiconductor device may include gate electrodes spaced apart from each other on a substrate and stacked vertically relative to an upper surface of the substrate. The semiconductor device may include an interlayer insulating layer stacked on the substrate alternately with the gate electrode. In addition, the semiconductor device may include a channel structure passing through the gate electrode and extending vertically relative to the upper surface of the substrate. Each of the channel structures may include a channel layer extending vertically relative to the upper surface of the substrate, a tunneling insulating layer located on the channel layer and extending vertically relative to the upper surface of the substrate, a charge storage layer located on the tunneling insulating layer in a respective region between the gate electrode and the side surface of the tunneling insulating layer, and a first blocking insulating layer located respectively on the charge storage layer. The first layer of the first blocking insulating layer may be located on the upper and lower surfaces of the first layer of the charge storage layer, and may also be located on the side surface of the first layer of the charge storage layer facing the first gate electrode of the gate electrode. In a first direction perpendicular to the upper surface of the substrate, the height of each of the charge storage layers may be less than the distance between a pair of interlayer insulating layers adjacent to each other.

[0007] According to some embodiments of the present invention, a semiconductor device may include gate electrodes spaced apart from each other on a substrate and stacked vertically relative to an upper surface of the substrate. The semiconductor device may include an interlayer insulating layer stacked on the substrate alternately with the gate electrode. In addition, the semiconductor device may include a channel structure extending vertically relative to the upper surface of the substrate through the gate electrode. Each of the channel structures may include a tunneling insulating layer and a channel layer extending vertically relative to the upper surface of the substrate, and a charge storage layer and a blocking insulating layer located on the side surface of the gate electrode and between the side surface of the gate electrode and the tunneling insulating layer. The first layer in the charge storage layer and the first layer in the blocking insulating layer may be separated from the second layer in the charge storage layer and the second layer in the blocking insulating layer by the first layer in the interlayer insulating layer. The blocking insulating layer may completely surround the charge storage layer together with the tunneling insulating layer, respectively. In addition, the upper surface and the lower surface of the blocking insulating layer may be in contact with the interlayer insulating layer.

[0008] According to some embodiments of the present inventive concept, a semiconductor device may include gate electrodes spaced apart from each other on a substrate and stacked vertically relative to an upper surface of the substrate. The semiconductor device may include an interlayer insulating layer alternately stacked with the gate electrode on the substrate. The semiconductor device may include a channel layer passing through the gate electrode and extending vertically relative to the upper surface of the substrate. The semiconductor device may include a tunneling insulating layer between a side surface of the interlayer insulating layer and the channel layer and extending vertically relative to the upper surface of the substrate. The semiconductor device may include a charge storage layer respectively located between the gate electrode and the tunneling insulating layer. A first layer in the charge storage layer may be located between a side surface of a first gate electrode in the gate electrode and a side surface of the tunneling insulating layer, and between a pair of interlayer insulating layers adjacent to each other in a vertical direction. The semiconductor device may include a first blocking insulating layer respectively located on the charge storage layer. A first layer in the first blocking insulating layer may be located on an upper surface and a lower surface of the first layer in the charge storage layer, and may be located on a side surface of the first layer in the charge storage layer facing a side surface of the first gate electrode in the gate electrode, and may be located between the pair of interlayer insulating layers adjacent to each other in a vertical direction. In addition, the semiconductor device may include second blocking insulating layers respectively located on the gate electrodes. The first layer of the second blocking insulating layers may be located on the upper surface, the lower surface and the side surface of the first gate electrode of the gate electrodes, and may have an upper surface substantially coplanar with the upper surface of the first layer of the first blocking insulating layers.

[0009] According to some embodiments of the present invention, a method for manufacturing a semiconductor device includes: alternately stacking horizontal sacrificial layers and interlayer insulating layers on a substrate to form a stacked structure; forming a channel hole passing through the horizontal sacrificial layers and the interlayer insulating layer; removing a portion of the horizontal sacrificial layer exposed through the channel hole to form a recessed area; filling the recessed area in the channel hole with a first vertical sacrificial layer and a second vertical sacrificial layer in sequence; oxidizing a portion of the second vertical sacrificial layer from the channel hole to form an oxidized sacrificial layer; removing the oxidized sacrificial layer and a portion of the first vertical sacrificial layer to expose the side surface of the interlayer insulating layer; nitriding the remaining unoxidized second vertical sacrificial layer to form a charge storage layer; forming a tunneling insulating layer and a channel layer in sequence in the channel hole; forming an opening passing through the horizontal sacrificial layer and the interlayer insulating layer; removing the horizontal sacrificial layer through the opening to form a lateral opening; removing the oxidized sacrificial layer exposed through the lateral opening; and forming a blocking insulating layer on the charge storage layer exposed through the lateral opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view schematically illustrating a semiconductor device according to example embodiments;

[0012] Figure 2 is a cross-sectional view schematically illustrating a semiconductor device according to an example embodiment;

[0013] Figure 3 is a partially enlarged view schematically illustrating a semiconductor device according to an example embodiment;

[0014] FIG. 4A to FIG. 4C is a partially enlarged view of a semiconductor device according to an example embodiment;

[0015] Figure 5A and Figure 5B are a cross-sectional view and a partially enlarged view schematically illustrating a semiconductor device according to an example embodiment, respectively;

[0016] Fig. 6A and Figure 6B are a cross-sectional view and a partially enlarged view schematically illustrating a semiconductor device according to an example embodiment, respectively;

[0017] Figure 7 is a partially enlarged view schematically illustrating a semiconductor device according to an example embodiment;

[0018] Figure 8 is a cross-sectional view schematically illustrating a semiconductor device according to an example embodiment;

[0019] Fig. 9 is a cross-sectional view schematically illustrating a semiconductor device according to an example embodiment;

[0020] Fig.10 is a cross-sectional view schematically illustrating a semiconductor device according to an example embodiment;

[0021] FIG. 11A to FIG. 11L is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0022] FIG. 12A to FIG. 12C is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0023] FIG. 13A to FIG. 13C is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0025] Figure 1 is a plan view schematically illustrating a semiconductor device according to example embodiments.

[0026] Figure 2 is a cross-sectional view schematically illustrating a semiconductor device according to example embodiments. Figure 2 Shown along Figure 1 A cross section taken along section line II'.

[0027] Figure 3 FIG. 1 is a partially enlarged view schematically showing a semiconductor device according to an example embodiment. Figure 3 In the Figure 2 An enlarged view of portion 'A'.

[0028] Reference Figures 1 to 3 , the semiconductor device 100 may include: a substrate 101; gate electrodes 130, which are spaced apart from each other on the substrate 101 and stacked perpendicularly to the substrate 101; interlayer insulating layers 120, which are alternately stacked with the gate electrodes 130; a channel structure CH, which passes through the gate electrodes 130, extends in a direction perpendicular to the upper surface of the substrate 101, and has a channel layer 140 disposed therein; and a separation region SR, which extends into and through the stacking structure GS of the interlayer insulating layer 120 and the gate electrodes 130.

[0029] Each of the channel structures CH may include a tunneling insulating layer 142, a charge storage layer 143, and a first blocking insulating layer 144 stacked in sequence on / from the channel layer 140, and may also include a channel insulating layer 150 between opposite sidewalls of the channel layer 140, a channel pad 155 in an upper end of the channel structure CH, and an epitaxial layer 107 disposed below the channel layer 140. In addition, the semiconductor device 100 may further include a source conductive layer 180 and a separation insulating layer 185 disposed in the separation region SR, and a second blocking insulating layer 146 surrounding at least a portion of the gate electrode 130.

[0030] In the semiconductor device 100 , memory cell strings may be constructed around each channel layer 140 , and a plurality of memory cell strings may be arranged in a plurality of rows and columns in the X direction and the Y direction.

[0031] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as bulk silicon, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, etc.

[0032] The gate electrodes 130 may be stacked to be vertically spaced apart on the substrate 101 to form a stacked structure GS together with the interlayer insulating layer 120. The gate electrode 130 may include a lower gate electrode 130G forming a gate of a ground selection transistor, a memory gate electrode 130M constituting a plurality of memory cells, and an upper gate electrode 130S forming a gate of a string selection transistor. The number of memory gate electrodes 130M constituting a memory cell may vary according to the capacity of the semiconductor device 100 (e.g., may be determined according to the capacity of the semiconductor device 100). According to example embodiments, the upper gate electrode 130S and the lower gate electrode 130G constituting the string selection transistor and the ground selection transistor, respectively, may each be one, two or more gate electrodes, and may have the same structure as the memory gate electrode 130M constituting the memory cell or a different structure. A portion of the gate electrode 130 (e.g., a memory gate electrode 130M adjacent to the upper gate electrode 130S or the lower gate electrode 130G) may be a dummy gate electrode.

[0033] The gate electrodes 130 may be stacked to be vertically spaced apart from each other on the substrate 101, and may be provided to be separated from each other in the X direction by a separation region SR extending in the Y direction. The gate electrodes 130 between a pair of separation regions SR may form a memory block, but the scope of the memory block is not limited thereto. A portion of the gate electrodes 130 (e.g., the memory gate electrode 130M) may form a single layer in one memory block.

[0034] The gate electrode 130 may include a metal material such as tungsten (W). In some embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In example embodiments, the gate electrode 130 may further include a diffusion barrier outside thereof. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0035] The interlayer insulating layer 120 may be disposed between the gate electrodes 130. In a manner similar to the gate electrodes 130, the interlayer insulating layers 120 may be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride. The interlayer insulating layer 120 may have a substantially flat upper surface and lower surface. The side surface of the interlayer insulating layer 120 may have a structure that protrudes horizontally toward the separation region SR beyond the side surface of the gate electrode 130. In example embodiments, in / adjacent to the separation region SR, the side surface of the interlayer insulating layer 120 may be coplanar with the side surface of the gate electrode 130.

[0036] The channel structures CH may each form a memory cell string, and may be arranged to be spaced apart from each other in multiple rows and columns on the substrate 101. The channel structures CH may be arranged to form a grid, or may be arranged in a zigzag shape in one direction. The channel structure CH may have a columnar shape (or other elongated vertical shapes), and may have an inclined side portion so that its width narrows as it approaches the substrate 101 according to the aspect ratio. Each of the channel structures CH may include a channel layer 140, a tunneling insulating layer 142, a charge storage layer 143, a first blocking insulating layer 144, a channel insulating layer 150, a channel pad 155, and an epitaxial layer 107. For example, in the current specification, the channel structure CH may be used as a term that includes not only a columnar region, but also a charge storage layer 143 and a first blocking insulating layer 144 (which may be components of a region surrounding the outside of the columnar region). The tunneling insulating layer 142 , the charge storage layer 143 , and the first blocking insulating layer 144 of the channel structure CH may form a gate dielectric layer together with the second blocking insulating layer 146 .

[0037] The channel layer 140 may be formed to have a ring shape surrounding the channel insulating layer 150, but according to example embodiments, the channel layer 140 may have a columnar shape such as a column or a prism without the channel insulating layer 150. A lower portion of the channel layer 140 may be connected to the epitaxial layer 107. The channel layer 140 may include a semiconductor material such as polysilicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including a p-type impurity or an n-type impurity. The channel structures CH arranged in a straight line between a pair of separation regions SR in the X direction may be connected to different bit lines, respectively, according to the arrangement of the upper wiring structure connected to the channel pad 155.

[0038] The tunneling insulating layer 142 may be disposed between the side surface of the interlayer insulating layer 120 and the channel layer 140 on the channel layer 140, may extend perpendicularly to the upper surface of the substrate 101, and may be arranged as a single layer in the single channel structure CH. The tunneling insulating layer 142 may tunnel charges through to reach the charge storage layer 143, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof.

[0039] The charge storage layer 143 may be disposed on the tunneling insulating layer 142, and the gate electrode 130 may be disposed in a region recessed in an outward direction from the channel structure CH. The charge storage layer 143 may be disposed between the interlayer insulating layers 120 adjacent to each other in the vertical direction to overlap the interlayer insulating layer 120 in a plan view or in the Z direction. Therefore, the charge storage layer 143 may be disposed to be separated from each other between the gate electrodes 130 adjacent to each other in the vertical direction (for example, separated from each other by the interlayer insulating layer 120), and may be disposed to be separated into a plurality of layers in one channel structure CH. Figure 3 As shown, the surface of the charge storage layer 143 that does not contact the tunneling insulating layer 142 may have a convex round shape toward the gate electrode 130. The degree of roundness of this shape may vary differently according to some embodiments. Each of the charge storage layers 143 may have a structure completely surrounded by the tunneling insulating layer 142 and the first blocking insulating layer 144. The charge storage layer 143 may be a charge trapping layer or a floating gate conductive layer, and when the charge storage layer 143 includes a charge trapping layer, it may be formed of silicon nitride.

[0040] The height (i.e., vertical thickness) D2 of each of the charge storage layers 143 is smaller than the distance D1 between the interlayer insulating layers 120, and the interlayer insulating layers 120 may be vertically adjacent to each other in a direction perpendicular to the upper surface of the substrate 101 (e.g., in the Z direction). This is because the charge storage layer 143 may be arranged to be surrounded by the first blocking insulating layer 144 between the interlayer insulating layers 120 adjacent to each other. In addition, the height D2 of the charge storage layer 143 may be smaller than the height of one of the gate electrodes 130. The thickness T1 of the charge storage layer 143 in the X direction may be, for example, in the range of about 4 nanometers (nm) to about 6 nm. The thickness range of the charge storage layer 143 may be determined in consideration of the relative relationship with the thickness of other nearby layers, the magnitude of the voltage applied to the gate electrode 130, and the like.

[0041] The first blocking insulating layer 144 may be disposed on the charge storage layer 143 and between the second blocking insulating layer 146 and the charge storage layer 143. Each of the first blocking insulating layers 144 may be disposed on the upper and lower surfaces of the charge storage layer 143 (e.g., surround / cover the upper and lower surfaces of the charge storage layer 143), and may be disposed on the outer surface of the charge storage layer 143 facing the gate electrode 130 (e.g., surround / cover the outer surface). For example, the first blocking insulating layer 144 may be disposed to surround all surfaces of the charge storage layer 143 except for the surface where the charge storage layer 143 contacts the tunnel insulating layer 142. In a similar manner to the charge storage layer 143, the first blocking insulating layer 144 may be disposed to be separated from each other between the gate electrodes 130 adjacent to each other in the vertical direction. The first blocking insulating layer 144 may be defined by the interlayer insulating layer 120 and disposed only between the interlayer insulating layers 120 to overlap with the interlayer insulating layer 120 in the Z direction. The first blocking insulating layer 144 may not vertically extend in the Z direction on the side surface of the interlayer insulating layer 120 .

[0042] The upper surface and the lower surface of the first blocking insulating layer 144 may be in contact with the interlayer insulating layer 120 adjacent thereto, respectively. The inner side surface of the first blocking insulating layer 144 may be in contact with the charge storage layer 143, and the outer side surface of the first blocking insulating layer 144 may be in contact with the second blocking insulating layer 146. The inner side surface and the outer side surface of the first blocking insulating layer 144 may have a convex round shape toward the gate electrode 130. On the upper surface and the lower surface of the charge storage layer 143, the inner side surface of the first blocking insulating layer 144 at the upper end and the lower end may be in contact with the tunneling insulating layer 142, and may be substantially coplanar with the inner side surface of the charge storage layer 143. In addition, the upper surface and the lower surface of the first blocking insulating layer 144 may be substantially coplanar with the upper surface and the lower surface of the second blocking insulating layer 146, respectively.

[0043] The second blocking insulating layer 146 may be disposed on an outer side surface of the first blocking insulating layer 144 (e.g., a side of the first blocking insulating layer 144 facing the gate electrode 130 instead of facing the channel structure CH), and may extend horizontally along the gate electrode 130. Each of the second blocking insulating layers 146 may surround the upper surface, the lower surface, and the side surface of the gate electrode 130. The outer side surface of the second blocking insulating layer 146 contacting the first blocking insulating layer 144 may have a shape that is concavely rounded toward the channel layer 140.

[0044] The first blocking insulating layer 144 and the second blocking insulating layer 146 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), high-k dielectric materials, or combinations thereof. In this case, high-k dielectric materials refer to materials with a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material with a dielectric constant of . For example, the high-k dielectric material may include aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), praseodymium oxide (Pr 2 O 3 ) or a combination thereof. The first blocking insulating layer 144 and the second blocking insulating layer 146 may include different materials. For example, the first blocking insulating layer 144 may include silicon oxide (SiO 2 ), and the second blocking insulating layer 146 may include aluminum oxide (Al 2 O 3 In example embodiments, the interlayer insulating layer 120, the tunnel insulating layer 142, and the first blocking insulating layer 144 may include the same material.

[0045] In the semiconductor device, the charge storage layer 143 of the gate dielectric layer (e.g., constituting the gate dielectric layer) can be disposed separately from each other between the gate electrodes 130 adjacent to each other in the vertical direction, thereby suppressing / preventing degradation of electrical characteristics (e.g., degradation of retention characteristics due to charge diffusion). In addition, as the charge storage layer 143 is formed using an improved / optimized manufacturing process, the first blocking insulating layer 144 can be disposed to surround the charge storage layer 143.

[0046] The channel pad 155 may be provided to cover the upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. For example, the channel pad 155 may include doped polysilicon.

[0047] The epitaxial layer 107 may be disposed on the substrate 101 at the lower end of the channel structure CH, and disposed on the side surface of at least one gate electrode 130. A side insulating layer 106 may also be disposed between the epitaxial layer 107 and the gate electrode 130. The epitaxial layer 107 may be disposed in a recessed region of the substrate 101. An upper surface of the epitaxial layer 107 may be higher than an upper surface of the lowest gate electrode 130, and may be lower than a lower surface of the gate electrode 130 on the lowest gate electrode 130, but is not limited thereto. In example embodiments, the epitaxial layer 107 may be omitted. In this case, the channel layer 140 may be directly connected to the substrate 101, or may be connected to another conductive layer on the substrate 101.

[0048] The separation region SR may pass through the gate electrode 130 and the interlayer insulating layer 120 between the channel layer 140, may extend in the Y direction, and may be connected to the substrate 101. The source conductive layer 180 and the separation insulating layer 185 may be arranged in the separation region SR. The source conductive layer 180 may have a shape in which its width decreases toward the substrate 101 due to a large aspect ratio, but is not limited thereto. In example embodiments, the source conductive layer 180 may have a side surface perpendicular to the upper surface of the substrate 101.

[0049] The source conductive layer 180 may be electrically insulated from the gate electrode 130 by the separation insulating layer 185. Therefore, the gate electrodes 130 in the stacked structure GS may be separated from each other in the X direction, while the source conductive layer 180 is interposed between them. The source conductive layer 180 may be arranged in a line shape extending in the Y direction, and may correspond to the common source line of the semiconductor device 100. For example, the source conductive layer 180 may be arranged every four to eight columns of the channel layer 140 in the X direction, but is not limited thereto. The separation insulating layer 185 may partially expand and protrude between the interlayer insulating layers 120 to contact the side surface of the gate electrode 130. The source conductive layer 180 may include a conductive material such as polysilicon, metal, etc., and the separation insulating layer 185 may include an insulating material such as silicon oxide, silicon nitride, etc. In some embodiments, the source conductive layer 180 may be omitted from the separation region SR, and the insulating material may be filled only in the separation region SR. In this case, the region corresponding to the common source line may be located in or on the substrate 101.

[0050] The cell region insulating layer 190 may be disposed on the stacked structure GS of the gate electrode 130 , and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0051] FIG. 4A to FIG. 4C is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 4A to FIG. 4C is corresponding to Figure 2 An enlarged view of the area of ​​portion 'A'.

[0052] Reference Figure 4A In the semiconductor device 100a, the first blocking insulating layer 144a may have different thicknesses on the upper surface, the lower surface, and the outer side surface of the charge storage layer 143. In the first blocking insulating layer 144a, the thickness T2 on the outer side surface of the charge storage layer 143 may be greater than the thickness T3 on the upper surface and the lower surface of the charge storage layer 143. Such a structure may be formed along the space between the charge storage layer 143 and the interlayer insulating layer 120 in the process of forming the first blocking insulating layer 144a.

[0053] Reference Figure 4B, in the semiconductor device 100b, the charge storage layer 143a may have a recessed portion CR on the inner side surface of the charge storage layer 143a contacting the tunneling insulating layer 142. The recessed portion CR may be formed in the central region of the charge storage layer 143a in the vertical direction, and may have a concave shape toward the central portion of the charge storage layer 143a. In some embodiments, the tunneling insulating layer 142 may also have a recessed portion in a region corresponding to the recessed portion CR of the charge storage layer 143a. In this case, the recessed portion of the tunneling insulating layer 142 may have a freer shape than the recessed portion CR of the charge storage layer 143a. This structure may be described below with reference to Fig. 11C The recess forming process of the horizontal sacrificial layer 110 is described in accordance with the depth of the recess.

[0054] Reference Figure 4C , in the semiconductor device 100c, the inner side surfaces at the upper and lower ends of the first blocking insulating layer 144b may not be coplanar with the inner side surfaces of the charge storage layer 143, and the first blocking insulating layer 144b may have a shape that partially extends into the tunneling insulating layer 142. For example, the first blocking insulating layer 144b may be configured such that the inner side ends of the first blocking insulating layer 144b protrude toward the tunneling insulating layer 142 on the upper and lower surfaces of the charge storage layer 143 and enter the tunneling insulating layer 142. Such a structure may be formed in the following case: before the formation process of the first blocking insulating layer 144b, in the following reference Fig.11J The removal process of the first vertical sacrificial layer 115 is described in which a corresponding region of the tunnel insulating layer 142 is partially removed.

[0055] Figure 5A and Figure 5B are a cross-sectional view and a partially enlarged view schematically illustrating a semiconductor device according to example embodiments, respectively. Figure 5B yes Figure 5A An enlarged view of portion 'B'.

[0056] Reference Figure 5A and Figure 5BIn the semiconductor device 100d, the inner side surface of the charge storage layer 143b is not coplanar with the side surface of the interlayer insulating layer 120, and the charge storage layer 143b may have a structure protruding toward the central portion of the channel structure CH (e.g., toward the channel layer 140). For example, the length D3 of a portion of the charge storage layer 143b that protrudes horizontally in the X direction beyond the side surface of the interlayer insulating layer 120 may be less than half of the total thickness of the charge storage layer 143b in the X direction, but may vary differently in some embodiments. The tunneling insulating layer 142 may surround the protruding area of ​​the charge storage layer 143b and may extend perpendicularly to the upper surface of the substrate 101. Therefore, the tunneling insulating layer 142 may have a curvature corresponding to the arrangement of the charge storage layer 143b. In addition, the channel layer 140 may also have a curvature corresponding to the arrangement of the charge storage layer 143b accordingly.

[0057] Such a structure can be formed in the following cases: Fig.11F In the depicted removal process of the oxidized sacrificial layer 118 , the interlayer insulating layer 120 and the first vertical sacrificial layer 115 are partially removed above and below the charge storage layer 143 b .

[0058] Fig. 6A and Figure 6B are a cross-sectional view and a partially enlarged view schematically illustrating a semiconductor device according to example embodiments, respectively. Figure 6B yes Fig. 6A An enlarged view of portion 'C' of FIG.

[0059] Refer to 6A and Figure 6B In the semiconductor device 100e, the first blocking insulating layer 144c may not be limited to being disposed between the gate electrode 130 and the charge storage layer 143, but may be disposed to extend horizontally along the gate electrode 130. Therefore, the first blocking insulating layer 144c may be disposed to surround the charge storage layer 143 in a region adjacent to the channel layer 140, and may be disposed to surround the gate electrode 130 and the second blocking insulating layer 146. In this case, the upper and lower surfaces of the first blocking insulating layer 144c may contact the interlayer insulating layer 120. Specifically, the inner side surface of the first blocking insulating layer 144c (e.g., the side surface of the first blocking insulating layer 144c contacting the charge storage layer 143) may have a convex round shape toward the gate electrode 130, and the outer side surface of the first blocking insulating layer 144c (e.g., the side surface of the first blocking insulating layer 144c contacting the second blocking insulating layer 146) may have a convex round shape toward the channel layer 140. In addition, a side surface of the second blocking insulating layer 146 facing the channel layer 140 (eg, a side surface of the second blocking insulating layer 146 contacting the first blocking insulating layer 144 c ) may have a convex rounded shape toward the channel layer 140 .

[0060] Such a structure of the first blocking insulating layer 144c may be formed in the following case: Figure 11K In the formation process of the first blocking insulating layer described above, the first blocking insulating layer is formed by a deposition process rather than an oxidation process.

[0061] Figure 7 is a partially enlarged view schematically illustrating a semiconductor device according to example embodiments. Figure 7 is corresponding to Fig. 6A An enlarged view of the area of ​​portion 'C'.

[0062] Reference Figure 7 In the semiconductor device 100f, the first blocking insulating layer 144c may have a thickness as described above. Fig. 6A and Figure 6B The structures described above extend horizontally along the gate electrode 130 in a similar manner. Specifically, the semiconductor device 100f may further include a third blocking insulating layer 148 disposed between the charge storage layer 143 and the first blocking insulating layer 144c.

[0063] The third blocking insulating layer 148 may include a material different from that of the first blocking insulating layer 144c and the second blocking insulating layer 146. Although the thickness of the third blocking insulating layer 148 is shown as thinner than the thickness of the first blocking insulating layer 144c, the thickness is not limited thereto and may vary differently according to some embodiments. For example, the thickness of the third blocking insulating layer 148 may be thicker than the thickness of the first blocking insulating layer 144c. When the third blocking insulating layer 148 is included as described above, the second blocking insulating layer 146 may be omitted according to some embodiments.

[0064] Figure 8 is a cross-sectional view schematically illustrating a semiconductor device according to example embodiments.

[0065] Reference Figure 8 In the semiconductor device 100g, according to Figure 2 Different from the semiconductor device 100, the channel structure CHa may not include the epitaxial layer 107, and the semiconductor device 100g may further include a first conductive layer 104 and a second conductive layer 105 disposed between the substrate 101 and the interlayer insulating layer 120. In addition, the separation region SR may be filled with only the separation insulating layer 185.

[0066] The first conductive layer 104 and the second conductive layer 105 may be arranged to be stacked on the upper surface of the substrate 101. At least a portion of the first conductive layer 104 and the second conductive layer 105 may be used as a common source line of the semiconductor device 100g, or may be used as a common source line of the semiconductor device 100g together with the substrate 101. The first conductive layer 104 may be directly connected to the channel layer 140 around the channel structure CHa. The first conductive layer 104 and the second conductive layer 105 may include a semiconductor material such as polysilicon. In this case, at least the first conductive layer 104 may be a doped layer, and the second conductive layer 105 may be a doped layer or may be a layer including impurities dissipated from the first conductive layer 104.

[0067] In the channel structure CHa, the channel layer 140 and the tunnel insulating layer 142 may be arranged to extend into the substrate 101. A portion of the tunnel insulating layer 142 may be removed from the lower end, and the first conductive layer 104 may be connected to the channel layer 140 in the region where the tunnel insulating layer 142 is removed. In this way, the shape of the common source line including the first conductive layer 104 and the second conductive layer 105 may be applied to FIG. 4A to FIG. 7 Embodiment of the invention.

[0068] Fig. 9 is a cross-sectional view schematically illustrating a semiconductor device according to example embodiments.

[0069] Reference Fig. 9 In the semiconductor device 100h, the stack structure of the gate electrode 130 may include a first stack structure GS1 and a second stack structure GS2 stacked in a vertical direction, and the channel structure CHb may include a first channel structure CH1 and a second channel structure CH2 stacked in a vertical direction. When the number of stacked gate electrodes 130 is large, the structure of the channel structure CHb may be introduced to stably form the channel structure CHb.

[0070] The channel structure CHb may have a form in which the first channel structure CH1 of the first stacked structure GS1 and the second channel structure CH2 of the second stacked structure GS2 are connected to each other, and may have a bent portion due to the difference in width of the regions connected to each other. The channel layer 140, the tunneling insulating layer 142, and the channel insulating layer 150 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 may be provided only at the upper end of the second channel structure CH2 in the upper portion. In example embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 155. In this case, the channel pad 155 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2. The semiconductor device 100h may be as shown. Figure 8The semiconductor device 100h includes a first conductive layer 104 and a second conductive layer 105 as in the embodiment of the present invention, but is not limited thereto. For example, instead of the first conductive layer 104 and the second conductive layer 105, the semiconductor device 100h may further include an epitaxial layer 107 disposed at the lower end of the channel structure CHb, as shown in FIG. Figure 2 As in the embodiment of .

[0071] A relatively thick upper interlayer insulating layer 125 may be disposed on the uppermost portion of the first stacked structure GS1. The shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may vary differently in some embodiments. For other elements / configurations, the above reference may be equally applied. Figures 1 to 3 Description.

[0072] Fig.10 is a cross-sectional view schematically illustrating a semiconductor device according to example embodiments.

[0073] Reference Fig.10 , the semiconductor device 100i may include a memory cell region CELL and a peripheral circuit region PERI stacked in a vertical direction. The memory cell region CELL may be disposed on the peripheral circuit region PERI. Figure 2 For the semiconductor device 100 of the present invention, although the peripheral circuit region PERI may be disposed on the substrate 101 in an area not shown, in this example embodiment, the memory cell region CELL and the peripheral circuit region PERI may be stacked in the vertical direction. In the example embodiment, the memory cell region CELL may be disposed below the peripheral circuit region PERI. For the memory cell region CELL, the above reference to Figures 1 to 3 Description.

[0074] The peripheral circuit region PERI may include a base substrate 201 , and circuit elements 220 , circuit contact plugs 270 , and circuit wirings 280 arranged on the base substrate 201 .

[0075] The bottom substrate 201 may have an upper surface extending in the X direction and the Y direction. In the bottom substrate 201, an element isolation layer may be separately formed to define an active region. A source / drain region 205 including impurities may be provided in a portion of the active region. The bottom substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0076] The circuit elements 220 may include planar transistors. Each of the circuit elements 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain region 205 may be disposed in the base substrate 201 and located on both sides (eg, opposite sides) of the circuit gate electrode 225.

[0077] The peripheral region insulating layer 290 may be disposed on the circuit element 220 on the base substrate 201. The circuit contact plug 270 may pass through the peripheral region insulating layer 290 to be connected to the source / drain region 205. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit wiring 280 may be connected to the circuit contact plug 270, and may be provided in a plurality of layers.

[0078] In the semiconductor device 100i, the peripheral circuit region PERI may be manufactured first. Then, the substrate 101 of the memory cell region CELL may be formed thereon to manufacture the memory cell region CELL. The substrate 101 may have the same size as the base substrate 201, or may be formed smaller than the base substrate 201. The memory cell region CELL and the peripheral circuit region PERI may be connected to each other in an area not shown. For example, one or more ends of the gate electrode 130 in the Y direction may be electrically connected to the circuit element 220. Such a configuration in which the memory cell region CELL and the peripheral circuit region PERI are stacked in the vertical direction may be applied to FIG. 4A to FIG. 9 Embodiment of the invention.

[0079] FIG. 11A to FIG. 11L is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 11A to FIG. 11L Shows the corresponding Figure 2 sectional view of .

[0080] Reference Fig.11A , a stack structure may be formed by alternately stacking horizontal sacrificial layers 110 and interlayer insulating layers 120 on a substrate 101 .

[0081] The horizontal sacrificial layer 110 may be a layer replaced by the gate electrode 130 through a subsequent operation. The horizontal sacrificial layer 110 may be formed of a material different from that of the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the horizontal sacrificial layer 110 may be formed of a material different from that of the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some embodiments, the thicknesses of the interlayer insulating layers 120 may not all be the same. For example, the lowermost interlayer insulating layer 120 may be formed to be relatively thin, while the uppermost interlayer insulating layer 120 may be formed to be relatively thick. The thicknesses of the interlayer insulating layer 120 and the horizontal sacrificial layer 110 and the number of films constituting them may be different from those shown. Fig.11A A cell region insulating layer 190 is formed on / in the uppermost portion of the stacked structure as shown.

[0082] Reference Fig. 11B, the channel hole CHH may be formed to pass through the stack structure of the horizontal sacrificial layer 110 and the interlayer insulating layer 120 , and the epitaxial layer 107 may be formed in a lower portion of the channel hole CHH.

[0083] The channel hole CHH may be formed by anisotropically etching the horizontal sacrificial layer 110 and the interlayer insulating layer 120, and the channel hole CHH may be formed in the shape of a hole. Due to the height of the stacked structure, the sidewall of the channel hole CHH may not be perpendicular to the upper surface of the substrate 101. The channel hole CHH may be formed to recess a portion of the substrate 101.

[0084] The epitaxial layer 107 may be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 107 may be formed as a single layer or multiple layers. The epitaxial layer 107 may include polycrystalline silicon doped with or without impurities, single crystal silicon, polycrystalline germanium, or single crystal germanium. In some embodiments, the epitaxial layer 107 may be omitted.

[0085] Reference Fig. 11C , the horizontal sacrificial layer 110 exposed through the channel holes CHH may be partially removed.

[0086] The horizontal sacrificial layer 110 may be partially removed from the channel hole CHH. Thus, a recessed area may be formed outside the channel hole CHH, from which the portion of the horizontal sacrificial layer 110 is removed. For example, the removal operation may be performed by a wet etching process. Thus, the side surface of the horizontal sacrificial layer 110 exposed toward the channel hole CHH may be further away from the central portion of the channel hole CHH than the side surface of the interlayer insulating layer 120.

[0087] Reference Fig.11D , the first vertical sacrificial layer 115 and the second vertical sacrificial layer 117 may be formed on the outer wall of the channel hole CHH.

[0088] The first vertical sacrificial layer 115 and the second vertical sacrificial layer 117 may be formed along the side surface of the horizontal sacrificial layer 110 and the side surface of the interlayer insulating layer 120 exposed by the channel hole CHH. The first vertical sacrificial layer 115 may be formed relatively thin, and the recessed area of ​​the horizontal sacrificial layer 110 may be completely filled with the first vertical sacrificial layer 115 and the second vertical sacrificial layer 117. The first vertical sacrificial layer 115 and the second vertical sacrificial layer 117 may include different materials. The first vertical sacrificial layer 115 may include a material different from that of the horizontal sacrificial layer 110. For example, the first vertical sacrificial layer 115 may include silicon oxide, and the second vertical sacrificial layer 117 may include polysilicon.

[0089] Reference Fig.11E , a portion of the second vertical sacrificial layer 117 may be oxidized to form an oxidized sacrificial layer 118 .

[0090] The oxidized sacrificial layer 118 may be formed by oxidizing the second vertical sacrificial layer 117 to a predetermined thickness in the region where the second vertical sacrificial layer 117 is exposed through the channel hole CHH. The oxidation operation may be performed under the following conditions: at least on the side surface of the interlayer insulating layer 120, all the second vertical sacrificial layers 117 formed on the first vertical sacrificial layer 115 are oxidized. Therefore, the second vertical sacrificial layer 117 formed in the region where the horizontal sacrificial layer 110 is recessed may remain unoxidized. On the side surface of the horizontal sacrificial layer 110, the remaining second vertical sacrificial layers 117 may be separated from each other in the vertical direction.

[0091] Reference Fig.11F , the oxidized sacrificial layer 118 may be removed.

[0092] The oxidized sacrificial layer 118 exposed through the channel hole CHH may be selectively removed by, for example, a wet etching process. For example, when the oxidized sacrificial layer 118 is formed of the same material as that of the first vertical sacrificial layer 115, the first vertical sacrificial layer 115 on the side surface of the interlayer insulating layer 120 may also be removed together in this operation. Therefore, the first vertical sacrificial layer 115 and the second vertical sacrificial layer 117 may remain confined to the recessed area of ​​the horizontal sacrificial layer 110, and may have a form separated from each other along the horizontal sacrificial layer 110 in the Z direction.

[0093] Reference Fig.11G , the second vertical sacrificial layer 117 may be nitrided to form a charge storage layer 143 .

[0094] The second vertical sacrificial layer 117 exposed through the channel hole CHH may be selectively nitrided. The nitridation operation may be performed by injecting a nitride gas through the channel hole CHH. For example, when the second vertical sacrificial layer 117 is formed of polysilicon, the charge storage layer 143 of silicon nitride may be formed by the nitridation operation.

[0095] As such, the second vertical sacrificial layer 117 may be nitrided to form the charge storage layers 143 so that the charge storage layers 143 may be respectively formed on the side surfaces of the horizontal sacrificial layers 110 without operating unchanged and may be formed to have a substantially constant thickness.

[0096] Reference Fig.11H , a tunneling insulating layer 142 , a channel layer 140 , and a channel insulating layer 150 may be sequentially formed on the charge storage layer 143 , and a channel pad 155 may be formed in an upper portion of the channel hole CHH.

[0097] The tunneling insulating layer 142 and the channel layer 140 may be formed to have a uniform thickness using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The tunneling insulating layer 142 and the channel layer 140 may be formed to extend perpendicularly to the substrate 101. The tunneling insulating layer 142 may be formed to cover the exposed surface of the charge storage layer 143, and the channel layer 140 may be formed to be connected to the epitaxial layer 107 in the lower portion of the channel hole CHH. The channel insulating layer 150 may be formed to fill the inner space of the channel layer 140, and may be an insulating material. In some embodiments, the channel layer 140 may be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 may be formed of a conductive material such as polysilicon.

[0098] Reference Fig.11I , an opening OP passing through the stacked structure of the horizontal sacrificial layer 110 and the interlayer insulating layer 120 may be formed, and the horizontal sacrificial layer 110 may be removed through the opening OP to form a lateral opening LT.

[0099] First, before forming the opening OP, a cell region insulating layer 190 may be formed on the channel pad 155. Figure 1 and Figure 2 The opening OP is formed at the position of the separation region SR. The opening OP may be formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure. The opening OP may be formed in a groove shape extending in the Y direction, and the substrate 101 may be exposed in / through the lower portion of the opening OP.

[0100] For example, the horizontal sacrificial layer 110 may be selectively removed relative to the interlayer insulating layer 120 and the first vertical sacrificial layer 115 using a wet etching process. Therefore, a plurality of lateral openings LT may be formed between the interlayer insulating layers 120, and a portion of the first vertical sacrificial layer 115 may be exposed through the lateral openings LT.

[0101] Reference Fig.11J , the first vertical sacrificial layer 115 exposed through the lateral opening LT may be removed.

[0102] For example, the first vertical sacrificial layer 115 may be selectively removed by a wet etching process to expose the outer side surface of the charge storage layer 143. For example, when the first vertical sacrificial layer 115 is formed of the same material as the interlayer insulating layer 120, the interlayer insulating layer 120 exposed by the lateral opening LT may also be partially removed in this operation. In this case, the height of the lateral opening LT may be increased.

[0103] Reference Figure 11K, a first blocking insulating layer 144 covering the upper surface, the lower surface, and the outer side surface of the charge storage layer 143 may be formed in the lateral opening LT.

[0104] The first blocking insulating layer 144 may be formed by an oxidation operation in which an oxidizing gas is supplied through the lateral opening LT. When the first blocking insulating layer 144 is formed, a portion of the charge storage layer 143 may be consumed. The first blocking insulating layer 144 may be formed to surround all outer surfaces of the charge storage layer 143 that do not contact the tunneling insulating layer 142, and may be formed to contact the interlayer insulating layer 120. In this operation, the side insulating layer 106 may also be formed on the side surface of the epitaxial layer 107. Therefore, a channel structure CH including the epitaxial layer 107, the channel layer 140, the tunneling insulating layer 142, the channel insulating layer 150, the channel pad 155, the charge storage layer 143, the first blocking insulating layer 144, and the side insulating layer 106 may be formed.

[0105] The first blocking insulating layer 144c may be prepared by forming the first blocking insulating layer 144c using a deposition process instead of an oxidation process in this operation. FIG. 6A to FIG. 7 In this case, since the deposition process is performed not only around the charge storage layer 143 but also on the upper and lower surfaces of the interlayer insulating layer 120, it is possible to form FIG. 6A to FIG. 7 The first blocking insulating layer 144c is formed. Figure 7 In the case of the embodiment of FIG. 1 , after the third blocking insulating layer 148 is formed on the first vertical sacrificial layer 115 in advance, the first blocking insulating layer 144 c may be formed through a deposition process in this operation.

[0106] Reference Fig.11L , a second blocking insulating layer 146 may be formed in the lateral opening LT.

[0107] The second blocking insulating layer 146 may be formed on upper and lower surfaces of the interlayer insulating layer 120 and outer side surfaces of the first blocking insulating layer 144 exposed through the lateral opening LT.

[0108] Next, refer to Figure 2 , the gate electrode 130 may be formed by filling a conductive material in the lateral opening LT, and the separation insulating layer 185 and the source conductive layer 180 may be formed in the opening OP.

[0109] The conductive material may include a metal, polysilicon, or a metal silicide material. After forming the gate electrode 130, the conductive material deposited in the opening OP may be removed by an additional process. The separation insulating layer 185 may be formed in the form of a spacer in the opening OP. For example, after depositing the insulating material, the separation insulating layer 185 may be formed by removing the insulating material formed on the substrate 101 in the lower portion of the opening OP. Next, the source conductive layer 180 may be prepared by depositing a conductive material on the separation insulating layer 185 to form the source conductive layer 180. Figure 2 A semiconductor device 100 is provided.

[0110] FIG. 12A to FIG. 12C is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 12A to FIG. 12C Shows the corresponding Figure 2 sectional view of .

[0111] Reference Fig. 12A First, you can follow the same method to execute the above reference FIG. 11A to FIG. 11F The described operations allow the first and second vertical sacrificial layers 115 and 117 and the oxidized sacrificial layer 118 to be formed through the channel holes CHH, and the oxidized sacrificial layer 118 may be subsequently removed.

[0112] Then, if Fig. 12A As shown, the tunnel insulating layer 142, the channel layer 140, and the channel insulating layer 150 may be sequentially formed on the second vertical sacrificial layer 117. In addition, the channel pad 155 may be formed in the upper portion of the channel hole CHH. For the operation of forming the tunnel insulating layer 142, the channel layer 140, the channel insulating layer 150, and the channel pad 155, the above reference 140 may be equally applied. Fig.11H Description.

[0113] Reference Fig. 12B , an opening OP passing through the stacked structure of the horizontal sacrificial layer 110 and the interlayer insulating layer 120 may be formed, and the horizontal sacrificial layer 110 may be removed through the opening OP to form a lateral opening LT, and the first vertical sacrificial layer 115 may be removed.

[0114] First, the opening OP may be formed in Figure 1 For example, the horizontal sacrificial layer 110 may be selectively removed relative to the interlayer insulating layer 120 and the first vertical sacrificial layer 115 using a wet etching process. Therefore, the plurality of lateral openings LT may be formed between the interlayer insulating layers 120, and a portion of the first vertical sacrificial layer 115 may be exposed through the lateral openings LT.

[0115] Next, the first vertical sacrificial layer 115 may be selectively removed by, for example, a wet etching process to expose the second vertical sacrificial layer 117. For example, when the first vertical sacrificial layer 115 is formed of the same material as that of the interlayer insulating layer 120, the interlayer insulating layer 120 exposed through the lateral opening LT may also be partially removed in this operation. In this case, the height of the lateral opening LT may be increased.

[0116] Reference Fig. 12C , the second vertical sacrificial layer 117 exposed through the lateral opening LT may be nitrided to form a charge storage layer 143 .

[0117] The exposed second vertical sacrificial layer 117 may be selectively nitrided by injecting a nitriding gas through the lateral opening LT. For example, when the second vertical sacrificial layer 117 is formed of polysilicon, the charge storage layer 143 of silicon nitride may be formed by a nitridation operation. As described above, according to the manufacturing method of this example embodiment, the execution order of each operation of forming the charge storage layer 143 by a nitridation operation may be the same as that described above with reference to FIG. 11A to FIG. 11L Differences in the manufacturing methods described.

[0118] Next, you can follow the same method to execute the above reference Figure 11K and Fig.11L The operations of forming the first blocking insulating layer 144 and the second blocking insulating layer 146 are described to manufacture Figure 2 A semiconductor device 100 is provided.

[0119] FIG. 13A to FIG. 13C is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 13A to FIG. 13C Shows the corresponding Figure 8 sectional view of .

[0120] Reference Fig.13A , first and second source sacrificial layers 111 and 112 and a second conductive layer 105 may be formed on the substrate 101, and horizontal sacrificial layers 110 and interlayer insulating layers 120 may be alternately stacked to form a stacked structure.

[0121] First, the first source sacrificial layer 111 and the second source sacrificial layer 112 may include different materials and may be stacked on the substrate 101 so that the first source sacrificial layer 111 is disposed above and below the second source sacrificial layer 112. The first source sacrificial layer 111 and the second source sacrificial layer 112 may be Figure 8For example, the first source sacrificial layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second source sacrificial layer 112 may be formed of the same material as the horizontal sacrificial layer 110. The second conductive layer 105 may be deposited on the first source sacrificial layer 111 and the second source sacrificial layer 112.

[0122] Next, refer to the above Fig.11A Similar to those described, a horizontal sacrificial layer 110 , an interlayer insulating layer 120 , and a cell area insulating layer 190 (or a plurality of cell area insulating layers 190 ) may be formed on the second conductive layer 105 .

[0123] Reference Fig. 13B First, you can follow the same approach as above. FIG. 11B to FIG. 11G The described operations are performed to form the charge storage layer 143. Specifically, in this example embodiment, the charge storage layer 143 and the first vertical sacrificial layer 115 may be formed on the side surface of the second source sacrificial layer 112.

[0124] Then, if Fig. 13B As shown, a channel layer 140, a tunnel insulating layer 142, a channel insulating layer 150, and a channel pad 155 may be formed. For the operation of forming the tunnel insulating layer 142, the channel layer 140, the channel insulating layer 150, and the channel pad 155, the above reference 140 may be equally applied. Fig.11H In this example embodiment, in a lower portion of the channel hole CHH, the channel layer 140 and the tunnel insulating layer 142 may be provided to extend into the substrate 101 .

[0125] Reference Fig. 13C An opening OP may be formed through the stacked structure of the horizontal sacrificial layer 110, the first and second source sacrificial layers 111 and 112, and the interlayer insulating layer 120. After removing the first and second source sacrificial layers 111 and 112 through the opening OP, the first conductive layer 104 may be formed.

[0126] In example embodiments, before removing the first source sacrificial layer 111 and the second source sacrificial layer 112, a spacer layer may be formed on the sidewall of the opening OP to protect the horizontal sacrificial layer 110. After removing the second source sacrificial layer 112 through the opening OP in advance, the first source sacrificial layer 111 may be removed. The first source sacrificial layer 111 and the second source sacrificial layer 112 may be removed by, for example, a wet etching process. In the removal operation of the first source sacrificial layer 111, the tunneling insulating layer 142 exposed in the region where the second source sacrificial layer 112 is removed may also be partially removed. After the first conductive layer 104 may be formed by depositing a conductive material in the region where the first source sacrificial layer 111 and the second source sacrificial layer 112 are removed, the spacer layer may be removed. The first conductive layer 104 may be in direct contact with the channel layer 140 in the region where the tunneling insulating layer 142 is removed.

[0127] Then, as mentioned above Fig.11I The horizontal sacrificial layer 110 may be removed through the opening OP, and the above reference may be performed in the same manner. Figures 11J to 11L Describe the operation to prepare Figure 8 In the method for manufacturing the semiconductor device 100g, the execution order of each operation of forming the charge storage layer 143 may be as described above with reference to FIG. 12A to FIG. 12C Descriptive changes.

[0128] A semiconductor device with improved reliability may be provided by discontinuously / separately providing a charge storage layer between memory cells (eg, vertically separated from each other by an interlayer insulating layer) and arranging a blocking insulating layer to surround the charge storage layer.

[0129] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: gate electrodes spaced apart from each other on a substrate and stacked vertically with respect to an upper surface of the substrate; an interlayer insulating layer, which is alternately stacked with the gate electrodes on the substrate; as well as a channel structure that passes through the gate electrode and extends vertically relative to the upper surface of the substrate, Each of the channel structures includes: a channel layer extending vertically relative to the upper surface of the substrate, a tunneling insulating layer located on the channel layer and extending vertically relative to the upper surface of the substrate, a charge storage layer located on the tunneling insulating layer in respective regions between the gate electrode and the side surface of the tunneling insulating layer, and a first blocking insulating layer respectively located on the charge storage layer. wherein the first layer in the first blocking insulating layer is located on the upper surface and the lower surface of the first layer in the charge storage layer, and is also located on the side surface of the first layer in the charge storage layer facing the first gate electrode in the gate electrode, wherein, in a first direction perpendicular to the upper surface of the substrate, the height of each of the charge storage layers is smaller than the distance between a pair of interlayer insulating layers adjacent to each other, and The charge storage layer includes a protruding portion that protrudes horizontally toward the channel layer beyond a side surface of the interlayer insulating layer.

2. The semiconductor device according to claim 1, wherein Each of the charge storage layers is surrounded by a corresponding one of the tunneling insulating layer and the first blocking insulating layer.

3. The semiconductor device according to claim 1, wherein The first blocking insulating layer contacts the tunnel insulating layer and does not vertically extend on a side surface of the interlayer insulating layer.

4. The semiconductor device according to claim 1, further comprising second blocking insulating layers respectively located on the gate electrodes, in, The first layer of the second blocking insulating layer is located on the upper surface, lower surface and side surfaces of the first gate electrode of the gate electrodes, and has an upper surface and a lower surface substantially coplanar with the upper surface and the lower surface of the first layer of the first blocking insulating layer, respectively.

5. The semiconductor device according to claim 4, wherein: A side surface of the second blocking insulating layer contacts a side surface of the first blocking insulating layer.

6. The semiconductor device according to claim 4, wherein: The first blocking insulating layer includes silicon oxide, and the second blocking insulating layer includes aluminum oxide.

7. The semiconductor device according to claim 1, wherein The thickness of each of the charge storage layers in a second direction parallel to the upper surface of the substrate ranges from 4 nanometers to 6 nanometers.

8. The semiconductor device according to claim 1, wherein The first layer in the first blocking insulating layer has a first thickness on the upper and lower surfaces of the first layer in the charge storage layer and a second thickness greater than the first thickness on the side surface of the first layer in the charge storage layer.

9. The semiconductor device according to claim 1, wherein: Each of the charge storage layers has a recessed portion contacting the tunnel insulating layer.

10. The semiconductor device according to claim 1, wherein The first blocking insulating layer extends between the interlayer insulating layer and the gate electrode.

11. The semiconductor device according to claim 10, further comprising: A third blocking insulating layer is between a first layer in the first blocking insulating layers and a first layer in the charge storage layers. 12 . The semiconductor device according to claim 1 , further comprising at least one conductive layer on the substrate, below the gate electrode and the interlayer insulating layer, and in contact with the channel layer.

13. A semiconductor device comprising: gate electrodes spaced apart from each other on a substrate and stacked vertically with respect to an upper surface of the substrate; an interlayer insulating layer, which is alternately stacked with the gate electrodes on the substrate; as well as a channel structure that passes through the gate electrode and extends vertically relative to the upper surface of the substrate, Each of the channel structures includes: a tunneling insulating layer and a channel layer extending vertically relative to the upper surface of the substrate, and a charge storage layer and a blocking insulating layer located on the side surface of the gate electrode and between the side surface of the gate electrode and the tunneling insulating layer. wherein the first layer in the charge storage layer and the first layer in the blocking insulating layer are separated from the second layer in the charge storage layer and the second layer in the blocking insulating layer by the first layer in the interlayer insulating layer, The blocking insulating layer and the tunneling insulating layer completely surround the charge storage layer respectively. wherein the upper surface and the lower surface of the blocking insulating layer are in contact with the interlayer insulating layer, and The charge storage layer includes a protruding portion that protrudes horizontally toward the channel layer beyond a side surface of the interlayer insulating layer.

14. The semiconductor device according to claim 13, wherein: The interlayer insulating layer has substantially planar upper and lower surfaces.

15. The semiconductor device according to claim 13, wherein: A height of each of the charge storage layers in a direction perpendicular to an upper surface of the substrate is smaller than a distance between a pair of interlayer insulating layers adjacent to each other.

16. The semiconductor device according to claim 13, wherein: The charge storage layer is located between the interlayer insulating layers to overlap the interlayer insulating layers in a direction perpendicular to an upper surface of the substrate.

17. A semiconductor device comprising: gate electrodes spaced apart from each other on a substrate and stacked vertically with respect to an upper surface of the substrate; an interlayer insulating layer, which is alternately stacked with the gate electrodes on the substrate; a channel layer passing through the gate electrode and extending vertically relative to an upper surface of the substrate; a tunneling insulating layer, which is located between the side surface of the interlayer insulating layer and the channel layer and extends vertically relative to the upper surface of the substrate; a charge storage layer, which is respectively located between the gate electrode and the tunneling insulating layer, wherein the first layer of the charge storage layer is located between the side surface of the first gate electrode of the gate electrodes and the side surface of the tunneling insulating layer, and between a pair of interlayer insulating layers adjacent to each other in a vertical direction, and the charge storage layer includes a protruding portion protruding horizontally toward the channel layer beyond the side surface of the interlayer insulating layer; first blocking insulating layers respectively located on the charge storage layers, wherein the first one of the first blocking insulating layers is located on the upper surface and the lower surface of the first one of the charge storage layers, and on the side surface of the first one of the charge storage layers facing the side surface of the first one of the gate electrodes, and between the pair of interlayer insulating layers adjacent to each other in the vertical direction; and a second blocking insulating layer respectively located on the gate electrodes, The first layer in the second blocking insulating layer is located on the upper surface, the lower surface and the side surface of the first gate electrode in the gate electrodes, and has an upper surface that is substantially coplanar with the upper surface of the first layer in the first blocking insulating layer.

18. The semiconductor device according to claim 17, wherein: A side surface of a first one of the charge storage layers protrudes toward a first one of the gate electrodes.

19. The semiconductor device according to claim 17, wherein: The side surface of the first layer in the first blocking insulating layer facing the side surface of the first gate electrode in the gate electrode has a convex round shape toward the first gate electrode in the gate electrode, and the side surface of the first layer in the second blocking insulating layer facing the channel layer has a concavely rounded shape toward the channel layer.

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